High frequency power supply device and output control method thereof

Abstract

The present invention provides a high-frequency power supply device and an output control method thereof, capable of consistently aligning the phases of output high-frequency pulses, even in a configuration that generates synchronization pulses and clock pulses separately. A high-frequency power supply device and an output control method thereof are provided. The high-frequency power supply device outputs high-frequency pulses to a target device based on synchronization pulses and clock pulses. The output control method comprises the following steps: detecting the cycle time of one cycle of the synchronization pulse and determining the phase difference between the synchronization pulse and the clock pulse one cycle prior; calculating the oscillation frequency and number of pulses of the next cycle based on the cycle time and phase difference; generating a clock pulse based on an oscillation frequency signal, and determining the oscillation frequency and number of pulses of the next cycle to offset the phase difference one cycle prior when forming a high-frequency pulse based on a cycle reference signal, a level setting signal, a pulse number signal, and the clock pulse, so that the phase is constant after the cycle time of the next cycle has elapsed.

Description

Technical Field

[0001] The present invention relates to a high-frequency power supply device suitable for a plasma generator, and more particularly to a high-frequency power supply device that outputs high-frequency pulses to an object device based on a synchronization pulse and a clock pulse, and an output control method thereof. Background Art

[0002] High-frequency power supply devices are used for powering ultrasonic oscillations, generating induction power, or generating plasma. These devices combine a synchronization pulse, which determines the output period of the high-frequency pulses, with a clock pulse, which determines the pulse period of the high-frequency component of the oscillation, to output high-frequency pulses containing a high-frequency component at a predetermined period and amplitude. In particular, switching-mode high-frequency power supply devices are known as high-frequency power supply devices for plasma generators, in which the amplitude of a single oscillation period includes both a high level (first level) and a low level (second level).

[0003] As a plasma processing apparatus utilizing such a switching high-frequency power supply, Patent Document 1 discloses a plasma etching apparatus, for example. Within a processing chamber filled with an etching gas and housing a semiconductor wafer as a processing target, an upper electrode and a lower electrode are positioned facing each other with the processing target interposed therebetween. A high-frequency voltage is applied from a high-frequency power supply to these electrodes. Discharge between the upper and lower electrodes converts the etching gas into plasma, thereby etching the processing target. In such an apparatus, the applied voltage from the high-frequency power supply must be stable in order to uniformly process the entire surface of the processing target.

[0004] In order to stably generate plasma in a plasma etching apparatus, Patent Document 2, for example, discloses a technique in which a matching network is connected between a high-frequency generator and a plasma processing chamber to convert the complex impedance of the plasma observed from the end of a transmission path to the nominal impedance of the high-frequency generator. This technique then performs feedback control on the voltage of an induction coil that supplies high-frequency power to the plasma processing chamber. This control technique uses the matching network to align the phase of the power waveform applied to the induction coil through feedback control, thereby stabilizing substrate processing.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 11-214363

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 2007-514300 Summary of the Invention

[0009] Problems to be solved by the invention

[0010] As described above, in conventional high-frequency power supply devices, the synchronization pulse generator that generates the synchronization pulses and the clock pulse generator that generates the clock pulses are typically separate components, and the two components operate independently. Therefore, the phase of the output waveform generated based on the clock pulses, which are among the high-frequency pulses output at the timing of the synchronization pulses, inevitably becomes inconsistent when the output level of the high-frequency pulses is switched. As a result, the number of pulses generated by the first amplitude level and the number of pulses generated by the second amplitude level become uneven between the multiple high-frequency pulses that oscillate continuously, causing jitter.

[0011] To address the unstable output waveform caused by the oscillation structure of such a high-frequency power supply, a technique such as that described in Patent Document 2 has been employed. However, this technique requires the addition of additional structures (such as a matching network) between the plasma processing apparatus and the high-frequency power supply, complicating power supply control. Furthermore, this technique cannot address fluctuations in the output waveform of the high-frequency pulse at speeds exceeding the response speed of the matching network. Therefore, this technique does not fundamentally address the issues associated with switching-type high-frequency power supplies.

[0012] The present invention is completed to solve the above-mentioned conventional problems, and its purpose is to provide a high-frequency power supply device and an output control method thereof, which can make the phase of the output high-frequency pulse always consistent even if the structure generates synchronization pulses and clock pulses separately.

[0013] Means for solving problems

[0014] To solve the above-mentioned problems, a high-frequency power supply device according to one representative embodiment of the present invention outputs a high-frequency pulse to an object device based on a synchronization pulse and a clock pulse, and is characterized in that it includes: a synchronization pulse generating mechanism that generates a synchronization pulse including output level information and output timing information of the high-frequency pulse; an output level setting mechanism that generates an output level signal for setting the output level of the high-frequency pulse based on the output level information; an oscillation waveform setting mechanism that transmits a frequency setting signal and a pulse number setting signal for setting the oscillation frequency and the number of pulses of the high-frequency pulse based on a phase difference between the synchronization pulse and the clock pulse; and an oscillation mechanism that receives a period reference signal of the synchronization pulse, the output level signal, the frequency setting signal, and the pulse number setting signal to oscillate the high-frequency pulse, the synchronization pulse generating mechanism including: a synchronization pulse forming circuit that forms the synchronization pulse; and a period reference signal generator that generates a period reference signal at a period reference time included in the timing information, and the output level setting mechanism including: a level discriminating unit that determines the period reference signal based on the output level signal. The oscillation waveform setting mechanism includes a circuit for determining an output level to be set in the high-frequency pulse; and a level setting signal generating unit that receives the determination result of the level determining unit and generates a level setting signal. The oscillation waveform setting mechanism includes: a synchronization pulse period detecting unit that detects a period time of one period of the synchronization pulse; a phase difference determining unit that determines a phase difference between the synchronization pulse and the clock pulse at least one period prior to the high-frequency pulse; and an output parameter determining unit that calculates an oscillation frequency and a pulse number of the high-frequency pulse in the next period of oscillation based on the period time and the phase difference, and transmits an oscillation frequency signal and a pulse number signal. The oscillation mechanism includes: a clock pulse generator that generates the clock pulse based on the oscillation frequency signal; and an oscillation amplifier that receives the period reference signal, the level setting signal, the pulse number signal, and the clock pulse and forms the high-frequency pulse based on these signals. The output parameter determining unit determines the oscillation frequency and pulse number of the next period to offset the phase difference one period prior to the next period, so that the phase of the next period after the period time has elapsed is constant.

[0015] Another aspect of the present invention is an output control method for a high-frequency power supply device that outputs a high-frequency pulse to an object device based on a synchronization pulse and a clock pulse, the output control method comprising the steps of: generating an output level signal for setting the output level of the high-frequency pulse based on output level information included in the waveform of the synchronization pulse, and generating a period reference signal based on output timing information; detecting a cycle time of one cycle of the synchronization pulse and determining a phase difference between the synchronization pulse and the clock pulse at least one cycle prior to the high-frequency pulse; calculating an oscillation frequency and a number of pulses of the high-frequency pulse in a next cycle based on the cycle time and the phase difference, and transmitting an oscillation frequency signal and a pulse number signal; and generating the clock pulse based on the oscillation frequency signal, receiving the period reference signal, the level setting signal, the pulse number signal, and the clock pulse, and forming the high-frequency pulse based on these signals, determining an oscillation frequency and a number of pulses of the next cycle to cancel the phase difference one cycle prior to the next cycle, so that the phase of the next cycle after the cycle time of the next cycle is constant.

[0016] According to the present invention having such a structure, since it is constructed to detect the cycle time of one cycle of the synchronization pulse and to determine the phase difference between the synchronization pulse and the clock pulse at least one cycle before the high-frequency pulse, the oscillation frequency and the number of pulses of the high-frequency pulse of the next cycle oscillation are calculated based on these cycle time and phase difference, an oscillation frequency signal and a pulse number signal are sent, a clock pulse is generated based on the oscillation frequency signal, and a cycle reference signal, a level setting signal, a pulse number signal and a clock pulse are received. When a high-frequency pulse is formed based on these signals, the oscillation frequency and the number of pulses of the next cycle that offset the phase difference of one cycle before are determined so that the phase after the cycle time of the next cycle has passed is fixed. Therefore, even if the structure generates the synchronization pulse and the clock pulse separately, the phase of the output high-frequency pulse can be always consistent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a block diagram showing an outline of a high-frequency power supply device as a representative example of the present invention.

[0018] Figure 2 Yes Figure 1 A block diagram showing an example of a specific configuration of a synchronization pulse generating mechanism shown.

[0019] Figure 3 Yes Figure 1 A block diagram showing an example of a specific configuration of an output level setting mechanism is shown.

[0020] Figure 4 Yes Figure 1A block diagram showing an example of a specific configuration of an oscillation waveform setting mechanism is shown.

[0021] Figure 5 Yes Figure 1 A block diagram showing an example of a specific structure of the oscillation mechanism shown.

[0022] Figure 6 Yes means through Figure 1 Graph showing an example of a high-frequency pulse output waveform obtained by the high-frequency power supply device shown.

[0023] Figure 7 This is a graph showing an example of an output waveform obtained by an output control method of a high-frequency power supply device according to a representative example of the present invention. DETAILED DESCRIPTION

[0024] Below, use Figures 1 to 7 Representative specific examples of the high-frequency power supply device and the output control method thereof according to the present invention will be described.

[0025] Figure 1 This is a block diagram showing an outline of a high-frequency power supply device as a representative example of the present invention.

[0026] Figure 1 The high-frequency power supply device 100 shown in FIG. 1 includes: a synchronization pulse generating unit 110 for generating a synchronization pulse P1 including output level information and output timing information of a high-frequency pulse PO to be output; and an output level setting unit 120 for generating an output level signal S for setting the output level of the high-frequency pulse PO based on the output timing information of the synchronization pulse P1. L1 、S L2 Oscillation waveform setting mechanism 130, which sends a frequency setting signal S that sets the oscillation frequency and the number of pulses of the high-frequency pulse PO based on the phase difference between the synchronization pulse P1 and the clock pulse P2 F And the pulse number setting signal S N And an oscillating mechanism 140, which receives a periodic reference signal S of the synchronization pulse P1 S , output level signal S L1 and S L2 , frequency setting signal S F And the pulse number setting signal S N , oscillating a high-frequency pulse PO. The high-frequency pulse PO outputted from the high-frequency power supply device 100 is supplied to a target device 10 such as a plasma, a laser generator, an induction heating device, or an ultrasonic oscillator.

[0027] Figure 2 Yes Figure 1 The block diagram of an example of the specific structure of the synchronization pulse generating mechanism shown in FIG. Figure 2As shown, the synchronization pulse generating mechanism 110 includes: a synchronization pulse forming circuit 112, which forms the above-mentioned synchronization pulse P1; and a period reference signal generator 114, which generates a period reference signal S at the period reference moment in the synchronization pulse P1. S In addition, the synchronization pulse P1 outputted from the synchronization pulse forming circuit 112 is also supplied to the output level setting unit 120 and the oscillation waveform setting unit 130 described later.

[0028] As an example, the synchronous pulse forming circuit 112 includes output level information (e.g., amplitude value) and output timing information (e.g., amplitude switching timing), and outputs a roughly rectangular periodic pulse waveform with two output levels L1 and L2 on the vertical axis defined by the time on the horizontal axis. Figure 2 In the embodiment, the case where the output levels are set to the high level L1 and the low level L2 is illustrated. However, as long as it is a periodic substantially rectangular wave, a pulse waveform based on three or more output levels may be used.

[0029] The synchronization pulse P1 is not limited to a rectangular wave, and may include any waveform such as a sine wave or an extremely short pulse as long as it includes output level information and output timing information.

[0030] Furthermore, the synchronization pulse P1 may be composed of a plurality of signal waveforms. As an example of this, a method of obtaining an output level and an output timing by performing AND processing on a plurality of signal waveforms can be exemplified.

[0031] The period reference signal generator 114 determines the time reference of the period, which is one of the characteristics of the sync pulse P1, based on the sync pulse P1 received from the sync pulse forming circuit 112, i.e., output timing information, and outputs the period reference signal S at the determined timing. S At this time, as an example of the time reference of the cycle, for example, the time when the low level L2 switches (rises) to the high level L1 can be cited. In addition, the period reference signal S S The number of timings in one cycle is not limited to one. For example, in addition to the rising timing from the low level L2 to the high level L1 described above, the switching (falling) timing from the high level L1 to the low level L2 may also be used.

[0032] Figure 3 Yes Figure 1 The block diagram of an example of a specific structure of the output level setting mechanism shown in FIG. Figure 3As shown, the output level setting mechanism 120 includes: a level determination unit 122, which issues a first level setting instruction S1 or a second level setting instruction S2 according to the amplitude value of the synchronization pulse P1 (output level information); and a level setting signal generating unit 124, which receives the first level setting instruction S1 and the second level setting instruction S2 issued by the level determination unit 122 and generates a level setting signal (first level setting signal S1). L1 Or the second level setting signal S L2 ). In addition, the level setting signal generating unit 124 further includes: a first level setting signal generator 126, which generates a first level setting signal S upon receiving a first level setting instruction S1. L1 And a second level setting signal generator 128, which generates a second level setting signal S when receiving a second level setting instruction S2 L2 .

[0033] The level determination unit 122 receives the synchronization pulse P1 from the synchronization pulse forming circuit 112 and issues a predetermined setting command in real time based on the output level of the synchronization pulse P1. For example, the level determination unit 122 issues a first level setting command S1 while the synchronization pulse P1 is at a high level L1, and issues a second level setting command S2 when the synchronization pulse P1 switches to a low level L2.

[0034] exist Figure 3 In the specific example shown, the level setting signal generator 124 includes a first level setting signal generator 126 and a second level setting signal generator 128. However, the level setting signal generator 124 may include three or more level setting signal generators. In addition, when the first level setting signal generator 126 receives the first level setting instruction S1 from the level determination unit 122, it transmits the first level setting signal S1 to the oscillation mechanism 140 during the period. L1 On the other hand, when the second level setting signal generator 128 receives the second level setting instruction S2 from the level determination unit 122, it sends the second level setting signal S to the oscillation mechanism 140 during the period. L2 .

[0035] Figure 4 Yes Figure 1 The block diagram of an example of the specific structure of the oscillation waveform setting mechanism shown in FIG. Figure 4 As shown, the oscillation waveform setting mechanism 130 includes a synchronization pulse period detection unit 132 that detects a period time T of one period of the synchronization pulse P1 received from the synchronization pulse generation mechanism 110. n Phase difference determination unit 134, which determines at least one cycle of the high frequency pulse PO before the synchronization pulse P1 and the phase difference ΔP of the clock pulse P2; and an output parameter determination unit, which is based on these cycle time Tn The oscillation frequency and number of pulses of the high-frequency pulse PO of the next cycle oscillation are calculated using the phase difference ΔP, and the oscillation frequency signal S is sent. F And the pulse number signal S N .

[0036] The synchronization pulse cycle detection unit 132 detects the cycle time T of each cycle of the synchronization pulse P1 received from the synchronization pulse generation unit 110. n (n is a natural number), send a continuous cycle containing the cycle time T of each cycle n The periodic time signal S P As an example, the synchronization pulse period detection unit 132 receives the synchronization pulse P1 in conjunction with the period reference signal generator 114, and transmits the period reference signal S S The interval (time) is measured and the cycle time T is set as each cycle n .

[0037] The phase difference determination unit 134 receives the synchronization pulse P1 from the synchronization pulse generation unit 110 and the clock pulse P2 from the oscillation unit 140, calculates the phase difference ΔP between the two, and generates the result as a phase difference signal S D As an example, the phase difference determination unit 134 detects the periodic reference signal S in the synchronization pulse P1 sent from the synchronization pulse period detection unit 132. S The sending time of is used as a reference, and the difference between the time of the next time with the same phase (for example, rising) as the clock pulse P2 from this time is calculated as the phase difference ΔP.

[0038] The output waveform parameter determination unit 136 determines the period time signal S received from the synchronization pulse period detection unit 132 based on the period time signal S received from the synchronization pulse period detection unit 132. P and the phase difference signal S received from the phase difference determination unit 134 D , calculate the oscillation frequency and number of pulses of the high-frequency pulse PO of the next cycle of oscillation, and send an oscillation frequency signal S to the oscillation mechanism 140 F And the pulse number signal S N At this time, the pulse number signal S N is determined to be the specified oscillation frequency signal S F The number of pulses corresponding to each frequency value.

[0039] In addition, for example, the periodic time signal S is determined based on the synchronization pulse P1 and the clock pulse P2 of the currently oscillating high-frequency pulse PO. P And the phase difference signal S DAs the waveform control of the high-frequency pulse PO of the next cycle is applied based on the calculated transmission frequency and number of pulses, the phase of the high-frequency pulse PO is aligned at the end of the next cycle (the start time of successive cycles).

[0040] Here, as an example of a determined oscillation frequency, the output waveform parameter determination unit 136 selects from three frequencies: a reference intermediate frequency, a smaller frequency than the reference frequency, and a larger frequency than the reference frequency. The difference between the intermediate frequency and the larger and smaller frequencies is determined based on the characteristics of the amplifier, filter, and other components of the hardware (e.g., an ultrasonic oscillator or plasma processing device) incorporating the high-frequency power supply device of the present invention. For example, it is set to approximately ±3% of the intermediate frequency. By multiplying the thus determined oscillation frequency by a predetermined number of pulses, the pulse width (duration) of each pulse within a single cycle can be varied.

[0041] In addition, the output waveform parameter determination unit 136 may be configured to determine the oscillation frequency and the number of pulses so that the phase after the cycle time of the next cycle (end time) always matches the timing of the rise or fall of the pulse.

[0042] Figure 5 Yes Figure 1 A block diagram of an example of a specific structure of an oscillating mechanism is shown. Figure 5 As shown, the oscillation mechanism 140 includes a clock pulse generator 142, which generates an oscillation frequency signal S according to the oscillation frequency signal S received from the oscillation waveform setting mechanism 130. F Generates a clock pulse P2 in a predetermined high frequency range; and an oscillation amplifier 144 which receives a periodic reference signal S from the synchronization pulse generating mechanism 110 S , the first level setting signal S from the output level setting mechanism 120 L1 and the second level setting signal S L2 , the pulse number signal S from the oscillation waveform setting mechanism 130 N , and the above-mentioned clock pulse P2, and form a high-frequency pulse PO based on these signals.

[0043] The clock pulse generator 142 generates an oscillation frequency signal S based on the oscillation frequency signal S received from the oscillation waveform setting mechanism 130. F , a unit that generates a high-frequency (hundreds of kHz to tens of MHz) clock pulse P2 corresponding to the output of the high-frequency pulse PO, generates a clock pulse P2 of, for example, 13.56 MHz. At this time, the clock pulse generator 142 can use the received oscillation frequency signal S F A component of any form such as a form in which the instructed oscillation frequency shifts to a corresponding frequency each time switching occurs.

[0044] The oscillation amplifier 144 is based on the periodic reference signal S S To determine the oscillation timing of the high frequency pulse PO, and based on the first level setting signal S L1 and the second level setting signal S L2 The amplitude of the clock pulse P2 is amplified to generate a high frequency pulse PO and oscillate. F The corresponding pulse number signal S N The high-frequency pulse PO is output continuously with the specified frequency and number of pulses.

[0045] Figure 6 It means by Figure 1 A graph showing an example of the output waveform of a high-frequency pulse obtained by the high-frequency power supply device shown in FIG. Figure 1 In the high frequency power supply device 100 shown in FIG. 1 , first, Figure 6 As shown in (a), the synchronization pulse P1 formed by the synchronization pulse forming circuit 112 of the synchronization pulse generating mechanism 110 is formed at time T L1 The interval becomes high level L1, at time T L2 The periodic pulse signal becomes a low level L2. And, as described above, the rising time to the high level L1, for example, as a time reference of one pulse cycle, is extracted from the synchronization pulse P1, and the periodic reference signal generator 114 sends the periodic reference signal S to the oscillation mechanism 140 at each rising time. S .

[0046] On the other hand, as described above, the synchronization pulse P1 is also supplied to the output level setting mechanism 120 , and the output level at each time is set by the level determination unit 122 of the output level setting mechanism 120 .

[0047] Then, the first level setting signal S is continuously sent from the first level setting signal generator 126 or the second level setting signal generator 128 to the oscillation mechanism 140. L1 Or the second level setting signal S L2 That is, refer to Figure 6 (a), at time T L1 The first level setting signal S is sent in the interval L1 , at time T L2 The second level setting signal S is sent in the interval L2 .

[0048] Next, in the oscillation amplifier 144 of the oscillation mechanism 140, the first level setting signal S L1 Or the second level setting signal S L2, the amplitude value of the clock pulse P2 is amplified. That is, after continuously receiving the first level setting signal S L1 In the case of Figure 6 As shown in (b), the average height of the output clock pulse P2 is a continuous pulse of the high level L1. On the other hand, when the first level setting signal S is continuously received L2 In the case of Figure 6 As shown in (c), the average height of the output clock pulse P2 is a continuous pulse of low level L2.

[0049] Furthermore, if these operations are performed continuously with time from the generation of the synchronization pulse P1, Figure 6 As shown in (d), the periodic reference signal S is received from the oscillation mechanism 140. S Pulses are continuously generated from the moment of time T L1 Similarly, at time T L2 The continuous pulses of the low level L2 are oscillated. In this way, the output is 1 cycle T n (n is a natural number) interval of high-frequency pulse PO.

[0050] Figure 7 1 is a graph showing an example of an output waveform obtained by an output control method of a high frequency power supply device according to a representative example of the present invention. Figure 7 In order to facilitate the explanation, the time T of each cycle is shown. n In the case of 8 pulses, for example, when the oscillation frequency of the high-frequency pulse PO is about 400kHz, each cycle includes about 30 pulses, and when the oscillation frequency is about 13.56MHz, each cycle includes more than 1000 pulses. In the output control method of a high-frequency power supply device of a representative example of the present invention, as shown in FIG. Figure 7 As shown in (a), the detection is done by Figures 1 to 6 The output cycle time T of the high frequency pulse PO output operation is described in n The phase difference between the synchronization pulse P1 and the clock pulse P2 in one cycle.

[0051] Specifically, when the pulse frequency of one pulse of the clock pulse P2 is formed by, for example, continuous pulses based on the above-mentioned intermediate frequency PM, the cycle time T n The starting time t0 (i.e. the periodic reference signal S SThe phase difference ΔP between the synchronization pulse P1 and the output high-frequency pulse PO is detected (at the time of transmission). In this case, the phase difference ΔP is not simply represented by the horizontal axis in the diagram, but rather refers to the elapsed time during which the output changes within a single pulse. Furthermore, the intermediate frequency PM is approximately equal to an integer multiple of the synchronization pulse P1.

[0052] Then, at the next cycle time T n+1 From the start time t2 to the time T L1 Specifically, using the pulses based on the intermediate frequency PM as a reference, the number of pulses N (N is a natural number) is selected so that the phase difference when replacing them with, for example, the high-frequency frequency PL becomes ΔP.

[0053] [Formula 1]

[0054]

[0055] That is, as an example, the number of pulses N that satisfies the above-mentioned formula 1 may be selected.

[0056] In this case, if the intermediate frequency PM is not equal to an integer multiple of the synchronization pulse P1, the period difference α between the synchronization pulse P1 and the clock pulse P2 is added to the right side of the above equation 1 to account for the period difference α. However, if the difference between the intermediate frequency PM and the integer multiple is set to be smaller than the resolution of the clock pulse generator 142, the period difference α can be omitted.

[0057] Therefore, in the next cycle T n+1 At the end time t4 of the clock pulse, the phase difference ΔP between the synchronization pulse P1 and the high-frequency pulse PO based on the clock pulse P2 is eliminated. That is, at time t2, the output waveform has a phase difference ΔP at an amplitude value A1, but at time t4, the phase difference is corrected to 0 at an amplitude value A2. In this case, it is preferable to control the phase of the pulse at the corrected time t4 so that it always coincides with the timing of the pulse's rise or fall.

[0058] On the other hand, Figure 7 As shown in (b), when the pulse based on the intermediate frequency PM is used as a reference, the number of pulses N may be selected so that the phase difference becomes ΔP when it is replaced by, for example, the small side frequency PS.

[0059] [Formula 2]

[0060]

[0061] That is, as an example, the number of pulses N that satisfies the above-mentioned formula 2 may be selected.

[0062] Therefore, with Figure 7Similarly, in the case shown in (a), at the next cycle time T n+1 At the end time t4, the phase difference ΔP between the synchronization pulse P1 and the high-frequency pulse PO based on the clock pulse P2 is eliminated. That is, at time t2, the output waveform has a phase difference ΔP with an amplitude value A1, but at time t4, the phase difference is corrected to 0 with an amplitude value A2.

[0063] By having the above-mentioned structure, the high-frequency power supply device and the output control method thereof of the present invention are configured to detect the cycle time T of one cycle of the synchronization pulse P1. n , and at least determine the phase difference ΔP between the synchronization pulse P1 and the clock pulse P2 one cycle before the high-frequency pulse PO, based on the cycle time T n The oscillation frequency and number of pulses of the high-frequency pulse PO of the next cycle oscillation are calculated using the phase difference ΔP, and the oscillation frequency signal S is sent. F And the pulse number signal S N , according to the oscillation frequency signal S F Generates clock pulse P2 and receives periodic reference signal S S , first level setting signal S L1 and the second level setting signal S L2 , pulse number signal S N and clock pulse P2, when the high frequency pulse PO is formed based on these signals, the cycle time T of the next cycle is passed. n+1 The way the phase is fixed after oscillation determines the oscillation frequency and number of pulses in the next cycle that offsets the phase difference ΔP of one cycle before. Therefore, even if the structure generates synchronization pulses and clock pulses separately, the phase of the output high-frequency pulses can always be consistent.

[0064] In addition, the description in the above embodiment is an example of the high-frequency power supply device and output control method thereof of the present invention, and the present invention is not limited to each embodiment. In addition, those skilled in the art can make various modifications without departing from the main purpose of the present invention, and they are not excluded from the scope of the present invention.

[0065] For example, in the above embodiment, the time T of one cycle of the high-frequency pulse PO is exemplified. L1 The control action of the phase difference ΔP based on the pulse modulation is offset in the interval, but it can also be configured to be only in the time T L2 The control for canceling the phase difference ΔP is performed in the interval or in two intervals simultaneously. As a result, output control for accurately canceling the phase difference can be performed in a shorter time.

[0066] Explanation of symbols

[0067] 10 Target device

[0068] 100 High-frequency power supply device

[0069] 110 Synchronous pulse generation mechanism

[0070] 112 Synchronous pulse forming circuit

[0071] 114 Periodic Reference Signal Generator

[0072] 116 Timing mechanism

[0073] 120 Output level setting mechanism

[0074] 122, 222, 322 level discrimination unit

[0075] 124 Level setting signal generating unit

[0076] 126 First level setting signal generator

[0077] 128 Second level setting signal generator

[0078] 130 Oscillation waveform setting mechanism

[0079] 132 Synchronous pulse period detection unit

[0080] 134 Phase difference determination unit

[0081] 136 Output waveform parameter determination unit

[0082] 140 Oscillation mechanism

[0083] 142 Clock Pulse Generator

[0084] 144 Oscillator Amplifier

[0085] PO high frequency pulse

[0086] P1 synchronization pulse

[0087] P2 clock pulse

[0088] S S Periodic reference signal

[0089] S L1 First level setting signal

[0090] S L2 Second level setting signal

[0091] S F Oscillation frequency signal

[0092] S N Pulse number signal

[0093] T n 、Tn+1 Cycle time.

Claims

1. A high-frequency power supply device that outputs high-frequency pulses to an object device based on a synchronization pulse and a clock pulse, characterized in that: The high-frequency power supply device comprises: a synchronization pulse generating mechanism for generating a synchronization pulse including output level information and output timing information of the high-frequency pulse; an output level setting mechanism for generating an output level signal for setting an output level of the high-frequency pulse based on the output level information; an oscillation waveform setting mechanism that sends a frequency setting signal and a pulse number setting signal for setting the oscillation frequency and the number of pulses of the high-frequency pulse based on a phase difference between the synchronization pulse and the clock pulse; as well as an oscillation mechanism that receives the period reference signal of the synchronization pulse, the output level signal, the frequency setting signal, and the pulse number setting signal to oscillate the high-frequency pulse. The synchronization pulse generating mechanism comprises: a synchronization pulse forming circuit that forms the synchronization pulse; and a periodic reference signal generator that generates a periodic reference signal at a periodic reference time included in the output timing information, The output level setting mechanism includes: a level determination unit that determines an output level set in the high-frequency pulse based on the output level signal; and a level setting signal generating unit that receives the determination result of the level determining unit and generates a level setting signal; The oscillation waveform setting mechanism includes: a synchronization pulse period detection unit configured to detect a period of one period of the synchronization pulse; a phase difference determination unit configured to determine a phase difference between the synchronization pulse and the clock pulse at least one cycle before the high-frequency pulse; and an output parameter determination unit that calculates the oscillation frequency and the number of pulses of the high-frequency pulse of the next cycle oscillation based on the cycle time and the phase difference, and transmits an oscillation frequency signal and a pulse number signal; The oscillating mechanism comprises: a clock pulse generator that generates the clock pulse based on the oscillation frequency signal; and an oscillation amplifier that receives the period reference signal, the level setting signal, the pulse number signal, and the clock pulse, and forms the high-frequency pulse based on these signals, The output parameter determination unit determines the oscillation frequency and the number of pulses of the next cycle for canceling the phase difference of the previous cycle so that the phase is fixed after the cycle time of the next cycle has elapsed.

2. The high-frequency power supply device according to claim 1, characterized in that The level setting signal includes a first level setting signal that specifies a first output level of the high-frequency pulse and a second level setting signal that specifies a second output level. The level setting signal generating section includes a first level setting signal generator that generates the first level setting signal and a second level setting signal generator that generates the second level setting signal.

3. The high-frequency power supply device according to claim 1 or 2, characterized in that: The oscillation frequency is composed of a reference intermediate frequency, a smaller frequency than the intermediate frequency, and a larger frequency than the intermediate frequency.

4. The high-frequency power supply device according to claim 1 or 2, characterized in that: The output parameter determination unit determines the oscillation frequency and the number of pulses so that the phase after the cycle time of the next cycle always matches the rising or falling timing of the synchronization pulse.

5. A method for controlling the output of a high-frequency power supply device, wherein the high-frequency power supply device outputs a high-frequency pulse to an object device based on a synchronization pulse and a clock pulse, characterized in that: The output control method comprises the following steps: generating an output level signal for setting the output level of the high-frequency pulse based on output level information included in the waveform of the synchronization pulse, and generating a period reference signal based on output timing information; generating a level setting signal according to the output level signal; detecting a period of one cycle of the synchronization pulse, and determining a phase difference between the synchronization pulse and the clock pulse at least one cycle before the high-frequency pulse; Calculating the oscillation frequency and the number of pulses of the high-frequency pulse of the next periodic oscillation according to the cycle time and the phase difference, and sending an oscillation frequency signal and a pulse number signal; as well as When the clock pulse is generated according to the oscillation frequency signal, and the period reference signal, the level setting signal, the pulse number signal and the clock pulse are received, and the high-frequency pulse is formed based on these signals, the oscillation frequency and the number of pulses of the next cycle for offsetting the phase difference of the previous cycle are determined so that the phase after the cycle time of the next cycle is fixed.

6. The output control method of a high-frequency power supply device according to claim 5, characterized in that: The level setting signal includes a first level setting signal that defines a first output level of the high-frequency pulse and a second level setting signal that defines a second output level.

7. The output control method of a high-frequency power supply device according to claim 5 or 6, characterized in that: The oscillation frequency is composed of a reference intermediate frequency, a smaller frequency than the intermediate frequency, and a larger frequency than the intermediate frequency.

8. The output control method of a high-frequency power supply device according to claim 5 or 6, characterized in that: The oscillation frequency and the number of pulses are determined so that the phase after the cycle time of the next cycle always coincides with the rising or falling timing of the synchronization pulse.

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