Semiconductor device and method of forming the same

Abstract

Various embodiments of the present disclosure relate to a semiconductor device and a method for forming the same. The semiconductor device includes a substrate. A cavity is disposed in the substrate. A microelectromechanical system (MEMS) layer is disposed on the substrate. The MEMS layer includes a movable diaphragm disposed on the cavity. The movable diaphragm includes a central region and a peripheral region. The movable diaphragm is flat in the central region of the movable diaphragm. The movable diaphragm is corrugated in the peripheral region of the movable diaphragm.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for forming the same. Background Art

[0002] Microelectromechanical system (MEMS) is a technology that integrates miniaturized mechanical and electromechanical components on an integrated chip. MEMS devices are often made using microfabrication techniques. In recent years, MEMS devices have gained a wide range of applications. For example, MEMS devices can be found in mobile phones (e.g., accelerometers, gyroscopes, digital compasses), speakers, microphones, pressure sensors, microfluidic components (e.g., valves, pumps), optical switches (e.g., mirrors), imaging devices (e.g., micromachined ultrasonic transducers (MUTs)), etc. Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, a cavity, and a micro-electromechanical system layer. The cavity is arranged in the substrate. The micro-electromechanical system layer is arranged on the substrate, wherein: the micro-electromechanical system layer comprises a movable membrane arranged on the cavity; the movable membrane comprises a central area and a peripheral area; the movable membrane is flat in the central area of ​​the movable membrane; and the movable membrane is corrugated in the peripheral area of ​​the movable membrane.

[0004] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, a cavity, and a micro-electromechanical system layer. The cavity is arranged in the substrate. The micro-electromechanical system layer is arranged on the substrate, wherein: the micro-electromechanical system layer comprises a movable membrane arranged on the cavity; the movable membrane has a flat portion and a corrugated portion; and the corrugated portion of the movable membrane surrounds the flat portion of the movable membrane in the lateral direction.

[0005] An embodiment of the present invention provides a method for forming a semiconductor device, the method comprising: forming a plurality of corrugated grooves in a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer lines the plurality of corrugated grooves; forming a micro-electromechanical system layer on the dielectric layer and in the plurality of corrugated grooves; forming a plurality of corrugated grooves in the micro-electromechanical system layer; forming a diaphragm opening in the micro-electromechanical system layer, wherein the diaphragm opening is formed such that the plurality of corrugated grooves and the plurality of corrugated grooves are arranged between the diaphragm openings; and forming a cavity in the substrate, wherein the cavity is formed such that the diaphragm opening is arranged between the side walls of the cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of semiconductor devices with improved signal distortion are shown.

[0008] Figure 2 Show Figure 1 An enlarged cross-sectional view of some embodiments of a movable diaphragm of a semiconductor device is shown.

[0009] Figure 3 Show Figure 1 Cross-sectional views of some other embodiments of semiconductor devices are shown.

[0010] Figure 4 Show Figure 1 Simplified layout diagrams of some embodiments of semiconductor devices are shown.

[0011] Figure 5 Show Figure 1 Simplified layout diagrams of some embodiments of semiconductor devices are shown.

[0012] Figure 6 Show Figure 1 Cross-sectional views of some other embodiments of a movable membrane of a semiconductor device are shown.

[0013] Figures 7 to 18 A series of cross-sectional views illustrating some embodiments of methods of forming a semiconductor device having improved signal distortion.

[0014] Fig.19 A flow chart illustrating some embodiments of a method of forming a semiconductor device having improved signal distortion. DETAILED DESCRIPTION

[0015] The present disclosure will now be described with reference to the drawings, wherein the same reference numerals are used to refer to the same elements throughout the drawings, and wherein the structures shown are not necessarily drawn to scale. It should be understood that this detailed description and the corresponding drawings do not limit the scope of the present disclosure in any way, and the detailed description and the drawings only provide several examples to illustrate some ways in which the concepts of the present invention can be expressed.

[0016] The present disclosure provides many different embodiments or examples for implementing the different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0018] In some embodiments, the integrated chip includes a microelectromechanical system (MEMS) device (e.g., a MEMS speaker). The MEMS speaker includes a substrate and a MEMS layer disposed on the substrate. A cavity is disposed in the substrate. The MEMS layer includes a movable diaphragm overlying the cavity. Typically, the movable diaphragm is a flat movable diaphragm (e.g., the movable diaphragm is flat across the entire movable diaphragm). An actuator (e.g., a piezoelectric device) is configured to move the movable diaphragm in response to an electrical signal, thereby causing the MEMS speaker to output a certain range of sound (e.g., between about 20 hertz (Hz) and about 20,000 Hz). For example, for a MEMS speaker that outputs the range of sound, the actuator applies force to the flat movable diaphragm at different frequencies, thereby causing the flat movable diaphragm to oscillate at corresponding frequencies.

[0019] One challenge faced by MEMS speakers is signal distortion (e.g., audio distortion). A flat movable diaphragm is a source of audio distortion (e.g., distortion of the sound output by the MEMS speaker). The flat movable diaphragm causes audio distortion (e.g., non-flat frequency response) due to resonance distortion in the high frequency range (e.g., between about 1,000 Hz and about 20,000 Hz) caused by the shape of the flat movable diaphragm. For example, in order for a MEMS speaker to output sound in that range at a given output level (e.g., 65 dB), the applied force needs to oscillate the flat movable diaphragm with the same amplitude across the corresponding frequencies. In other words, if the applied force causes the flat movable diaphragm to oscillate with different amplitudes across the corresponding frequencies, the MEMS speaker will undesirably output sound in that range at different output levels, resulting in audio distortion.

[0020] More specifically, when a specific sound (e.g., a sound in a high frequency range) is output, the actuator periodically provides a force to the flat movable diaphragm, which causes the flat movable diaphragm to oscillate at a specific frequency, thereby causing the MEMS speaker to output the specific sound. Due to the shape of the flat movable diaphragm, the specific frequency is equal to or close to the natural frequency of the flat movable diaphragm. Therefore, when an oscillating force is applied to the flat movable diaphragm at a specific frequency, the flat movable diaphragm will oscillate at a higher amplitude (e.g., due to constructive interference) than when the same force is applied to the flat movable diaphragm at other frequencies (e.g., frequencies below about 1,000 Hz). Therefore, due to the shape of the flat movable diaphragm, the MEMS speaker may have poor audio distortion (e.g., high audio distortion) in the high frequency range.

[0021] Various embodiments of the present application relate to a semiconductor device (e.g., a MEMS speaker) having improved (e.g., reduced) signal distortion (e.g., audio distortion). The semiconductor device includes a cavity disposed in a substrate. A MEMS layer is disposed on the substrate. The MEMS layer includes a movable diaphragm disposed on the cavity. The movable diaphragm includes a central region and a peripheral region. The movable diaphragm is flat in the central region of the movable diaphragm, and the movable diaphragm is corrugated in the peripheral region of the movable diaphragm.

[0022] The corrugated portion of the movable diaphragm acts as a damping element that reduces and / or limits the oscillation of the flat portion of the movable diaphragm. Since the corrugated portion of the movable diaphragm acts as a damping element, the corrugated portion of the movable diaphragm can reduce the variation in the amplitude of the flat portion of the movable diaphragm across the range of frequencies at which the flat movable diaphragm is driven (e.g., by an actuating device). Therefore, the semiconductor device (e.g., MEMS speaker) of the present application can improve (e.g., reduce) signal distortion (e.g., audio distortion) in a high frequency range (e.g., between about 1,000 Hz and about 20,000 Hz).

[0023] Figure 1 A cross-sectional view 100 of some embodiments of a semiconductor device 102 having improved signal distortion is shown.

[0024] like Figure 1 As shown in the cross-sectional view 100, a semiconductor device 102 (e.g., a microelectromechanical system (MEMS) device) includes a substrate 104. The substrate 104 includes any type of semiconductor body (e.g., a single crystal silicon / complementary metal oxide silicon (CMOS) block, germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), silicon on insulator (SOI), etc.). The substrate 104 can be doped (e.g., doped with n-type or p-type dopants) or undoped (e.g., intrinsic). In some embodiments, the substrate 104 can be referred to as a semiconductor substrate 104. The substrate 104 has a back side 104b and a front side 104f opposite to the back side 104b of the substrate 104.

[0025] A cavity 106 is disposed in the substrate 104. The cavity 106 extends from the back side 104b of the substrate 104 into the substrate 104. In some embodiments, the cavity 106 has angled sidewalls. In such embodiments, the angle between the sidewalls of the cavity 106 and the back side 104b of the substrate may be an obtuse angle or an acute angle. In other embodiments, the sidewalls of the cavity 106 may be substantially vertical (e.g., extending from the back side 104b of the substrate 104 at substantially right angles). In some embodiments, the sidewalls of the cavity 106 may be substantially straight. In other embodiments, the sidewalls of the cavity 106 may be rounded.

[0026] A micro-electromechanical system (MEMS) layer 108 is disposed on the front side 104f of the substrate 104. The MEMS layer 108 may be or include, for example, a semiconductor material (e.g., polycrystalline silicon, amorphous silicon, single crystal silicon, SiGe, Ge, etc.), a metal (e.g., aluminum (Al), copper (Cu), aluminum copper (AlCu)), an oxide (e.g., silicon dioxide (SiO 2 )), nitrides (e.g., silicon nitride (SiN)), oxynitrides (e.g., silicon oxynitride (SiO X N Y )), some other material suitable as a MEMS layer, or a combination of the foregoing materials. In some embodiments, the MEMS layer 108 is polysilicon.

[0027] In some embodiments, a first dielectric layer 110 is disposed between the MEMS layer 108 and the substrate 104. In other embodiments, the first dielectric layer 110 is omitted. The first dielectric layer 110 may be or include, for example, an oxide (e.g., SiO 2 ), nitrides (such as SiN), oxynitrides (such as SiO X N Y ), some other dielectric material, or a combination of the foregoing materials. In some embodiments, the first dielectric layer 110 is silicon dioxide (SiO 2 ).

[0028] The MEMS layer 108 includes a movable diaphragm 112. The movable diaphragm 112 includes a flat portion 114 of the MEMS layer 108 and a corrugated portion 116 of the MEMS layer 108. The flat portion 114 of the MEMS layer 108 is disposed in a central region 118 of the movable diaphragm 112. In some embodiments, the flat portion 114 of the MEMS layer 108 is referred to as the flat portion 114 of the movable diaphragm 112 (e.g., because the movable diaphragm 112 includes the flat portion 114 of the MEMS layer 108).

[0029] The corrugated portion 116 of the MEMS layer 108 is disposed in a peripheral region 120 of the movable diaphragm 112. In some embodiments, the corrugated portion 116 of the MEMS layer 108 is referred to as the corrugated portion 116 of the movable diaphragm 112 (e.g., because the movable diaphragm 112 includes the corrugated portion 116 of the MEMS layer 108). In some embodiments, the peripheral region 120 of the movable diaphragm 112 laterally surrounds the central region 118 of the movable diaphragm 112. In such embodiments, the peripheral region 120 of the movable diaphragm 112 may extend laterally around the central region 118 of the movable diaphragm 112 in a closed loop path. In other embodiments, the peripheral region 120 of the movable diaphragm 112 includes a first portion and a second portion disposed on opposite sides of the central region 118 of the movable diaphragm 112.

[0030] In some embodiments, the flat portion 114 of the MEMS layer 108 defines a central region 118 of the movable diaphragm 112. In other words, the boundaries of the flat portion 114 of the MEMS layer 108 define the boundaries of the central region 118 of the movable diaphragm 112. In still other embodiments, the corrugated portion 116 of the MEMS layer 108 defines a peripheral region 120 of the movable diaphragm 112. In other words, the boundaries of the corrugated portion 116 of the MEMS layer 108 define the boundaries of the peripheral region 120 of the movable diaphragm 112. For example, in an embodiment in which the flat portion 114 of the MEMS layer 108 defines a central region 118 of the movable diaphragm 112, the corrugated portion 116 of the MEMS layer 108 defines a peripheral region 120 of the movable diaphragm 112, and the peripheral region 120 of the movable diaphragm 112 laterally surrounds the central region 118 of the movable diaphragm 112, the corrugated portion 116 of the MEMS layer 108 laterally surrounds the flat portion 114 of the MEMS layer 108.

[0031] The flat portion 114 of the MEMS layer 108 has an upper surface and a bottom surface. Both the upper surface and the bottom surface of the flat portion 114 of the MEMS layer 108 extend continuously between opposite sides of the corrugated portion 116 of the MEMS layer 108. In some embodiments, the bottom surface and the upper surface of the flat portion 114 of the MEMS layer 108 are substantially flat.

[0032] In some embodiments, the inner boundary of the corrugated portion 116 of the MEMS layer 108 is defined by a point where the bottom surface 126 of the MEMS layer 108 extends at an angle from the bottom surface of the flat portion 114 of the MEMS layer 108. In other words, the point where the bottom surface 126 of the MEMS layer 108 extends at an angle from the bottom surface of the flat portion 114 of the MEMS layer 108 defines the point where the flat portion 114 of the MEMS layer 108 ends and the corrugated portion 116 of the MEMS layer 108 begins. In some embodiments, the bottom surface 126 of the MEMS layer 108 is beveled, such as Figure 1 100. In other embodiments, the bottom surface 126 of the MEMS layer 108 is substantially vertical. In some embodiments, the bottom surface 126 of the MEMS layer 108 is referred to as the bottom surface 126 of the movable diaphragm 112.

[0033] The corrugated portion 116 of the MEMS layer 108 includes one or more ridges 122 and one or more grooves 124. For example, the corrugated portion 116 of the MEMS layer 108 includes a first ridge 122a, a second ridge 122b, a third ridge 122c, a first groove 124a, and a second groove 124b. The one or more ridges 122 and the one or more grooves 124 alternate from the flat portion 114 of the MEMS layer 108 to the first outer sidewall 128 of the movable diaphragm 112. For example, the first ridge 122a is disposed closest to the flat portion 114 of the MEMS layer 108, the third ridge 122c is disposed closest to the first outer side wall 128 of the movable diaphragm 112, the second ridge 122b is disposed between the first ridge 122a and the third ridge 122c, the first groove 124a is disposed between the first ridge 122a and the second ridge 122b (e.g., directly between the first ridge 122a and the second ridge 122b), and the second groove 124b is disposed between the second ridge 122b and the third ridge 122c (e.g., directly between the second ridge 122b and the third ridge 122c).

[0034] In some embodiments, a second dielectric layer 130 is disposed on the MEMS layer 108. The second dielectric layer 130 may be or include, for example, an oxide (e.g., SiO 2 ), nitrides (such as SiN), oxynitrides (such as SiO X N Y ), some other dielectric material, or a combination of the foregoing materials. In some embodiments, the second dielectric layer 130 is silicon dioxide (SiO 2 In some other embodiments, the first dielectric layer 110 and the second dielectric layer 130 include the same material (eg, SiO 2 ).

[0035] One or more actuators 132 are disposed on the MEMS layer 108. The actuator 132 is configured to move the movable diaphragm 112 in response to receiving an electrical signal. More specifically, in some embodiments, the semiconductor device 102 is a MEMS speaker. In such an embodiment, the actuator 132 is configured to move the movable diaphragm in response to receiving an electrical signal, so that the movable diaphragm 112 outputs a sound wave (e.g., sound). In other words, the actuator 132 is configured to move the movable diaphragm 112 in response to receiving an electrical signal, so that the semiconductor device 102 outputs a certain range of sound (e.g., between about 20 Hertz (Hz) and about 20,000 Hz). For example, in order to make the semiconductor device 102 output a certain range of sound, the actuator 132 applies force to the movable diaphragm 112 at different frequencies, so that the movable diaphragm 112 oscillates at the corresponding frequencies.

[0036] The corrugated portion 116 of the MEMS layer 108 acts as a damping element that reduces and / or limits the oscillation of the flat portion 114 of the MEMS layer 108. Since the corrugated portion 116 of the MEMS layer 108 acts as a damping element, the corrugated portion 116 of the MEMS layer 108 can reduce the variation of the amplitude of the flat portion 114 of the MEMS layer 108 across the range of frequencies at which the movable diaphragm 112 is driven (e.g., by the actuator 132). Therefore, since the semiconductor device 102 (e.g., a MEMS speaker) includes the movable diaphragm 112, the semiconductor device 102 can have good signal distortion (e.g., low audio distortion) in a high frequency range (e.g., between about 1,000 Hz and about 20,000 Hz).

[0037] In some embodiments, the actuator 132 is a piezoelectric actuator, such as Figure 1 100. In this embodiment, the actuator 132 includes a lower electrode 134, a piezoelectric structure 136 overlying the lower electrode 134, and an upper electrode 138 overlying the piezoelectric structure 136. The lower electrode 134 can be or include, for example, platinum (Pt), titanium (Ti), copper (Cu), gold (Au), aluminum (Al), zinc (Zn), tin (Sn), some other conductive material, or a combination of the foregoing materials. The piezoelectric structure 136 can include, for example, lead zirconate titanate (PZT), zinc oxide (ZnO), barium titanate (BaTiO 3 ), potassium niobate (KNbO 3 ), sodium-tungsten-oxide (Na 2 WO 3 ), barium-sodium-niobium-oxide (Ba 2 NeA 5 O 5 ), lead-potassium-niobium-oxide (Pb 2 Kb 5 O 15 ), lanthanum silicate (La 3 Ga 5 SiO 14 ), gallium phosphate (GaPO 4 ), lithium-niobium-oxide (LiNbO 3 ), lithium tantalate (LiTaO 3 ), some other piezoelectric material, or a combination of the foregoing materials. The upper electrode 138 can be or include, for example, platinum (Pt), titanium (Ti), copper (Cu), gold (Au), aluminum (Al), zinc (Zn), tin (Sn), some other conductive material, or a combination of the foregoing materials. In some embodiments, the lower electrode 134 and the upper electrode 138 include the same material (e.g., Pt). Although Figure 1The illustrated cross-sectional view 100 shows the actuator 132 as a piezoelectric actuator, but it is understood that the semiconductor device 102 may include other types of actuators (eg, electrostatic actuators, thermal actuators, magnetic actuators, etc.) configured to move the movable diaphragm 112 .

[0038] In some embodiments, the actuator 132 may laterally surround the movable diaphragm 112, such as Figure 1 As shown in the cross-sectional view 100 shown. In such an embodiment, the lower electrode 134, the piezoelectric structure 136 and / or the upper electrode 138 may surround the movable diaphragm 112 in the lateral direction. In some other embodiments, the actuator 132 has an annular layout (e.g., a rectangular annular shape, a square annular shape, a circular annular shape, an elliptical annular shape, etc.). In such an embodiment, the lower electrode 134, the piezoelectric structure 136 and / or the upper electrode 138 may have an annular layout. In some embodiments, the lower electrode 134 extends in a closed loop path in the lateral direction around the movable diaphragm 112. In some other embodiments, the upper electrode 138 extends in a closed loop path in the lateral direction around the movable diaphragm 112. In some other embodiments, the piezoelectric structure 136 extends in a closed loop path in the lateral direction around the movable diaphragm 112. In other embodiments, the piezoelectric structure 136 may include a plurality of discrete piezoelectric structures, and the plurality of discrete piezoelectric structures are arranged in the lateral direction around the movable diaphragm 112. In such an embodiment, the lower electrode 134 and the upper electrode 138 may contact each of the plurality of discrete piezoelectric structures and extend laterally around the movable diaphragm 112 in a closed loop path.

[0039] In some embodiments, the actuator 132 overlies a first portion of the MEMS layer 108 and a second portion of the MEMS layer 108. The first portion of the MEMS layer 108 overlies the substrate 104. The second portion of the MEMS layer 108 overlies the cavity 106 and is disposed between the movable diaphragm 112 and the first portion of the MEMS layer 108. As such, the first portion of the MEMS layer 108 is more rigid than the second portion of the MEMS layer 108. Therefore, by applying a voltage across the piezoelectric structure 136, the piezoelectric structure 136 can be deflected, thereby causing the movable diaphragm 112 to move (e.g., oscillate). In some embodiments, the first portion of the MEMS layer 108 may be referred to as a “fixed” portion of the MEMS layer 108 (e.g., because the first portion of the MEMS layer 108 is relatively inflexible), and the second portion of the MEMS layer 108 may be referred to as a “flexible” portion of the MEMS layer 108 (e.g., because the second portion of the MEMS layer 108 is capable of being moved (e.g., bent) by the actuator 132).

[0040] Figure 2 Show Figure 1 An enlarged cross-sectional view 200 of some embodiments of the movable diaphragm 112 of the semiconductor device 102 is shown.

[0041] like Figure 2 As shown in the cross-sectional view 200 of FIG. 1 , the flat portion 114 of the MEMS layer 108 has a first width 202. In some embodiments, the first width 202 is between about 5 millimeters (mm) and about 20 mm. The flat portion 114 of the MEMS layer 108 has a thickness 204. The thickness 204 of the flat portion 114 of the MEMS layer 108 may be between about 3 micrometers (μm) and about 8 μm. The corrugated portion 116 of the MEMS layer 108 has a second width 206. In some embodiments, the second width 206 is between about 1.5 μm and about 5 μm. In some embodiments, the ratio of the first width 202 to the second width 206 is between 20000:1.5 and 1000:1. In some embodiments, if the ratio of the first width 202 to the second width 206 is greater than 20000:1.5, the corrugated portion 116 of the MEMS layer 108 may not sufficiently reduce and / or limit (e.g., suppress) the oscillation of the flat portion 114 of the MEMS layer 108, so that the semiconductor device 102 has poor signal distortion (e.g., high audio distortion) in the high frequency range. In still other embodiments, if the ratio of the first width 202 to the second width 206 is less than 1000:1, the output level (e.g., decibel (dB) level) of the semiconductor device 102 (e.g., a MEMS speaker) may be less than a predetermined threshold level.

[0042] The one or more grooves 124 have a first depth 208. The first depth 208 of the one or more grooves 124 may be between about 0.3 μm and about 1 μm. In some embodiments, the ratio of the first depth 208 to the thickness 204 of the flat portion 114 of the MEMS layer 108 may be between about 8:0.3 and 3:1. In some embodiments, if the ratio of the first depth 208 to the thickness 204 of the flat portion 114 of the MEMS layer 108 is greater than 8:0.3, the corrugated portion 116 of the MEMS layer 108 may not be able to sufficiently suppress the oscillation of the flat portion 114 of the MEMS layer 108, so that the semiconductor device 102 has poor signal distortion in the high frequency range. In some other embodiments, if the ratio of the first depth 208 to the thickness 204 of the flat portion 114 of the MEMS layer 108 is less than 3:1, the output level of the semiconductor device 102 may be less than a predetermined threshold level.

[0043] The one or more grooves 124 have a third width 210. In some embodiments, the third width 210 is between about 1.5 μm and about 5 μm. In some embodiments, if the third width 210 is less than about 1.5 μm, the corrugated portion 116 of the MEMS layer 108 may not be able to sufficiently suppress the oscillation of the flat portion 114 of the MEMS layer 108, so that the semiconductor device 102 has poor signal distortion in the high frequency range. In yet other embodiments, if the third width 210 is greater than about 5 μm, the output level of the semiconductor device 102 may be less than a predetermined threshold level.

[0044] The corrugated portion 116 of the MEMS layer 108 may include between 1 and approximately 10 grooves 124. The corrugated portion 116 of the MEMS layer 108 may include between 1 and approximately 11 ridges 122. In some embodiments, if the corrugated portion 116 of the MEMS layer 108 includes less than one groove 124 and / or less than one ridge 122, the corrugated portion 116 of the MEMS layer 108 may not be able to adequately suppress the oscillation of the flat portion 114 of the MEMS layer 108. In yet other embodiments, if the corrugated portion 116 of the MEMS layer 108 includes more than approximately ten grooves 124 and / or more than approximately eleven ridges 122, the output level of the semiconductor device 102 may be less than a predetermined threshold level.

[0045] In some embodiments, the sidewalls of the one or more grooves 124 are beveled, such as Figure 2 200. In other embodiments, the sidewalls of the one or more grooves 124 may be substantially vertical. More specifically, in some embodiments, the sidewalls of the grooves 124 may extend from the upper surface of the corresponding ridge 122 at an angle α between about 45 degrees and 90 degrees. In some embodiments, the first outer sidewall 128 of the movable diaphragm 112 is substantially vertical, such as Figure 2 200. In other embodiments, the first outer sidewall 128 of the movable diaphragm 112 may be beveled.

[0046] In some embodiments, the bottom surface of the one or more grooves 124 is substantially flat. Figure 2 200. In other embodiments, the bottom surface of the one or more grooves 124 may be rounded. In still other embodiments, the bottom surface of the one or more grooves 124 may be disposed vertically between the upper surface of the flat portion 114 of the MEMS layer 108 and the bottom surface of the flat portion 114 of the MEMS layer 108. In some embodiments, the upper surface of the one or more ridges 122 is substantially flat, such as Figure 2 As shown in the cross-sectional view 200 of FIG. In other embodiments, the upper surface of the one or more ridges 122 may be rounded.

[0047] Figure 3 Show Figure 1 A cross-sectional view 300 of some other embodiments of the semiconductor device 102 is shown.

[0048] like Figure 3 As shown in the cross-sectional view 300 of , the piezoelectric structure 136 is disposed vertically between the lower electrode 134 and the upper electrode 138. In some embodiments, the opposite sidewalls of the piezoelectric structure 136 are disposed laterally between the opposite sidewalls of the lower electrode 134. In yet other embodiments, the opposite sidewalls of the upper electrode 138 are disposed laterally between the opposite sidewalls of the piezoelectric structure 136.

[0049] A first passivation layer 302 is disposed over the MEMS layer 108 and the one or more actuators 132. The first passivation layer 302 may be or include, for example, an oxide (e.g., SiO 2 ), nitrides (such as SiN), oxynitrides (such as SiO X N Y ), titanium nitride (TiN), aluminum oxide (Al 2 O 3 ), some other protective material, or a combination of the foregoing materials. In some embodiments, the first passivation layer 302 lines the second dielectric layer 130, the lower electrode 134, the piezoelectric structure 136, and the upper electrode 138. In some embodiments, the sidewalls of the first passivation layer 302 are laterally disposed between the lower electrode 134 and the movable diaphragm 112. In yet other embodiments, the sidewalls of the first passivation layer 302 are substantially aligned with the sidewalls of the second dielectric layer 130 and / or the sidewalls of the MEMS layer 108.

[0050] A third dielectric layer 304 is disposed above the MEMS layer 108 and the one or more actuators 132. The third dielectric layer 304 may be or include, for example, an oxide (e.g., SiO 2 ), nitrides (such as SiN), oxynitrides (such as SiO X N Y ), some other dielectric material, or a combination of the foregoing materials. In some embodiments, the third dielectric layer 304 is silicon dioxide (SiO 2 In some other embodiments, the third dielectric layer 304, the first dielectric layer 110 and / or the second dielectric layer 130 include the same material (eg, SiO 2 ).

[0051] In some embodiments, the third dielectric layer 304 is disposed over the first passivation layer 302. In yet other embodiments, the third dielectric layer 304 lines the first passivation layer 302. The sidewalls of the third dielectric layer 304 may be disposed laterally between the lower electrode 134 and the movable diaphragm 112. In some embodiments, the sidewalls of the third dielectric layer 304 are substantially aligned with the sidewalls of the first passivation layer 302, the sidewalls of the second dielectric layer 130, and / or the sidewalls of the MEMS layer 108.

[0052] A first conductive structure 306 is disposed over the MEMS layer 108 and the second dielectric layer 130. In some embodiments, the first conductive structure 306 is disposed over the first passivation layer 302 and / or the third dielectric layer 304. In still other embodiments, the first conductive structure 306 partially lines the third dielectric layer 304. The first conductive structure 306 may be or include, for example, aluminum copper (AlCu), copper (Cu), aluminum (Al), tungsten (W), gold (Au), silver (Ag), some other conductive material, or a combination of the foregoing materials.

[0053] The first conductive structure 306 is electrically coupled to the upper electrode 138. The first conductive structure 306 provides an electrical path from a first electronic device (not shown) (e.g., an insulated gate field-effect transistor (IGFET)) to the upper electrode 138. The first electronic device is configured to provide a first bias voltage to the upper electrode 138. In some embodiments, the first electronic device is disposed on / in the MEMS layer 108 (e.g., laterally spaced apart from the one or more actuator devices 132 and the movable diaphragm 112). In other embodiments, the first electronic device is disposed on a separate integrated chip (IC) different from the semiconductor device 102. In such embodiments, the separate IC may be bonded to an IC including the semiconductor device 102 such that the first electronic device is electrically coupled to the first conductive structure 306. In other such embodiments, the separate IC and the IC including the semiconductor device 102 may be electrically coupled via one or more input / output (I / O) structures (e.g., bonding pads, solder bumps, etc.).

[0054] A second conductive structure 308 is disposed over the MEMS layer 108 and the second dielectric layer 130. In some embodiments, the second conductive structure 308 is disposed over the first passivation layer 302 and / or the third dielectric layer 304. In still other embodiments, the second conductive structure 308 partially lines the third dielectric layer 304. The second conductive structure 308 may be or include, for example, aluminum copper (AlCu), copper (Cu), aluminum (Al), tungsten (W), gold (Au), silver (Ag), some other conductive material, or a combination of the foregoing materials. In some embodiments, the first conductive structure 306 and the second conductive structure 308 include the same material (e.g., AlCu).

[0055] The second conductive structure 308 is electrically coupled to the lower electrode 134. The second conductive structure 308 provides an electrical path from a second electronic device (not shown) (e.g., an IGFET) to the lower electrode 134. The second electronic device is configured to provide a second bias voltage to the lower electrode 134. In some embodiments, the second electronic device is disposed on / in the MEMS layer 108 (e.g., laterally spaced apart from the one or more actuators 132 and the movable diaphragm 112). In other embodiments, the second electronic device is disposed on a separate IC. In such an embodiment, the separate IC may be bonded to an IC including the semiconductor device 102 such that the second electronic device is electrically coupled to the second conductive structure 308 and the first electronic device is electrically coupled to the first conductive structure 306. Since the first electronic device is configured to provide a first bias voltage to the upper electrode 138 and the second electronic device is configured to provide a second bias voltage to the lower electrode 134, a voltage may be selectively applied across the piezoelectric structure 136. Thus, by applying a voltage across the piezoelectric structure 136, the piezoelectric structure 136 may be deflected, thereby selectively causing the movable diaphragm 112 to move (eg, oscillate) at different frequencies.

[0056] A second passivation layer 310 is disposed over the MEMS layer 108, the one or more actuators 132, the first conductive structure 306, the second conductive structure 308, and the movable diaphragm 112. The second passivation layer 310 may be or include, for example, a nitride (e.g., SiN), an oxide (e.g., SiO 2 ), nitrogen oxides (e.g., SiO X N Y ), some other passivation material, or a combination of the foregoing materials. In some embodiments, the second passivation layer 310 is silicon nitride (SiN). In yet other embodiments, the second passivation layer 310 comprises a material different from the first passivation layer 302, the third dielectric layer 304, the second dielectric layer 130, and / or the first dielectric layer 110.

[0057] In some embodiments, the second passivation layer 310 lines the first conductive structure 306, the second conductive structure 308, the third dielectric layer 304, and the movable diaphragm 112. More specifically, the second passivation layer 310 lines the corrugated portion 116 (e.g., the one or more grooves 124 and the one or more ridges 122) of the MEMS layer 108 and the flat portion 114 of the MEMS layer 108. The second passivation layer 310 also bridges one or more gaps disposed between the movable diaphragm 112 and other portions of the MEMS layer 108 (e.g., portions of the MEMS layer 108 attached to the substrate 104). In some embodiments, since the second passivation layer 310 bridges the one or more gaps disposed between the movable diaphragm 112 and the other portions of the MEMS layer 108, the second passivation layer 310 may at least partially support the movable diaphragm 112, so that the movable diaphragm 112 is suspended above the cavity 106 (e.g., suspended directly above the cavity 106). In yet other embodiments, one or more tethers (not shown) (e.g., tether portions of the MEMS layer 108) may at least partially support the movable diaphragm 112 such that the movable diaphragm 112 is suspended above (e.g., directly above) the cavity 106. In yet other embodiments, the second passivation layer 310 contacts (e.g., directly contacts) the first conductive structure 306, the second conductive structure 308, the third dielectric layer 304, the first passivation layer 302, the second dielectric layer 130, the other portions of the MEMS layer 108, and the movable diaphragm 112.

[0058] Figure 4 Show Figure 1 A simplified layout diagram 400 of some embodiments of the semiconductor device 102 is shown. Figure 4 The simplified layout diagram 400 is "simplified" because Figure 4 The simplified layout diagram 400 shown only shows the piezoelectric structure 136 and the movable diaphragm 112 .

[0059] like Figure 4 As shown in the simplified layout diagram 400 of FIG. 4 , the peripheral region 120 of the movable membrane 112 has a first portion 120a of the peripheral region 120 and a second portion 120b of the peripheral region 120. The first portion 120a of the peripheral region 120 and the second portion 120b of the peripheral region 120 are disposed on opposite sides of the central region 118 of the movable membrane 112.

[0060] The first outer sidewalls 128 of the movable diaphragm 112 are opposite to each other and spaced apart in the first direction. In some embodiments, the movable diaphragm 112 includes a second outer sidewall 402. The second outer sidewalls 402 of the movable diaphragm 112 are opposite to each other and spaced apart in a second direction substantially perpendicular to the first direction. In some embodiments, the first portion 120a of the peripheral region 120, the second portion 120b of the peripheral region 120, and the central region 118 of the movable diaphragm 112 extend continuously between the second outer sidewall 402 of the movable diaphragm 112. In such embodiments, the central region 118 separates the first portion 120a of the peripheral region 120 from the second portion 120b of the peripheral region 120 laterally. In yet other embodiments, the first portion 120a of the peripheral region 120 extends laterally (e.g., in the first direction) from the central region 118 of the movable diaphragm 112 to one of the first outer sidewalls 128 of the movable diaphragm 112. In still other embodiments, the second portion 120 b of the peripheral region 120 extends laterally from the central region 118 of the movable diaphragm 112 to the other of the first outer sidewalls 128 of the movable diaphragm 112 .

[0061] In some embodiments, the corrugated portion 116 of the MEMS layer 108 includes a first section 116a of the corrugated portion 116 and a second section 116b of the corrugated portion 116. The first section 116a of the corrugated portion 116 is disposed in a first portion 120a of the peripheral region 120. The second section 116b of the corrugated portion 116 is disposed in a second portion 120b of the peripheral region 120. In some embodiments, the flat portion 114 of the MEMS layer 108 defines a central region 118 of the movable diaphragm 112, such as Figure 4 In some other embodiments, the corrugated portion 116 defines the peripheral region 120 of the movable diaphragm 112, such as Figure 4 As shown in the simplified layout diagram 400. More specifically, as Figure 4 As shown in the simplified layout diagram 400 of FIG. 4 , the first section 116 a of the corrugated portion 116 may define a first portion 120 a of the peripheral region 120 , and the second section 116 b of the corrugated portion 116 may define a second portion 120 b of the peripheral region 120 .

[0062] The first section 116a of the corrugated portion 116 includes a first set of one or more ridges 122 and one or more grooves 124. For example, the first section 116a of the corrugated portion 116 includes a first ridge 122a, a second ridge 122b, a third ridge 122c, a first groove 124a, and a second groove 124b. The first set of one or more ridges 122 and one or more grooves 124 alternate from the flat portion 114 of the MEMS layer 108 to one of the first outer sidewalls 128 of the movable diaphragm 112.

[0063] The second section 116b of the corrugated portion 116 includes a second set of one or more ridges 122 and one or more grooves 124. For example, the second section 116b of the corrugated portion 116 includes a fourth ridge 122d, a fifth ridge 122e, a sixth ridge 122f, a third groove 124c, and a fourth groove 124d. The one or more ridges 122 and the one or more grooves 124 of the second set alternate from the flat portion 114 of the MEMS layer 108 to the other of the first outer sidewall 128 of the movable diaphragm 112.

[0064] In some embodiments, one or more slots 404 are provided in the piezoelectric structure 136. The one or more slots 404 extend from one or more inner sidewalls of the piezoelectric structure 136 toward one or more outer sidewalls of the piezoelectric structure 136. Figure 4 As shown in the simplified layout diagram 400 of FIG. 1 , the one or more slots 404 include a first slot 404a and a second slot 404b. The first slot 404a and the second slot 404b extend from a first inner sidewall of the piezoelectric structure 136. The first slot 404a also extends from a second inner sidewall of the piezoelectric structure 136. The second slot 404b also extends from a third inner sidewall of the piezoelectric structure 136, and the third inner sidewall is opposite to the second inner sidewall of the piezoelectric structure 136.

[0065] In some embodiments, the one or more slots 404 extend from corresponding inner sidewalls of the piezoelectric structure 136 at substantially similar angles. Figure 4 As shown in the simplified layout diagram 400 of FIG. 1 , the first slot 404a extends from the first inner sidewall of the piezoelectric structure 136 at a first angle and extends from the second inner sidewall of the piezoelectric structure 136 at a second angle. The second slot 404b also extends from the first inner sidewall of the piezoelectric structure 136 at a first angle and extends from the third inner sidewall of the piezoelectric structure 136 at a second angle. In some embodiments, the first angle is substantially the same as the second angle (e.g., 45 degrees). In other embodiments, the first angle is different from the second angle.

[0066] Figure 5 Show Figure 1 A simplified layout diagram 500 of some embodiments of the semiconductor device 102 is shown. Figure 5 The simplified layout diagram 500 is "simplified" because Figure 5 The simplified layout diagram 500 shown only shows the piezoelectric structure 136 and the movable diaphragm 112 .

[0067] like Figure 5As shown in the simplified layout diagram 500 of FIG. 5 , the peripheral region 120 of the movable diaphragm 112 extends laterally around the central region 118 of the movable diaphragm 112 in a closed-loop path. In some embodiments, the peripheral region 120 of the movable diaphragm 112 also extends continuously from the central region 118 of the movable diaphragm 112 to both the first outer sidewall 128 and the second outer sidewall 402. The corrugated portion 116 of the MEMS layer 108 may extend laterally around the flat portion 114 of the MEMS layer 108 in a closed-loop path. In some embodiments, the corrugated portion 116 of the MEMS layer 108 also extends continuously from the flat portion 114 of the MEMS layer 108 to both the first outer sidewall 128 and the second outer sidewall 402. In yet other embodiments, the corrugated portion 116 of the MEMS layer 108 defines the peripheral region 120 of the movable diaphragm 112, as shown in FIG. Figure 5 A simplified layout diagram 500 is shown.

[0068] In some embodiments, the one or more grooves 124 extend laterally around the central region 118 of the movable diaphragm 112 in a closed-loop path, respectively. In such embodiments, the plurality of grooves 124 may be concentric. In still other embodiments, the one or more ridges 122 extend laterally around the central region 118 of the movable diaphragm 112 in a closed-loop path, respectively. In such embodiments, the plurality of ridges 122 may be concentric. Since the one or more grooves 124 and the one or more ridges 122 extend laterally around the central region 118 of the movable diaphragm 112 in a closed-loop path, the semiconductor device 102 may have even better signal distortion (e.g., even lower audio distortion) in a high frequency range (e.g., since the one or more grooves 124 and the one or more ridges 122 reduce stress along both the first axis and the second axis perpendicular to the first axis).

[0069] Figure 6 Show Figure 1 A cross-sectional view 600 of some other embodiments of the movable diaphragm 112 of the semiconductor device 102 is shown.

[0070] like Figure 6 As shown in the cross-sectional view 600 of FIG. 6 , the inner boundary of the corrugated portion 116 that is not the MEMS layer 108 is defined by the point where the bottom surface 126 of the MEMS layer 108 extends at an angle from the bottom surface of the flat portion 114 of the MEMS layer 108 (see, e.g., Figure 1), but rather the inner boundary of the corrugated portion 116 of the MEMS layer 108 is defined by a point where the sidewall of one of the grooves 124 extends at an angle from the upper surface of the flat portion 114 of the MEMS layer 108. In other words, the point where the sidewall of the one of the grooves 124 extends at an angle from the upper surface of the flat portion 114 of the MEMS layer 108 defines a point where the flat portion 114 of the MEMS layer 108 ends and the corrugated portion 116 of the MEMS layer 108 begins. For example, the first groove 124a is disposed closer to the flat portion 114 of the MEMS layer 108 than each of the other grooves 124 and each of the ridges 122. The first groove 124a includes a sidewall 602. The point where the sidewall 602 of the first groove 124a extends at an angle from the upper surface of the flat portion 114 of the MEMS layer 108 defines the point where the flat portion 114 of the MEMS layer 108 ends and the corrugated portion 116 of the MEMS layer 108 begins.

[0071] In some embodiments, one or more of the ridges 122 may refer to a peak where two side walls of the movable diaphragm 112 meet, such as Figure 6 600 of . For example, the corrugated portion 116 of the MEMS layer 108 includes a first groove 124a, a second groove 124b, a second ridge 122b, and a third ridge 122c. The first groove 124a and the second groove 124b each have an angled sidewall that meets at a first peak. In such an embodiment, the second ridge 122b may refer to the first peak. In addition, the angled sidewall of the second groove 124b may meet the first outer sidewall 128 of the movable diaphragm 112 at the second peak. In such an embodiment, the third ridge 122c may refer to the second peak. It should be understood that in some embodiments, some of the ridges 122 of the corrugated portion 116 of the MEMS layer 108 may refer to peaks and some other of the ridges 122 of the corrugated portion 116 of the MEMS layer 108 may refer to substantially flat (or rounded) upper surfaces.

[0072] Figures 7 to 18 A series of cross-sectional views 700 through 1800 illustrate some embodiments of a method of forming a semiconductor device 102 with improved signal distortion. Figures 7 to 18 This is an explanation of one method, but it should be understood that Figures 7 to 18 The structures shown in are not limited to the methods described but can be used independently of the methods described.

[0073] like Figure 7 As shown in the cross-sectional view 700 of FIG. 1 , a plurality of corrugated grooves 702 are formed in the substrate 104. The corrugated grooves 702 extend from the front side 104f of the substrate 104 into the substrate 104. The corrugated grooves 702 may have angled sidewalls, such as Figure 7As shown in the cross-sectional view 700 of FIG. 702 . In other embodiments, the sidewalls of the corrugated groove 702 may be substantially vertical. In some embodiments, the corrugated groove 702 may have a substantially flat bottom surface, such as Figure 7 As shown in the cross-sectional view 700 of FIG. In other embodiments, the bottom surface of the corrugated groove 702 may be rounded. In some embodiments, the plurality of corrugated grooves 702 may include between 1 and 10 individual corrugated grooves.

[0074] In some embodiments, the process of forming the plurality of corrugated grooves 702 includes forming a patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) on the front side 104f of the substrate 104. The patterned masking layer may be formed by forming a masking layer (not shown) on the front side 104f of the substrate 104 (e.g., by a spin coating process); exposing the masking layer to a pattern (e.g., by a photolithography process, such as optical lithography, extreme ultraviolet lithography, etc.); and developing the masking layer to form a patterned masking layer. Thereafter, with the patterned masking layer in place, an etching process is performed on the substrate 104 to selectively etch the substrate 104 according to the patterned masking layer. The etching process removes unmasked portions of the substrate 104, thereby forming the plurality of corrugated grooves 702. In some embodiments, the etching process may be, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, some other etching processes, or a combination of the foregoing processes.

[0075] like Figure 8 As shown in the cross-sectional view 800 of FIG. 1 , a first dielectric layer 110 is formed on the front side 104f of the substrate 104 and in the plurality of corrugated grooves 702. In some embodiments, the first dielectric layer 110 is formed on the front side 104f of the substrate 104 and lines the plurality of corrugated grooves 702. In some embodiments, the process of forming the first dielectric layer 110 includes depositing or growing a first dielectric material on the substrate 104, thereby forming the first dielectric layer 110. The first dielectric material may be or include, for example, an oxide (e.g., SiO 2 ), nitrides (such as SiN), oxynitrides (such as SiO X N Y ), some other dielectric material, or a combination of the foregoing materials. In some embodiments, the first dielectric material is silicon dioxide (SiO 2The first dielectric material may be deposited or grown by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, some other deposition or growth process, or a combination of the foregoing processes.

[0076] like Fig. 9 As shown in the cross-sectional view 900 of , a MEMS layer 108 is formed over the first dielectric layer 110 and the substrate 104. The MEMS layer 108 is formed to fill the plurality of corrugated grooves 702. The MEMS layer 108 includes a flat portion 114 and a corrugated portion 116. The flat portion 114 of the MEMS layer 108 has an upper surface and a bottom surface. Both the upper surface and the bottom surface of the flat portion 114 of the MEMS layer 108 extend continuously between opposite sides of the corrugated portion 116 of the MEMS layer 108. In some embodiments, the bottom surface and the upper surface of the flat portion 114 of the MEMS layer 108 are substantially flat.

[0077] In some embodiments, the corrugated portion 116 of the MEMS layer 108 laterally surrounds the flat portion 114 of the MEMS layer 108. In such embodiments, the corrugated portion 116 of the MEMS layer 108 may extend laterally around the flat portion 114 of the MEMS layer 108 in a closed loop path. In other embodiments, the corrugated portion 116 of the MEMS layer 108 includes a first segment and a second segment disposed on opposite sides of the flat portion 114 of the MEMS layer 108.

[0078] The corrugated portion 116 of the MEMS layer 108 includes one or more ridges 122 and one or more grooves 124. For example, the corrugated portion 116 of the MEMS layer 108 may include a first ridge 122a, a second ridge 122b, a third ridge 122c, a first groove 124a, and a second groove 124b. The one or more ridges 122 and the one or more grooves 124 alternate in a predetermined pattern (e.g., back and forth) throughout the corrugated portion 116 of the MEMS layer 108.

[0079] In some embodiments, the inner boundary of the corrugated portion 116 of the MEMS layer 108 is defined by a point where the bottom surface 126 of the MEMS layer 108 extends at an angle from the bottom surface of the flat portion 114 of the MEMS layer 108. In other words, the point where the bottom surface 126 of the MEMS layer 108 extends at an angle from the bottom surface of the flat portion 114 of the MEMS layer 108 defines the point where the flat portion 114 of the MEMS layer 108 ends and the corrugated portion 116 of the MEMS layer 108 begins. In some embodiments, the bottom surface 126 of the MEMS layer 108 is beveled, such as Fig. 9 900. In other embodiments, the bottom surface 126 of the MEMS layer 108 is substantially vertical.

[0080] In some embodiments, the process of forming the MEMS layer 108 includes depositing the MEMS layer 108 on the first dielectric layer 110 and in the plurality of corrugated grooves 702. The MEMS layer 108 may be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing processes. For example, in some embodiments, the MEMS layer 108 is polysilicon. In such an embodiment, polysilicon (e.g., by CVD) is deposited on the first dielectric layer 110 and fills the plurality of corrugated grooves 702, thereby forming the MEMS layer 108.

[0081] In some embodiments, MEMS layer 108 is deposited as a conformal layer, such as Fig. 9 900. In this embodiment, due to the plurality of corrugated grooves 702, the one or more ridges 122 and the one or more grooves 124 are formed during the deposition of the MEMS layer 108. In this way, the dimensions (e.g., depth, width, angle of the sidewalls, etc.) of the corrugated grooves 702 are such that the one or more ridges 122 and the one or more grooves 124 can be of a predetermined size (see, e.g., Figure 2 )form.

[0082] It should be understood that the one or more ridges 122 and the one or more grooves 124 may be formed by other techniques. For example, the MEMS layer 108 may be formed to have a flat upper surface and without the one or more ridges 122 or the one or more grooves 124 initially formed in the MEMS layer 108. A patterned masking layer may then be formed on the MEMS layer 108. Thereafter, with the patterned masking layer in place, an etching process is performed on the MEMS layer 108 to selectively etch the MEMS layer 108 according to the patterned masking layer. The etching process removes the unmasked portions of the MEMS layer 108, thereby forming the one or more ridges 122 and the one or more grooves 124. In some embodiments, the etching process may be, for example, a wet etching process, a dry etching process, an RIE process, some other etching process, or a combination of the foregoing processes.

[0083] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , a second dielectric layer 130 is formed on the MEMS layer 108 and in the one or more grooves 124. In some embodiments, the second dielectric layer 130 is formed to have one or more divots 1002, and the one or more divots 1002 are respectively disposed on the one or more grooves 124 (for example, disposed directly above the one or more grooves 124). In some embodiments, the process of forming the second dielectric layer 130 includes depositing or growing a second dielectric material on the MEMS layer 108 and in the one or more grooves 124, thereby forming the second dielectric layer 130. The second dielectric material may be or include, for example, an oxide (for example, SiO 2 ), nitrides (such as SiN), oxynitrides (such as SiO X N Y ), some other dielectric material, or a combination of the foregoing materials. In some embodiments, the second dielectric material is silicon dioxide (SiO 2 The second dielectric material may be deposited or grown by, for example, CVD, PVD, ALD, thermal oxidation, some other deposition or growth process, or a combination of the foregoing processes.

[0084] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , a planarization process 1102 is performed on the second dielectric layer 130. The planarization process 1102 removes the upper portion of the second dielectric layer 130 (at Fig.11 The planarization process 1102 is shown by a dotted line in the cross-sectional view 1100 and planarizes the upper surface of the second dielectric layer 130. In some embodiments, the planarization process 1102 may be, for example, a chemical-mechanical polishing (CMP) process.

[0085] like Fig.12As shown in the cross-sectional view 1200 of FIG. 1 , one or more actuators 132 are formed on the second dielectric layer 130 and the MEMS layer 108. In some embodiments, the actuator 132 is a piezoelectric actuator, such as Fig.12 As shown in the cross-sectional view 1200 of FIG. 1200 , in this embodiment, the actuator 132 includes a lower electrode 134 , a piezoelectric structure 136 overlying the lower electrode 134 , and an upper electrode 138 overlying the piezoelectric structure 136 .

[0086] In some embodiments, the process of forming the actuator 132 includes forming a lower electrode 134 on the second dielectric layer 130. In some embodiments, the process of forming the lower electrode 134 includes depositing a first conductive layer (not shown) on the second dielectric layer 130. The first conductive layer may be or include, for example, platinum (Pt), titanium (Ti), copper (Cu), gold (Au), aluminum (Al), zinc (Zn), tin (Sn), some other conductive material, or a combination of the foregoing materials. The first conductive layer may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing processes. A first patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) is then formed on the first conductive layer. Thereafter, with the first patterned masking layer in place, a first etching process is performed on the first conductive layer to remove the unmasked portion of the first conductive layer, thereby forming the lower electrode 134. In some embodiments, the first etching process may be, for example, a wet etching process, a dry etching process, a RIE process, some other etching processes, or a combination of the foregoing processes. In yet other embodiments, the first patterned masking layer may be stripped.

[0087] Then, a piezoelectric structure 136 is formed on the lower electrode 134 and the second dielectric layer 130. In some embodiments, the process of forming the piezoelectric structure 136 includes depositing a piezoelectric layer (not shown) on the lower electrode 134 and the second dielectric layer 130. The piezoelectric layer may be or include, for example, lead zirconate titanate (PZT), zinc oxide (ZnO), barium titanate (BaTiO 3 ), potassium niobate (KNbO 3 ), sodium-tungsten-oxide (Na 2 WO 3 ), barium-sodium-niobium-oxide (Ba 2 NeA 5 O 5 ), lead-potassium-niobium-oxide (Pb 2 Kb 5 O 15 ), lanthanum silicate (La 3 Ga 5 SiO 14 ), gallium phosphate (GaPO 4), lithium-niobium-oxide (LiNbO 3 ), lithium tantalate (LiTaO 3 ), some other piezoelectric material, or a combination of the foregoing materials. The piezoelectric layer may be deposited by, for example, CVD, PVD, ALD, sputtering, a sol-gel process, some other deposition process, or a combination of the foregoing processes. A second patterned masking layer (not shown) (e.g., a positive / negative photoresist, a hard mask, etc.) is then formed on the piezoelectric layer. Thereafter, with the second patterned masking layer in place, a second etching process is performed on the piezoelectric layer to remove the unmasked portion of the piezoelectric layer, thereby forming a piezoelectric structure 136. In some embodiments, the second etching process may be, for example, a wet etching process, a dry etching process, an RIE process, some other etching process, or a combination of the foregoing processes. In yet other embodiments, the second patterned masking layer may be stripped.

[0088] Thereafter, an upper electrode 138 is formed over the piezoelectric structure 136, the lower electrode 134, and the second dielectric layer 130. In some embodiments, the process of forming the upper electrode 138 includes depositing a second conductive layer (not shown) over the piezoelectric structure 136, the lower electrode 134, and the second dielectric layer 130. The second conductive layer may be or include, for example, platinum (Pt), titanium (Ti), copper (Cu), gold (Au), aluminum (Al), zinc (Zn), tin (Sn), some other conductive material, or a combination of the foregoing materials. In some embodiments, the first conductive layer and the second conductive layer are the same material (e.g., Pt). The second conductive layer may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing processes. A third patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) is then formed over the second conductive layer. Thereafter, with the third patterned masking layer in place, a third etching process is performed on the second conductive layer to remove the unmasked portion of the second conductive layer, thereby forming the upper electrode 138. In some embodiments, the third etching process may be, for example, a wet etching process, a dry etching process, an RIE process, some other etching process, or a combination of the foregoing processes. In yet other embodiments, the third patterned masking layer may be stripped.

[0089] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a diaphragm opening 1302 is formed in the MEMS layer 108. The diaphragm opening 1302 extends through (e.g., completely through) the MEMS layer 108 and exposes portions of the first dielectric layer 110. In some embodiments, the diaphragm openings 1302 are discrete from one another (e.g., spaced apart from one another by portions of the MEMS layer 108). In other embodiments, the diaphragm openings 1302 are portions of a larger diaphragm opening that extends continuously through the MEMS layer 108 in a closed loop path.

[0090] The diaphragm openings 1302 are formed such that the corrugated portions 116 of the MEMS layer 108 and the flat portions 114 of the MEMS layer 108 are disposed between the diaphragm openings 1302. For example, in embodiments where the diaphragm openings 1302 are separate from one another, the diaphragm openings 1302 are formed such that the corrugated portions 116 of the MEMS layer 108 and the flat portions 114 of the MEMS layer 108 are disposed between opposing ones of the diaphragm openings 1302, or in embodiments where the diaphragm openings 1302 refer to portions of a larger diaphragm opening that continuously extends through the MEMS layer 108 in a closed-loop path, the diaphragm openings 1302 are formed such that the corrugated portions 116 of the MEMS layer 108 and the flat portions 114 of the MEMS layer 108 are disposed within the inner perimeter of the larger diaphragm opening.

[0091] In some embodiments, the process of forming the diaphragm opening 1302 includes forming a patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) over the second dielectric layer 130, the MEMS layer 108, the lower electrode 134, the piezoelectric structure 136, and the upper electrode 138. Thereafter, with the patterned masking layer in place, an etching process is performed on the second dielectric layer 130 and the MEMS layer 108 according to the patterned masking layer. The etching process removes the unmasked portion of the second dielectric layer 130 and the unmasked portion of the MEMS layer 108, thereby forming the diaphragm opening 1302. In some embodiments, the etching process stops at the first dielectric layer 110 (e.g., the first dielectric layer 110 acts as an etching stop layer). In yet other embodiments, the etching process may be, for example, a wet etching process, a dry etching process, an RIE process, some other etching process, or a combination of the foregoing processes.

[0092] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , a first passivation layer 302 is formed over the second dielectric layer 130, the lower electrode 134, the piezoelectric structure 136, and the upper electrode 138. In some embodiments, the first passivation layer 302 is formed to line the second dielectric layer 130, the lower electrode 134, the piezoelectric structure 136, and the upper electrode 138. In yet other embodiments, the first passivation layer 302 is formed to have sidewalls that are substantially aligned with sidewalls of the second dielectric layer 130 and / or sidewalls of the MEMS layer 108.

[0093] Likewise Fig.14As shown in the cross-sectional view 1400 of FIG. 1 , a third dielectric layer 304 is formed over the first passivation layer 302. In some embodiments, the third dielectric layer 304 is formed to line the first passivation layer 302. In yet other embodiments, the third dielectric layer 304 is formed to have sidewalls that are substantially aligned with sidewalls of the first passivation layer 302, sidewalls of the second dielectric layer 130, and / or sidewalls of the MEMS layer 108.

[0094] In some embodiments, the process of forming the first passivation layer 302 and the third dielectric layer 304 includes depositing the first passivation layer 302 on the second dielectric layer 130, the lower electrode 134, the piezoelectric structure 136, and the upper electrode 138. In some embodiments, the first passivation layer 302 is also deposited on the first dielectric layer 110 and / or in the diaphragm opening 1302. The first passivation layer 302 can be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing processes. Then, the third dielectric layer 304 is deposited on the first passivation layer 302. In some embodiments, the third dielectric layer 304 is also deposited in the diaphragm opening 1302. The third dielectric layer 304 can be deposited by, for example, CVD, PVD, ALD, some other deposition process, or a combination of the foregoing processes.

[0095] A patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) is then formed over the third dielectric layer 304 and the first passivation layer 302. Thereafter, with the patterned masking layer in place, an etching process is performed on the third dielectric layer 304 and the first passivation layer 302 to remove the unmasked portions of the third dielectric layer 304 and the unmasked portions of the first passivation layer 302. In some embodiments, the etching process may be, for example, a wet etching process, a dry etching process, an RIE process, some other etching process, or a combination of the foregoing processes.

[0096] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a first conductive structure 306 and a second conductive structure 308 are formed over the MEMS layer 108 and the second dielectric layer 130. The first conductive structure 306 is electrically coupled to the upper electrode 138. The second conductive structure 308 is electrically coupled to the lower electrode 134. In some embodiments, the first conductive structure 306 is formed over the first passivation layer 302, the third dielectric layer 304, the lower electrode 134, the piezoelectric structure 136, and the upper electrode 138. In yet other embodiments, the first conductive structure 306 is formed to extend from the upper electrode 138 in a vertical direction and partially line the third dielectric layer 304. In some embodiments, the second conductive structure 308 is formed over the first passivation layer 302, the third dielectric layer 304, and the lower electrode 134. In yet other embodiments, the second conductive structure 308 is formed to extend from the lower electrode 134 in a vertical direction and partially line the third dielectric layer 304.

[0097] In some embodiments, the process of forming the first conductive structure 306 and the second conductive structure 308 includes forming a first patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) on the third dielectric layer 304 and the second dielectric layer 130. With the first patterned masking layer in place, a first etching process is then performed on the third dielectric layer 304 and the first passivation layer 302. The first etching process removes the unmasked portion of the third dielectric layer 304 and the unmasked portion of the first passivation layer 302, thereby forming a through-hole opening extending through (e.g., completely through) the third dielectric layer 304 and the first passivation layer 302 in a vertical direction. One of the through-hole openings exposes the upper electrode 138 and the other of the through-hole openings exposes the lower electrode 134. In some embodiments, the first etching process may be, for example, a wet etching process, a dry etching process, an RIE process, some other etching process, or a combination of the foregoing processes. In some further embodiments, the first patterned masking layer is stripped.

[0098] A conductive layer is then deposited over the third dielectric layer 304 and the second dielectric layer 130. The conductive layer is also deposited into the via opening (e.g., filling the via opening). The conductive layer may be or include, for example, aluminum copper (AlCu), copper (Cu), aluminum (Al), tungsten (W), gold (Au), silver (Ag), some other conductive material, or a combination of the foregoing materials. The conductive layer may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing processes.

[0099] Thereafter, a second patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) is formed over the third dielectric layer 304, the second dielectric layer 130, and the conductive layer. With the second patterned masking layer in place, a second etching process is then performed on the conductive layer. The second etching process removes the unmasked portion of the conductive layer, thereby forming the first conductive structure 306 and the second conductive structure 308. In some embodiments, the second etching process may be, for example, a wet etching process, a dry etching process, an RIE process, some other etching process, or a combination of the foregoing processes. In other embodiments, the first conductive structure 306 and the second conductive structure 308 may be formed by one or more other processes (e.g., a damascene process).

[0100] like Fig.16As shown in the cross-sectional view 1600 of , the portion of the second dielectric layer 130 disposed between the diaphragm openings 1302 is removed. In some embodiments, the process of removing the portion of the second dielectric layer 130 disposed between the diaphragm openings 1302 includes forming a patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) on the third dielectric layer 304, the second dielectric layer 130, the first conductive structure 306, and the second conductive structure 308. The patterned masking layer exposes (e.g., does not mask) the portion of the second dielectric layer 130 disposed between the diaphragm openings 1302. With the patterned masking layer in place, an etching process is then performed on the second dielectric layer 130. The etching process removes the unmasked portion of the second dielectric layer 130, thereby removing the portion of the second dielectric layer 130 disposed between the diaphragm openings 1302. In some embodiments, the etching process may be, for example, a wet etching process, a dry etching process, an RIE process, some other etching process, or a combination of the foregoing processes.

[0101] In some embodiments, the etching process may reduce the thickness of the portion of the MEMS layer 108 disposed between the diaphragm openings 1302, such as Fig.16 1600. In other embodiments, the etching process may stop on the MEMS layer 108 (e.g., the MEMS layer 108 acts as an etch stop layer). The etching process may reduce the thickness of the portion of the MEMS layer disposed between the diaphragm openings 1302 to between about 3 μm and about 8 μm. It should be understood that in other embodiments, the portion of the second dielectric layer 130 disposed between the diaphragm openings 1302 may be removed before forming the first conductive structure 306 and / or the second conductive structure 308 (e.g., the second dielectric layer 130 may be removed by the etching process used to form the third dielectric layer 304).

[0102] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , a second passivation layer 310 is formed over the MEMS layer 108, the first conductive structure 306, the second conductive structure 308, the third dielectric layer 304, and the first dielectric layer 110. The second passivation layer 310 is also formed in the diaphragm opening 1302. In some embodiments, the second passivation layer 310 is formed to line the first conductive structure 306, the second conductive structure 308, the third dielectric layer 304, the diaphragm opening 1302, and the portion of the MEMS layer 108 disposed between the diaphragm opening 1302. More specifically, the second passivation layer 310 is formed to line the corrugated portion 116 (e.g., the one or more grooves 124 and the one or more ridges 122) of the MEMS layer 108 and the flat portion 114 of the MEMS layer 108. The second passivation layer 310 is formed to extend across the bottom surface of the diaphragm opening 1302 in a horizontal direction.

[0103] In some embodiments, the process of forming the second passivation layer 310 includes depositing the second passivation layer 310 on the first conductive structure 306, on the second conductive structure 308, on the third dielectric layer 304, on the portion of the MEMS layer 108 disposed between the diaphragm openings 1302, and the second passivation layer 310 lines the diaphragm openings 1302. The second passivation layer 310 may be formed by, for example, CVD, PVD, ALD, some other deposition process, or a combination of the foregoing processes. In some embodiments, the second passivation layer 310 is deposited as a conformal layer.

[0104] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , a cavity 106 is formed in the substrate 104. The cavity 106 extends into the substrate 104 from the back side 104b of the substrate 104 opposite the front side 104f of the substrate 104. The cavity 106 is formed such that the diaphragm opening 1302 (see, for example, Fig.17 ) is disposed between the sidewalls of cavity 106. In some embodiments, cavity 106 is formed to have angled sidewalls, such as Fig.18 As shown in the cross-sectional view 1800 of FIG. 106 , it should be understood that the angled sidewalls of the cavity 106 may be inclined inwardly toward each other (e.g., Fig.18 1800) or may be tilted outwardly away from each other. In other embodiments, the cavity 106 is formed to have substantially vertical sidewalls or rounded sidewalls.

[0105] By forming the cavity 106, the portion of the MEMS layer 108 disposed between the diaphragm openings 1302 is released from being attached to the substrate 104, thereby forming a movable diaphragm 112 including the corrugated portion 116 of the MEMS layer 108 and the flat portion 114 of the MEMS layer 108. In other words, after the portion of the MEMS layer 108 disposed between the diaphragm openings 1302 is released, the portion of the MEMS layer 108 disposed between the diaphragm openings 1302 is referred to as the movable diaphragm 112 (e.g., because the movable diaphragm 112 can be moved by the actuator 132). The movable diaphragm 112 includes a first outer sidewall 128. In some embodiments, the first outer sidewalls 128 of the movable diaphragm 112 correspond to sidewalls of the diaphragm openings 1302 (e.g., sidewalls of the MEMS layer 108), respectively.

[0106] In some embodiments, the process of forming the cavity 106 includes: Fig.17The structure shown in the cross-sectional view 1700 of is flipped (e.g., rotated 180 degrees). Thereafter, a patterned masking layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) is formed on the back side 104b of the substrate 104. With the patterned masking layer in place, an etching process is then performed on the substrate 104 and the first dielectric layer 110 to remove the unmasked portions of the substrate 104 and the unmasked portions of the first dielectric layer 110, thereby forming the cavity 106. In other embodiments, the etching process may stop on the first dielectric layer 110 (e.g., the first dielectric layer 110 acts as an etch stop layer). In some embodiments, the etching process may be, for example, a wet etching process, a dry etching process, an RIE process, some other etching process, or a combination of the foregoing processes.

[0107] Since the second passivation layer 310 is formed to line the diaphragm opening 1302 and to extend in the horizontal direction across the bottom surface of the diaphragm opening 1302 (see, e.g. Fig.17 ), so the second passivation layer 310 can at least partially support the movable diaphragm 112 so that the movable diaphragm 112 is suspended above the cavity 106 (e.g., suspended directly above the cavity 106). In some other embodiments, one or more tethers (not shown) (e.g., tether portions of the MEMS layer 108) can at least partially support the movable diaphragm 112 so that the movable diaphragm 112 is suspended above the cavity 106 (e.g., suspended directly above the cavity 106). In some embodiments, the formation of the cavity 106 completes the formation of the semiconductor device 102 (e.g., a MEMS speaker). In some embodiments, after the cavity 106 is formed, the diaphragm opening 1302 can be referred to as a gap (e.g., a gap in the MEMS layer 108 disposed between the movable diaphragm 112 and the attached portion of the MEMS layer 108).

[0108] Although not shown, it should be understood that after forming the cavity 106, Fig.18 The structure shown in the cross-sectional view 1800 of FIG. 1 is flipped (e.g., rotated 180 degrees). Thereafter, an interconnect structure (e.g., an interlayer dielectric (ILD) structure having metal interconnects disposed therein) may be formed over the MEMS layer 108 and the one or more actuators 132 so that the one or more actuators 132 may be electrically coupled to one or more I / O structures (e.g., bonding pads, solder bumps, etc.).

[0109] Fig.19 Flowchart 1900 illustrates some embodiments of a method of forming a semiconductor device 102 with improved signal distortion. Fig.19The illustrated flow chart 1900 is illustrated and described herein as a series of actions or events, however it should be understood that the order in which such actions or events are shown should not be construed as having a limiting meaning. For example, some actions may occur in different orders and / or synchronously with other actions or events other than those illustrated and / or described herein. In addition, not all illustrated actions may be required to implement one or more aspects or embodiments described herein, and one or more of the illustrated actions herein may be implemented in one or more separate actions and / or stages.

[0110] At act 1902, a plurality of corrugated grooves are formed in a substrate. Figure 7 Cross-sectional view 700 of some embodiments corresponding to act 1902 is shown.

[0111] At act 1904, a microelectromechanical system (MEMS) layer is formed over the substrate and at least partially in the plurality of corrugated grooves, wherein the MEMS layer includes a planar portion and a corrugated portion. Figure 8 to Figure 9 A series of cross-sectional views 800 through 900 of some embodiments corresponding to act 1904 are shown.

[0112] At act 1906 , a dielectric layer is formed over the MEMS layer and the substrate. Figure 10 to Figure 11 A series of cross-sectional views 1000 through 1100 of some embodiments corresponding to act 1906 are shown.

[0113] At act 1908, an actuation device is formed over the MEMS layer and the dielectric layer. Fig.12 Cross-sectional view 1200 of some embodiments corresponding to act 1908 is shown.

[0114] At act 1910 , a diaphragm opening is formed in the MEMS layer, wherein the diaphragm opening is formed such that a corrugated portion of the MEMS layer and a flat portion of the MEMS layer are disposed between the diaphragm opening. Fig.13 Cross-sectional view 1300 of some embodiments corresponding to act 1910 is shown.

[0115] At act 1912, a cavity is formed in a substrate, wherein the cavity is formed such that a diaphragm opening is disposed between sidewalls of the cavity. Figures 14 to 18 A series of cross-sectional views 1400 through 1800 of some embodiments corresponding to act 1912 are shown.

[0116] In some embodiments, the present application provides a semiconductor device. The semiconductor device includes a substrate. A cavity is disposed in the substrate. A microelectromechanical system (MEMS) layer is disposed on the substrate. The MEMS layer includes a movable diaphragm disposed on the cavity. The movable diaphragm includes a central region and a peripheral region. The movable diaphragm is flat in the central region of the movable diaphragm. The movable diaphragm is corrugated in the peripheral region of the movable diaphragm.

[0117] In the above-mentioned semiconductor device, wherein: the peripheral area of ​​the movable diaphragm includes a first part of the peripheral area and a second part of the peripheral area; and the first part of the peripheral area and the second part of the peripheral area are arranged on opposite sides of the central area of ​​the movable diaphragm.

[0118] In the above-mentioned semiconductor device, wherein: the first part of the peripheral area, the second part of the peripheral area and the central area of ​​the movable diaphragm extend continuously between the first relative side walls of the movable diaphragm; and the central area of ​​the movable diaphragm separates the first part of the peripheral area from the second part of the peripheral area in the laterally direction.

[0119] In the above-mentioned semiconductor device, wherein: the movable diaphragm has a second relative side wall; the second relative side walls of the movable diaphragm are spaced apart in a first direction; the first relative side walls of the movable diaphragm are spaced apart in a second direction perpendicular to the first direction; the first part of the peripheral area extends laterally from the central area to one of the second relative side walls of the movable diaphragm; and the second part of the peripheral area extends laterally from the central area to the other of the second relative side walls of the movable diaphragm.

[0120] In the above-mentioned semiconductor device, the peripheral region of the movable membrane extends in a closed loop path in a laterally direction around the central region of the movable membrane.

[0121] In the above-mentioned semiconductor device, the peripheral region of the movable membrane is a continuous region extending from the central region to an outer side wall of the movable membrane in a lateral direction.

[0122] In the above semiconductor device, wherein: the peripheral region includes one or more grooves and one or more ridges; and the one or more grooves and the one or more ridges alternate from the central region of the movable membrane to the outer sidewall of the movable membrane.

[0123] In the above semiconductor device, the one or more grooves are concentric with the one or more ridges.

[0124] The above-mentioned semiconductor device also includes: a piezoelectric actuator, wherein the piezoelectric actuator is configured to move the movable diaphragm in response to an electrical signal; and a passivation layer, which is arranged on the piezoelectric actuator and the movable diaphragm, wherein the passivation layer pads the micro-electromechanical system layer in both the central area of ​​the movable diaphragm and the peripheral area of ​​the movable diaphragm.

[0125] In some embodiments, the present application provides a semiconductor device. The semiconductor device includes a substrate. A cavity is disposed in the substrate. A microelectromechanical system (MEMS) layer is disposed on the substrate. The MEMS layer includes a movable diaphragm disposed on the cavity. The movable diaphragm has a flat portion and a corrugated portion. The corrugated portion of the movable diaphragm laterally surrounds the flat portion of the movable diaphragm.

[0126] In the above semiconductor device, wherein: the corrugated portion of the movable membrane includes alternating ridges and grooves; and the grooves include beveled sidewalls.

[0127] In the above semiconductor device, wherein: one of the ridges is farther from the flat portion than each of the other ridges of the ridges; and an outer sidewall of the movable membrane extends from an upper surface of the one of the ridges and is substantially vertical.

[0128] In the above semiconductor device, a bottom surface of the groove is substantially flat.

[0129] In the above semiconductor device, an upper surface of the ridge is substantially flat.

[0130] In the above-mentioned semiconductor device, the bottom surface of the groove is provided between the upper surface of the flat portion of the movable diaphragm and the bottom surface of the flat portion of the movable diaphragm.

[0131] The semiconductor device further includes: an actuator disposed on the micro-electromechanical system layer, wherein the actuator is configured to move the movable membrane in response to an electrical signal.

[0132] In the above semiconductor device, the actuator includes a piezoelectric structure disposed between an upper electrode and a lower electrode.

[0133] In some embodiments, the present application provides a method for forming a semiconductor device. The method includes forming a plurality of corrugated grooves in a substrate. A dielectric layer is formed on the substrate, and the dielectric layer lines the plurality of corrugated grooves. A microelectromechanical system (MEMS) layer is formed on the dielectric layer and in the plurality of corrugated grooves. A plurality of corrugated grooves are formed in the MEMS layer. A diaphragm opening is formed in the MEMS layer, wherein the diaphragm opening is formed such that the plurality of corrugated grooves and the plurality of corrugated grooves are disposed between the diaphragm openings. A cavity is formed in the substrate, wherein the cavity is formed such that the diaphragm opening is disposed between the sidewalls of the cavity.

[0134] In the above method for forming a semiconductor device, the cavity is formed so that a portion of the MEMS layer located between the membrane openings is released, thereby forming a movable membrane, the movable membrane including a corrugated portion of the movable membrane and a flat portion of the movable membrane.

[0135] In the above-mentioned method of forming a semiconductor device, it also includes: after the diaphragm opening is formed, forming a passivation layer on the micro-electromechanical system layer and the dielectric layer, wherein the passivation layer lines the micro-electromechanical system layer, the diaphragm opening and the multiple corrugated grooves, and wherein the formation of the diaphragm opening exposes some portions of the dielectric layer.

[0136] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: substrate; a cavity disposed in the substrate; A micro-electromechanical system layer is disposed on the substrate, wherein: The MEMS layer includes a movable membrane disposed over the cavity; The movable diaphragm includes a central area and a peripheral area; said movable diaphragm being flat in said central region of said movable diaphragm; The movable diaphragm is corrugated in the peripheral region of the movable diaphragm; and The peripheral region of the movable diaphragm includes a bottom surface including a first ridge and a first groove, and an upper surface including a second groove above the first ridge of the bottom surface and a second ridge above the first groove of the bottom surface.

2. The semiconductor device according to claim 1, wherein: The peripheral region of the movable diaphragm includes a first portion of the peripheral region and a second portion of the peripheral region; and The first portion of the peripheral region and the second portion of the peripheral region are disposed on opposite sides of the central region of the movable diaphragm.

3. The semiconductor device according to claim 2, wherein: The first portion of the peripheral region, the second portion of the peripheral region, and the central region of the movable diaphragm extend continuously between first opposing side walls of the movable diaphragm; and The central region of the movable diaphragm laterally separates the first portion of the peripheral region from the second portion of the peripheral region.

4. The semiconductor device according to claim 3, wherein: The movable diaphragm has a second opposing side wall; the second opposing side walls of the movable diaphragm are spaced apart in a first direction; the first opposing side walls of the movable diaphragm being spaced apart in a second direction perpendicular to the first direction; The first portion of the peripheral region extends laterally from the central region to one of the second opposing side walls of the movable diaphragm; and The second portion of the peripheral region extends laterally from the central region to the other of the second opposing side walls of the movable diaphragm. 5 . The semiconductor device according to claim 1 , wherein the peripheral region of the movable membrane extends laterally around the central region of the movable membrane in a closed loop path. 6 . The semiconductor device according to claim 5 , wherein the peripheral region of the movable membrane is a continuous region extending from the central region to an outer sidewall of the movable membrane in a lateral direction.

7. The semiconductor device according to claim 1, wherein: The first groove and the first ridge include a plurality of portions alternately disposed from the central area of ​​the movable diaphragm to the outer sidewall of the movable diaphragm. The semiconductor device according to claim 1 , wherein the second groove is concentric with the second ridge.

9. The semiconductor device according to claim 1, further comprising: a piezoelectric actuator, wherein the piezoelectric actuator is configured to cause movement of the movable diaphragm in response to an electrical signal; as well as A passivation layer is disposed over the piezoelectric actuator and the movable diaphragm, wherein the passivation layer lines the micro-electromechanical system layer in both the central region of the movable diaphragm and the peripheral region of the movable diaphragm.

10. A semiconductor device comprising: substrate; a cavity disposed in the substrate; A micro-electromechanical system layer is disposed on the substrate, wherein: The MEMS layer includes a movable membrane disposed over the cavity; The movable diaphragm has a flat portion and a corrugated portion; The corrugated portion of the movable diaphragm laterally surrounds the flat portion of the movable diaphragm; and The corrugated portion includes a bottom surface including first ridges and first grooves and an upper surface including second grooves above the first ridges of the bottom surface and second ridges above the first grooves of the bottom surface.

11. The semiconductor device according to claim 10, wherein: The first groove includes a beveled sidewall.

12. The semiconductor device according to claim 10, wherein: An outer sidewall of the movable diaphragm extends from an upper surface of the second ridge and is substantially vertical. 13 . The semiconductor device according to claim 10 , wherein a bottom surface of the first trench is substantially flat. The semiconductor device according to claim 10 , wherein an upper surface of the second ridge is substantially flat. 15 . The semiconductor device according to claim 10 , wherein a bottom surface of the second groove is disposed between an upper surface of the planar portion of the movable diaphragm and a bottom surface of the planar portion of the movable diaphragm.

16. The semiconductor device according to claim 10, further comprising: An actuator is disposed on the micro-electromechanical system layer, wherein the actuator is configured to move the movable membrane in response to an electrical signal.

17. The semiconductor device according to claim 16, wherein the actuator comprises a piezoelectric structure disposed between an upper electrode and a lower electrode.

18. A method of forming a semiconductor device, the method comprising: forming a plurality of corrugated grooves in a substrate; forming a dielectric layer over the substrate, wherein the dielectric layer lines the plurality of corrugated grooves; forming a micro-electromechanical system layer over the dielectric layer and in the plurality of corrugated grooves; forming a plurality of corrugated grooves in the MEMS layer; forming a diaphragm opening in the MEMS layer, wherein the diaphragm opening is formed such that the plurality of corrugated grooves and the plurality of corrugated slots are disposed between the diaphragm opening; as well as A cavity is formed in the substrate to form a movable diaphragm, wherein the cavity is formed so that the diaphragm opening is disposed between side walls of the cavity, the movable diaphragm includes a corrugated portion and a flat portion, the corrugated portion includes a bottom surface and an upper surface, the bottom surface includes a first ridge and a first groove, the upper surface includes a second groove above the first ridge of the bottom surface and a second ridge above the first groove of the bottom surface. 19 . The method of forming a semiconductor device according to claim 18 , wherein the cavity is formed so that a portion of the MEMS layer located between the membrane openings is released, thereby forming the movable membrane.

20. The method for forming a semiconductor device according to claim 19, further comprising: After the membrane opening is formed, a passivation layer is formed over the MEMS layer and the dielectric layer, wherein the passivation layer lines the MEMS layer, the membrane opening, and the plurality of corrugated grooves, and wherein the membrane opening is formed to expose portions of the dielectric layer.

Images