Data processing apparatus, method, computer device, storage medium and program product

Abstract

The application provides a data processing device, method, computer equipment, storage medium and program product, and relates to the technical field of computers. The log file of a processor pipeline to be analyzed is read into the memory, and the timestamp information of the machine code in the log file when the machine code is executed by the processor to be analyzed is obtained by analysis, so that the log file is read into the memory in batches. Based on the timestamp information, a time axis in a target analysis page is generated, the target analysis page is used to display the execution process of the machine code by the processor to be analyzed, and in response to a time to be displayed triggered based on the time axis, the machine code corresponding to the time to be displayed is parsed from the log file, and the machine code to be displayed is translated into assembly program code. The execution process of the assembly program code by the processor to be analyzed can be displayed in the target analysis page, the time triggered based on the time axis is translated at any time and quickly displayed, and the efficiency of data processing is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer technology, and discloses a data processing device and method, a computer device, a storage medium and a program product. BACKGROUND

[0002] With the development of technology, the processing performance of chip hardware is getting stronger and stronger, and the execution speed of CPU (Central Processing Unit) on instructions is also getting faster and faster. The CPU executes instructions through pipeline technology internally, and the pipeline technology of the CPU is a technology of decomposing instructions into multiple steps and overlapping the operations of different steps of instructions, so as to realize parallel processing of several instructions and speed up the program running process. Each step of the instruction has its own independent circuit to process, and each step is completed to the next step, while the previous step processes the subsequent instructions. Since the instructions executed by the CPU based on the pipeline technology are machine codes, the technical personnel in the field need to translate them into assembly codes when analyzing the performance of the CPU.

[0003] In the related art, the analysis can be performed through the following data processing process: the machine codes in the log file of the CPU are extracted one by one into the memory, and the machine codes are translated one by one into assembly program codes, and then the assembly program codes are filled one by one into the analysis module to analyze the performance of the CPU.

[0004] However, the entire process of extracting, translating and filling the machine codes one by one into the analysis module is time-consuming and low in efficiency, so the efficiency of the above data processing is low. SUMMARY

[0005] The present application provides a data processing device and method, a computer device, a storage medium and a program product, which can effectively prevent the problem of program code decompilation. The technical solution is as follows:

[0006] In one aspect, a data processing device is provided, and the device includes a processor, which is configured to:

[0007] read a log file of a processor pipeline to be analyzed into a memory, and parse the timestamp information of machine codes in the log file when the machine codes are executed by the processor to be analyzed;

[0008] generate a time axis in a target analysis page based on the timestamp information, the target analysis page being used to display the execution process of the machine codes by the processor to be analyzed;

[0009] in response to a to-be-displayed time triggered based on the time axis, parse to-be-displayed machine codes corresponding to the to-be-displayed time from the log file, and translate the to-be-displayed machine codes into assembly program codes;

[0010] displaying, in the target analysis page, an execution process of the assembler code by the processor to be analyzed.

[0011] In a possible implementation, the processor is further configured to:

[0012] based on the timestamp information, parsing a first line of machine code at an initial time point from the log file, and translating the first line of machine code into a first line of assembler code;

[0013] displaying, in the target analysis page, the first line of assembler code.

[0014] In a possible implementation, the processor is further configured to:

[0015] based on a target register group corresponding to the machine code to be displayed, filling the assembler code into a display position corresponding to the target register group in the target analysis page, so as to display, in the target analysis page, a process of fetching an instruction by the target register group and a process executed by the processor to be analyzed during execution of the assembler code.

[0016] In a possible implementation, the processor is further configured to:

[0017] detecting a triggering operation in the target analysis page;

[0018] in response to the triggering operation on the time axis in the target analysis page, determining a time point to be displayed corresponding to the triggering operation based on a machine code rollback manner triggered by the triggering operation.

[0019] In a possible implementation, the processor is further configured to:

[0020] parsing execution information of the machine code to be displayed from the log file, so as to display, in the target analysis page, an execution process of the assembler code by the processor to be analyzed based on the execution information.

[0021] In a possible implementation, the execution information of the machine code to be displayed includes a program counter pointer, an instruction execution state of each register group, and a register head and tail pointer position.

[0022] In another aspect, a data processing method is provided, and the method includes:

[0023] reading a log file of a processor pipeline to be analyzed into a memory, and parsing timestamp information of machine code in the log file when the machine code is executed by the processor to be analyzed;

[0024] generate a time axis in a target analysis page based on the timestamp information, the target analysis page being used to show an execution process of the to-be-analyzed processor on the machine code;

[0025] in response to a to-be-shown time triggered based on the time axis, parse to-be-shown machine code corresponding to the to-be-shown time from the log file, and translate the to-be-shown machine code into assembly code;

[0026] display the execution process of the to-be-analyzed processor on the assembly code in the target analysis page.

[0027] In a possible implementation manner, the method further includes:

[0028] based on the timestamp information, parse first-line machine code of an initial time from the log file, and translate the first-line machine code into first-line assembly code;

[0029] display the first-line assembly code in the target analysis page.

[0030] In a possible implementation manner, the displaying the execution process of the to-be-analyzed processor on the assembly code in the target analysis page includes:

[0031] based on a target register group corresponding to the to-be-shown machine code, fill the assembly code into a display position corresponding to the target register group in the target analysis page;

[0032] in the target analysis page, display a process of fetching an instruction by the target register group and a process of execution by the to-be-analyzed processor during the execution of the assembly code.

[0033] In a possible implementation manner, before the parsing the to-be-shown machine code corresponding to the to-be-shown time from the log file in response to the to-be-shown time triggered based on the time axis, the method further includes:

[0034] detect a trigger operation in the target analysis page;

[0035] in response to the trigger operation on the time axis in the target analysis page, determine a to-be-shown time corresponding to the trigger operation based on a machine code rollback manner triggered by the trigger operation.

[0036] In a possible implementation manner, the displaying the execution process of the to-be-analyzed processor on the assembly code in the target analysis page includes:

[0037] parse execution information of the to-be-shown machine code from the log file;

[0038] Based on the execution information, the execution process of the assembler code by the processor to be analyzed is displayed on the target analysis page.

[0039] In one possible implementation, the execution information of the machine code to be displayed includes: a program counter pointer, the instruction execution status of each register group, and the positions of the register head and tail pointers.

[0040] On the other hand, a computer device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the above-described data processing method.

[0041] On the other hand, a computer-readable storage medium is provided that stores a computer program thereon, which, when executed by a processor, implements the above-described data processing method.

[0042] On the other hand, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described data processing method.

[0043] The beneficial effects of the technical solutions provided in this application are:

[0044] The data processing apparatus provided in this application reads the log files of the processor pipeline to be analyzed into memory and parses the timestamp information of the machine code in the log files when the processor to be analyzed executes them, thereby batch reading the log files into memory; based on the timestamp information, a timeline in the target analysis page is generated, which is used to display the execution process of the machine code by the processor to be analyzed; in response to the display time triggered by the timeline, the machine code to be displayed corresponding to the display time is parsed from the log files and translated into assembly code; the execution process of the assembly code by the processor to be analyzed can then be displayed on the target analysis page, realizing a fast display process based on the timeline-triggered moment, translating and displaying at any time, avoiding the tedious process of extracting, filling and translating one by one, thus reducing the time consumption of the display and analysis processes and improving the efficiency of data processing. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.

[0046] Figure 1 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0047] Figure 2 A schematic flowchart illustrating the data processing method executed by the processor provided in this application embodiment;

[0048] Figure 3 A schematic diagram of a register visualization system interface provided in this application embodiment;

[0049] Figure 4 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0050] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0051] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0052] Those skilled in the art will understand that, unless otherwise stated, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. The terms “comprising” and “including” as used in the embodiments of this application mean that the corresponding feature can be implemented as the presented feature, information, data, step, or operation, but do not exclude implementation as other features, information, data, steps, or operations supported by this art.

[0053] Figure 1 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Figure 1 As shown, the data processing apparatus includes a processor for data processing.

[0054] This processor is used to perform tasks such as data processing. Figure 2 The data processing methods shown are as follows: Figure 2 As shown, during data processing, the processor specifically executes the following data processing steps 201 to 204:

[0055] Step 201: Read the log file of the processor pipeline to be analyzed into memory, and parse the timestamp information of the machine code in the log file when it was executed by the processor to be analyzed;

[0056] Step 202: Based on the timestamp information, generate a timeline in the target analysis page. This target analysis page is used to display the execution process of the machine code by the processor to be analyzed.

[0057] Step 203: In response to the time to be displayed triggered based on the time axis, parse the machine code to be displayed corresponding to the time to be displayed from the log file, and translate the machine code to be displayed into assembly code;

[0058] Step 204: Display the execution process of the assembler code by the processor to be analyzed on the target analysis page.

[0059] It's important to note that processor pipelining is a technique that breaks down instructions into multiple steps and overlaps the operations of different instructions, allowing several instructions to be processed in parallel to accelerate program execution. Each step of an instruction has its own independent circuitry for processing; after each step is completed, the process moves to the next step, while the previous step processes the subsequent instructions. Processor pipelining can reach levels of over ten stages. The instructions executed in processor pipelining are in machine code form, which needs to be translated into assembly language for easy analysis of processor performance.

[0060] The processor to be analyzed refers to the processor for which performance analysis is required. For example, this application uses a 32-bit RISC-V processor as an example. For instance, the RISC-V processor to be analyzed may include a re-order buffer, which includes a bank module. This bank module (heap module) is the implementation of the RISC-V processor's register file, through which the RISC-V processor fetches instructions and executes corresponding instructions. When performing performance analysis on the RISC-V processor, the machine code instructions in the RISC-V processor's pipeline log (LOG) file can be used and translated into assembly code to analyze the bank module within the RISC-V processor.

[0061] In step 201, the log file may include various machine codes and timestamp information. The timestamp information refers to the time when each machine code was executed. For example, the instruction corresponding to machine code A is executed at time t1, and the instruction corresponding to machine code B is executed at time t2. This application can import the log file into memory. For example, taking a RISC-V processor as an example, the RISC-V processor pipeline LOG file can be imported into the memory buffer, such as importing it into the memory address corresponding to the bank module visualization system in the memory buffer. Furthermore, the LOG file is parsed to extract the timestamp information and machine code information.

[0062] In step 202, the target analysis page is a page displayed when the execution process of the machine code executed by the processor to be analyzed is traced back. In this application, the data processing device may further include a display screen, on which the processor of the data processing device can display the target analysis page during data processing. The target analysis page may include a timeline, which is used to trigger the display of the tracing progress of the execution process of each machine code in the log file. For example, the target analysis page may be a register visualization system interface, such as a bank module visualization system interface. For example, this application generates the timeline in the target analysis page using timestamp information. For instance, the start and end times of the timeline can be generated based on the timestamp information. The start time may be the execution time corresponding to the first machine code in the log file; the end time may be the execution time corresponding to the last machine code in the log file.

[0063] Figure 3 A schematic diagram of a register visualization system interface is provided, such as... Figure 3 As shown, taking the RISC-V processor as an example, a timeline is generated in the lower area of ​​the register visualization system interface based on this timestamp. This timeline corresponds to a start time and an end time. Figure 3 As shown, this application can also display the execution cycle in the area surrounding the timeline, such as the total cycle and the current cycle number.

[0064] After the timeline is displayed on the target analysis page, you can trace back the machine code execution process at the corresponding moment according to the current display progress of the timeline, and display it on the target analysis page.

[0065] like Figure 3 As shown, taking the target analysis page as an example of a register visualization system interface, this register visualization system interface may also include a timeline trigger control. Users can use this trigger control to activate the progress to be displayed on the timeline, thereby triggering the display of the machine code execution process at the corresponding moment. In step 203, when a moment to be displayed is received from the timeline triggered in the register visualization system interface, the machine code corresponding to that moment can be parsed from the log file and translated into assembly code; thus obtaining the display information corresponding to that moment. Based on the display information corresponding to that moment, the machine code execution process corresponding to that moment can be displayed in step 204.

[0066] In one possible implementation, the processor in the data processing device is further configured to perform the following steps 401-402:

[0067] Step 401: Based on the timestamp information, parse the first line of machine code at the initial moment from the log file and translate the first line of machine code into the first line of assembly code.

[0068] Step 402: Display the first line of assembly code on the target analysis page.

[0069] The first line of machine code at this initial moment can be the first line of machine code in the log file, that is, the first machine code executed. The processor in the data processing device can also execute steps 401 and 402 to fill the assembly code in the initial moment register into the target analysis page.

[0070] In this application, when the log file is read into memory, the machine code, timestamps, and other information in the log file are also temporarily stored in memory. In one possible example, the log file may contain a large amount of machine code, and the log file may be large. If the large amount of machine code in the log file is immediately translated into assembly when the log file is read into memory, the parsing and translation process would be very time-consuming, easily leading to lengthy translation and analysis processes, thereby reducing processing efficiency and affecting user experience. Therefore, in this application, the machine code in the log file can be temporarily stored in memory but not parsed first. For example, in step 201, only the pipeline LOG file of the 32-bit RISC-V processor is imported first to generate the timeline in the register visualization system interface. At this time, through steps 401-402, the assembly instructions in the initial time bank module can be filled into the register visualization system interface. Specifically, the machine code information of the instructions in banks 0 to 3 in the first line of the LOG file is translated into assembly program code, and the assembly program code is presented in the bank module visualization system interface.

[0071] In one possible implementation, the processor in the data processing device is further configured to perform the following steps 501-502:

[0072] Step 501: Detect the triggering operations in the target analysis page.

[0073] Step 502: In response to the trigger operation on the timeline in the target analysis page, determine the time to be displayed corresponding to the trigger operation based on the machine code backtracking method triggered by the trigger operation.

[0074] The machine code backtracking method may include, but is not limited to: automatic forward backtracking, automatic backward backtracking, jump backtracking, and forward or backward backtracking for a specified period. The time to be displayed can be the current time to be backtracked on the target analysis page. The time to be displayed may be determined based on how the user triggers the timeline.

[0075] like Figure 3As shown, in this target analysis page, the area surrounding the timeline includes trigger controls for that timeline. Users can use these trigger controls to select the backtracking method for the machine code, displaying the machine code execution process at the corresponding moment on the timeline according to that backtracking method. These trigger controls may include, but are not limited to: 100 cycles backward, 100 cycles forward, jump, automatic backward, automatic forward, number of cycles forward / backward per cycle, pause interval, etc. For example, if the user triggers 10 cycles forward, the moment to be displayed will be the moment 10 cycles after the current display time on the timeline. If the current display time is the first cycle, the moment to be displayed can be the moment corresponding to the 10th cycle. As another example, if the user triggers automatic forward, the moment to be displayed will be the moment after the current display time ends, as the user proceeds sequentially along the timeline from the current display time.

[0076] In one possible implementation, the processor is also used to perform the following step 601:

[0077] Step 601: Based on the target register group corresponding to the machine code to be displayed, fill the assembly program code into the display position corresponding to the target register group in the target analysis page, so as to display the process of instruction fetching by the target register group and execution by the processor to be analyzed during the execution of the assembly program code in the target analysis page.

[0078] In this application, the processor to be analyzed may include at least one register group. The processor to be analyzed can fetch instructions through each register group so that it can execute corresponding instructions. Accordingly, the target analysis page can also display the data according to each register group. For example, as... Figure 3 As shown, the Figure 3 The image shows the bank module in a 32-bit RISC-V processor, such as... Figure 3 In a simplified version, the RISC-CV processor's bank module can include 4 groups, each with 32 items, for a total of 128 items, which can be numbered as bank0, bank1, bank2, and bank3 respectively.

[0079] The processor in this data processing device can fill the display position of the corresponding register group in the target analysis page with the machine code to be displayed. This target register group is the register group used when the processor fetches instructions for the machine code to be displayed during execution. For example, if the log file records that the RISC-V processor uses register group bank3 to fetch instructions for machine code A, then the assembly code corresponding to machine code A will be filled into the display position corresponding to bank3. Figure 3 The table showing the column containing bank3.

[0080] The configuration information in this log file records the register groups corresponding to each machine code. This configuration information can be used to determine the machine code to be fetched for each register group, and the corresponding assembly code can be filled into the corresponding position on the target analysis page. For example, this configuration information could be the starting line information of the LOG file.

[0081] In step 601, during the timeline progression, the machine code for the time to be displayed is sequentially parsed from the log file and translated into corresponding assembly code. This assembly code is then filled into the corresponding positions (bank0-bank3) on the visualization system interface of the bank module. In processor pipeline technology, the processor under analysis can process instructions fetched from multiple register groups in parallel. Therefore, this application batch-retrieves multiple machine codes corresponding to multiple register groups for the time to be displayed from the log file and translates these machine codes into assembly code to fill into the visualization system interface. This batch-translates the machine code in the log file into assembly, avoiding the tedious process of parsing, translating, and filling each code individually, saving parsing and translation time and greatly improving data processing efficiency. Subsequently, by triggering operations such as forward, backward, jump, and autoplay on the timeline, the visualization process of bank module instruction execution can be realized, reconstructing the instruction execution of the bank module in real-time, thereby improving the efficiency of performance analysis and debugging of the processor under analysis.

[0082] It should be noted that in steps 401-402, the register set corresponding to the first line of assembly code is obtained, and this first line of assembly code is then filled into the table in the column containing the corresponding register set on the target analysis page. For example... Figure 3 As shown, the first thing to be filled is the assembly code corresponding to the first line of machine code in the initial bank module. For example, in the bank module visualization system, one of bank0 to bank3 can be filled. In addition, the specific item in bank0 to bank3 to be filled can be determined according to the information of the starting line of the pipeline LOG file.

[0083] In one possible implementation, the processor in the data processing device is further configured to perform the following step 701:

[0084] Step 701: Parse the execution information of the machine code to be displayed from the log file, and display the execution process of the processor to be analyzed on the target analysis page based on the execution information.

[0085] In one possible implementation, the execution information of the machine code to be displayed includes: a program counter pointer, the instruction execution status of each register group, and the positions of the register head and tail pointers. For example, the column information required in a 32-bit RISC-V processor pipeline LOG file may include, but is not limited to, the following 1 to 5 items:

[0086] 1. Timestamp column (in picoseconds): Timestamp information for each machine code can be extracted from the timestamp column.

[0087] 2. Pointer column: This pointer column carries the program counter pointer, and the program counter pointer included in the execution information can be obtained from the pointer column.

[0088] 3. Instruction Machine Code Column: This instruction machine code column is used to represent the register group corresponding to each machine code. For example, the register group includes bank0, bank1, bank2 and bank3. This instruction machine code column can store each bank in the bank module and the corresponding instruction machine code; the machine code corresponding to each register group can be obtained from the instruction machine code column.

[0089] 4. Status column: Used to indicate whether an instruction is being executed or has been executed. For example, the status columns for bank0 to bank3 mark the execution status of each machine code corresponding to bank0 to bank3. The instruction execution status of each register group can be obtained from the status column.

[0090] 5. Head and Tail Pointer Position Columns: Used to record the new instruction fetching the current value of the register and / or the instruction currently being executed by the register. For example, the head and tail pointer position columns for the bank module, where the head pointer points to the new instruction fetched by the current bank module, and the tail pointer points to the instruction currently being executed by the current bank module. The head and tail pointer positions of the registers can be obtained from the head and tail pointer position columns.

[0091] It should be noted that during CPU schematic design, it is necessary to assess the rationality of the CPU pipeline design and whether its performance meets the standards in order to evaluate processor performance. Therefore, it is necessary to clarify how the instruction flow of the CPU pipeline is executed. However, related technologies analyze and translate machine code one by one, which is time-consuming, labor-intensive, inefficient, and unsuitable for development and debugging. According to the data processing method proposed in this application, the log file is first read into memory at once to achieve batch reading of machine code; then, the machine code at the time to be displayed is parsed and translated in batches using a timeline, and the execution process of the corresponding assembly program code is displayed on the target analysis page, thereby realizing the rapid reconstruction of the instruction execution flow of the imported CPU pipeline LOG file. The entire process of instruction storage and execution of the 32-bit RISC processor bank module can be quickly presented on the bank visualization system interface, improving data processing efficiency and effectively improving the debugging efficiency of CPU designers.

[0092] The data processing apparatus provided in this application reads the log files of the processor pipeline to be analyzed into memory and parses the timestamp information of the machine code in the log files when the processor to be analyzed executes them, thereby batch reading the log files into memory; based on the timestamp information, a timeline in the target analysis page is generated, which is used to display the execution process of the machine code by the processor to be analyzed; in response to the display time triggered by the timeline, the machine code to be displayed corresponding to the display time is parsed from the log files and translated into assembly code; the execution process of the assembly code by the processor to be analyzed can then be displayed on the target analysis page, realizing a fast display process based on the timeline-triggered moment, translating and displaying at any time, avoiding the tedious process of extracting, filling and translating one by one, thus reducing the time consumption of the display and analysis processes and improving the efficiency of data processing.

[0093] Figure 4 This is a flowchart illustrating a data processing method provided in an embodiment of this application. Figure 4 As shown, the method includes:

[0094] Step S410: Read the log file of the processor pipeline to be analyzed into memory, and parse the timestamp information of the machine code in the log file when it was executed by the processor to be analyzed;

[0095] Step S420: Based on the timestamp information, generate a timeline in the target analysis page. The target analysis page is used to display the execution process of the machine code by the processor to be analyzed.

[0096] Step S430: In response to the time to be displayed triggered based on the time axis, parse the machine code to be displayed corresponding to the time to be displayed from the log file, and translate the machine code to be displayed into assembly code;

[0097] Step S440: Display the execution process of the assembler code by the processor to be analyzed on the target analysis page.

[0098] In one possible implementation, the method further includes:

[0099] Based on the timestamp information, the first line of machine code at the initial moment is parsed from the log file, and the first line of machine code is translated into the first line of assembly code.

[0100] The first line of assembly code is displayed on the target analysis page.

[0101] In one possible implementation, the execution process of the assembler code by the processor being analyzed is displayed on the target analysis page, including:

[0102] Based on the target register group corresponding to the machine code to be displayed, the assembly program code is filled into the display position corresponding to the target register group in the target analysis page;

[0103] The target analysis page displays the process of instruction fetching from the target register set and execution by the processor being analyzed during the execution of the assembly code.

[0104] In one possible implementation, before parsing the machine code to be displayed corresponding to the time to be displayed from the log file in response to the time to be displayed triggered based on the timeline, the method further includes:

[0105] Detect the triggered actions in the target analysis page;

[0106] In response to a trigger operation on the timeline in the target analysis page, the time to be displayed corresponding to the trigger operation is determined based on the machine code backtracking method triggered by the trigger operation.

[0107] In one possible implementation, the execution process of the assembler code by the processor being analyzed is displayed on the target analysis page, including:

[0108] The execution information of the machine code to be displayed is obtained by parsing the log file;

[0109] Based on this execution information, the execution process of the assembler code by the processor to be analyzed is displayed on the target analysis page.

[0110] In one possible implementation, the execution information of the machine code to be displayed includes: a program counter pointer, the instruction execution status of each register group, and the positions of the register head and tail pointers.

[0111] The data processing method provided in this application reads the log files of the processor pipeline to be analyzed into memory and parses the timestamp information of the machine code in the log files when the processor to be analyzed executes them, thereby batch reading the log files into memory; based on the timestamp information, a timeline in the target analysis page is generated, which is used to display the execution process of the machine code by the processor to be analyzed; in response to the display time triggered by the timeline, the machine code to be displayed corresponding to the display time is parsed from the log files and translated into assembly code; the execution process of the assembly code by the processor to be analyzed can then be displayed on the target analysis page. This achieves a fast display process based on the timeline-triggered moment, translating and displaying at any time, avoiding the tedious process of extracting, filling, and translating each code one by one, thus reducing the time consumption of the display and analysis processes and improving the efficiency of data processing.

[0112] It should be noted that the data processing apparatus provided in the above embodiments is only illustrated by the division of the above functional modules during data processing. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computer device can be divided into different functional modules to complete all or part of the functions described above. In addition, the data processing apparatus and data processing method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0113] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. For example... Figure 5 As shown, the computer device includes: a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps of a data processing method. Compared with related technologies, this method can implement a data processing method, which includes:

[0114] Step S410: Read the log file of the processor pipeline to be analyzed into memory, and parse the timestamp information of the machine code in the log file when it was executed by the processor to be analyzed;

[0115] Step S420: Based on the timestamp information, generate a timeline in the target analysis page. The target analysis page is used to display the execution process of the machine code by the processor to be analyzed.

[0116] Step S430: In response to the time to be displayed triggered based on the time axis, parse the machine code to be displayed corresponding to the time to be displayed from the log file, and translate the machine code to be displayed into assembly code;

[0117] Step S440: Display the execution process of the assembler code by the processor to be analyzed on the target analysis page.

[0118] In one possible implementation, the method further includes:

[0119] Based on the timestamp information, the first line of machine code at the initial moment is parsed from the log file, and the first line of machine code is translated into the first line of assembly code.

[0120] The first line of assembly code is displayed on the target analysis page.

[0121] In one possible implementation, the execution process of the assembler code by the processor being analyzed is displayed on the target analysis page, including:

[0122] Based on the target register group corresponding to the machine code to be displayed, the assembly program code is filled into the display position corresponding to the target register group in the target analysis page;

[0123] The target analysis page displays the process of instruction fetching from the target register set and execution by the processor being analyzed during the execution of the assembly code.

[0124] In one possible implementation, before parsing the machine code to be displayed corresponding to the time to be displayed from the log file in response to the time to be displayed triggered based on the timeline, the method further includes:

[0125] Detect the triggered actions in the target analysis page;

[0126] In response to a trigger operation on the timeline in the target analysis page, the time to be displayed corresponding to the trigger operation is determined based on the machine code backtracking method triggered by the trigger operation.

[0127] In one possible implementation, the execution process of the assembler code by the processor being analyzed is displayed on the target analysis page, including:

[0128] The execution information of the machine code to be displayed is obtained by parsing the log file;

[0129] Based on this execution information, the execution process of the assembler code by the processor to be analyzed is displayed on the target analysis page.

[0130] In one possible implementation, the execution information of the machine code to be displayed includes: a program counter pointer, the instruction execution status of each register group, and the positions of the register head and tail pointers.

[0131] The data processing method provided in this application reads the log files of the processor pipeline to be analyzed into memory and parses the timestamp information of the machine code in the log files when the processor to be analyzed executes them, thereby batch reading the log files into memory; based on the timestamp information, a timeline in the target analysis page is generated, which is used to display the execution process of the machine code by the processor to be analyzed; in response to the display time triggered by the timeline, the machine code to be displayed corresponding to the display time is parsed from the log files and translated into assembly code; the execution process of the assembly code by the processor to be analyzed can then be displayed on the target analysis page. This achieves a fast display process based on the timeline-triggered moment, translating and displaying at any time, avoiding the tedious process of extracting, filling, and translating each code one by one, thus reducing the time consumption of the display and analysis processes and improving the efficiency of data processing.

[0132] In one alternative embodiment, a computer device is provided, such as Figure 5 As shown, Figure 5 The computer device 500 shown includes a processor 501 and a memory 503. The processor 501 and the memory 503 are connected, for example, via a bus 502. Optionally, the computer device 500 may further include a transceiver 504, which can be used for data interaction between the computer device and other computer devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 504 is not limited to one type, and the structure of the computer device 500 does not constitute a limitation on the embodiments of this application.

[0133] Processor 501 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 501 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0134] Bus 502 may include a pathway for transmitting information between the aforementioned components. Bus 502 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 502 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0135] The memory 503 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation herein.

[0136] The memory 503 is used to store computer programs that execute the embodiments of this application, and the execution is controlled by the processor 501. The processor 501 is used to execute the computer programs stored in the memory 503 to implement the steps shown in the foregoing method embodiments.

[0137] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the steps and corresponding content of the aforementioned method embodiments.

[0138] This application also provides a computer program product, including a computer program that, when executed by a processor, can implement the steps and corresponding content of the aforementioned method embodiments.

[0139] The terms "first," "second," "third," "fourth," "1," "2," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown in the figures or text.

[0140] It should be understood that although arrows indicate various operation steps in the flowcharts of this application's embodiments, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application's embodiments, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all steps in each flowchart, based on the actual implementation scenario, may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application's embodiments do not limit this.

[0141] The above description is only an optional implementation method for some implementation scenarios of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application without departing from the technical concept of this application also fall within the protection scope of the embodiments of this application.

Claims

1. A data processing apparatus, characterized in that, The device includes a processor, the processor being configured to: The log file of the processor pipeline to be analyzed is read into memory, and the timestamp information of the machine code in the log file when it is executed by the processor to be analyzed is parsed. Based on the timestamp information, a timeline is generated in the target analysis page, which is used to display the execution process of the machine code by the processor to be analyzed; In response to the time to be displayed triggered based on the time axis, the machine code to be displayed corresponding to the time to be displayed is parsed from the log file, and the machine code to be displayed is translated into assembly code; Based on the target register group corresponding to the machine code to be displayed, the assembly program code is filled into the display position corresponding to the target register group in the target analysis page; The target analysis page displays the process of instruction fetching from the target register set and execution by the processor to be analyzed during the execution of the assembly program code.

2. The data processing apparatus according to claim 1, characterized in that, The processor is also used for: Based on the timestamp information, the first line of machine code at the initial moment is parsed from the log file, and the first line of machine code is translated into the first line of assembly code. The first line of assembly code is displayed on the target analysis page.

3. The data processing apparatus according to claim 1, characterized in that, The processor is also used for: Detect the triggered operations in the target analysis page; In response to a trigger operation on the timeline in the target analysis page, the time to be displayed corresponding to the trigger operation is determined based on the machine code backtracking method triggered by the trigger operation.

4. The data processing apparatus according to claim 1, characterized in that, The processor is also used for: The execution information of the machine code to be displayed is obtained by parsing the log file, and the execution process of the processor to be analyzed on the target analysis page is displayed based on the execution information.

5. The data processing apparatus according to claim 4, characterized in that, The execution information of the machine code to be displayed includes: the program counter pointer, the instruction execution status of each register group, and the position of the register head and tail pointers.

6. A data processing method, characterized in that, The method includes: The log file of the processor pipeline to be analyzed is read into memory, and the timestamp information of the machine code in the log file when it is executed by the processor to be analyzed is parsed. Based on the timestamp information, a timeline is generated in the target analysis page, which is used to display the execution process of the machine code by the processor to be analyzed; In response to the time to be displayed triggered based on the time axis, the machine code to be displayed corresponding to the time to be displayed is parsed from the log file, and the machine code to be displayed is translated into assembly code; Based on the target register group corresponding to the machine code to be displayed, the assembly program code is filled into the display position corresponding to the target register group in the target analysis page; The target analysis page displays the process of instruction fetching from the target register set and execution by the processor to be analyzed during the execution of the assembly program code.

7. The data processing method according to claim 6, characterized in that, The method further includes: Based on the timestamp information, the first line of machine code at the initial moment is parsed from the log file, and the first line of machine code is translated into the first line of assembly code. The first line of assembly code is displayed on the target analysis page.

8. The data processing method according to claim 6, characterized in that, Before parsing the machine code to be displayed corresponding to the time to be displayed from the log file in response to the time to be displayed triggered based on the time axis, the method further includes: Detect the triggered operations in the target analysis page; In response to a trigger operation on the timeline in the target analysis page, the time to be displayed corresponding to the trigger operation is determined based on the machine code backtracking method triggered by the trigger operation.

9. The data processing method according to claim 6, characterized in that, The process of displaying instruction fetching from the target register set and execution by the processor to be analyzed during the execution of the assembly program code on the target analysis page includes: The execution information of the machine code to be displayed is obtained by parsing the log file; Based on the execution information, the execution process of the assembler code by the processor to be analyzed is displayed on the target analysis page.

10. The data processing method according to claim 9, characterized in that, The execution information of the machine code to be displayed includes: the program counter pointer, the instruction execution status of each register group, and the position of the register head and tail pointers.

11. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the data processing method according to any one of claims 6 to 10.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data processing method according to any one of claims 6 to 10.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the data processing method according to any one of claims 6 to 10.

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