Display panel and display device

Abstract

A display panel comprises a display area; the display panel further comprises a first flexible substrate, a second flexible substrate and a plurality of first data lines, the plurality of first data lines are located between the stacked first flexible substrate and the second flexible substrate; the plurality of first data lines are distributed in the display area; the display panel further comprises a plurality of pixel driving circuits and a plurality of second data lines, the plurality of pixel driving circuits and the plurality of second data lines are located in the display area, and the plurality of pixel driving circuits and the plurality of second data lines are located on a side of the second flexible substrate away from the first data lines; the plurality of pixel driving circuits are arranged in an array; the plurality of first data lines are connected to the plurality of second data lines in a one-to-one correspondence; wherein the plurality of first data lines comprise a portion arranged along a column direction of the pixel driving circuit array, the pixel driving circuit comprises a driving transistor, and the orthographic projection of at least the portion of the plurality of first data lines arranged along a column direction of the pixel driving circuit array on the first flexible substrate does not overlap with the orthographic projection of a channel region of the driving transistor on the first flexible substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, the development of full-screen displays has been very rapid, which has put forward new requirements for the screen shape. Display screens are moving towards the full-screen era. In order to increase the screen-to-body ratio, narrow-border products are receiving more and more attention. Summary of the invention

[0003] In a first aspect, an embodiment of the present disclosure provides a display panel, including a display area;

[0004] The display panel further includes a first flexible substrate, a second flexible substrate and a plurality of first data lines.

[0005] The plurality of first data lines are located between the stacked first flexible substrate and the second flexible substrate; the plurality of first data lines are distributed in the display area;

[0006] The display panel further includes a plurality of pixel driving circuits and a plurality of second data lines, which are located in the display area, and the plurality of pixel driving circuits and the plurality of second data lines are located on a side of the second flexible substrate away from the first data lines;

[0007] The plurality of pixel driving circuits are arranged in an array; the plurality of first data lines are connected to the plurality of second data lines in a one-to-one correspondence;

[0008] The plurality of first data lines include portions that are routed in a column direction of a pixel driving circuit array, the pixel driving circuit includes a driving transistor, and an orthographic projection of at least portions of the plurality of first data lines that are routed in a column direction of the pixel driving circuit array on the first flexible substrate does not overlap with an orthographic projection of a channel region of the driving transistor on the first flexible substrate.

[0009] In some embodiments, the display area includes a first area and a second area, and the first area and the second area are connected;

[0010] The display panel further includes a non-display area, the non-display area includes a bending area, the bending area is located on a side of the first area away from the second area, the bending area, the first area and the second area are arranged in sequence along a second direction; the second direction is a column direction of the pixel driving circuit array;

[0011] The first area includes a first sub-area, a second sub-area and a third sub-area, and the first sub-area, the second sub-area and the third sub-area are arranged in sequence along a first direction and connected to each other; the first direction is a row direction of the pixel driving circuit array;

[0012] The bending area is connected to the second sub-area;

[0013] The first flexible substrate, the plurality of first data lines and the second flexible substrate extend from the second sub-region to the bending region;

[0014] The plurality of first data lines in the second sub-area include a first portion, a second portion and a third portion; the first portion, the second portion and the third portion are arranged in sequence along the first direction;

[0015] The first portion extends from the second sub-region to the first sub-region, the third portion extends from the second sub-region to the third sub-region, and the second portion extends from the second sub-region to the second region.

[0016] In some embodiments, the first portion, the second portion and the third portion distributed in the second sub-region extend along the second direction, and any two adjacent first data lines are symmetrically distributed on opposite sides of a channel region of the driving transistor;

[0017] In the second sub-area, two first data lines are distributed within the orthographic projection area of ​​any one of the pixel driving circuits on the first flexible substrate.

[0018] In some embodiments, the first sub-area includes a first partition and a second partition; the third sub-area includes a first partition and a second partition;

[0019] The first sub-area and the second sub-area are arranged in sequence along the first direction and are connected to each other; the second sub-area is located on a side of the first sub-area away from the second sub-area;

[0020] The first portion extends to the first subarea of ​​the first subarea;

[0021] The third portion extends to the first sub-area of ​​the third sub-area;

[0022] The first portion includes a plurality of the first data lines;

[0023] The third portion includes a plurality of the first data lines.

[0024] In some embodiments, the first portion and the third portion distributed in the first partition extend along the first direction, and the first data line is located between two adjacent rows of pixel driving circuits;

[0025] In the first partition, two first data lines are distributed between any two adjacent rows of the pixel driving circuits; and the first data lines and the orthographic projections of the channel regions of the switching transistors in the pixel driving circuits on the first flexible substrate do not overlap.

[0026] In some embodiments, it further includes a plurality of redundant routing lines located in the first partition and arranged in an array;

[0027] The plurality of redundant routing lines extend along the second direction, and any two adjacent redundant routing lines along the first direction are symmetrically distributed on opposite sides of a channel region of a driving transistor;

[0028] In the first partition, any one of the pixel driving circuits has two redundant wirings distributed in an orthographic projection area on the first flexible substrate;

[0029] Each row of the redundant routing lines is connected to a first data line extending along the first direction; each row of the redundant routing lines does not overlap with the orthographic projections of other first data lines extending along the first direction on the first flexible substrate;

[0030] The length of each of the redundant wirings does not exceed the length of an orthographic projection area of ​​the pixel driving circuit on the first flexible substrate along the second direction.

[0031] In some embodiments, the first portion further extends to the second sub-area of ​​the first sub-area;

[0032] The third portion also extends to the second sub-area of ​​the third sub-region.

[0033] In some embodiments, the first portion and the third portion distributed in the second partition extend along the second direction, and any two adjacent first data lines along the first direction are symmetrically distributed on opposite sides of a channel region of the driving transistor;

[0034] In the second partition, two first data lines are distributed within the orthographic projection area of ​​any one of the pixel driving circuits on the first flexible substrate.

[0035] In some embodiments, the width of the connecting portion between the first region and the second region is equal to the width of the second region along the first direction;

[0036] The first portion also extends to the second area;

[0037] The third portion also extends to the second region.

[0038] In some embodiments, the first portion, the second portion, and the third portion distributed in the second area are arranged in sequence along the first direction, and the first portion, the second portion, and the third portion extend along the second direction respectively;

[0039] The plurality of second data lines are sequentially arranged along the first direction, and the plurality of second data lines extend along the second direction;

[0040] In the second area, one first data line is distributed in the orthographic projection area of ​​any one of the pixel driving circuits on the first flexible substrate; and the orthographic projections of the plurality of first data lines overlap with the orthographic projections of the plurality of second data lines on the first flexible substrate in a one-to-one correspondence.

[0041] In some embodiments, the non-display area further includes an upper frame area located on a side of the second area away from the first area, and the upper frame area is connected to the second area;

[0042] The first flexible substrate, the plurality of first data lines and the second flexible substrate further extend from the second area to the upper frame area;

[0043] The pixel driving circuit comprises a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are sequentially arranged away from the second flexible substrate; an insulating layer is arranged between the first conductive layer and the second conductive layer;

[0044] The first conductive layer includes a plurality of first graphics, and the orthographic projections of the plurality of first graphics on the first flexible substrate extend from the upper frame area to the second area;

[0045] The plurality of first data lines located in the upper frame area are connected to the plurality of first graphics one by one through first via holes provided in the second flexible substrate;

[0046] The second conductive layer includes the plurality of second data lines;

[0047] The plurality of first patterns located in the second region are connected to the plurality of second data lines one by one through second via holes opened in the insulating layer.

[0048] In some embodiments, it further includes a plurality of light-emitting units and an encapsulation layer.

[0049] The plurality of light emitting units are located in the display area and on a side of the pixel driving circuit away from the second flexible substrate;

[0050] The plurality of light-emitting units are arranged in an array, and the plurality of light-emitting units are connected to the plurality of pixel driving circuits in a one-to-one correspondence;

[0051] The encapsulation layer is located on a side of the light-emitting unit away from the pixel driving circuit, and is used to encapsulate the light-emitting unit;

[0052] The upper boundary of the encapsulation layer is located in the upper frame area;

[0053] The first via hole does not overlap with an orthographic projection of the packaging layer on the first flexible substrate.

[0054] In some embodiments, the first conductive layer further comprises a plurality of second patterns located in the display area, and the plurality of second patterns are respectively used as a plate of a storage capacitor in each of the pixel driving circuits;

[0055] The second pattern does not overlap with the orthographic projections of the plurality of first data lines on the first flexible substrate.

[0056] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0058] Figure 1a It is a schematic top view of a structure in which a fan-shaped wiring area of ​​a display panel is arranged in a display area in an embodiment of the present disclosure.

[0059] Figure 1b for Figure 1a Schematic diagram of the enlarged P position.

[0060] Figure 1c for Figure 1b A further enlarged view of the front side of the data signal access area is shown in FIG.

[0061] Figure 1d for Figure 1b A further enlarged view of the back side of the data signal access area is shown in FIG.

[0062] Figure 1e For along Figure 1c Structural section view of the EE' section line.

[0063] Figure 2 A schematic diagram of mura patterns appearing on a display panel when the display panel is tested by a pixel driving circuit lighting test.

[0064] Figure 3It is a schematic diagram showing that the display panel does not have a mura phenomenon when the OLED light-emitting unit is not illuminated by driving the pixel circuit.

[0065] Figure 4 It is a schematic top view of the structure of the display side of another display panel in an embodiment of the present disclosure.

[0066] Figure 5 for Figure 4 A partial enlarged schematic diagram of the first area in the figure.

[0067] Figure 6 For along Figure 4 Structural section view of the AA' cutting line.

[0068] Figure 7 For along Figure 4 Structural section view of the BB' section line.

[0069] Figure 8 For along Figure 4 Structural section view of the CC' section line.

[0070] Fig. 9 Schematic diagram of the top view of the distribution of the first data lines in the second sub-area in the embodiment of the present disclosure.

[0071] Fig.10 It is an enlarged schematic diagram of the third part of the first data lines extending and distributed to the first partition in the embodiment of the present disclosure.

[0072] Fig.11 Schematic diagram of top view of the distribution of first data lines in the first partition in the embodiment of the present disclosure.

[0073] Fig.12 is a circuit diagram of an exemplary pixel driving circuit.

[0074] Fig.13 Schematic diagram of top view of the distribution of the first data lines in the third part of the second partition in the embodiment of the present disclosure.

[0075] Fig.14 For along Figure 4 Structural section view of the DD' section line. DETAILED DESCRIPTION

[0076] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the display panel and the display device provided by the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0077] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as being limited to the embodiments set forth in the present disclosure. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0078] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions, but are not intended to be limiting.

[0079] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0080] In the related art, the display panel usually has a fanout routing area (Fanout routing area), which is located in the non-display area and is used to lead the data signal line from the driving terminal to the display area to provide the corresponding data signal for the pixel driving circuit in the display area. However, this design method in the related art will significantly increase the size of the lower frame, which is not conducive to the realization of an extremely narrow frame.

[0081] In order to solve the above problems, in a first aspect, an embodiment of the present disclosure provides a display panel, referring to Figure 1a , is a schematic diagram of a structure in which a fan-shaped routing area of ​​a display panel is set in the display area in an embodiment of the present disclosure. The fan-shaped routing area of ​​the display panel can be set in the display area, and setting the fan-shaped routing area 110 (i.e., the fanout routing area, i.e., the divergent routing area like a trumpet mouth) of the display panel in the display area 100 is conducive to realizing an extremely narrow frame of the display panel. The fan-shaped routing area 110 is set in the display area 100 by adding a layer of metal routing (i.e., SD0 layer routing 9) to the bottom layer of the backplane of the display panel display area 100. The SD0 layer routing 9 introduces the display data signal of the display panel from the bending area 103 outside the display area 100 (bent to the back of the display panel to be bound and connected with the peripheral circuit located on the back of the display panel) to the display area 100, and the SD0 layer routing 9 in the display area 100 realizes fan-shaped expansion so as to connect the display data signal to each data line 10, and the data line 10 inputs the display data signal into each column of pixels, thereby realizing the display of each column of pixels.

[0082] Reference Figure 1aIn order to ensure that the display data signal transmitted by the data line is close to the driving end and far from the driving end, the access area 111 of the display data signal (i.e., the connection area between the SD0 layer wiring and the data line) is designed to be located in the middle row of pixels along the extension direction of the data line 10 in the display area 100. Assuming that M rows of pixels are arranged in the display area 100, the area where the middle row of pixels is located can be the area where a row of pixels is located in the middle, such as the area where the M / 2 (integer) row of pixels is located, or it can be the area where multiple rows of pixels are located in the middle, such as the area where the M / 2-2 (integer) row, the M / 2-1 (integer) row, the M / 2 (integer) row, and the M / 2+1 (integer) row of pixels are located. Refer to Figure 1b , Figure 1c and Figure 1d , Figure 1b for Figure 1a A magnified schematic diagram of the P position in the middle; Figure 1c for Figure 1b A further enlarged view of the front side of the data signal access area is shown in FIG.

[0083] Figure 1d for Figure 1b A further enlarged view of the back of the data signal access area is shown in FIG. Figure 1c and Figure 1d As can be seen in the figure, the SD0 layer wiring 9 located at the bottom layer is connected to the data line 10 (the data line 10 is covered by the SD0 layer wiring 9) through the via 11.

[0084] In some embodiments, reference Figure 1e , for along Figure 1c The structural section view of the EE' section line. Figure 1c Only the cross-sectional structure of the via 11 can be shown on the cross-sectional surface of the EE' section line in FIG. Figure 1eThe positions of the film layers of the transistor are also schematically shown. In the display area 100, the first flexible substrate 1, the SD0 layer wiring 9, and the second flexible substrate 2 are stacked in sequence, and the active layer 13, the first gate insulating layer 14, the first gate layer 15, the second gate insulating layer 16, the second gate layer 17, the intermediate dielectric layer 18, the SD1 conductive layer 19 and the flat layer 21 are arranged on the side of the second flexible substrate 2 away from the SD0 layer wiring 9; the active layer 13, the first gate insulating layer 14, the first gate layer 15, the second gate insulating layer 16, the second gate layer 17, the intermediate dielectric layer 18, the SD1 conductive layer 19 and the flat layer 21 are arranged away from the second flexible substrate 2 in sequence. In the area where the middle row of pixels where the access area 111 for displaying data signals is located, the data line 10 is located in the SD1 conductive layer 19; the SD0 layer wiring 9 is connected to the second gate layer 17 through vias provided in the second flexible substrate 2, the first gate insulating layer 14, and the second gate insulating layer 16; the second gate layer 17 is connected to the data line 10 located in the SD1 conductive layer 19 through vias provided in the intermediate dielectric layer 18; thus, the connection between the SD0 layer wiring 9 and the data line 10 is realized. The vias provided in the second flexible substrate 2, the first gate insulating layer 14, and the second gate insulating layer 16 and the vias provided in the intermediate dielectric layer 18 together constitute the vias 11 that realize the connection between the SD0 layer wiring 9 and the data line 10.

[0085] In some embodiments, reference Figure 1b , Figure 1c and Figure 1d , the access area 111 for display data signals can be the area where the middle 3-4 rows of pixels are located. In the area where any row of pixels in the middle of the access area 111 for display data signals is located, the vias 11 for connecting the multiple SD0 layer wirings 9 and the multiple data lines 10 in a one-to-one correspondence are not on a straight line, because the setting position of each via 11 needs to avoid overlapping with other conductive film layers except the second gate layer in the orthographic projection direction; and the setting position of each conductive film layer in each pixel area is different, so in the area where any row of pixels in the middle of the access area 111 for display data signals is located, the vias 11 for connecting the multiple SD0 layer wirings 9 and the multiple data lines 10 in a one-to-one correspondence are not on a straight line.

[0086] In some embodiments, reference Figure 1a and Figure 1bThe display panel also includes a reference power supply line 22, which is located in the display area 100; the reference power supply line 22 and the SD0 layer line 9 are located in the same layer, and the reference power supply line 22 is located in an area outside the distribution area of ​​the SD0 layer line 9, and the two are insulated from each other; the reference power supply line 22 is in a grid shape, and the grid-shaped reference power supply line 22 covers the area outside the distribution area of ​​the SD0 layer line 9 in the display area 100. The display panel also includes an anode layer, a pixel definition layer, a light-emitting functional layer and a cathode layer, and the anode layer, the pixel definition layer and the cathode layer are sequentially stacked on the flat layer; an opening is opened in the pixel definition layer, and the light-emitting functional layer is located in the opening; the reference power supply line 22 is connected to the cathode layer through the connecting leads in the frame area around the periphery of the display area 100 to provide a reference power supply for the cathode layer; this can reduce the load and power consumption of the display panel.

[0087] Reference Figure 2 , which is a schematic diagram of mura patterns appearing on the display panel when the pixel driving circuit is turned on for testing; Figure 3 , which is a schematic diagram of the display panel not having a mura phenomenon when the OLED light-emitting unit is not illuminated by the driving pixel circuit; Figure 2 and Figure 3 It can be judged from the test results that the appearance of mura is not caused by the uneven anode of the OLED light-emitting unit, but because the SD0 layer wiring is irregularly arranged under the driving transistor channel area of ​​the pixel driving circuit, which makes the driving transistor channel area uneven, and then causes the width-to-length ratio of the driving transistor channel area to change, so that the driving current of the driving transistor changes, and finally causes the mura phenomenon.

[0088] In order to solve the above-mentioned mura problem, the present disclosure provides a display panel, referring to Figure 1c , Figure 1d and Figure 1eThe display panel includes a display area 100; the display panel also includes a first flexible substrate 1, a second flexible substrate 2 and a plurality of first data lines (i.e., SD0 layer routing lines 9), the plurality of first data lines are located between the stacked first flexible substrate 1 and the second flexible substrate 2; the plurality of first data lines are distributed in the display area 100; the display panel also includes a plurality of pixel driving circuits and a plurality of second data lines (i.e., data lines 10 located in the SD1 conductive layer), located in the display area 100, and the plurality of pixel driving circuits and the plurality of second data lines are located on a side of the second flexible substrate 2 away from the first data lines; the plurality of pixel driving circuits are arranged in an array; the plurality of first data lines are connected to the plurality of second data lines in a one-to-one correspondence; wherein the plurality of first data lines include a portion 90 that is routed along a column direction of the pixel driving circuit array, the pixel driving circuit includes a driving transistor, and the orthographic projection of the portion 90 that is routed along a column direction of the pixel driving circuit array on the first flexible substrate 1 does not overlap with the orthographic projection of the channel region 41 of the driving transistor on the first flexible substrate 1.

[0089] In order to solve the above-mentioned mura problem, the present disclosure provides another display panel. Figure 4 , is a schematic top view of the structure of another display side of a display panel in an embodiment of the present disclosure; Figure 5 for Figure 4 A partial enlarged schematic diagram of the first zone in the middle; Figure 6 For along Figure 4 Structural section view of the AA' section line;

[0090] Figure 7 For along Figure 4 Structural section view of the BB' section line; Figure 8 For along Figure 4 The display panel includes a display area 100; the display panel also includes a first flexible substrate 1, a second flexible substrate 2 and a plurality of first data lines 3, the plurality of first data lines 3 are located between the stacked first flexible substrate 1 and the second flexible substrate 2; the plurality of first data lines 3 are distributed in the display area 100; the display panel also includes a plurality of pixel driving circuits 4 and a plurality of second data lines 5, which are located in the display area 100, and the plurality of pixel driving circuits 4 and the plurality of second data lines 5 are located on a side of the second flexible substrate 2 away from the first data lines 3; the plurality of pixel driving circuits 4 are arranged in an array; the plurality of first data lines 3 are connected to the plurality of second data lines 5 in a one-to-one correspondence; wherein the pixel driving circuit 4 includes a driving transistor, and the orthographic projection of the plurality of first data lines 3 on the first flexible substrate 1 does not overlap with the orthographic projection of the channel region of the driving transistor on the first flexible substrate 1.

[0091] In this embodiment, the display panel may be an organic electroluminescent display panel. The display panel includes a plurality of light-emitting units, and the light-emitting units may be OLED (Organic Light Emitting Diode) light-emitting units. In some embodiments, the OLED light-emitting units are top-emitting units, and the pixel driving circuit 4 is arranged in the entire display area 100. The pixel driving circuit 4 may be a 7T1C (i.e., seven transistors and one capacitor) circuit, a 7T2C circuit, a 6T1C circuit, a 6T2C circuit, or a 9T2C circuit.

[0092] By making the orthographic projections of the plurality of first data lines 3 on the first flexible substrate 1 not overlap with the orthographic projections of the channel region of the driving transistor on the first flexible substrate 1, it is possible to prevent the first data lines 3 from being irregularly routed under the channel region of the driving transistor, thereby preventing the channel region of the driving transistor from being uneven, and then preventing the width-to-length ratio of the channel region of the driving transistor from changing, thereby preventing the driving current of the driving transistor from changing, and ultimately preventing mura defects from occurring during display, thereby ensuring the quality of the display panel.

[0093] In some embodiments, reference Figure 4 and Figure 8 , the display area 100 includes a first area 101 and a second area 102, the first area 101 and the second area 102 are connected; a plurality of first data lines 3 extend from the first area 101 to the second area 102; the display panel also includes a non-display area, the non-display area includes a bending area 103, the bending area 103 is located on a side of the first area 101 away from the second area 102, the bending area 103, the first area 101 and the second area 102 are arranged in sequence along the second direction Y; the second direction Y is the column direction of the pixel driving circuit array; the first area 101 includes a first sub-area 104, a second sub-area 105 and a third sub-area 106, the first sub-area 104, the second sub-area 105 and the third sub-area 106 are arranged in sequence along the first direction X and The first direction X is the row direction of the pixel driving circuit array; the bending area 103 is connected to the second sub-area 105; the first flexible substrate 1, the plurality of first data lines 3 and the second flexible substrate 2 extend from the second sub-area 105 to the bending area 103; the plurality of first data lines 3 in the second sub-area 105 include a first portion 31, a second portion 32 and a third portion 33; the first portion 31, the second portion 32 and the third portion 33 are arranged in sequence along the first direction X; the first portion 31 extends from the second sub-area 105 to the first sub-area 104, the third portion 33 extends from the second sub-area 105 to the third sub-area 106, and the second portion 32 extends from the second sub-area 105 to the second area 102.

[0094] In this embodiment, the first portion 31 , the second portion 32 and the third portion 33 respectively include a plurality of first data lines 3 . Figure 4Only two first data lines 3 in the first part 31, two first data lines 3 in the second part 32 and two first data lines 3 in the third part 33 are schematically drawn. The two first data lines 3 in the first part 31, the second part 32 and the third part 33 can representatively illustrate the direction and distribution of the first data lines 3 in each part.

[0095] Among them, since the connection width between the bending area 103 and the first area 101 is smaller than the connection width between the first area 101 and the bending area 103, the routing of the plurality of first data lines 3 connected from the bending area 103 to the first area 101 is fan-shaped (i.e., fanout distribution, i.e., a divergent distribution like a trumpet mouth), and when the plurality of first data lines 3 are routed from the first area 101 to the second area 102, the fan-shaped distribution is diffused into a uniform distribution. The plurality of first data lines 3 distributed in the first area 101 realize the fan-shaped routing distribution in the display area 100, which greatly reduces the width of the frame area compared to the situation in the public technology where the fan-shaped routing is distributed in the frame area, and is conducive to realizing an extremely narrow frame.

[0096] In this embodiment, the display area 100 is composed of a first area 101 and a second area 102. Figure 1a In the case where the fan-shaped routing is distributed in a partial area of ​​the display area, multiple first data lines 3 are arranged on the entire surface of the display area 100, thereby avoiding uneven routing caused by the fan-shaped routing being distributed only in a partial area of ​​the display area, and improving the distribution uniformity of the fan-shaped routing in the display area 100, thereby improving the display effect of the display panel.

[0097] In some embodiments, reference Fig. 9 , which is a top view schematic diagram of the distribution of the first data lines in the second sub-area in the embodiment of the present disclosure; the drive transistors in the multiple pixel driving circuits are arranged in the same position; the first part 31, the second part 32 and the third part 33 distributed in the second sub-area 105 extend along the second direction Y, and any two adjacent first data lines 3 are symmetrically distributed on opposite sides of a driving transistor channel area 41; in the second sub-area 105, any pixel driving circuit has two first data lines 3 distributed in the orthographic projection area on the first flexible substrate.

[0098] In some embodiments, the orthographic projection area of ​​the pixel driving circuit on the first flexible substrate includes an area surrounded by two adjacent gate lines and two adjacent second data lines 5, and the orthographic projections of the two adjacent second data lines 5 on the first flexible substrate may also fall within the orthographic projection area of ​​the pixel driving circuit.

[0099] In some embodiments, symmetrical distribution means that the positions of the two first data lines 3 are symmetrical. Due to limitations of the manufacturing process, symmetrical distribution includes not only the physically symmetrical arrangement of the two first data lines 3 graphics, but also the incomplete physical symmetry of the two first data lines 3 graphics.

[0100] In some embodiments, reference Figure 4 and Figure 5 , the first sub-area 104 includes a first sub-area 107 and a second sub-area 108; the third sub-area 106 includes a first sub-area 107 and a second sub-area 108; the first sub-area 107 and the second sub-area 108 are arranged in sequence along the first direction X and are connected to each other; the second sub-area 108 is located on a side of the first sub-area 107 away from the second sub-area 105; the first portion 31 extends to the first sub-area 107 of the first sub-area 104; refer to Fig.10 , which is an enlarged schematic diagram of the third part extending to the first partition in the embodiment of the present disclosure; the third part 33 extends to the first partition 107 of the third sub-region 106; the first part 31 includes multiple first data lines 3; the third part 33 includes multiple first data lines 3.

[0101] In some embodiments, reference Fig.10 and Fig.11 , Fig.11 Schematic diagram of the top view of the distribution of the first data lines in the first partition in the embodiment of the present disclosure; the first data lines 3 located in different partitions extend in different directions, for example: the first part and the third part distributed in the first partition 107 extend along the first direction X, and the first data line 3 is located between two adjacent rows of pixel driving circuits 4; in the first partition 107, two first data lines 3 are distributed between any two adjacent rows of pixel driving circuits 4; and the first data line 3 and the channel region 42 of the switching transistor in the pixel driving circuit 4 do not overlap with the orthographic projection on the first flexible substrate.

[0102] In some embodiments, if the pixel driving circuit is a 7T1C circuit, refer to Fig.12, which is a circuit diagram of an exemplary pixel driving circuit; the pixel driving circuit includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7 and a storage capacitor Cst. The drain of the data writing transistor T4 is electrically connected to the source of the driving transistor T3, the source of the data writing transistor T4 is configured to be electrically connected to the data line Data (i.e., the second data line in the embodiment of the present disclosure) to receive the data signal, and the gate of the data writing transistor T4 is configured to be electrically connected to the first scanning signal line Ga1 to receive the scanning signal; the second plate of the storage capacitor Cst is electrically connected to the first power supply voltage line VDD, and the first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3; the source of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, the drain of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3, and the gate of the threshold compensation transistor T2 is configured to be electrically connected to the second scanning signal line Ga2 to receive the compensation control signal; the source of the first reset transistor T1 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, the drain of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the first reset transistor T1 is configured to be electrically connected to the first reset control signal line Rst1 to receive the first reset control signal; the drain of the second reset transistor T7 is configured to be electrically connected to the second reset power supply terminal Vinit2 to receive the first reset signal, the source of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting unit D, and the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the second reset control signal; the source of the first light-emitting control transistor T5 is electrically connected to the first power supply voltage line VDD, the drain of the first light-emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal; the source of the second light-emitting control transistor T6 is electrically connected to the drain of the driving transistor T3, the drain of the second light-emitting control transistor T6 is electrically connected to the first electrode D1 of the light-emitting unit D, and the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal; the second electrode of the light-emitting unit D is electrically connected to the second power supply terminal VSS (i.e., the reference power supply wiring in the embodiment of the present disclosure).

[0103] Among them, the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6 and the second reset transistor T7 are all switch transistors.

[0104] In some embodiments, if the pixel driving circuit 4 is a 7T1C circuit, the switch transistor in the pixel driving circuit 4 may refer to a first reset transistor T1, a threshold compensation transistor T2, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second reset transistor T7. The channel regions 42 of the first reset transistor T1, the threshold compensation transistor T2, the first light emission control transistor T5, and the second light emission control transistor T6 are located near the boundary region of two adjacent rows of pixel driving circuits 4, so the first data line 3 is prevented from overlapping with the orthographic projection of the channel regions 42 of the switch transistors T5, T6, T1, and T2 in the pixel driving circuit 4 on the first flexible substrate. By making the orthographic projections of the first data line 3 and the channel region 42 of the switching transistor in the pixel driving circuit 4 not overlap on the first flexible substrate, it is possible to prevent the first data line 3 from being irregularly routed under the channel region 42 of the switching transistor, thereby preventing the channel region 42 of the switching transistor from being uneven, and then preventing the width-to-length ratio of the channel region 42 of the switching transistor from changing, thereby preventing the switching performance of the switching transistor from changing, and ultimately preventing mura defects when the display panel is turned on when the driving transistor does not perform threshold compensation and when the display panel is tested for lighting, thereby ensuring the quality of the display panel.

[0105] In some embodiments, reference Fig.11 The display panel further includes a plurality of redundant routing lines 6, which are located in the first partition 107 and arranged in an array; the plurality of redundant routing lines 6 extend along the second direction Y, and any two adjacent redundant routing lines 6 along the first direction X are symmetrically distributed on opposite sides of a driving transistor channel region 41; in the first partition 107, any pixel driving circuit 4 has two redundant routing lines 6 distributed in the orthographic projection area on the first flexible substrate; each row of redundant routing lines 6 is connected to a first data line 3 extending along the first direction X; the orthographic projections of each row of redundant routing lines 6 on the first flexible substrate do not overlap with those of other first data lines 3 extending along the first direction X; the length of each redundant routing line 6 does not exceed the length of the orthographic projection area of ​​the pixel driving circuit 4 on the first flexible substrate along the second direction Y.

[0106] In some embodiments, the first data line 3 in the first partition 107 is a horizontal line extending along the first direction X, and the first data line 3 of the horizontal line in the first partition 107 is perpendicular to the first data line 3 of the vertical line extending along the second direction Y in the second sub-region 105, which will cause the first data line 3 to have an uneven routing phenomenon in the overall perception of the first region 101; by setting a redundant routing line 6 in the first partition 107, that is, adding a vertical redundant routing line 6 on the basis of the horizontal routing in the first partition 107, the phenomenon of uneven routing in the overall perception of the first region 101 can be reduced, and the redundant routing line 6 is similar to the routing line of the second sub-region 105, and also avoids the channel region 41 of the driving transistor, and is symmetrically distributed on opposite sides of the channel region 41 of the driving transistor, so as to avoid the occurrence of mura during the lighting test. Each row of redundant routing lines 6 is connected to a first data line 3 extending along the first direction X, so as to prevent the redundant routing line 6 from causing signal crosstalk to the first data line 3 when it is suspended.

[0107] In some embodiments, reference Figure 4 , Figure 5 and Fig.13 , Fig.13 3 is a top view schematic diagram of the distribution of the third part of the first data line in the second partition in the embodiment of the present disclosure; the first part 31 also extends to the second partition 108 of the first sub-region 104; the third part 33 also extends to the second partition 108 of the third sub-region 106.

[0108] In some embodiments, the first portion 31 and the third portion 33 distributed in the second partition 108 extend along the second direction Y, and any two adjacent first data lines 3 along the first direction X are symmetrically distributed on opposite sides of a driving transistor channel region 41; in the second partition 108, any pixel driving circuit 4 has two first data lines 3 distributed within the orthographic projection area on the first flexible substrate.

[0109] In some embodiments, reference Figure 4 and Fig.13 , the width of the connecting portion between the first area 101 and the second area 102 is equal to the width of the second area 102 along the first direction X; the first portion 31 also extends to the second area 102; and the third portion 33 also extends to the second area 102.

[0110] In some embodiments, the first portion 31, the second portion 32, and the third portion 33 distributed in the second area 102 are arranged in sequence along the first direction X, and the first portion 31, the second portion 32, and the third portion 33 extend along the second direction Y respectively; the plurality of second data lines 5 are arranged in sequence along the first direction X, and the plurality of second data lines 5 extend along the second direction Y; in the second area 102, any pixel driving circuit 4 has a first data line 3 distributed in the orthographic projection area on the first flexible substrate; and the orthographic projections of the plurality of first data lines 3 and the plurality of second data lines 5 on the first flexible substrate overlap one by one. In this way, the first data lines 3 located in the lower layer are conveniently connected to the second data lines 5 located in the upper layer.

[0111] In some embodiments, since the plurality of first data lines 3 in the first area 101 are distributed in a fan shape, the distribution density of the first data lines 3 in the first area 101 is greater than the distribution density of the first data lines 3 in the second area 102 .

[0112] In some embodiments, reference Figure 4 and Fig.14 , Fig.14 For along Figure 4 The non-display area further comprises an upper frame area 109, which is located on a side of the second area 102 away from the first area 101, and the upper frame area 109 is connected to the second area 102; the first flexible substrate 1, the plurality of first data lines 3 and the second flexible substrate 2 also extend from the second area 102 to the upper frame area 109; the pixel driving circuit 4 comprises a first conductive layer and a second conductive layer, which are sequentially arranged away from the second flexible substrate 2; an insulating layer 7 is arranged between the first conductive layer and the second conductive layer; the first conductive layer comprises a plurality of first graphics 8, and the orthographic projections of the plurality of first graphics 8 on the first flexible substrate 1 extend from the upper frame area 109 to the second area 102; the plurality of first data lines 3 located in the upper frame area 109 are connected to the plurality of first graphics 8 one by one through the first via holes 20 provided in the second flexible substrate 2; the second conductive layer comprises a plurality of second data lines 5; the plurality of first graphics 8 located in the second area 102 are connected to the plurality of second data lines 5 one by one through the second via holes 70 provided in the insulating layer 7. In this way, the plurality of first data lines 3 are arranged in the entire display area 100 , thereby improving the distribution uniformity of the plurality of first data lines 3 in the display area 100 , and further improving the display effect of the display panel.

[0113] In some embodiments, the first conductive layer also includes multiple second graphics (not shown in the figure), which are located in the display area, and the multiple second graphics are respectively used as a plate of a storage capacitor in each pixel driving circuit; the second graphics do not overlap with the orthographic projection of the multiple first data lines on the first flexible substrate.

[0114] In some embodiments, the pixel driving circuit includes an active layer, a first gate layer, a first conductive layer, and a second conductive layer, wherein the active layer, the first gate layer, the first conductive layer, and the second conductive layer are sequentially arranged away from the second flexible substrate, and any adjacent two layers are insulated from each other by an inorganic insulating layer. The active layer includes patterns of a channel region of a driving transistor and a channel region of a switching transistor; the first gate layer includes patterns of a gate line, a gate of a driving transistor, and a gate of a switching transistor; wherein the gate of the driving transistor is used as a plate of a storage capacitor in the pixel driving circuit; the first conductive layer includes a first pattern 8 and a second pattern, wherein the second pattern is used as another plate of a storage capacitor in the pixel driving circuit, that is, the second pattern overlaps with the positive projection of the gate of the driving transistor on the first flexible substrate, and the second pattern and the gate of the driving transistor constitute a storage capacitor. The second conductive layer includes patterns of a plurality of second data lines 5 and patterns of source and drain electrodes of the driving transistor and the switching transistor in the pixel driving circuit.

[0115] In some embodiments, reference Figure 4 and Fig.14 The display panel further includes a plurality of light-emitting units and an encapsulation layer 12. The plurality of light-emitting units are located in the display area 100 and are located on the side of the pixel driving circuit away from the second flexible substrate. The plurality of light-emitting units are arranged in an array, and the plurality of light-emitting units are connected to the plurality of pixel driving circuits one by one. The encapsulation layer 12 is located on the side of the light-emitting unit away from the pixel driving circuit, and is used to encapsulate the light-emitting unit. The upper boundary S of the encapsulation layer 12 is located in the upper frame area 109. The first via hole 20 does not overlap with the orthographic projection of the encapsulation layer on the first flexible substrate. That is, the first via hole 20 is located outside the upper boundary S of the encapsulation layer.

[0116] In some embodiments, the light emitting unit is an organic electroluminescent unit, ie, an OLED (Organic Light Emitting Diode) light emitting unit.

[0117] The display panel provided by the embodiment of the present disclosure can improve or avoid irregular routing of the first data lines under the channel region of the driving transistor by making the orthographic projection of at least the portion of the plurality of first data lines routed along the column direction of the pixel driving circuit array not overlap with the orthographic projection of the channel region of the driving transistor on the first flexible substrate, thereby improving or avoiding unevenness of the channel region of the driving transistor, and then improving or avoiding changes in the width-to-length ratio of the channel region of the driving transistor, so as to improve or avoid changes in the driving current of the driving transistor, and finally improving or avoiding mura defects when the display panel is turned on when the driving transistor does not perform threshold compensation and when the display panel is tested for lighting, thereby ensuring the quality of the display panel.

[0118] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display panel in the above embodiment.

[0119] By adopting the display panel in the above embodiment, it is possible to avoid mura defects in the display device during lighting test, thereby ensuring the quality of the display device.

[0120] The display device may be any product or component having a display function, such as an OLED panel, an OLED TV, a mobile phone, a tablet computer, a notebook computer, a display, a digital photo frame, a navigator, or the like.

[0121] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel comprising a display area; The display panel further includes a first flexible substrate, a second flexible substrate and a plurality of first data lines. The plurality of first data lines are located between the stacked first flexible substrate and the second flexible substrate; the plurality of first data lines are distributed in the display area; The display panel further includes a plurality of pixel driving circuits and a plurality of second data lines, which are located in the display area, and the plurality of pixel driving circuits and the plurality of second data lines are located on a side of the second flexible substrate away from the first data lines; The plurality of pixel driving circuits are arranged in an array; the plurality of first data lines are connected to the plurality of second data lines in a one-to-one correspondence; in, The plurality of first data lines include portions that are routed in a column direction of a pixel driving circuit array, the pixel driving circuit includes a driving transistor, and an orthographic projection of at least the portions of the plurality of first data lines that are routed in a column direction of the pixel driving circuit array on the first flexible substrate does not overlap with an orthographic projection of a channel region of the driving transistor on the first flexible substrate.

2. The display panel according to claim 1, wherein: The display area includes a first area and a second area, and the first area and the second area are connected; The display panel further includes a non-display area, the non-display area includes a bending area, the bending area is located on a side of the first area away from the second area, the bending area, the first area and the second area are arranged in sequence along a second direction; the second direction is a column direction of the pixel driving circuit array; The first area includes a first sub-area, a second sub-area and a third sub-area, and the first sub-area, the second sub-area and the third sub-area are arranged in sequence along a first direction and connected to each other; the first direction is a row direction of the pixel driving circuit array; The bending area is connected to the second sub-area; The first flexible substrate, the plurality of first data lines and the second flexible substrate extend from the second sub-region to the bending region; The plurality of first data lines in the second sub-area include a first portion, a second portion and a third portion; the first portion, the second portion and the third portion are arranged in sequence along the first direction; The first portion extends from the second sub-region to the first sub-region, the third portion extends from the second sub-region to the third sub-region, and the second portion extends from the second sub-region to the second region.

3. The display panel according to claim 2, wherein: The first portion, the second portion and the third portion distributed in the second sub-region extend along the second direction, and any two adjacent first data lines are symmetrically distributed on two opposite sides of a channel region of the driving transistor; In the second sub-area, two first data lines are distributed within the orthographic projection area of ​​any one of the pixel driving circuits on the first flexible substrate.

4. The display panel according to claim 3, wherein: The first sub-area includes a first partition and a second partition; the third sub-area includes a first partition and a second partition; The first sub-area and the second sub-area are arranged in sequence along the first direction and are connected to each other; the second sub-area is located on a side of the first sub-area away from the second sub-area; The first portion extends to the first subarea of ​​the first subarea; The third portion extends to the first sub-area of ​​the third sub-area; The first portion includes a plurality of the first data lines; The third portion includes a plurality of the first data lines.

5. The display panel according to claim 4, wherein: The first part and the third part distributed in the first partition extend along the first direction, and the first data line is located between two adjacent rows of pixel driving circuits; In the first partition, two first data lines are distributed between any two adjacent rows of the pixel driving circuits; and the first data lines and the orthographic projections of the channel regions of the switching transistors in the pixel driving circuits on the first flexible substrate do not overlap.

6. The display panel according to claim 5, wherein: Also included are a plurality of redundant routing lines located in the first partition and arranged in an array; The plurality of redundant routing lines extend along the second direction, and any two adjacent redundant routing lines along the first direction are symmetrically distributed on opposite sides of a channel region of a driving transistor; In the first partition, any one of the pixel driving circuits has two redundant wirings distributed in an orthographic projection area on the first flexible substrate; Each row of the redundant routing lines is connected to a first data line extending along the first direction; each row of the redundant routing lines does not overlap with the orthographic projections of other first data lines extending along the first direction on the first flexible substrate; The length of each of the redundant wirings does not exceed the length of an orthographic projection area of ​​the pixel driving circuit on the first flexible substrate along the second direction.

7. The display panel according to any one of claims 4 to 6, wherein: The first portion also extends to the second sub-area of ​​the first sub-area; The third portion also extends to the second sub-area of ​​the third sub-region.

8. The display panel according to claim 7, wherein: The first part and the third part distributed in the second partition extend along the second direction, and any two adjacent first data lines along the first direction are symmetrically distributed on opposite sides of a channel region of the driving transistor; In the second partition, two first data lines are distributed within the orthographic projection area of ​​any one of the pixel driving circuits on the first flexible substrate.

9. The display panel according to claim 7, wherein: The width of the connecting portion between the first region and the second region is equal to the width of the second region along the first direction; The first portion also extends to the second area; The third portion also extends to the second region.

10. The display panel according to claim 9, wherein: The first portion, the second portion and the third portion distributed in the second area are arranged in sequence along the first direction, and the first portion, the second portion and the third portion extend along the second direction respectively; The plurality of second data lines are sequentially arranged along the first direction, and the plurality of second data lines extend along the second direction; In the second area, one first data line is distributed in the orthographic projection area of ​​any one of the pixel driving circuits on the first flexible substrate; and the orthographic projections of the plurality of first data lines overlap with the orthographic projections of the plurality of second data lines on the first flexible substrate in a one-to-one correspondence.

11. The display panel according to claim 10, wherein: The non-display area further includes an upper frame area located on a side of the second area away from the first area, and the upper frame area is connected to the second area; The first flexible substrate, the plurality of first data lines and the second flexible substrate further extend from the second area to the upper frame area; The pixel driving circuit comprises a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are sequentially arranged away from the second flexible substrate; an insulating layer is arranged between the first conductive layer and the second conductive layer; The first conductive layer includes a plurality of first graphics, and the orthographic projections of the plurality of first graphics on the first flexible substrate extend from the upper frame area to the second area; The plurality of first data lines located in the upper frame area are connected to the plurality of first graphics one by one through first via holes provided in the second flexible substrate; The second conductive layer includes the plurality of second data lines; The plurality of first patterns located in the second region are connected to the plurality of second data lines one by one through second via holes opened in the insulating layer.

12. The display panel according to claim 11, wherein: It also includes a plurality of light-emitting units and an encapsulation layer, The plurality of light emitting units are located in the display area and on a side of the pixel driving circuit away from the second flexible substrate; The plurality of light-emitting units are arranged in an array, and the plurality of light-emitting units are connected to the plurality of pixel driving circuits in a one-to-one correspondence; The encapsulation layer is located on a side of the light-emitting unit away from the pixel driving circuit, and is used to encapsulate the light-emitting unit; The upper boundary of the encapsulation layer is located in the upper frame area; The first via hole does not overlap with an orthographic projection of the packaging layer on the first flexible substrate.

13. The display panel according to claim 11, wherein: The first conductive layer further comprises a plurality of second patterns located in the display area, and the plurality of second patterns are respectively used as a plate of a storage capacitor in each of the pixel driving circuits; The second pattern does not overlap with the orthographic projections of the plurality of first data lines on the first flexible substrate.

14. A display device, wherein: A display panel comprising any one of claims 1-13.

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