Data reading method and circuit of memory and memory

Abstract

The application discloses a data reading method and circuit of a memory and the memory, wherein the method comprises the following steps: obtaining a stable voltage value, and pre-charging a main path and each of a plurality of first bypasses of a reading circuit according to the stable voltage value, and sampling a current of the main path and a corresponding first bypass to obtain a corresponding current value; receiving a control signal, and controlling the main path and the corresponding first bypass to conduct a branch path according to the control signal, so as to obtain a corresponding current difference value according to the current value of the main path and the corresponding first bypass, obtain a corresponding voltage difference value according to the current difference value, latch a data reading result of a group of outputs according to the voltage difference value, and repeat the above steps until the data reading result of the main path and each of the plurality of first bypasses is obtained; thus, the reading effect of reducing the peak current and improving the parallel speed is achieved by pre-charging and switching the path to generate the current difference.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a data reading method of a memory, a data reading circuit of a memory, and a memory. Background Art

[0002] In the related art, there are generally two methods for using sense amplifiers (SA) for input and output (IO) reading in existing in-memory arithmetic memory macros. First, using a large number of sense amplifiers for IO reading can achieve a shorter read time, but will result in a larger peak current and larger area loss. Second, using a smaller number of sense amplifiers for sequential reading can reduce peak current and area loss, but will result in a longer read time. Summary of the Invention

[0003] The present invention aims to at least partially address one of the technical problems in the above-mentioned technologies. To this end, one object of the present invention is to provide a method for reading data from a memory device, which reduces peak current and increases parallel speed by generating a current difference through precharging and switching paths.

[0004] A second objective of the present invention is to provide a data reading circuit for a memory.

[0005] A third object of the present invention is to provide a memory.

[0006] To achieve the above-mentioned object, a first embodiment of the present invention provides a method for reading data from a memory, comprising the following steps:

[0007] S1, obtaining a stable voltage value, and pre-charging a main path of a reading circuit and each of a plurality of first bypass paths according to the stable voltage value;

[0008] S2, sampling current of the main circuit and a corresponding first bypass circuit to obtain corresponding current values;

[0009] S3, receiving a control signal, and controlling the main path and the corresponding first bypass path to conduct branches according to the control signal, so as to obtain a corresponding current difference according to the current values ​​of the main path and the corresponding first bypass path;

[0010] S4, obtaining a corresponding voltage difference according to the current difference, so as to latch the voltage difference into a set of output data reading results;

[0011] S5, repeating steps S2-S4 to obtain data reading results of the main path and each of the plurality of first bypass paths.

[0012] According to a data reading method of a memory according to an embodiment of the present invention, first, a stable voltage value is obtained, and a main path of a reading circuit and each of a plurality of first bypass paths are precharged according to the stable voltage value. Next, current sampling is performed on the main path and a corresponding first bypass to obtain a corresponding current value. Then, a control signal is received, and the main path and a corresponding first bypass are controlled to conduct branches according to the control signal, so as to obtain a corresponding current difference according to the current value of the main path and the corresponding first bypass. Next, a corresponding voltage difference is obtained according to the current difference, so as to latch a data reading result into a group of outputs according to the voltage difference. Finally, the above steps are repeated until the data reading results of the main path and each of the plurality of first bypass paths are obtained. Thus, the reading effect of reducing the peak current and increasing the parallel speed is achieved by precharging and switching the paths to generate a current difference.

[0013] In addition, the data reading method of the memory proposed in the above embodiment of the present invention may also have the following additional technical features:

[0014] Optionally, the main path corresponds to a reference current, and each of the multiple first bypass paths corresponds to a source line current.

[0015] Optionally, the reference current and the source line current are pre-charged so that their voltage values ​​reach a stable voltage value.

[0016] Optionally, the main circuit and the corresponding first bypass conduction branch are controlled according to the control signal so as to obtain a corresponding current difference according to the current values ​​of the main circuit and the corresponding first bypass, including: controlling the main circuit conduction branch according to the first control signal so that the current generated at its first end is a reference current value and the current generated at its second end is a source line current value, so as to obtain a first current difference between the two ends of the first node; controlling the corresponding first bypass conduction branch according to the second control signal so that the current generated at its first end is a source line current value and the current generated at its second end is a reference current value, so as to obtain a second current difference between the two ends of the second node.

[0017] Optionally, obtaining a corresponding voltage difference based on the current difference includes: multiplying the first current difference by the time for obtaining the current difference, and then dividing it by the capacitance value of the first node to obtain the voltage difference of the first node; multiplying the second current difference by the time for obtaining the current difference, and then dividing it by the capacitance value of the second node to obtain the voltage difference of the second node.

[0018] Optionally, when a data reading result is latched into a group of outputs according to the voltage difference, the reference current is provided by a second bypass.

[0019] To achieve the above-mentioned purpose, a data reading circuit of a memory proposed in an embodiment of the second aspect of the present invention includes: a pre-charging unit, wherein the pre-charging unit is used to obtain a stable voltage value and pre-charge the main path and each of the multiple first bypasses in the reading circuit according to the stable voltage value; a sampling unit, wherein the sampling unit is used to sample the current of the main path and the corresponding first bypass to obtain the corresponding current value; a control unit, wherein the control unit is used to receive a control signal and control the main path and the corresponding first bypass to conduct the branch according to the control signal, so as to obtain a corresponding current difference according to the current value of the main path and the corresponding first bypass; and a latch unit, wherein the latch unit is used to obtain a corresponding voltage difference according to the current difference, so as to latch the data reading result into a group of outputs according to the voltage difference.

[0020] According to a data reading circuit of a memory according to an embodiment of the present invention, a pre-charging unit is provided for obtaining a stable voltage value, and pre-charging a main path and each of a plurality of first bypass paths in the reading circuit according to the stable voltage value; a sampling unit is used for sampling current of the main path and a corresponding first bypass to obtain a corresponding current value; a control unit is used for receiving a control signal, and controlling the main path and a corresponding first bypass to conduct branches according to the control signal, so as to obtain a corresponding current difference according to the current value of the main path and the corresponding first bypass; a latch unit is used for obtaining a corresponding voltage difference according to the current difference, so as to latch a data reading result into a group of outputs according to the voltage difference; thereby, the reading effect of reducing peak current and improving parallel speed is achieved by generating a current difference through pre-charging and switching paths.

[0021] To achieve the above-mentioned purpose, the third embodiment of the present invention proposes a memory, including a data reading circuit of the memory as described above; thereby, the reading effect of reducing peak current and increasing parallel speed is achieved by generating current difference through precharging and switching paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a flow chart of a method for reading data from a memory according to an embodiment of the present invention;

[0023] Figure 2 A circuit schematic diagram of a data reading circuit of a memory according to an embodiment of the present invention;

[0024] Figure 3 A circuit schematic diagram of a pre-charging link of a data reading circuit of a memory according to an embodiment of the present invention;

[0025] Figure 4 A circuit schematic diagram of a current sampling link of a data reading circuit of a memory according to an embodiment of the present invention;

[0026] Figure 5 A circuit schematic diagram of a current difference generating link of a data reading circuit of a memory according to an embodiment of the present invention;

[0027] Figure 6 A circuit schematic diagram of a latch output link of a data reading circuit of a memory according to an embodiment of the present invention;

[0028] Figure 7 A circuit schematic diagram of a data reading circuit of a memory according to an embodiment of the present invention repeatedly executing other bypass links;

[0029] Figure 8 FIG. 1 is a waveform diagram of a data reading circuit of a memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0031] In related technologies, multi-array read verification typically uses multiple parallel or multiplexed circuits. This results in significant area loss while significantly increasing the circuit's duty cycle. Furthermore, precharging the array circuit requires a long current sampling time and high peak current stabilization, which are important considerations for circuit performance, power consumption, and area.

[0032] To this end, the present invention proposes a data reading method for a memory, which precharges the array with a target SL voltage in the standby state, can reduce peak current, and does not require precharging the SL parasitic capacitance from ground to the SL reading voltage. At the same time, it has multiple bypass paths to enable multiple SLs to be precharged simultaneously, reducing time overhead; and uses the SA part as a common, sharing the SA and reference current, which can complete multi-bit result output within one cycle and reduce circuit area.

[0033] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0034] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0035] like Figure 2 As shown, the data reading circuit of the memory includes three PMOS tubes (P0-P2) and two capacitors (C0-C1), two switches SW, a gated SAEN controlled cross-coupled N-latch (NS2-NS4), a non-gated N-latch (NS0-NS1), three SL voltage clamping transistors (NC0-NC2) and five NMOS tube path switches (N0-N4), and the bypass circuit Input-switch-1 (IS1) / IS2 / IS3 includes a pre-charge PMOS tube P3, a clamping NMOS tube NC3 and three path switches (N5-N7).

[0036] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for reading data from a memory according to an embodiment of the present invention. Figure 1 As shown, the data reading method of the memory includes the following steps:

[0037] S1 , obtaining a stable voltage value, and precharging a main path of a reading circuit and each of a plurality of first bypass paths according to the stable voltage value.

[0038] That is, the main path of the reading circuit and each of the multiple first bypass paths are precharged simultaneously according to the stable voltage value, thereby reducing the current sampling time of the array unit, further shortening the reading time, and achieving a 20% speed improvement.

[0039] As an embodiment, the working principle diagram of the reading circuit corresponding to the above steps is as follows: Figure 3 As shown, the control switch SW is closed, and a switch control signal is applied to the gate SG of the NMOS transistor N0 and the gate S0 of the NMOS transistor N3 to control the NMOS transistor N0 and the NMOS transistor N3 to be turned on, and the path switch N7 in the three bypass circuits is turned on, so that the five paths are pre-charged at the same time.

[0040] As an embodiment, the main circuit corresponds to the reference current I REF , each of the multiple first bypasses corresponds to the source line current I SL .

[0041] It should be noted that if Figure 2 As shown, this embodiment includes 4 first bypasses, each corresponding to a source line current of I SL<0> , I SL<1> , I SL<2> and ISL<3> The first bypass can be increased or decreased according to actual needs, and the present invention does not make specific limitations on this.

[0042] As an embodiment, the reference current and the source line current are precharged so that their voltage values ​​reach a stable voltage value.

[0043] That is to say, in the pre-charge stage, the reference current I REF and source line current I SL<0> , I SL<1> , I SL<2> , I SL<3> Precharge to a stable voltage value for current mode sensing, where the stable voltage value is the value fed back by other circuits.

[0044] S2, sampling currents of the main circuit and a corresponding first bypass circuit to obtain corresponding current values.

[0045] As an example, Figure 4 As shown, it is a working principle diagram of the reading circuit corresponding to this step, wherein the control switch SW is disconnected, and the switch control signal is applied to the gate SG of the NMOS transistor N0 and the gate S0 of the NMOS transistor N3 to control the NMOS transistor N0 and the NMOS transistor N3 to be turned on, thereby REF and source line current I SL<0> The gate-source voltage is stored by capacitor C0-C1 and PMOS tube P0-P1.

[0046] S3, receiving a control signal, and controlling the main circuit and a corresponding first bypass circuit to conduct branches according to the control signal, so as to obtain a corresponding current difference according to the current values ​​of the main circuit and the corresponding first bypass circuit.

[0047] As an embodiment, the main circuit conduction branch is controlled according to the first control signal so that the current generated at its first end is a reference current value and the current generated at its second end is a source line current value, so as to obtain a first current difference between the two ends of the first node; and the corresponding first bypass conduction branch is controlled according to the second control signal so that the current generated at its first end is a source line current value and the current generated at its second end is a reference current value, so as to obtain a second current difference between the two ends of the second node.

[0048] As a specific embodiment, Figure 5 As shown, it is a working principle diagram of the reading circuit corresponding to this step, wherein, through the above steps, the capacitors C0-C1 are used to make the PMOS tubes P0-P1 remember the reference current I REF and source line current I SL<0>Therefore, in this step, it is only necessary to apply the control signal to the gate SR of the NMOS tube N1 and the gate S1 of the NMOS tube N2 to control the NMOS tube N1 and the NMOS tube N2 to be turned on, so that the first node Q L and the second node Q R The upper and lower ends have different currents, thereby obtaining a corresponding current difference.

[0049] S4, obtaining a corresponding voltage difference according to the current difference, so as to latch the voltage difference into a set of output data reading results.

[0050] As an embodiment, obtaining a corresponding voltage difference based on the current difference includes: multiplying the first current difference by the time to obtain the first current difference, and then dividing it by the capacitance value of the first node to obtain the voltage difference of the first node; multiplying the second current difference by the time to obtain the second current difference, and then dividing it by the capacitance value of the second node to obtain the voltage difference of the second node.

[0051] That is, the first node Q is obtained according to the following formula L and the second node Q R The corresponding voltage difference is:

[0052]

[0053]

[0054] It should be noted that the signal margin is amplified to twice the traditional level by generating a current difference through switching paths.

[0055] In addition, as an example, Figure 6 As shown in FIG, it is a working principle diagram of a reading circuit corresponding to a data reading result latched into a group of outputs according to a voltage difference, wherein the voltage difference can be judged according to an existing latch table, thereby outputting a group of 1 or 0 to complete the data reading. For example, if Less than The output is 1 if Greater than The output result is 0.

[0056] As an embodiment, when a data reading result is latched into a group of outputs according to the voltage difference, the reference current is provided by the second bypass.

[0057] like Figure 6 As shown, when the gated SAEN controls the cross-coupled N-latch (NS2-NS4) and the non-gated N-latch (NS0-NS1) works, the NMOS tube path switch N4 in the second bypass is turned on to provide a reference current I REF , thus avoiding the reference voltage from decreasing.

[0058] S5, repeating steps S2-S4 to obtain data reading results of the main path and each of the plurality of first bypass paths.

[0059] As an example, Figure 7 As shown, after the voltage difference is latched into a set of results 1 or 0, the bypass SL is turned on in sequence. <1> -SL <3> , continue to repeat steps S2-S4 to obtain a result 1 or 0 corresponding to each bypass, and finally obtain 4 results corresponding to 4 SLs.

[0060] In addition, the complete waveform diagram of each stage in the memory data reading circuit is as follows Figure 8 As shown, it can be seen from the waveform that QL and QR can correctly output the differential 1 and 0 results when the SAEN signal is turned on.

[0061] In summary, the memory data reading method of the present invention reduces the current sampling time of array cells through precharging, further shortening the reading time and achieving a 20% speed improvement. Sequential switching for reading within the same system time period shares the SA and reference current, achieving a small area while reducing peak current, with area and peak current improvements of 40% and 43.8%, respectively. Cells not switched for reading perform current sampling in branch circuits, achieving a preparatory effect before switching, improving reading speed and reducing energy consumption. The signal margin is amplified to twice the traditional level by generating a current difference through switching paths.

[0062] In order to implement the above embodiment, the embodiment of the present invention further proposes a data reading circuit of a memory, such as Figure 2-7 As shown, the data reading circuit of the memory includes: a pre-charging unit 201 , a sampling unit 202 , a control unit 203 and a latch unit 204 .

[0063] Among them, the pre-charging unit 201 is used to obtain a stable voltage value, and pre-charge the main path and each of the multiple first bypasses in the reading circuit according to the stable voltage value; the sampling unit 202 is used to sample the current of the main path and the corresponding first bypass to obtain the corresponding current value; the control unit 203 is used to receive a control signal, and control the main path and the corresponding first bypass to conduct the branch according to the control signal, so as to obtain the corresponding current difference according to the current value of the main path and the corresponding first bypass; the latch unit is used to obtain the corresponding voltage difference according to the current difference, so as to latch the data reading result into a group of outputs according to the voltage difference.

[0064] It should be noted that the above description of the data reading method of the memory is also applicable to the data reading circuit of the memory, and will not be repeated here.

[0065] In summary, according to a data reading circuit of a memory device according to an embodiment of the present invention, a pre-charging unit is provided for obtaining a stable voltage value, and pre-charging the main path and each of the multiple first bypasses in the reading circuit according to the stable voltage value; the sampling unit is used to sample the current of the main path and the corresponding first bypass to obtain the corresponding current value; the control unit is used to receive a control signal, and control the main path and the corresponding first bypass to conduct the branch according to the control signal, so as to obtain the corresponding current difference according to the current value of the main path and the corresponding first bypass; the latch unit is used to obtain the corresponding voltage difference according to the current difference, so as to latch the data reading result into a group of outputs according to the voltage difference; thereby, the reading effect of reducing the peak current and increasing the parallel speed is achieved by generating a current difference through pre-charging and switching paths.

[0066] In addition, an embodiment of the present invention further proposes a memory including a data reading circuit of the memory as described above; the memory according to the embodiment of the present invention achieves the reading effect of reducing peak current and increasing parallel speed by generating current difference through precharging and switching paths.

[0067] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0068] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0069] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0070] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0071] It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claim. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third etc. does not indicate any order. These words may be interpreted as names.

[0072] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0073] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

[0074] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0075] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0076] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0077] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0078] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A method for reading data from a memory, characterized in that: The method comprises: S1, obtaining a stable voltage value, and pre-charging a main path of a reading circuit and each of a plurality of first bypass paths according to the stable voltage value; S2, sampling current of the main circuit and a corresponding first bypass circuit to obtain corresponding current values; S3, receiving a control signal, and controlling the main path and the corresponding first bypass path to conduct branches according to the control signal, so as to obtain a corresponding current difference according to the current values ​​of the main path and the corresponding first bypass path; S4, obtaining a corresponding voltage difference according to the current difference, so as to latch the voltage difference into a set of output data reading results; S5, repeating steps S2-S4 to obtain data reading results of the main path and each of the plurality of first bypass paths; The step of controlling the main circuit and the corresponding first bypass circuit to conduct branches according to the control signal so as to obtain a corresponding current difference according to current values ​​of the main circuit and the corresponding first bypass circuit includes: Controlling the main circuit to conduct the branch circuit according to the first control signal so that the current generated at the first end is a reference current value and the current generated at the second end is a source line current value, so as to obtain a first current difference between the two ends of the first node; According to the second control signal, the corresponding first bypass conductive branch is controlled so that the current generated at the first end is the source line current value and the current generated at the second end is the reference current value, so as to obtain a second current difference between the two ends of the second node.

2. The method for reading data from a memory according to claim 1, wherein: The main path corresponds to a reference current, and each of the plurality of first bypass paths corresponds to a source line current.

3. The method for reading data from a memory according to claim 2, wherein: The reference current and the source line current are precharged so that their voltage values ​​reach a stable voltage value.

4. The method for reading data from a memory according to claim 1, wherein: Obtaining a corresponding voltage difference according to the current difference includes: multiplying the first current difference by the time of obtaining the current difference, and then dividing the result by the capacitance value of the first node to obtain a voltage difference at the first node; The second current difference is multiplied by the time for obtaining the current difference, and the resultant value is divided by the capacitance value of the second node to obtain the voltage difference of the second node.

5. The method for reading data from a memory according to claim 4, wherein: When a data reading result is latched into a group of outputs according to the voltage difference, the reference current is provided by the second bypass.

6. A data reading circuit for a memory, characterized in that: include: a pre-charging unit, the pre-charging unit being configured to obtain a stable voltage value and pre-charge a main path and each of a plurality of first bypass paths in the reading circuit according to the stable voltage value; a sampling unit, configured to sample currents of the main circuit and a corresponding first bypass circuit to obtain corresponding current values; a control unit, the control unit being configured to receive a control signal and control the main circuit and a corresponding first bypass circuit to conduct branches according to the control signal, so as to obtain a corresponding current difference according to current values ​​of the main circuit and the corresponding first bypass circuit; a latch unit, the latch unit being configured to obtain a corresponding voltage difference according to the current difference, so as to latch a data reading result into a set of outputs according to the voltage difference; The control unit is further configured to control the main circuit to conduct the branch circuit according to the first control signal, so that the current generated at the first end is a reference current value and the current generated at the second end is a source line current value, so as to obtain a first current difference between the two ends of the first node; According to the second control signal, the corresponding first bypass conductive branch is controlled so that the current generated at the first end is the source line current value and the current generated at the second end is the reference current value, so as to obtain a second current difference between the two ends of the second node.

7. A memory, characterized in that: A data reading circuit comprising the memory as claimed in claim 6.

Images