Semiconductor memory with temperature dependence

Abstract

This invention provides a temperature-dependent semiconductor memory. The semiconductor memory includes a memory array, a temperature sensor circuit, and a pump circuit. The temperature sensor circuit provides a temperature-dependent signal. The pump circuit is coupled to the temperature sensor circuit and the memory array. The pump circuit outputs a charge pump output voltage to the memory array based on the temperature-dependent signal. The charge pump output voltage is determined according to the temperature-dependent signal.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly to a temperature-dependent semiconductor memory. Background Technology

[0002] In conventional semiconductor memories, the output voltage of the charge pump is constant. However, the size of modern semiconductors is constantly shrinking, and memory designs are becoming increasingly diverse. Therefore, conventional semiconductor memories can exhibit a wide and rapid temperature variation range. That is, conventional semiconductor memories have the problem of difficulty in optimizing the control voltage under temperature variations, which can further adversely affect memory functionality. Therefore, several solutions based on embodiments are provided below regarding how to provide a novel temperature-dependent semiconductor memory. Summary of the Invention

[0003] This invention relates to a temperature-dependent semiconductor memory that can automatically adjust the operating voltage in the memory array according to temperature changes.

[0004] The temperature-dependent semiconductor memory of the present invention includes a memory array, a temperature sensor circuit, and a pump circuit. The temperature sensor circuit provides a temperature-dependent signal. The pump circuit is coupled to the temperature sensor circuit and the memory array. The pump circuit outputs a charge pump output voltage to the memory array based on the temperature-dependent signal. The charge pump output voltage is determined according to the temperature-dependent signal.

[0005] Based on the above, according to the temperature-dependent semiconductor memory of the present invention, the semiconductor memory can adjust the charge pump output voltage based on the current temperature of the semiconductor memory, wherein the charge pump output voltage can be used as the relevant internal operating voltage in the semiconductor memory. Therefore, the semiconductor memory of the present invention can effectively reduce the influence of temperature on the semiconductor memory.

[0006] To make the foregoing easier to understand, several embodiments with accompanying drawings are described in detail below. Attached Figure Description

[0007] Figure 1 This is a schematic circuit diagram of a semiconductor memory according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic circuit diagram of a voltage comparator circuit according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic circuit diagram of a semiconductor memory according to a first embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram illustrating the relationship between logic signals and temperature according to an embodiment of the present invention.

[0011] Figure 5 This is a schematic circuit diagram of a semiconductor memory according to a second embodiment of the present invention.

[0012] Figure 6 This is a schematic circuit diagram of the internal circuit of a temperature sensor according to an embodiment of the present invention.

[0013] Figure 7 This is a schematic diagram illustrating the relationship between temperature sensing voltage and temperature according to an embodiment of the present invention.

[0014] Figure 8 This is a schematic circuit diagram of a semiconductor memory according to a third embodiment of the present invention.

[0015] Figure 9 This is a schematic circuit diagram of a sensing amplifier control circuit and an equalization control circuit for a semiconductor memory according to an embodiment of the present invention.

[0016] Figure 10A This is a schematic diagram illustrating how the operating voltages of the sensing amplifier control circuit and the equalization control circuit change with temperature.

[0017] Figures 10B to 10D For the present invention Figure 9 A schematic diagram illustrating the variation of multiple operating voltages with temperature in an embodiment.

[0018] Figure 11 This is a schematic circuit diagram of the word line circuit of a memory cell according to an embodiment of the present invention.

[0019] Figure 12A This is a schematic diagram illustrating how the operating voltages of multiple switching gate circuits on a data bus change with temperature.

[0020] Figures 12B to 12D For the present invention Figure 11 A schematic diagram illustrating the variation of multiple operating voltages with temperature in an embodiment.

[0021] Figure 13 This is a schematic circuit diagram of a data bus conversion gate circuit according to an embodiment of the present invention.

[0022] [Symbol Explanation]

[0023] 100, 300, 500, 800: Semiconductor memory

[0024] 110, 310, 510, 810: Pump circuit

[0025] 111, 311, 511, 811: Charge pumps

[0026] 112, 312, 512, 812: Voltage comparator circuits

[0027] 120, 320, 520, 820: Memory arrays

[0028] 130, 330, 530, 830: Temperature sensor circuit

[0029] 331, 531, 831: Temperature sensors

[0030] 332: Voltage Selector

[0031] 333: Voltage divider resistor

[0032] 401, 402, 403, 404, 405: Logical code sequence codes

[0033] 900: Control Circuit

[0034] 901, 902, 903, 904, 905, 906, 907, 908, 909, 1101, 1301: Transistors

[0035] 1100: Word Line Circuit

[0036] 1121, 5311, 8121: Comparators

[0037] 1122, 1123, 5312, 5313, 8122, 8123: Resistors

[0038] 1300: Switching gate circuit

[0039] AS: Analog signal

[0040] BL1, BL2, BL3: Bit lines

[0041] EN: Pump start signal

[0042] GIOB: Global Input / Output Bus

[0043] IK, IS: Turn off leakage current

[0044] LIOB: Area Input / Output Bus

[0045] LS: Logic Signal

[0046] N1: Circuit node

[0047] RA, RB: Resistors

[0048] Va, Vb, Vc, Vd: Threshold voltages

[0049] VA: Reference voltage

[0050] VBB: Reverse Bias

[0051] Vcs: Constant voltage

[0052] VC: Conversion voltage

[0053] Vfb, Vfb': Feedback voltage

[0054] Vgs: Voltage

[0055] VH: High voltage level

[0056] VKK: Reset Voltage

[0057] VL: Low voltage level

[0058] Vp: Charge pump output voltage

[0059] Vp1, Vp2: Control signal voltages

[0060] Vp3: Equalization Voltage

[0061] VPP: Programming Voltage

[0062] Vref, Vref': Reference voltage

[0063] Vt: Temperature sensing voltage

[0064] Vt_H, Vt_L: slashes

[0065] WL: Word Line Detailed Implementation

[0066] It should be understood that other embodiments and structural changes may be utilized without departing from the scope of the invention. Furthermore, it should be understood that the wording or terminology used herein is for descriptive purposes and should not be considered limiting. The use of “comprising,” “including,” or “having,” and variations thereof herein, is intended to cover the items listed thereafter and their equivalents, as well as additional items. Unless otherwise limited, the terms “connection,” “coupled,” and “electrical connection,” and variations thereof, are used extensively herein and cover direct and indirect connections, couplings, and installations.

[0067] Figure 1 This is a schematic circuit diagram of a semiconductor memory according to an embodiment of the present invention. See also... Figure 1The semiconductor memory 100 includes a pump circuit 110, a memory array 120, and a temperature sensor circuit 130. The pump circuit 110 is coupled to the memory array 120 and the temperature sensor circuit 130. The pump circuit 110 includes a charge pump 111 and a voltage comparator circuit 112. The charge pump 111 is coupled to the memory array 120. The voltage comparator circuit 112 is coupled to the temperature sensor circuit 130. In one embodiment of the invention, the semiconductor memory 100 may be, for example, a NAND flash memory, dynamic random access memory (DRAM), or other types of memory. The temperature sensor circuit 130 is disposed in the semiconductor memory 100 and is used to sense the temperature of the semiconductor memory 100. The temperature of the semiconductor memory 100 may be the circuit center temperature or the circuit board temperature, but the invention is not limited thereto. The temperature sensor circuit 130 may output a temperature-dependent signal to the voltage comparator circuit 112 based on the temperature of the semiconductor memory 100.

[0068] In one embodiment of the invention, voltage comparator circuit 112 outputs a pump activation signal EN to charge pump 111 based on a reference voltage and a feedback voltage corresponding to the charge pump output voltage Vp. The charge pump output voltage is determined based on a temperature-dependent signal. Charge pump 111 outputs the charge pump output voltage Vp to memory array 120 based on the pump activation signal EN. Specifically, the pump activation signal EN can be a high voltage level or a low voltage level depending on the comparison result of voltage comparator circuit 112. If charge pump 111 is a positive voltage charge pump and the pump activation signal EN is a high voltage level, charge pump 111 is activated to increase the voltage level of charge pump output voltage Vp until the pump activation signal EN changes to a low voltage level. If charge pump 111 is a negative voltage charge pump and the pump activation signal EN is a high voltage level, charge pump 111 is activated to decrease the voltage level of charge pump output voltage Vp until the pump activation signal EN changes to a low voltage level. In one embodiment of the invention, the charge pump output voltage Vp can be the operating voltage of the internal circuitry of the memory array 120. In other words, the charge pump 111 and the voltage comparator circuit 112 form a feedback circuit. In one embodiment of the invention, the reference voltage or feedback voltage is determined based on a temperature-dependent signal, and the charge pump output voltage Vp is also determined based on the temperature-dependent signal.

[0069] Figure 2 This is a schematic circuit diagram of a voltage comparator circuit according to an embodiment of the present invention. See also... Figure 1 and Figure 2In one embodiment of the present invention, the voltage comparator circuit 112 may include a comparator 1121, a resistor 1122, and a resistor 1123. A first terminal of resistor 1122 is coupled to the charge pump output voltage Vp, and a second terminal of resistor 1122 is coupled to circuit node N1. A first terminal of resistor 1123 is coupled to circuit node N1, and a second terminal of resistor 1123 is coupled to ground. A first input terminal of comparator 1121 is coupled to circuit node N1 to receive a feedback voltage Vfb. A second input terminal of comparator 1121 receives a reference voltage Vref. The output terminal of comparator 1121 outputs a pump start signal EN. Note that, see [link to relevant documentation] Figure 2 and Figure 3 The semiconductor memory 100 can change one of the feedback voltage Vfb and the reference voltage Vref to correspondingly change the pump target voltage.

[0070] Figure 3 This is a schematic circuit diagram of a semiconductor memory according to a first embodiment of the present invention. Figure 4 This is a schematic diagram illustrating the relationship between logic signals and temperature according to an embodiment of the present invention. See also... Figure 3 The semiconductor memory 300 includes a pump circuit 310, a memory array 320, and a temperature sensor circuit 330. The pump circuit 310 is coupled to both the memory array 320 and the temperature sensor circuit 330. The pump circuit 310 includes a charge pump 311 and a voltage comparator circuit 312. The charge pump 311 is coupled to the memory array 320. The voltage comparator circuit 312 is coupled to the temperature sensor circuit 330. It should be noted that the voltage comparator circuit 312 may include... Figure 2 The voltage comparator circuit 112 in the embodiment has the same circuit unit.

[0071] In one embodiment of the present invention, the temperature sensor circuit 330 includes a temperature sensor 331, a voltage selector 332, and a voltage divider resistor 333. The temperature sensor 331 senses the temperature of the semiconductor memory 300 to output a logic signal LS. The voltage selector 332 is coupled to the temperature sensor 331 and the second input terminal of the comparator of the voltage comparator circuit 312. The voltage selector 332 receives the logic signal LS. The voltage divider resistor 333 is coupled to the voltage selector 332. The voltage divider resistor 333 generates multiple divided voltages to the voltage selector 332 based on a high voltage level VH and a low voltage level VL. In one embodiment of the present invention, the voltage selector 332 generates a reference voltage Vref based on the multiple divided voltages and the logic signal LS as a temperature-dependent signal provided to the second input terminal of the comparator of the voltage comparator circuit 312.

[0072] See Figure 3 and Figure 4The temperature sensor 331 can generate a temperature sensing voltage Vt based on the temperature sensing result. In one embodiment of the present invention, the temperature sensor 331 can be a negative temperature coefficient (NTC) sensor, so the temperature sensing voltage Vt is negatively correlated with the temperature sensed by the temperature sensor 331. The temperature sensor 331 can preset multiple threshold voltages Va, Vb, Vc, and Vd, and the threshold voltages Va, Vb, Vc, and Vd can correspond to multiple temperature values ​​Ta1, Ta2, Ta3, and Ta4, respectively. The temperature sensor 331 can compare the temperature sensing voltage Vt with the threshold voltages Va, Vb, Vc, and Vd to determine that the temperature sensing voltage Vt is between two of the threshold voltages Va, Vb, Vc, and Vd, thereby outputting a logic signal LS with a specific logic code sequence.

[0073] For example, when temperature sensor 331 determines that the temperature sensing voltage Vt is higher than the voltage threshold Vd (indicating that the current temperature of semiconductor memory 300 is lower than the temperature value Ta1), temperature sensor 331 can output a logic signal LS with a logic code sequence code 401, where the logic code sequence code 401 can be "1111". When temperature sensor 331 determines that the temperature sensing voltage Vt is between the voltage threshold Vd and the voltage threshold Vc (indicating that the current temperature of semiconductor memory 300 is between the temperature value Ta1 and the temperature value Ta2), temperature sensor 331 can output a logic signal LS with a logic code sequence code 402, where the logic code sequence code 402 can be "0111". When temperature sensor 331 determines that the temperature sensing voltage Vt is between the voltage threshold values ​​Vc and Vb (indicating that the current temperature of semiconductor memory 300 is between temperature values ​​Ta2 and Ta3), temperature sensor 331 can output a logic signal LS with a logic code sequence code 403, where logic code sequence code 403 can be "0011". When temperature sensor 331 determines that the temperature sensing voltage Vt is between the voltage threshold values ​​Vb and Va (indicating that the current temperature of semiconductor memory 300 is between temperature values ​​Ta3 and Ta4), temperature sensor 331 can output a logic signal LS with a logic code sequence code 404, where logic code sequence code 404 can be "0001". When temperature sensor 331 determines that the temperature sensing voltage Vt is lower than the voltage threshold value Va (indicating that the current temperature of semiconductor memory 300 is higher than temperature value Ta4), temperature sensor 331 can output a logic signal LS with a logic code sequence code 405, where logic code sequence code 405 can be "0000".

[0074] In one embodiment of the present invention, the temperature sensor 331 can output a logic signal LS with a specific logic code sequence determined according to the temperature of the semiconductor memory 300, so that the voltage selector 332 can output the corresponding reference voltage Vref to the second input terminal of the comparator of the voltage comparator circuit 312. Therefore, the voltage comparator circuit 312 can output a pump start signal EN according to the temperature change of the semiconductor memory 300, and the charge pump output voltage Vp changes with the temperature of the semiconductor memory 300. Therefore, the semiconductor memory 300 of the embodiment can have an automatic adjustment function of the operating voltage based on temperature changes. The semiconductor memory 300 can change the pump target voltage by changing the reference voltage Vref.

[0075] Figure 5 This is a schematic circuit diagram of a semiconductor memory according to a second embodiment of the present invention. Figure 6 This is a schematic circuit diagram of the internal circuit of a temperature sensor according to an embodiment of the present invention. Figure 7 This is a schematic diagram illustrating the relationship between temperature sensing voltage and temperature according to an embodiment of the present invention. See also... Figure 5 The semiconductor memory 500 includes a pump circuit 510, a memory array 520, and a temperature sensor circuit 530. The pump circuit 510 is coupled to the memory array 520 and the temperature sensor circuit 530. The pump circuit 510 includes a charge pump 511 and a voltage comparator circuit 512. The charge pump 511 is coupled to the memory array 520. The voltage comparator circuit 512 is coupled to the temperature sensor circuit 530. It should be noted that the voltage comparator circuit 512 may include... Figure 2 The voltage comparator circuit 112 in the embodiment has the same circuit unit. The temperature sensor circuit 530 includes a temperature sensor 531, and the temperature sensor 531 is coupled to the second input terminal of the comparator of the voltage comparator circuit 512. The temperature sensor 531 can provide an analog signal AS to the voltage comparator circuit 512 as a reference voltage.

[0076] See Figure 6 The temperature sensor 531 may include a comparator 5311, a resistor 5312, and a resistor 5313. In one embodiment of the invention, the first input terminal of the comparator 5311 is coupled to a constant voltage Vcs. The first terminal of the resistor 5312 is coupled to a temperature sensing voltage Vt. The second terminal of the resistor 5312 is coupled to a second input terminal of the comparator 5311. The first terminal of the resistor 5313 is coupled to the second input terminal of the comparator 5311, and the second terminal of the resistor 5313 is coupled to the output terminal of the comparator 5311. The output terminal of the comparator 5311 outputs an analog signal AS to the second input terminal of the comparator in the voltage comparator circuit 512 as a reference voltage.

[0077] See Figures 5 to 7 Temperature sensor 331 can generate a temperature sensing voltage Vt based on the temperature sensing result. In one embodiment of the invention, temperature sensor 531 can be a negative temperature coefficient sensor, therefore the temperature sensing voltage Vt is negatively correlated with the temperature sensed by temperature sensor 531. Based on the above circuit of temperature sensor 531, the temperature sensor can output an analog signal AS, and the analog signal AS is determined according to the temperature of semiconductor memory 300 sensed by temperature sensor 531. In one embodiment of the invention, the resistance ratio of resistor 5312 and resistor 5313 can be adjusted to change the slope of the voltage change of analog signal AS. The voltage change of analog signal AS can be, for example, as shown in the diagram. Figure 7 The slanted lines Vt_H or Vt_L are shown in the diagram. Therefore, the voltage comparator circuit 512 can output a pump start signal EN based on the temperature change of the semiconductor memory 500, so that the charge pump output voltage Vp changes with the temperature of the semiconductor memory 500. Therefore, the semiconductor memory 500 of this embodiment can have an automatic adjustment function for the operating voltage based on temperature changes. The semiconductor memory 500 can change the pump target voltage by changing the reference voltage (i.e., changing the analog signal AS).

[0078] Figure 8 This is a schematic circuit diagram of a semiconductor memory according to a third embodiment of the present invention. See also... Figure 8 The semiconductor memory 800 includes a pump circuit 810, a memory array 820, and a temperature sensor circuit 830. The pump circuit 810 is coupled to the memory array 820 and the temperature sensor circuit 830. The pump circuit 810 includes a charge pump 811 and a voltage comparator circuit 812. The charge pump 811 is coupled to the memory array 820. The voltage comparator circuit 812 is coupled to the temperature sensor circuit 830. The temperature sensor circuit 830 includes a temperature sensor 831, and the temperature sensor 831 can output a logic signal LS. It should be noted that the temperature sensor 831 may include... Figure 3 The temperature sensor 331 in the embodiment has the same circuit unit and the same signal generation mechanism.

[0079] In one embodiment of the present invention, the voltage comparator circuit 812 includes a comparator 8121, a resistor 8122, and a resistor 8123. A first terminal of resistor 8122 is coupled to the charge pump output voltage Vp, and a second terminal of resistor 8122 is coupled to circuit node N1. A first terminal of resistor 8123 is coupled to circuit node N1, and a second terminal of resistor 8123 is coupled to ground. A first input terminal of comparator 8121 is coupled to circuit node N1 to receive a feedback voltage Vfb'. A second input terminal of comparator 8121 receives a reference voltage Vref'. The output terminal of comparator 8121 outputs a pump start signal EN. In one embodiment of the present invention, resistors 8122 and 8123 are variable resistors. Temperature sensor 831 outputs a logic signal LS determined by the temperature of semiconductor memory 800, and voltage comparator circuit 812 adjusts at least one of resistors 8122 and 8123 according to the logic signal LS to correspondingly adjust the feedback voltage Vfb'. Comparator 8121 outputs a pump start signal EN based on the comparison result between the feedback voltage Vfb' and the reference voltage Vref'. The feedback voltage Vfb' is determined by the temperature sensed by temperature sensor 831, and the reference voltage Vref' can be a constant voltage so that the charge pump output voltage Vp also changes with the temperature of semiconductor memory 800. Therefore, the semiconductor memory 800 of this embodiment can have an automatic adjustment function of the operating voltage based on temperature changes. The semiconductor memory 800 can change the pump target voltage by changing the feedback voltage Vfb'.

[0080] Figure 9 This is a schematic circuit diagram of a sensing amplifier control circuit and an equalization control circuit for a semiconductor memory according to an embodiment of the present invention. See also... Figure 9 The control circuit 900 includes a plurality of transistors 901 to 909. In one embodiment of the invention, a first terminal of transistor 901 is coupled to a voltage source, and a control terminal of transistor 901 receives a control signal voltage Vp1. A first terminal of transistor 902 is coupled to a second terminal of transistor 901. A first terminal of transistor 903 is coupled to a second terminal of transistor 901. A first terminal of transistor 904 is coupled to a second terminal of transistor 902 and bit line BL1. A first terminal of transistor 905 is coupled to a second terminal of transistor 903 and bit line BL2. A control terminal of transistor 902 is coupled to a control terminal of transistor 905. A control terminal of transistor 903 is coupled to a control terminal of transistor 904. A first terminal of transistor 906 is coupled to the second terminals of transistors 904 and 905. A second terminal of transistor 906 is coupled to ground voltage. A control terminal of transistor 906 is coupled to a control signal voltage Vp2. In one embodiment of the invention, transistors 901 to 906 are used as sense amplifiers for a memory array.

[0081] In one embodiment of the present invention, a first terminal of transistor 907 is coupled to bit line BL1, and a second terminal of transistor 907 is coupled to a voltage source. A first terminal of transistor 908 is coupled to bit line BL2, and a second terminal of transistor 908 is coupled to a voltage source. The control terminals of transistors 907 and 908 are coupled to an equalization voltage Vp3. A first terminal of transistor 909 is coupled to bit line BL1, and a second terminal of transistor 909 is coupled to bit line BL2. The control terminal of transistor 909 is coupled to the equalization voltage Vp3. In one embodiment of the present invention, transistors 907 to 909 are configured as an equalization control circuit.

[0082] In one embodiment of the present invention, it can be Figure 1 , Figure 3 , Figure 5 as well as Figure 8 In at least one of the above embodiments, the charge pump output voltage Vp is output to the memory array as a memory control voltage. For example, see... Figure 9 can Figure 1 , Figure 3 , Figure 5 as well as Figure 8 In the above embodiments, at least one charge pump output voltage Vp is output to the sensing amplifier of the memory array as at least one of control signal voltage Vp1, control signal voltage Vp2, and equalization voltage Vp3. Alternatively, the charge pump output voltage Vp of at least one of the above embodiments can be used as the control signal voltage Vp1, control signal voltage Vp2, and equalization voltage Vp3. Figure 1 , Figure 3 , Figure 5 as well as Figure 8 In the above embodiments, at least one charge pump output voltage Vp is output to the sensing amplifier of the memory array as a reverse bias voltage for at least one of transistors 901, 904 to 906. Alternatively, the charge pump output voltage Vp of at least one of transistors 901, 904 to 906 can be used as a reverse bias voltage. Figure 1 , Figure 3 , Figure 5 as well as Figure 8 In the above embodiments, at least one charge pump output voltage Vp is output to the equalization control circuit of the memory array as a reverse bias voltage for at least one of transistors 907 to 909. Therefore, the effect of temperature on at least one of the sensing amplifier or equalization control circuit can be effectively reduced.

[0083] Figure 10A This is a schematic diagram illustrating how the operating voltages of the sense amplifier control circuit and the equalization control circuit change with temperature. See [link / reference]. Figure 9 and Figure 10AIf the reverse bias voltage VBB of one of transistors 901, 904, 906 to 909 is a fixed voltage (independent of temperature), then the off-leak current IS of the corresponding transistor can increase according to the temperature.

[0084] Figures 10B to 10D For the present invention Figure 9 A schematic diagram illustrating the variation of multiple operating voltages with temperature in an embodiment. See also... Figure 3 , Figure 9 as well as Figure 10B ,when Figure 3 In the above embodiment, when the charge pump output voltage Vp is output to the sense amplifier of the memory array as a reverse bias voltage VBB (temperature-dependent) of one of transistors 901, 904, 906 to 909, the reverse bias voltage VBB (i.e., changing the charge pump output voltage Vp) changes according to the logic signal LS, so that the reverse bias voltage VBB can decrease as the temperature increases. Therefore, Figure 3 The semiconductor memory 300 can change the reverse bias voltage VBB by changing the reference voltage Vref, so as to effectively suppress the turn-off leakage current IS (transistor standby current) of the corresponding transistor.

[0085] See Figure 5 , Figure 9 as well as Figure 10C ,when Figure 5 In the above embodiment, when the charge pump output voltage Vp is output to the sensing amplifier of the memory array as a reverse bias voltage VBB (dependent of temperature) of one of transistors 901, 904, 906 to 909, the reverse bias voltage VBB (i.e., changing the charge pump output voltage Vp) changes according to the analog signal AS (as a reference voltage), so that the reverse bias voltage VBB can decrease as the temperature increases. Therefore, Figure 5 The semiconductor memory 500 can change the reverse bias voltage VBB by changing the analog signal AS (as a reference voltage), so as to effectively suppress the turn-off leakage current IS (the transistor's standby current) of the corresponding transistor.

[0086] See Figure 8 , Figure 9 as well as Figure 10D ,when Figure 8When the charge pump output voltage Vp of the above embodiment is output to the sense amplifier of the memory array as a reverse bias voltage VBB (dependent on temperature) of one of transistors 901, 904, 906 to 909, the reverse bias voltage VBB (i.e., changing the charge pump output voltage Vp) is changed according to the logic signal LS, so that the reverse bias voltage VBB can decrease as the temperature increases. Specifically, the logic signal LS can change Figure 8 The resistor RA of the 8122 resistor, but Figure 8 The resistor RB of resistor 8123 is fixed, so that it can be changed accordingly. Figure 8 The resistance ratio of resistors 8122 and 8123. Then, the feedback voltage Vfb' changes according to the resistance ratio. Therefore, Figure 8 The semiconductor memory 800 can change the reverse bias voltage VBB by changing the feedback voltage Vfb', so as to effectively suppress the turn-off leakage current IS (transistor standby current) of the corresponding transistor.

[0087] Figure 11 This is a schematic circuit diagram of the word line circuit of a memory cell according to an embodiment of the present invention. See also... Figure 11 The memory cell includes word line circuitry 1100, and word line circuitry 1100 includes transistor 1101. In one embodiment of the invention, a first terminal of transistor 1101 is coupled to a reference voltage VA, and a second terminal of transistor 1101 is coupled to bit line BL3. A control terminal of transistor 1101 is coupled to word line WL and receives word line voltage via word line WL. The word line voltage may be programming voltage VPP or reset voltage VKK.

[0088] For example, it can be Figure 1 , Figure 3 , Figure 5 as well as Figure 8 In at least one of the above embodiments, the charge pump output voltage Vp is output to the memory cell of the memory array as a programming voltage VPP or a reset voltage VKK. Alternatively, the charge pump output voltage Vp can be output to the memory cell of the memory array as a programming voltage VPP or a reset voltage VKK. Figure 1 , Figure 3 , Figure 5 as well as Figure 8 In at least one of the above embodiments, the charge pump output voltage Vp is output to the memory cell of the memory array as a reverse bias voltage for the transistor 1101 coupled to the word line WL. Therefore, the effect of temperature on the word line circuit 1100 can be effectively reduced.

[0089] Figure 12A This is a schematic diagram illustrating how the operating voltages of multiple switching gate circuits on the data bus vary with temperature. See [link / reference] Figure 11 and Figure 12AIf the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB of transistor 1101 are fixed voltages (independent of temperature), then the off-leak current IK of transistor 1101 can increase according to temperature.

[0090] Figures 12B to 12D For the present invention Figure 11 A schematic diagram illustrating the variation of multiple operating voltages with temperature in an embodiment. See also... Figure 3 , Figure 11 as well as Figure 12B ,when Figure 3 When the charge pump output voltage Vp of the above embodiment is output to the memory cell of the memory array as the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB (depending on temperature) of transistor 1101, the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB (i.e., changing the charge pump output voltage Vp) changes according to the logic signal LS, and the voltage Vgs of transistor 1101 can be maintained at a specific voltage so that the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB can decrease as the temperature increases. Therefore, Figure 3 The semiconductor memory 300 can change the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB by changing the reference voltage Vref, so as to effectively suppress the turn-off leakage current IK of transistor 1101.

[0091] See Figure 5 , Figure 11 as well as Figure 12C ,when Figure 5 When the charge pump output voltage Vp of the above embodiment is output to the memory cell of the memory array as the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB (depending on temperature) of transistor 1101, the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB (i.e., changing the charge pump output voltage Vp) changes according to the analog signal AS (as a reference voltage), so that the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB can decrease as the temperature increases. Therefore, Figure 5 The semiconductor memory 500 can change the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB by changing the analog signal AS (as a reference voltage), so as to effectively suppress the turn-off leakage current IK of transistor 1101.

[0092] See Figure 8 , Figure 11 as well as Figure 12D ,when Figure 8When the charge pump output voltage Vp of the above embodiment is output to the memory cell of the memory array as the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB (depending on temperature) of transistor 1101, the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB (i.e., changing the charge pump output voltage Vp) is changed according to the logic signal LS, so that the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB can decrease as the temperature increases. Specifically, the logic signal LS can change Figure 8 The resistor RA of the 8122 resistor ( Figure 8 The resistor RB of resistor 8123 is fixed, so that the resistance can be changed accordingly. Figure 8 The resistance ratio of resistors 8122 and 8123. Then, the feedback voltage Vfb' changes according to the resistance ratio. Therefore, Figure 8 The semiconductor memory 800 can change the programming voltage VPP, reset voltage VKK, or reverse bias voltage VBB by changing the feedback voltage Vfb', so as to effectively suppress the turn-off leakage current IK of transistor 1101.

[0093] Figure 13 This is a schematic circuit diagram of a data bus conversion gate circuit according to an embodiment of the present invention. See also... Figure 13 The transfer gate circuit 1300 includes a transistor 1301. In one embodiment of the invention, a first terminal of the transistor 1301 is coupled to the regional input / output bus LIOB, and a second terminal of the transistor 1301 is coupled to the global input / output bus GIOB. The control terminal of the transistor 1301 is coupled to the switching voltage VC. For example, it can be... Figure 1 , Figure 3 , Figure 5 as well as Figure 8 In at least one of the above embodiments, the charge pump output voltage Vp is output to the conversion gate circuit 1300 as the conversion voltage VC. Alternatively, the charge pump output voltage Vp of at least one of the embodiments can be used as the conversion voltage VC. Figure 1 , Figure 3 , Figure 5 as well as Figure 8 In at least one of the above embodiments, the charge pump output voltage Vp is output to the switching gate circuit 1300 as the reverse bias voltage of the transistor 1301. Therefore, the effect on the temperature of the switching gate circuit 1300 can be effectively reduced. However, reference can be made to... Figures 11 to 12D The voltage change mechanism and related technical effects of the conversion gate circuit 1300 of the foregoing embodiments, which are taught or obtained in this embodiment, will not be repeated below.

[0094] In summary, the temperature-dependent semiconductor memory of the present invention can utilize a temperature sensor disposed in the semiconductor memory to obtain current temperature information, and adjust the output voltage of the charge pump based on the current temperature information, so as to effectively and timely reduce the impact of temperature on the semiconductor memory.

[0095] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover such modifications and variations, provided that they fall within the scope of the appended claims and their equivalents.

Claims

1. A temperature-dependent semiconductor memory, comprising: Memory array; Temperature sensor circuit, used to provide temperature-dependent signals; as well as A pump circuit, coupled to the temperature sensor circuit and the memory array, is used to output the charge pump output voltage to the memory array according to the temperature-dependent signal. The charge pump output voltage is determined based on the temperature-dependent signal. The pump circuit includes: A voltage comparator circuit, coupled to the temperature sensor circuit, is used to receive a reference voltage and the charge pump output voltage; and A charge pump is coupled to the voltage comparator circuit, wherein the voltage comparator circuit outputs a pump start signal to the charge pump based on the reference voltage and a feedback voltage corresponding to the output voltage of the charge pump, and the charge pump outputs its output voltage based on the pump start signal. The voltage comparator circuit mentioned above includes: A first resistor, wherein a first end of the first resistor is coupled to the output voltage of the charge pump, and a second end of the first resistor is coupled to a circuit node; A second resistor, wherein a first end of the second resistor is coupled to the circuit node, and a second end of the second resistor is coupled to ground voltage; and A first comparator, wherein a first input of the first comparator is coupled to the circuit node to receive the feedback voltage, a second input of the first comparator receives the reference voltage, and an output of the first comparator outputs the pump start signal. The reference voltage or the feedback voltage is determined based on the temperature-dependent signal. The temperature sensor circuit mentioned above includes: Temperature sensor, used to output logic signals; and A voltage selector, coupled to the temperature sensor and the second input terminal of the first comparator, is used to receive the logic signal; and A voltage divider resistor is coupled to the voltage selector and is used to generate multiple voltage dividers based on high and low voltage levels. The voltage selector generates the reference voltage based on the plurality of voltage dividers and the logic signal as the temperature-dependent signal provided to the first comparator.

2. The temperature-dependent semiconductor memory of claim 1, wherein the temperature sensor determines that the temperature sensing voltage is between two of a plurality of threshold voltages to output the logic signal having a specific logic code sequence.

3. The temperature-dependent semiconductor memory of claim 2, wherein the temperature sensing voltage is negatively correlated with the temperature sensed by the temperature sensor.

4. The temperature-dependent semiconductor memory as claimed in claim 1, wherein the temperature sensor circuit comprises: A temperature sensor is coupled to the second input terminal of the first comparator and is used to provide an analog signal as the reference voltage.

5. The temperature-dependent semiconductor memory of claim 4, wherein the temperature sensor comprises: A second comparator, wherein a first input terminal of the second comparator is coupled to a constant voltage; A third resistor, wherein a first end of the third resistor is coupled to a temperature sensing voltage, and a second end of the third resistor is coupled to a second input terminal of the second comparator; as well as A fourth resistor, wherein a first end of the fourth resistor is coupled to the second input terminal of the second comparator, and a second end of the fourth resistor is coupled to the output terminal of the second comparator. The analog signal is output from the output terminal of the second comparator.

6. The temperature-dependent semiconductor memory of claim 5, wherein the temperature sensing voltage is negatively correlated with the temperature sensed by the temperature sensor.

7. The temperature-dependent semiconductor memory of claim 1, wherein the first resistor and the second resistor are variable resistors, and the temperature sensor circuit comprises: A temperature sensor is coupled to the first resistor and the second resistor. The temperature sensor outputs a logic signal as the temperature-dependent signal to adjust the first resistance value of the first resistor and the second resistance value of the second resistor, thereby correspondingly adjusting the feedback voltage.

8. The temperature-dependent semiconductor memory of claim 7, wherein the temperature sensor determines that the temperature sensing voltage is between two of a plurality of threshold voltages to output the logic signal having a specific logic code sequence.

9. The temperature-dependent semiconductor memory of claim 8, wherein the temperature sensing voltage is negatively correlated with the temperature sensed by the temperature sensor.

10. The temperature-dependent semiconductor memory of claim 1, wherein the charge pump output voltage is negatively correlated with the temperature sensed via the temperature sensor circuit.

11. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the memory array as a memory control voltage.

12. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the sense amplifier of the memory array as a control signal voltage for the transistors in the sense amplifier.

13. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the sense amplifier of the memory array as a reverse bias voltage for the transistors in the sense amplifier.

14. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the equalization control circuit of the memory array as the equalization voltage or reverse bias voltage of the transistors in the equalization control circuit.

15. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the equalization control circuit of the memory array as a reverse bias voltage for the transistors in the equalization control circuit.

16. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the memory cells of the memory array as the word line voltage.

17. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the memory cells of the memory array as a reverse bias voltage for transistors coupled to word lines.

18. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the memory array as a conversion voltage for the data bus.

19. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the memory array as a reverse bias voltage for transistors coupled to the data bus.

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