RHC-16T anti-radiation SRAM unit, chip and module

Abstract

The application relates to an RHC-16T anti-radiation SRAM unit, a chip and a module. An RHC-16T anti-radiation SRAM unit based on a polarity reinforcement technology comprises four PMOS transistors P1-P4 and twelve NMOS transistors N1-N12; a bit line BL is electrically connected with the sources of N9 and N11, a bit line BLB is electrically connected with the sources of N10 and N12; a word line WL is electrically connected with the gates of N9, N10, N11 and N12; the drain of N9 is electrically connected with the drain of P2, the drain of N10 is electrically connected with the drain of P1, the drain of N11 is electrically connected with the drain of N3, and the drain of N12 is electrically connected with the drain of N4. N3 and N4 are respectively added between P3, N7 and P4, N8 to block a feedback loop, the stability of the unit is improved, the unit has a faster read-write speed, higher stability and stronger anti-radiation performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of static random access memory, in particular to a RHC-16T anti-radiation SRAM unit based on polarity hardening technology, a RHC-16T anti-radiation SRAM chip based on polarity hardening technology and a RHC-16T anti-radiation SRAM module based on polarity hardening technology. BACKGROUND

[0002] When a space electronic device enters a space radiation environment, the interference of space radiation particles on the SRAM unit will cause it to not work normally, thereby having a great impact on the spacecraft. The single event effect (Single Event Effect, abbreviated as SEE) caused by high-energy particles in the radiation environment to the electronic system is the most serious damage phenomenon, which has the greatest impact on the reliability of the memory. The most common consequence of SEE is single event upset (Single Event Upset, abbreviated as SEU), which will cause the data of the storage unit to change. Therefore, the anti-radiation performance of the SRAM unit has become an important problem that cannot be ignored in the development of integrated circuits today. There are various ways to solve the anti-radiation problem in the prior art, among which some guarantee the normal read and write speed of the unit while solving the anti-radiation problem, but the anti-radiation effect is limited; or the anti-radiation effect is obvious, but the read and write speed of the unit is slow. SUMMARY

[0003] Therefore, it is necessary to provide a RHC-16T anti-radiation SRAM unit, chip and module based on polarity hardening technology to solve the problem that the anti-radiation performance and read and write speed cannot be guaranteed at the same time.

[0004] To achieve the above object, the present application adopts the following technical scheme:

[0005] A RHC-16T anti-radiation SRAM unit based on polarity hardening technology comprises:

[0006] A PMOS transistor P1, the source of P1 is electrically connected with the source of P2, the source of P3 and the source of P4, the drain of P1 is electrically connected with the gate of P2, and the gate of P1 is electrically connected with the drain of P2;

[0007] A PMOS transistor P2, the source of P2 is electrically connected with the source of P1, the source of P3 and the source of P4, the drain of P2 is electrically connected with the gate of P1, the gate of N1, the drain of N2, the gate of N3, the drain of N5 and the drain of N9, and the gate of P2 is electrically connected with the drain of P1, the drain of N1, the gate of N2, the gate of N4, the drain of N6 and the drain of N10;

[0008] PMOS transistor P3: a source of P3 is electrically connected with a source of P4, a drain of P3 is electrically connected with a source of N3, a gate of P3 is electrically connected with a drain of N4, a gate of N5, a gate of N7, a drain of N8 and a drain of N12;

[0009] PMOS transistor P4: a source of P4 is electrically connected with a source of P3, a drain of P4 is electrically connected with a source of N4, a gate of P4 is electrically connected with a drain of N3, a gate of N6, a drain of N7, a gate of N8 and a drain of N11;

[0010] NMOS transistor N1: a source of N1 is electrically connected with a source of N2, a source of N5, a source of N6, a source of N7, a source of N8, a drain of N1 is electrically connected with a source of P1 and a gate of P2, a gate of N1 is electrically connected with a gate of P1, a drain of P2, a gate of N3 and a drain of N9;

[0011] NMOS transistor N2: a source of N2 is electrically connected with a source of N1, a drain of N2 is electrically connected with a drain of P2, a gate of N2 is electrically connected with a gate of P2, a drain of P1, a gate of N4, a drain of N6 and a drain of N10;

[0012] NMOS transistor N3: a source of N3 is electrically connected with a drain of P3, a drain of N3 is electrically connected with a gate of P4, a gate of N5, a drain of N7, a gate of N8 and a drain of N11, a gate of N3 is electrically connected with a gate of N1;

[0013] NMOS transistor N4: a source of N4 is electrically connected with a drain of P4, a drain of N4 is electrically connected with a gate of P3, a gate of N5, a gate of N7, a drain of N8 and a drain of N12, a gate of N4 is electrically connected with a gate of N2;

[0014] NMOS transistor N5: a source of N5 is electrically connected with a source of N6, a drain of N5 is electrically connected with a gate of N1 and a gate of N3, a gate of N5 is electrically connected with a gate of P3 and a gate of N7;

[0015] NMOS transistor N6: a source of N6 is electrically connected with a source of N5, a drain of N6 is electrically connected with a gate of N2 and a gate of N4, a gate of N6 is electrically connected with a gate of P4 and a gate of N8;

[0016] NMOS transistor N7: a source of N7 is electrically connected with a source of N8, a drain of N7 is electrically connected with a drain of N3, a gate of N7 is electrically connected with a gate of P3;

[0017] NMOS transistor N8: a source of N8 is electrically connected with a source of N7, a drain of N8 is electrically connected with a drain of N4, a gate of N8 is electrically connected with a gate of P4;

[0018] NMOS transistor N9: the source of N9 is electrically connected with the bit line BL, the drain of N9 is electrically connected with the gate of P1, and the gate of N9 is electrically connected with the word line WL;

[0019] NMOS transistor N10: the source of N10 is electrically connected with the bit line BLB, the drain of N10 is electrically connected with the gate of P2, and the gate of N10 is electrically connected with the word line WL;

[0020] NMOS transistor N11: the source of N11 is electrically connected with the bit line BL, the drain of N11 is electrically connected with the drain of N7, and the gate of N11 is electrically connected with the word line WL;

[0021] NMOS transistor N12: the source of N12 is electrically connected with the bit line BLB, the drain of N12 is electrically connected with the drain of N8, and the gate of N12 is electrically connected with the word line WL;

[0022] Transistors P1-P4, N4 and N4 are used as pull-up tubes; N1, N2, N5-N8 are used as pull-down tubes; transistors N9, N10, N11 and N12 are connected with nodes S1, S0, Q and QN respectively; transistors P1, N1 and P2, N2 respectively constitute an inverter one, and two inverters one are cross-coupled; P3, N7 and P4, N8 respectively constitute an inverter two, and N3 and N4 are added in the middle of two inverters two to block the feedback loop, so as to improve the stability of the storage unit.

[0023] Further, the gate length of transistors P1-P4 and N1-N12 is 65 nm, wherein the gate width of transistors P1, P2, P3 and P4 is 80 nm, the gate width of transistors N1 and N2 is 280 nm, and the gate width of transistors N3-N12 is 140 nm.

[0024] Further, the node Q and the node QN are main storage nodes, and the node S0 and the node S1 are redundant nodes.

[0025] In one embodiment, when the anti-radiation SRAM unit is in a holding operation, the bit lines BL and BLB are pre-charged to high level, the word line WL is low, and the initial state is maintained inside the circuit.

[0026] In one embodiment, when the anti-radiation SRAM unit is in a reading operation, the bit lines BL and BLB are pre-charged to high level, the word line WL is high, and transistors N9, N10, N11 and N12 are opened.

[0027] Further, if the data stored in the anti-radiation SRAM unit is "0", i.e. "Q=S1=0, QN=S0=1", the bit line BL is discharged to the ground through the discharge path 1:N9 and N2, the discharge path 2:N9 and N5, and the discharge path 3:N11 and N7, so that a potential difference is generated between the bit line BL and the bit line BLB, and the data is read out through the sense amplifier; if the data stored in the anti-radiation SRAM unit is "1", i.e. "Q=S1=1, QN=S0=0", the bit line BLB is discharged to the ground through the discharge path 1:N10 and N1, the discharge path 2:N10 and N6, and the discharge path 3:N12 and N8, so that a potential difference is generated between the bit line BL and the bit line BLB, and the data is read out through the sense amplifier.

[0028] In one embodiment, when the anti-radiation SRAM unit is in a write operation, the bit lines BL and BLB are pre-charged to the level signal to be written, the word line WL is at a high level, and the transistors N9, N10, N11 and N12 are turned on.

[0029] Further, if the bit line BL is at a high level and the bit line BLB is at a low level, "1" is written to the storage node S1 and the node Q through the transistors N9 and N11 respectively; if the bit line BL is at a low level and the bit line BLB is at a high level, "1" is written to the storage node QN and the node S0 through the transistors N10 and N12 respectively.

[0030] The application also includes an RHC-16T anti-radiation SRAM chip based on the polarity hardening technology, which is packaged by the circuit of the aforementioned RHC-16T anti-radiation SRAM unit based on the polarity hardening technology, and the pins of the anti-radiation SRAM chip include:

[0031] The first pin is electrically connected to the gate of the transistors N9-N12 through the word line WL;

[0032] The second pin is electrically connected to the source of the transistor N9 and the source of the transistor N11 through the bit line BL;

[0033] The third pin is electrically connected to the source of the transistor N10 and the source of the transistor N12 through the bit line BLB.

[0034] The application also includes an RHC-16T anti-radiation SRAM module based on the polarity hardening technology, which is packaged by the circuit of the aforementioned RHC-16T anti-radiation SRAM unit based on the polarity hardening technology, and the anti-radiation SRAM module includes:

[0035] The gate of the transistors N9, N10, N11 and N12 is electrically connected to the word line WL, thereby leading to a first connection end;

[0036] The source of the transistors N9 and N11 is electrically connected to the bit line BL, thereby leading to a second connection end;

[0037] The source of the transistor N10 and N12 is electrically connected to the bit line BLB, thereby leading out a third connection end.

[0038] The technical scheme provided by the application has the following beneficial effects:

[0039] The application adds N3 and N4 between the transistors P3, N7 and P4, N8 respectively to block the feedback loop, improve the stability of the unit, improve the anti-SEU capability of the unit, and make the unit have a faster read-write speed, higher stability and stronger anti-radiation performance. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 The structure schematic diagram of the DICE circuit in the prior art is provided for the application;

[0041] Figure 2 The structure schematic diagram of the Quatro circuit in the prior art is provided for the application;

[0042] Figure 3 The structure schematic diagram of the RHPD-12T circuit in the prior art is provided for the application;

[0043] Figure 4 The structure schematic diagram of the SEA14T circuit in the prior art is provided for the application;

[0044] Figure 5 The structure schematic diagram of the RHC-16T anti-radiation SRAM storage unit based on the polarity hardening technology is provided for the application;

[0045] Figure 6 The structure schematic diagram of the RHC-16T anti-radiation SRAM storage unit based on the polarity hardening technology is provided for the application; Figure 5 The timing waveform diagram of the RHC-16T anti-radiation SRAM storage unit is provided for the application;

[0046] Figure 7 The structure schematic diagram of the RHC-16T anti-radiation SRAM storage unit based on the polarity hardening technology is provided for the application; Figure 5 The transient waveform simulation diagram of the RHC-16T anti-radiation SRAM storage unit at different time points and different nodes subjected to double exponential current source pulse injection is provided for the application;

[0047] Figure 8 The structure schematic diagram of the RHC-16T anti-radiation SRAM storage unit based on the polarity hardening technology is provided for the application; Figure 5 The structure schematic diagram of the RHC-16T anti-radiation SRAM storage unit based on the polarity hardening technology is provided for the application; Figures 1-4 The hold static noise margin (abbreviated as HSNM), read static noise margin (abbreviated as RSNM) and write static noise margin (abbreviated as WSNM) comparison diagram of the prior art is provided for the application;

[0048] Figure 9 For based on Figure 5 A schematic diagram of the structure of the RHC-16T radiation-resistant SRAM chip. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] To improve the resistance of cells to SEU (Self-Enhancing Unstable Elements), existing technologies mainly include the following solutions: such as... Figure 1 The image shows a radiation-hardened SRAM cell called DICE, which consists of 12 transistors and has good write capability. However, it can only withstand single-node flips and cannot withstand double-node flips.

[0051] like Figure 2 The image shows a radiation-hardened SRAM cell called QUATRO, which consists of 10 transistors and has a small area, but its write capability is poor and it can only resist interference from low-energy particles.

[0052] like Figure 3 The image shows a radiation-hardened SRAM cell called RHPD-12T, which employs polarity hardening technology to reduce the number of sensitive nodes. While this cell resists all single-node flips, it can only resist some two-node flips.

[0053] like Figure 4 The image shows a radiation-hardened SRAM cell called SEA14T, which consists of 14 transistors and can withstand all single-node and some dual-node flips. However, because it only uses two NMOS transistors as transmission transistors, the read and write speed of this cell is relatively slow.

[0054] Based on the existing technical solutions described above, this embodiment addresses the problem of simultaneously failing to guarantee radiation resistance and read / write speed by providing an RHC-16T radiation-hardened SRAM cell based on polarity hardening technology. This embodiment improves cell stability and enhances SEU resistance by adding N3 and N4 between transistors P3 and N7 and between P4 and N8, respectively, to block the feedback loop.

[0055] like Figure 5As shown, the RHC-16T anti-radiation SRAM cell based on the polar reinforcement technology includes four PMOS transistors P1-P4 and twelve NMOS transistors N1-N12. All transistor gate lengths are 65 nm, in which P1, P2, P3 and P4 gate widths are 80 nm, N1 and N2 gate widths are 280 nm, and the gate widths of the remaining transistors are 140 nm. Inside the cell, there are four storage nodes in total, in which the main storage nodes are Q and QN, and the redundant nodes are S0 and S1. Transistors P1, N1 and P2, N2 respectively constitute an inverter one, and the two inverter ones are cross-coupled. P3, N7 and P4, N8 respectively constitute two inverters two, and N3 and N4 are respectively added in the middle of the two inverters two to block the feedback loop and improve the stability of the cell. P1, P2, P3, P4, N4 and N4 are pull-up tubes; N1, N2, N5, N6, N7 and N8 are pull-down tubes. N9, N10, N11 and N12 are transmission tubes, which are respectively connected with nodes S1, S0, Q and QN, and their switching states are controlled by the word line WL.

[0056] The bit line BL is electrically connected with the sources of the transmission tubes N9 and N11, and the bit line BLB is electrically connected with the sources of the transmission tubes N10 and N12; the word line WL is electrically connected with the gates of the transmission tubes N9, N10, N11 and N12; the drain of the transmission tube N9 is electrically connected with the drain of the PMOS transistor P2, the drain of the transmission tube N10 is electrically connected with the drain of the PMOS transistor P1, the drain of the transmission tube N11 is electrically connected with the drain of the NMOS transistor N3, and the drain of the transmission tube N12 is electrically connected with the drain of the NMOS transistor N4; VDD is electrically connected with the sources of the PMOS transistors P1, P2, P3 and P4, and VSS is electrically connected with the sources of the NMOS transistors N1, N2, N5, N6, N7 and N8.

[0057] The specific connection mode between the PMOS transistors P1-P4 and the NMOS transistors N1-N12 is as follows: the drain of the NMOS transistor N1 is electrically connected with the source of the PMOS transistor P1 and the gate of the PMOS transistor P2, and the gate of the NMOS transistor N1 is electrically connected with the gate of the PMOS transistor P1, the drain of the PMOS transistor P2, the gate of the NMOS transistor N3 and the drain of the NMOS transistor N9. The drain of the NMOS transistor N2 is electrically connected with the drain of the PMOS transistor P2, and the gate of the NMOS transistor N2 is electrically connected with the gate of the PMOS transistor P2, the drain of the PMOS transistor P1, the gate of the NMOS transistor N4, the drain of the NMOS transistor N6 and the drain of the NMOS transistor N10.

[0058] The source of the NMOS transistor N3 is electrically connected with the drain of the PMOS transistor P3, the drain of the NMOS transistor N3 is electrically connected with the gate of the PMOS transistor P4, the gate of the NMOS transistor N5, the drain of N7, the gate of N8 and the drain of N11, and the gate of the NMOS transistor N3 is electrically connected with the gate of N1. The source of the NMOS transistor N4 is electrically connected with the drain of the PMOS transistor P4, the drain of the NMOS transistor N4 is electrically connected with the gate of the PMOS transistor P3, the gate of the NMOS transistor N5, the gate of N7, the drain of N8 and the drain of N12, and the gate of the NMOS transistor N4 is electrically connected with the gate of N2.

[0059] The drain of the NMOS transistor N5 is electrically connected with the gate of N1 and the gate of N3, and the gate of the NMOS transistor N5 is electrically connected with the gate of P3 and the gate of N7. The drain of the NMOS transistor N6 is electrically connected with the gate of N2 and the gate of N4, and the gate of the NMOS transistor N6 is electrically connected with the gate of P4 and the gate of N8. The drain of the NMOS transistor N7 is electrically connected with the drain of N3, and the gate of the NMOS transistor N7 is electrically connected with the gate of P3. The drain of the NMOS transistor N8 is electrically connected with the drain of N4, and the gate of the NMOS transistor N8 is electrically connected with the gate of P4.

[0060] The source of the NMOS transistor N9 is electrically connected with the bit line BL, the drain of the NMOS transistor N9 is electrically connected with the gate of the PMOS transistor P1, and the gate of the NMOS transistor N9 is electrically connected with the word line WL. The source of the NMOS transistor N10 is electrically connected with the bit line BLB, the drain of the NMOS transistor N10 is electrically connected with the gate of the PMOS transistor P2, and the gate of the NMOS transistor N10 is electrically connected with the word line WL. The source of the NMOS transistor N11 is electrically connected with the bit line BL, the drain of the NMOS transistor N11 is electrically connected with the drain of the NMOS transistor N7, and the gate of the NMOS transistor N11 is electrically connected with the word line WL. The source of the NMOS transistor N12 is electrically connected with the bit line BLB, the drain of the NMOS transistor N12 is electrically connected with the drain of the NMOS transistor N8, and the gate of the NMOS transistor N12 is electrically connected with the word line WL.

[0061] The drain of the PMOS transistor P1 is electrically connected with the drains of the NMOS transistors N1, N6 and N10, the drain of the NMOS transistor N6, the gate of the PMOS transistor P2, and the gate of the PMOS transistor P1 is electrically connected with the drain of the PMOS transistor P2, the drain of the NMOS transistor N2, the gates of N1 and N3. The drain of the PMOS transistor P2 is electrically connected with the gate of the PMOS transistor P1, the gate of the NMOS transistor N1, the drain of N2, the gate of N3, the drain of N5 and the drain of N9, and the gate of the PMOS transistor P2 is electrically connected with the drain of the PMOS transistor P1, the drain of the NMOS transistor N1, the gate of N2, the gate of N4, the drain of N6 and the drain of N10.

[0062] The drain of the PMOS transistor P3 is electrically connected with the source of the NMOS transistor N3, and the gate of the PMOS transistor P3 is electrically connected with the drain of the NMOS transistor N4, the gate of N5, the gate of N7, the drain of N8 and the drain of N12. The drain of the PMOS transistor P4 is electrically connected with the source of the NMOS transistor N4, and the gate of the PMOS transistor P4 is electrically connected with the drain of the NMOS transistor N3, the gate of N6, the drain of N7, the gate of N8 and the drain of N11.

[0063] The principle of the RHC-16T anti-radiation SRAM unit based on the polarity reinforcement technology is as follows: during the maintaining operation, the bit lines BL and BLB are pre-charged to high level, the word line WL is low level, and the initial state is maintained in the circuit.

[0064] During the reading operation, the bit lines BL and BLB are pre-charged to high level in advance, the word line WL is high level, and the transmission tubes N9, N10, N11 and N12 are opened. During the reading operation, if the data stored in the unit circuit is "0", that is, "Q=S1=0, QN=S0=1", the bit line BL is discharged to ground through the discharge path 1: N9 and N2, the discharge path 2: N9 and N5, and the discharge path 3: N11 and N7, so that the bit line generates a potential difference, and the data is read through the sensitive amplifier. If the data stored in the unit is "1", that is, "Q=S1=1, QN=S0=0", the bit line BLB is discharged to ground through the discharge path 1: N10 and N1, the discharge path 2: N10 and N6, and the discharge path 3: N12 and N8, so that the bit line generates a potential difference, and the data is read through the sensitive amplifier.

[0065] In the write operation, the bit line BL and BLB are pre-charged to the level signal to be written, the word line WL is high, and the transfer tubes N9, N10, N11 and N12 are open. If BL is high and BLB is low, then "1" is written to the storage node S1 and Q through the transistors N9 and N11 respectively; if BL is low and BLB is high, then "1" is written to the storage node QN and S0 through the transistors N10 and N12 respectively.

[0066] When only considering the improvement of the cell circuit structure on the anti-radiation performance, if the storage node of the cell is bombarded by particles, since the nodes Q and QN of the cell are both surrounded by NMOS transistors. According to the polarity hardening principle, the sensitive node NMOS tube is bombarded by space particles, only a "1-0" voltage pulse is generated at the node, and the pulse cannot affect the state of other transistors due to the existence of the gate capacitance, which makes the external nodes S0 and S1 effectively avoid flipping, and the stability of the data of the Q and QN nodes ensures that the external nodes S0 and S1 can recover to the initial state after flipping, thereby improving the anti-SEU capability of the cell. If other non-critical nodes are bombarded by particles, the cell is less affected.

[0067] The RHC-16T anti-radiation SRAM cell based on the polarity hardening technology is simulated and verified, an average current value is set, the simulation temperature is 27 degrees, the source of P1, P2, P3 and P4 is connected to a 12V working voltage, and the simulation is carried out under this condition. The word line WL, the bit line BL and BLB, the storage node Q, QN, S0 and S1 timing waveform conditions are as shown in Figure 6 The transient waveform simulation conditions of the storage node Q, QN, S0 and S1 at different times and different nodes bombarded by a double exponential current source pulse are as shown in Figure 7 As shown in Figure 8 As shown in Figures 1-4 Compared with the prior art SRAM cell circuit in

[0068] The prior art SRAM cell circuit in Figures 1-4 and the anti-radiation SRAM cell of the present embodiment are compared and simulated in read delay, write delay and power consumption, and a simulation comparison table is obtained as shown in the following table. From the simulation comparison table, it can be known that the read-write time and power consumption of the overall circuit of the anti-radiation SRAM cell provided by the present embodiment are improved.

[0069] Simulation comparison table

[0070]

[0071]

[0072] The prior art SRAM cell circuit in Figures 1-4The critical charge comparison table is obtained by comparing the existing SRAM cell circuit and the radiation-resistant SRAM cell of this embodiment with the critical charge. As shown in the table below, it can be seen from the critical charge comparison table that the radiation-resistant SRAM cell provided in this embodiment has a higher critical charge value.

[0073] Critical Charge Comparison Table

[0074] Unit Critical charge (fc) DICE >50 Quatro 7.36 RHPD-12T 19.6 SEA14T >50 RHC-16T >30

[0075] Therefore, the RHC-16T radiation-resistant SRAM memory cell provided by this invention can improve the SEU resistance of the cell circuit and significantly increase the cell speed while sacrificing a small amount of cell power consumption.

[0076] like Figure 9 As shown, based on the aforementioned RHC-16T radiation-hardened SRAM cell based on polarity hardening technology, a further RHC-16T radiation-hardened SRAM chip based on polarity hardening technology is provided. This chip is formed by packaging the circuit of the RHC-16T radiation-hardened SRAM cell based on polarity hardening technology. The chip packaging mode makes it easier to promote and apply the RHC-16T radiation-hardened SRAM cell based on polarity hardening technology.

[0077] The RHC-16T radiation-hardened SRAM chip based on polarity hardening technology has the following pins: a first pin, which is electrically connected to the gates of transistors N9, N10, N11, and N12 via word line WL; a second pin, which is electrically connected to the sources of transistors N9 and N11 via bit line BL; and a third pin, which is electrically connected to the sources of transistors N10 and N12 via bit line BLB.

[0078] Based on the aforementioned RHC-16T radiation-hardened SRAM cell based on polarity hardening technology, this embodiment further includes an RHC-16T radiation-hardened SRAM module based on polarity hardening technology. This module adopts the circuit structure of the aforementioned RHC-16T radiation-hardened SRAM cell. The RHC-16T radiation-hardened SRAM module includes: gate electrical connection word lines WL for transistors N9, N10, N11, and N12, leading to a first connection terminal; source electrical connection bit lines BL for transistors N9 and N11, leading to a second connection terminal; and source electrical connection bit lines BLB for transistors N10 and N12, leading to a third connection terminal.

[0079] The RHC-16T anti-radiation SRAM unit based on the polar reinforcement technology is designed into a module, facilitating the promotion and application of the RHC-16T anti-radiation SRAM unit in the market, and facilitating the quick use of the RHC-16T anti-radiation SRAM unit by the person skilled in the art, which only needs to refer to the product instruction and make line connection to the module.

[0080] The technical features of the above embodiments can be combined in any manner, and for the sake of brevity, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0081] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the present application patent should be subject to the appended claims.

Claims

1. An RHC-16T radiation-hardened SRAM cell based on polarity hardening technology, characterized in that, It includes: PMOS transistor P1; PMOS transistor P2: The source of P2 is electrically connected to the source of P1, the drain of P2 is electrically connected to the gate of P1, and the gate of P2 is electrically connected to the drain of P1. PMOS transistor P3: The source of P3 is electrically connected to the source of P2; PMOS transistor P4: The source of P4 is electrically connected to the source of P3. NMOS transistor N1: The drain of N1 is electrically connected to the source of P1 and the gate of P2, and the gate of N1 is electrically connected to the gate of P1 and the drain of P2. NMOS transistor N2: The source of N2 is electrically connected to the source of N1, the drain of N2 is electrically connected to the drain of P2, and the gate of N2 is electrically connected to the gate of P2 and the drain of P1. NMOS transistor N3: The source of N3 is electrically connected to the drain of P3, the drain of N3 is electrically connected to the gate of P4, and the gate of N3 is electrically connected to the gate of N1. NMOS transistor N4: The source of N4 is electrically connected to the drain of P4, the drain of N4 is electrically connected to the gate of P3, and the gate of N4 is electrically connected to the gate of N2. NMOS transistor N5: The drain of N5 is electrically connected to the gate of N1 and the gate of N3, and the gate of N5 is electrically connected to the gate of P3, the drain of N4, and the drain of N3. NMOS transistor N6: The source of N6 is electrically connected to the source of N5, the drain of N6 is electrically connected to the gate of N2 and the gate of N4, and the gate of N6 is electrically connected to the gate of P4. NMOS transistor N7: The source of N7 is electrically connected to the source of N6, the drain of N7 is electrically connected to the drain of N3, and the gate of N7 is electrically connected to the gate of P3, the gate of N5, and the drain of N4. NMOS transistor N8: The source of N8 is electrically connected to the source of N7, the drain of N8 is electrically connected to the drain of N4, and the gate of N8 is electrically connected to the gate of P4 and the gate of N6. NMOS transistor N9: The source of N9 is electrically connected to the bit line BL, the drain of N9 is electrically connected to the gate of P1, and the gate of N9 is electrically connected to the word line WL. NMOS transistor N10: The source of N10 is electrically connected to the bit line BLB, the drain of N10 is electrically connected to the gate of P2, and the gate of N10 is electrically connected to the word line WL. NMOS transistor N11: The source of N11 is electrically connected to the bit line BL, the drain of N11 is electrically connected to the drain of N7, and the gate of N11 is electrically connected to the word line WL. NMOS transistor N12: The source of N12 is electrically connected to the bit line BLB, the drain of N12 is electrically connected to the drain of N8, and the gate of N12 is electrically connected to the word line WL. VDD is electrically connected to the sources of P1, P2, P3 and P4, and VSS is electrically connected to the sources of N1, N2, N5, N6, N7 and N8. The drains of N9, N10, N11, and N12 are connected to nodes S1, S0, Q, and QN, respectively. Transistors P1, N1 and P2, N2 form inverter one, which is cross-coupled; P3, N7 and P4, N8 form inverter two, and N3 and N4 are added between the two inverter two to block the feedback loop and improve the stability of the memory cell.

2. The RHC-16T radiation-hardened SRAM cell based on polarity hardening technology according to claim 1, characterized in that, The gate length of transistors P1 to P4 and N1 to N12 is 65nm. The gate width of transistors P1, P2, P3 and P4 is 80nm, the gate width of transistors N1 and N2 is 280nm, and the gate width of transistors N3 to N12 is 140nm.

3. The RHC-16T radiation-resistant SRAM cell based on polarity hardening technology according to claim 1, wherein node Q and node QN are master storage nodes, and node S0 and node S1 are redundant nodes.

4. The RHC-16T radiation-hardened SRAM cell based on polarity hardening technology according to claim 3, wherein when the radiation-hardened SRAM cell is in hold operation, the bit lines BL and BLB are precharged to a high level, the word line WL is at a low level, and the circuit maintains its initial state.

5. The RHC-16T radiation-hardened SRAM cell based on polarity hardening technology according to claim 3, wherein when the radiation-hardened SRAM cell is in a read operation, bit lines BL and BLB are precharged to a high level, word line WL is at a high level, and transistors N9, N10, N11, and N12 are turned on.

6. The RHC-16T radiation-hardened SRAM cell based on polarity hardening technology according to claim 5, if the data stored in the radiation-hardened SRAM cell is "0", that is, "Q=S1=0, QN=S0=1", the bit line BL is discharged to ground through discharge path 1: N9 and N2, discharge path 2: N9 and N5, and discharge path 3: N11 and N7, so that the bit lines BL and BLB generate a potential difference, and the data is read out by a sensitive amplifier; if the data stored in the radiation-hardened SRAM cell is "1", that is, "Q=S1=1, QN=S0=0", the bit line BLB is discharged to ground through discharge path 1: N10 and N1, discharge path 2: N10 and N6, and discharge path 3: N12 and N8, so that the bit lines BL and BLB generate a potential difference, and the data is read out by a sensitive amplifier.

7. The RHC-16T radiation-hardened SRAM cell based on polarity hardening technology according to claim 3, wherein when the radiation-hardened SRAM cell is in a write operation, the bit lines BL and BLB are precharged to the level signal to be written, the word line WL is high, and transistors N9, N10, N11 and N12 are turned on.

8. The RHC-16T radiation-resistant SRAM cell based on polarity hardening technology according to claim 7, if bit line BL is high and bit line BLB is low, then "1" is written to memory nodes S1 and Q respectively through transistors N9 and N11; if bit line BL is low and bit line BLB is high, then "1" is written to memory nodes QN and S0 respectively through transistors N10 and N12.

9. A radiation-hardened SRAM chip based on polarity hardening technology, characterized in that, It is packaged using the RHC-16T radiation-hardened SRAM cell based on polarity hardening technology as described in any one of claims 1-8, wherein the pins of the radiation-hardened SRAM chip include: The first pin is electrically connected to the gate of transistors N9 to N12 via word line WL; The second pin is electrically connected to the source of transistor N9 and the source of transistor N11 via bit line BL; The third pin is electrically connected to the source of transistors N10 and N12 via the bit line BLB.

10. An RHC-16T radiation-hardened SRAM module based on polarity hardening technology, characterized in that, It employs the circuitry of the RHC-16T radiation-hardened SRAM cell based on polarity hardening technology as described in any one of claims 1-8, wherein the radiation-hardened SRAM module comprises: The gates of transistors N9, N10, N11, and N12 are electrically connected to word lines WL, thereby leading to the first connection terminal; The source electrical connection bit line BL of transistors N9 and N11 leads to the second connection terminal; The source electrical connection bit line BLB of transistors N10 and N12 leads to the third connection terminal.

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