Method and storage device for over-erasure repair

Abstract

The present application provides a method for performing over-erasure repair on a non-volatile memory, a storage device capable of executing the method, and a computer-readable medium storing instructions for executing the method, wherein the non-volatile memory includes multiple storage blocks, and the method includes: a. performing local over-erasure repair on a first storage block among the multiple storage blocks, wherein the local over-erasure repair is performed word-by-word; b. performing full-word-line over-erasure verification on storage cells in the multiple storage blocks; and c. in response to determining that over-erased storage cells exist in storage cells on all word lines, performing local over-erasure repair on one storage block among the multiple storage blocks for which local over-erasure repair has not been performed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a programming method and a storage device for performing erased repair on a non-volatile memory. Background Art

[0002] As we enter the information age, the requirements for information storage are getting higher and higher, and thus the requirements for storage devices such as computers are also getting higher and higher. Non-volatile memory, as a storage medium that can be rewritten when in use, is widely used in various storage devices. Non-volatile memories such as flash memory, erasable programmable read-only memory (EPROM), and electronically erasable programmable read-only memory (EEPROM) can erase the storage unit and then reprogram the storage unit to delete the previously stored information and record new information.

[0003] However, during the erasing process, over-erasure may occur, which may affect programming, directly affect the normal operation of the memory, and even cause functional errors. Therefore, how to accurately and quickly detect the over-erasure phenomenon, thereby preventing the adverse effects caused by the over-erasure state and ensuring the normal operation of the memory has become one of the problems that technicians in this field need to solve urgently.

[0004] In the conventional over-erase repair process, the number and location of the storage cells with over-erase problems on the same bit line (BL) cannot be determined, so the leakage size cannot be well controlled. The problem brought about by this is that if the leakage is too large, it is very likely to exceed the load capacity of the BL charge pump. Once this happens, the efficiency of over-erase repair will be affected, and in extreme cases, the over-erase repair effect will not be achieved, resulting in functional failure.

[0005] In addition, conventional over-erase verification and repair both require a relatively low voltage source to bias all word lines, which requires a large load, and this is usually implemented through a voltage regulator, thereby consuming considerable chip area. Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] The present application is completed in view of the above-mentioned existing problems, and its purpose is to provide a method and a storage device for performing erased repair on a non-volatile memory, which can accurately and efficiently repair erased storage cells (ZQ: hereinafter referred to as ZQ).

[0008] Technical solutions to technical problems

[0009] In one embodiment of the present application for solving the above problem, a method for performing over-erasure repair on a non-volatile memory is provided, wherein the non-volatile memory includes a plurality of storage blocks, and the method includes:

[0010] a. performing local over-erasure repair on a first storage block among the plurality of storage blocks, the local over-erasure repair being performed word-by-word (WL: Word Line) and comprising: biasing a current word line to a first voltage to perform over-erasure verification on storage cells on the current word line, the first voltage being higher than voltages of other word lines in the first storage block; and in response to determining that an over-erased storage cell exists on the current word line, performing a repair operation on the over-erased storage cell on the current word line;

[0011] b. performing full word line over-erasure verification on the memory cells in the plurality of memory blocks, comprising: biasing all word lines in the plurality of memory blocks to a second voltage at the same time to perform over-erasure verification on the memory cells on all word lines; and

[0012] c. In response to determining that over-erased memory cells exist in the memory cells on all the word lines, performing the local over-erased repair on one of the memory blocks among the plurality of memory blocks on which the local over-erased repair has not been performed.

[0013] In one embodiment of the present application, step b and step c are repeated until there are no over-erased memory cells in the plurality of memory blocks.

[0014] In one embodiment of the present application, the local over-erasure repair further includes: determining the number and location of over-erased storage cells existing on the current word line.

[0015] In an embodiment of the present application, the over-erasure verification includes: determining whether the threshold voltage of the memory cell on the current word line is lower than a bottom voltage, the bottom voltage being a minimum value of an expected threshold voltage distribution of the erased memory cell.

[0016] In an embodiment of the present application, during the execution of the local over-erase repair, the voltage of the other word lines is biased to a negative voltage.

[0017] In an embodiment of the present application, the second voltage is 0V.

[0018] In one embodiment of the present application that solves the above-mentioned problem, a storage device is provided, comprising: a plurality of storage blocks, each storage block comprising an array of storage cells and a plurality of word lines, each of the plurality of word lines being coupled to a row of storage cells in the array of storage cells; and a controller, the controller being configured to execute a method as described in any one of the above-mentioned embodiments to perform over-erasure repair on the plurality of storage blocks.

[0019] In one embodiment of the present application that solves the above-mentioned problem, a non-volatile computer-readable storage medium is provided, on which instructions are stored, and when the instructions are executed by a processor, the processor executes a method as described in any one of the above-mentioned embodiments.

[0020] Effects of the Invention

[0021] According to the present application, erased storage cells can be repaired accurately and efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to be able to understand the present application in detail, a more specific description of the present application briefly summarized above can be obtained by reference to the embodiments, some of which are shown in the accompanying drawings. In order to facilitate understanding, the same reference numerals have been used as much as possible to indicate the same elements common to the various figures. However, it should be noted that the accompanying drawings only show typical embodiments of the present application and therefore should not be considered to limit the scope of the present application, because the present application may allow other equivalent embodiments. In the accompanying drawings:

[0023] Figure 1 is a schematic diagram showing voltage distribution of erased and programmed memory cells under normal conditions involved in the present application.

[0024] Figure 2 is a schematic diagram showing voltage distribution of erased and programmed memory cells in the presence of over-erasure phenomenon involved in the present application.

[0025] Figure 3 is a schematic diagram showing a memory cell in a case where an over-erasure phenomenon occurs in a nonvolatile memory.

[0026] Figure 4 Detailed description is a flowchart showing an example of a method for performing erase repair on a non-volatile memory according to an embodiment of the present application.

[0027] Figure 5 1 is a flowchart showing another example of a method for performing erase repair on a non-volatile memory according to an embodiment of the present application.

[0028] Figure 6 is a schematic block diagram showing a storage device according to an embodiment of the present application.

[0029] It is contemplated that elements of one embodiment of the disclosure may be beneficially applied to other embodiments without further recitation. DETAILED DESCRIPTION

[0030] The following is explained through specific embodiments, and those skilled in the art can clearly understand other advantages and technical effects of the present application from the contents disclosed in this specification. In addition, the present application is not limited to the following specific embodiments, and can also be implemented or applied through other different embodiments, and various modifications and changes can be made to the specific contents in this specification without departing from the spirit of the present application.

[0031] The present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "other embodiments", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "other embodiments" or "some embodiments" mentioned twice or multiple times in different positions in this specification do not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0032] It should be noted that in order to simplify the description disclosed in this application and thus help understand one or more embodiments, in the following description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the subject matter of this application requires more features than those mentioned in the claims. In fact, the features of an embodiment are less than all the features of a single embodiment disclosed below.

[0033] Below, specific embodiments of the present application are described in detail based on the accompanying drawings. The listed drawings are only for simple explanation and are not depicted according to actual size. They do not reflect the actual size of the relevant structures. For ease of understanding, the same reference numerals are used in the drawings to indicate the same elements shared by the drawings. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further description.

[0034] Below, refer to Figures 1 to 3 , the formation principle and influence of the over-erasure phenomenon involved in this application are briefly explained.

[0035] For non-volatile memory such as NOR flash memory, after the erase operation and write operation of the non-volatile memory are completed, the threshold voltage (VT: Threshold Voltage) of the erased storage cell of the non-volatile memory is generally distributed between 1V and 4V, while the threshold voltage (VT: Threshold Voltage) of the storage cell subjected to the write operation is generally distributed between 7V and 9V, such as Figure 1 As shown. Under normal circumstances, the minimum VT of the erased memory cells is 1V. When these memory cells are not selected (the word line voltage is 0), the difference between the gate-source voltage (VGS: Gate-Source Voltage) and VT of the memory cells of the non-volatile memory is -1V, that is, VGS-VT = -1V, so the memory cells will not leak electricity. It should be noted that Figure 1 The voltage V1 in (corresponding to the maximum value of the threshold voltage distribution of the erased memory cell, for example, 1V) can be used as the bottom voltage (i.e., the minimum value of the expected threshold voltage distribution of the erased memory cell) for over-erasure verification (also referred to as bottom voltage verification). Figure 1 The voltage V2 in (corresponding to the maximum value of the threshold voltage distribution of the erased memory cell, for example, 4V) can be used to verify whether the memory cell has been erased, which will be further described below.

[0036] However, due to the influence of various factors such as the inconsistency of the storage cells of the non-volatile memory, the erase and write operation cycles, and the erase operation control, the over-erasure situation where the voltage of the storage cell after the erase operation is less than 0V will often occur, which will not only occur on the storage cell currently being erased, but may also affect the storage cells in other areas of the shared substrate, thereby causing the VT to drop to near 0V. Figure 2 As shown, when the over-erasure phenomenon is serious and the VT is lower or more memory cells are over-erased, there is a large leakage on the bit lines where leakage occurs. Even if these memory cells are not selected, it will have a negative impact on the selected memory cells that are to perform normal operations, and even functional errors may occur.

[0037] like Figure 3 As shown, for example, WL1 / BL0 is the memory cell being operated. Due to power failure or other uncontrollable factors during the erase process, the memory cell on WL1 / BL0 may leak. If the VT of other unselected memory cells (WL=0) on BL0 is less than 0 and the number is large, these memory cells will also generate large leakage on BL0 and have the following serious effects:

[0038] 1. During the read / verify operation, due to the influence of leakage on the BL, the VT of the read operation or the verify operation will be lower than the VT of the actually selected storage cell; and / or

[0039] 2. The write operation will cause the current generated by the charge pump to be seriously reduced in write efficiency due to these leakages (assuming that the charge pump outputs a certain BL current), and may even fail.

[0040] exist Figure 4 An example of a method for performing erased repair on a non-volatile memory according to the present application is shown in FIG.

[0041] The example method 400 may start at step 401. At step 401, a local over-erase repair may be performed on a first storage block among a plurality of storage blocks included in a non-volatile memory. This local over-erase repair may be performed in a word-line manner and may include: 1) biasing a current word line to a first voltage to perform an over-erase check on a storage cell on the current word line, wherein the first voltage may be higher than the voltage of other word lines in the first storage block (as a non-limiting example, the first voltage may be 3V, 5V, 10V, etc., while the voltage of other word lines may be 0V, -1V, -3V, etc.); and 2) in response to determining that an over-erased storage cell exists on the current word line, performing a repair operation on the over-erased storage cell on the current word line. The first storage block may be a non-volatile memory.

[0042] Optionally, the local over-erasure repair may further include: determining the number and position of over-erased storage cells on the current word line. Thus, information about the number and position of over-erased cells may be provided to an internal processor or an external processor, and then the information may be provided to a user (e.g., transmitting the information to the user via a transmission device or displaying the information to the user via a display device, etc.) or a computer device (e.g., sending the information to a computer device by wire or wirelessly so that the computer device can respond according to the information, etc.).

[0043] As a non-limiting example of over-erasure verification, the over-erasure verification may include: determining whether the threshold voltage of the memory cell on the current word line is lower than the bottom voltage, the bottom voltage being the minimum value of the expected threshold voltage distribution of the erased memory cell. If it is determined that the threshold voltage of the memory cell on the current word line is lower than the bottom voltage, it may be determined that the memory cell is in an over-erasure state.

[0044] As an example of a specific operation, for example, since the memory cell can be regarded as equivalent to NMOS (N-Metal-Oxide-Semiconductor), when a certain voltage, namely the gate voltage (VG: Gate Voltage) is applied to the word line, the voltage and the VT of the memory cell can generate a certain amount of current (for example, when VG>VT, the voltage may generate the following current: I 存储单元 =K×(VG-VT) 2From this equation, we can see that the current value of the memory cell is directly determined by the value of VG-VT, and K is a relatively large value, so it can be roughly understood that when VG is slightly larger than VT, there will be current, and VG can be equivalent to the VT of the memory cell). The current of the memory cell can be compared with the reference current (this reference current can be a preset constant current). When I 存储单元 If it is greater than this specific value, it means that VT is too small, otherwise it means that VT is too large. Therefore, the word line voltage can be used to control I 存储单元 Then, the voltage VG is compared with the reference current to determine the VT of the memory cell. As a more specific example, for example, if the memory cell that has been over-erased is defined as a memory cell with VT<0V, if the selected word line is biased to 0V (VG=0), then I 存储单元 =K(0-VT) 2 , which must be greater than 0, and if I 存储单元 If the current is greater than the set reference current, the memory cell is considered to be in an over-erased state.

[0045] Optionally, during the execution of the local over-erase repair, the voltage of other word lines (ie, unselected word lines) may be biased to a negative voltage, thereby achieving VGS<<0, and avoiding the influence of leakage caused by the over-erase phenomenon.

[0046] At step 402, a full word line over-erasure check may be performed on the memory cells in the plurality of memory blocks of the non-volatile memory. The full word line over-erasure check may include: biasing all word lines in the plurality of memory blocks to a second voltage at the same time to perform an over-erasure check on the memory cells on all word lines. Through the full word line over-erasure check, it may be checked whether there are other memory cells other than the first memory block (for example, in other memory blocks sharing the same substrate with the first memory block) that are affected by the erasure action to become an over-erasure state (at this time, there are no over-erased memory cells in the first memory block). As an example of a preferred embodiment, the second voltage may be 0V. However, it is not limited thereto, and the second voltage may also be other values, for example, a value lower than the bottom voltage value of the erased memory cell.

[0047] At step 403, in response to determining that over-erased memory cells exist in the memory cells on all word lines, local over-erasing repair may be performed on one of the memory blocks among the plurality of memory blocks on which local over-erasing repair has not been performed.

[0048] Optionally, step 402 and step 403 may be repeated until there are no over-erased storage units in the plurality of storage blocks. Thus, over-erased repair of the memory may be performed accurately and efficiently.

[0049] exist Figure 5Another specific non-limiting example of a method for performing erase repair on a non-volatile memory including a plurality of storage blocks is shown in FIG.

[0050] The method 500 may start at step 501. At step 501, a block erase check may be performed on a first storage block among a plurality of storage blocks. Figure 1 The block erase verification may be to check the maximum value of the voltage distribution of the erased memory cells (eg Figure 1 Is there a certain margin between the voltage V2 in the read voltage (for example, Figure 1 As a specific example, when an erase operation is completed, a memory cell A on a word line has a VT slightly smaller than 4V, and another memory cell B has a VT slightly larger than 4V. At this time, when 4V is applied to the word line for verification, the I of the memory cell A is 存储单元 is greater than the reference current, it can be seen that the VT of memory cell A is lower than 4V and has reached the specified voltage range, so it does not need to be erased. The I 存储单元 If the block erase verification succeeds (i.e., passes the verification), the method 500 may proceed to step 505 described later. If the block erase verification fails (i.e., fails the verification), the method 500 may proceed to step 502.

[0051] At step 502 , a block erase operation may be performed to erase a first memory block.

[0052] At step 503, an over-erasure check may be performed on the memory cells on each word line in the first memory block in a word-by-word manner. Specifically, the current word line (e.g., the selected word line) may be biased to a first voltage (e.g., 5V) higher than the voltages of other word lines in the first memory block to perform an over-erasure check on the memory cells on the current word line. Figure 1 The over-erasure verification may be to compare the minimum VT value and the bottom voltage (eg Figure 1, if the VT minimum value is lower than the bottom voltage, it can be determined that the storage cell has been over-erased. As another example, it can be determined whether there is a certain margin between the VT minimum value of the erased storage cell in the first storage block and 0V. If there is no certain margin (such as the VT minimum value is less than 0V), it can be determined that the storage cell has been over-erased. When the over-erasure check succeeds (i.e., passes the check) and no over-erased storage cell is detected, the method 500 can return to the aforementioned step 501. When the over-erasure check fails (i.e., fails the check) and an over-erased storage cell is detected, the method 500 can proceed to step 504.

[0053] At step 504, in response to determining that there are over-erased memory cells on the selected word line in the first storage block, a repair operation may be performed on the over-erased memory cells on the selected word line to eliminate the over-erasure problem of the memory cells on the word line. When step 504 is completed, method 500 may return to the aforementioned step 503 to continue to perform over-erasure verification on the selected word line or memory cells on other word lines in the first storage block.

[0054] At step 505, a full word line over-erasure check may be performed on the memory cells in the plurality of memory blocks. All word lines in the plurality of memory blocks may be biased to a second voltage (e.g., 0V) at the same time to perform an over-erasure check on the memory cells on all word lines in the plurality of memory blocks. When the full word line over-erasure check succeeds (i.e., passes the check) and no over-erased memory cells are detected, it may be indicated that the memory cells in the plurality of memory blocks being checked have no over-erasure phenomenon, and the method 500 is completed. When the full word line erasure check fails (i.e., fails the check) and an over-erased memory cell is detected, the method 500 may proceed to step 506.

[0055] At step 506, in response to determining that there are over-erased memory cells in the memory cells on all word lines, an over-erasure check may be performed on the memory cells on each word line in the memory blocks that have not been over-erased in the multiple memory blocks in a word-by-word manner. The process of this over-erasure check may be similar to or equivalent to the process of over-erasure check performed on the memory cells on each word line in the first memory block in step 503. When the over-erasure check succeeds (i.e., passes the check) and no over-erased memory cells are detected, it may be indicated that there is no over-erasure phenomenon in the memory cells in the multiple memory blocks being checked, and method 500 is completed. When the over-erasure check fails (i.e., fails the check) and an over-erased memory cell is detected, method 500 may proceed to step 507.

[0056] At step 507, in response to the presence of over-erased memory cells on the selected word line of the memory block on which the erasure check is performed in step 506, a repair operation may be performed on the over-erased memory cells on the selected word line to eliminate the over-erasure problem of the memory cells on the word line. When step 507 is completed, method 500 may return to the aforementioned step 506 to continue to perform over-erasure checks on the memory cells on the selected word line or other word lines.

[0057] In some embodiments, the operations included in the methods in the above embodiments may occur simultaneously, substantially simultaneously, or in an order different from that shown in the drawings.

[0058] In some embodiments, all or part of the operations included in the methods in the above embodiments may be optionally automatically performed by a program. In one example, the present application may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The (multiple) programs of the program product include the functions of the embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) a non-writable storage medium (e.g., a read-only memory device in a computer, such as a CD-ROM disk, flash memory, ROM chip, or any type of solid-state non-volatile semiconductor memory that can be read by a CD-ROM drive), on which information is permanently stored; and (ii) a writable storage medium (e.g., a disk storage or hard disk drive or any type of solid-state random access semiconductor memory), on which changeable information is stored. When implementing computer-readable instructions indicating the functions of the methods described herein, such a computer-readable storage medium is an embodiment of the present application.

[0059] exist Figure 6 An example of a storage device involved in the present application is shown in . The exemplary storage device 600 may include a plurality of storage blocks 610-1 to 610-n (n is a natural number greater than or equal to 2) and a controller 620. Each of the storage blocks 610-1 to 610-n may include an array of storage cells and a plurality of word lines, and each of the plurality of word lines may be coupled to a row of storage cells in the array of storage cells. It should be noted that "a row" does not necessarily refer to a row in a physical sense, but may refer to a collection of storage cells in an array of storage cells that are assigned to the same word line address. The controller 620 may be configured to perform erase repair on the plurality of storage blocks, for example, by the methods described in the above embodiments and other methods.

[0060] According to the present application, erased storage cells can be repaired accurately and efficiently.

[0061] According to the present application, by performing over-erasure verification and repair on each word line in the storage block, even if over-erasure occurs in the storage cell, it will not be affected because the non-selected word line is a negative voltage. Therefore, the number of storage cells that need to be repaired is easy to determine, ensuring the efficiency of the repair and preventing the charge pump from being overloaded.

[0062] According to the present application, since the over-erasure check performed on the first storage block and the over-erasure check performed on other storage blocks outside the first storage block can be the same or similar operations, except for the address range, the method is relatively simple for the control device (such as a state machine), thereby enabling the chip to occupy a smaller area.

[0063] According to the present application, by biasing all word lines of multiple storage blocks to the second voltage, since only the second voltage is needed to perform over-erasure detection, there is no need to use a voltage regulator as in conventional technology to bias all word lines, thereby saving chip area.

[0064] The optional embodiments of the present application are described in detail above. However, it should be understood that various embodiments and variations can be adopted without departing from the broad spirit and scope of the present application. A person of ordinary skill in the art can make many modifications and changes according to the concept of the present application without creative work. As a non-limiting example, a person skilled in the art may omit one or more of the various parts in the above-mentioned system or structure or add one or more parts to the above-mentioned system or structure, or replace a part or all of the various structures or systems involved in the present embodiment with other parts having the same or similar functions. Therefore, all technical solutions that can be obtained by logical analysis, reasoning or limited experiments based on the concept of the present application on the basis of the prior art should belong to the scope of protection determined by the claims of the present application.

[0065] It should be noted that although the present disclosure includes several embodiments, these embodiments are all non-restrictive (regardless of whether they have been marked as exemplary), and there are changes, substitutions and equivalents, which all fall within the scope of the present application. In addition, the described embodiments should not be interpreted as mutually exclusive, and on the contrary should be understood as potentially combinable (if these combinations are allowed). It should also be noted that there are many alternatives to realize the embodiments of the present disclosure. Therefore, the application is intended to interpret the attached claims as including all such changes, substitutions and equivalents that fall within the true spirit and scope of the present disclosure.

Claims

1. A method for performing over-erasure repair on a non-volatile memory, wherein the non-volatile memory comprises a plurality of storage blocks, the method comprising: a. performing a local over-erasure repair on a first memory block of the plurality of memory blocks, the local over-erasure repair being performed word-by-word and comprising: biasing a current word line to a first voltage to perform an over-erasure verification on memory cells on the current word line, the first voltage being higher than voltages of other word lines in the first memory block; and In response to determining that an over-erased memory cell exists on the current word line, performing a repair operation on the over-erased memory cell on the current word line; b. performing full word line over-erasure verification on the memory cells in the plurality of memory blocks, comprising: biasing all word lines in the plurality of memory blocks to a second voltage at the same time to perform over-erasure verification on the memory cells on all word lines; and c. In response to determining that over-erased memory cells exist in the memory cells on all the word lines, performing the local over-erased repair on one of the memory blocks among the plurality of memory blocks on which the local over-erased repair has not been performed.

2. The method according to claim 1, characterized in that Repeat step b and step c until there is no over-erased memory cell in the plurality of memory blocks.

3. The method according to claim 1, characterized in that The local over-erasure repair further includes: determining the number and location of over-erased storage cells existing on the current word line.

4. The method according to claim 1, characterized in that The over-erase verification includes determining whether a threshold voltage of a memory cell on the current word line is lower than a bottom voltage, the bottom voltage being a minimum value of an expected threshold voltage distribution of erased memory cells.

5. The method according to claim 1, characterized in that During the execution of the local over-erase repair, the voltage of the other word lines is biased to a negative voltage.

6. The method according to claim 1, characterized in that The second voltage is 0V.

7. A storage device, comprising: a plurality of memory blocks, each memory block comprising an array of memory cells and a plurality of word lines, each of the plurality of word lines being coupled to a row of memory cells in the array of memory cells; A controller is configured to execute the method according to any one of claims 1 to 6 to perform erasure repair on the plurality of storage blocks.

8. A non-transitory computer-readable storage medium having instructions stored thereon, which, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 6.

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