Detection Structure, Preparation and Detection Method for e-fuse Etching

Abstract

The present invention provides a detection structure, preparation and detection method for e-fuse etching. A reference metal layer and a detection metal layer are formed in a wafer dicing area and are synchronously formed with the e-fuse located in the active area of the wafer. The reference metal layer includes a reference metal connecting member and a reference metal resistance member, and the detection metal layer includes a detection metal connecting member and a detection metal resistance member. Metal columns and pads for electrical testing are correspondingly provided above the reference metal connecting member and the detection metal connecting member and are connected. Therefore, during the etching process, since there is a dielectric layer detection window above the detection metal resistance member, the detection metal resistance member is etched, causing the resistance value of the detection metal resistance member to change. Therefore, by monitoring the electrical performance data, i.e., the change in the resistance value, of the detection metal resistance member and the reference metal resistance member, the e-fuse etching situation can be reflected, eliminating the need for slice confirmation.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and particularly relates to a detection structure, preparation method, and detection method for e-fuse etching. Background Art

[0002] In the wafer manufacturing process, it is often necessary to connect the components formed in each film layer together to form a complete semiconductor device, or to connect the semiconductor device to other electronic components to form the required electronic circuit. To complete these connections, many pads need to be formed. It can be said that pads are important connection components in the wafer manufacturing process. Therefore, in the semiconductor field, pads have high requirements for conductivity and reliability.

[0003] An electronic fuse (e-fuse) is a protection device with a simple structure and convenient use, which is widely used in various electronic products. It uses a metal wire as a fuse element connected in series in the circuit. When an overload or short-circuit current passes through the fuse element, it melts due to its own heat generation, thereby breaking the circuit to play a protective role.

[0004] PAD is usually composed of the top metal layer of the wafer, and e-Fuse usually uses the metal layer below the top metal layer. During the preparation process, e-Fuse and PAD often use the same photomask, so the e-Fuse window opening is synchronized with the PAD window opening. In order to ensure the complete exposure of PAD for subsequent electrical connection in the manufacturing process, PAD over-etching is performed in the existing preparation process. In the detection of this etching process, the common practice in the industry is to capture the Ti / TiN signal on the upper layer of PAD, and then etch for a certain time to open Ti / TiN, or directly etch for a certain time and lose a little of the top metal layer and then default that PAD has been opened. However, the over-etching process of PAD will cause certain damage to the metal wires in the e-Fuse area and cause over-etching of the dielectric layer on both sides of the metal wires, affecting the performance of e-Fuse. Therefore, it is necessary to detect the etching situation of e-Fuse. Currently, the detection of this over-etching process can usually only be observed through failure analysis (FA) slicing, and the test convenience is extremely low. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a detection structure, preparation method, and detection method for e-fuse etching, which are used to solve the problem that it is difficult to perform convenient operations on the detection of e-fuse etching in the prior art.

[0006] To achieve the above purpose and other related purposes, the present invention provides a detection structure for e-fuse etching, and the detection structure includes:

[0007] A substrate, the substrate including a wafer active region and a wafer dicing region;

[0008] A reference metal layer, the reference metal layer being located on the wafer dicing region of the substrate, the reference metal layer including two spaced reference metal connectors and reference metal resistors correspondingly connected to the reference metal connectors, and the reference metal resistors being synchronously formed with the e-fuse located in the wafer active region;

[0009] A detection metal layer, the detection metal layer being located on the wafer dicing region of the substrate, the detection metal layer having the same morphology as the reference metal layer, the detection metal layer including two spaced detection metal connectors and detection metal resistors correspondingly connected to the detection metal connectors, and the detection metal resistors being synchronously formed with the e-fuse located in the wafer active region;

[0010] Metal pillars, the metal pillars being located on the reference metal connectors and the detection metal connectors, and one end of the metal pillars being connected to the corresponding reference metal connectors and detection metal connectors;

[0011] Bonding pads, the bonding pads being located on the metal pillars, and the bonding pads being connected to the other ends of the metal pillars;

[0012] A dielectric layer, the dielectric layer being located on the substrate to cover the substrate, the reference metal layer, the detection metal layer and the metal pillars, and the dielectric layer having a dielectric layer detection window exposing the bonding pads and a dielectric layer detection window exposing the detection metal resistors.

[0013] Optionally, the reference metal layer and the detection metal layer are both located in the wafer edge dicing region, both located in the wafer center dicing region, or distributed across the entire wafer dicing region.

[0014] Optionally, the reference metal layer and the detection metal layer are located in the wafer dicing regions of adjacent chips.

[0015] Optionally, the morphology of the detection metal resistors is linear or curved.

[0016] Optionally, the dielectric layer detection window completely exposes the detection metal resistors or exposes a part of the detection metal resistors.

[0017] The present invention also provides a preparation method for an e-fuse etching detection structure, including the following steps:

[0018] Provide a substrate, the substrate including a wafer active region and a wafer dicing region;

[0019] A reference metal layer and a detection metal layer with the same morphology are formed on the wafer dicing area of the substrate. Among them, the reference metal layer includes two reference metal connectors arranged at intervals and reference metal resistors correspondingly connected to the reference metal connectors. The detection metal layer includes two detection metal connectors arranged at intervals and detection metal resistors correspondingly connected to the detection metal connectors. And the reference metal layer and the detection metal layer are formed synchronously with the e-fuse located in the active area of the wafer.

[0020] A metal pillar, a pad and a dielectric layer are formed on the substrate. Among them, the metal pillar is located on the reference metal connector and the detection metal connector, and one end of the metal pillar is connected to the corresponding reference metal connector and the detection metal connector; the pad is located on the metal pillar, and the pad is connected to the other end of the metal pillar; the dielectric layer is located on the substrate to cover the substrate, the reference metal layer, the detection metal layer and the metal pillar.

[0021] A mask layer is formed on the dielectric layer and patterned.

[0022] The dielectric layer is etched to form a dielectric layer detection window exposing the pad and a dielectric layer detection window exposing the detection metal resistor.

[0023] Optionally, the dielectric layer includes a silicon oxide layer.

[0024] The present invention also provides a detection method for e-fuse etching, including the following steps:

[0025] Provide any one of the above detection structures;

[0026] Combined with the dielectric layer detection window, obtain the reference resistance value of the reference metal resistor and the detection resistance value of the detection metal resistor through the pad.

[0027] Compare the obtained reference resistance value with the detection resistance value to detect the etching of the e-fuse.

[0028] Optionally, the method of changing the detection resistance value includes changing one or a combination of the morphology of the detection metal resistor and the dielectric layer detection window.

[0029] Optionally, it further includes the step of comparing the detection resistance values of the detection metal resistors located in different wafer dicing areas to reflect the differences in the wafer manufacturing process in different areas.

[0030] As described above, the detection structure, preparation method and detection method for e-fuse etching of the present invention form a reference metal layer and a detection metal layer in the wafer cutting area that are synchronously formed with the e-fuse located in the active area of the wafer. Among them, the reference metal layer includes two reference metal connectors arranged at intervals and a reference metal resistor connected corresponding to the reference metal connectors. The detection metal layer includes two detection metal connectors arranged at intervals and a detection metal resistor connected corresponding to the detection metal connectors. And metal columns and pads for electrical testing are correspondingly arranged above the reference metal connectors and the detection metal connectors. Thus, during the etching process, since there is a dielectric layer detection window above the detection metal resistor, the detection metal resistor is etched, causing the resistance value of the detection metal resistor to change. Therefore, by monitoring the electrical performance data, that is, the change in the resistance value, of the detection metal resistor and the reference metal resistor, the situation of e-fuse etching can be reflected, eliminating the need for slice confirmation. Description of the Drawings

[0031] Figure 1 It shows a schematic diagram of the wafer structure in Embodiment 1 of the present invention.

[0032] Figure 2 It shows an enlarged schematic diagram of the detection structure in Embodiment 1 of the present invention.

[0033] Figure 3 It shows Figure 2 The cross-sectional structure schematic diagram along A-A in

[0034] Figure 4 It shows Figure 2 The cross-sectional structure schematic diagram along B-B in

[0035] Figure 5 It shows an enlarged schematic diagram of the reference metal layer and the dielectric layer window in Embodiment 1 of the present invention.

[0036] Figure 6 It shows Figure 5 The cross-sectional structure schematic diagram along A'-A' in

[0037] Figure 7 It shows an enlarged schematic diagram of the detection metal layer and the dielectric layer window in Embodiment 1 of the present invention.

[0038] Figure 8 It shows Figure 7 The cross-sectional structure schematic diagram along B'-B' in

[0039] Figure 9 It shows a process flow diagram for preparing the detection structure for e-fuse etching in Embodiment 2 of the present invention.

[0040] Figure 10 Shown is a flowchart for e-fuse etching detection in the third embodiment of the present invention.

[0041] Component label description

[0042] 10 Wafer

[0043] 20 Wafer active region

[0044] 30 Wafer dicing area

[0045] 100 Substrate

[0046] 201 Metal connector

[0047] 202 Electronic fuse

[0048] 211 Reference metal connector

[0049] 212 Reference metal resistor

[0050] 221 Detection metal connector

[0051] 222 Detection metal resistor

[0052] 300 Metal post

[0053] 400 Pad

[0054] 500 Dielectric layer

[0055] 511 Dielectric layer detection window

[0056] 512 Dielectric layer inspection window

[0057] Steps S1 to S5, Sa to Sc Detailed implementation manners

[0058] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0060] For convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers. Herein, when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element.

[0061] Herein, expressions such as "between... and..." may be used, which means including the endpoint values, and expressions such as "a plurality of" may be used, which means two or more, unless otherwise specifically defined. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the number of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0062] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, numbers, and proportions of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0063] Embodiment 1

[0064] As Figures 1 to 8 , this embodiment provides a detection structure for e-fuse etching, and the detection structure includes:

[0065] A substrate 100, the substrate 100 includes a wafer active region 20 and a wafer dicing region 30;

[0066] A reference metal layer, the reference metal layer is located on the wafer dicing region 30 of the substrate 100, the reference metal layer includes two spaced reference metal connectors 211 and a reference metal resistor 212 corresponding to and connected to the reference metal connectors 211, and the reference metal resistor 212 and the e-fuse located in the wafer active region 20 are formed synchronously;

[0067] A detection metal layer is detected. The detection metal layer is located on the wafer dicing area 30 of the substrate 100. The detection metal layer has the same morphology as the reference metal layer. The detection metal layer includes two spaced detection metal connectors 221 and detection metal resistors 222 correspondingly connected to the detection metal connectors 221. Moreover, the detection metal resistors 222 and the e-fuse located in the wafer active area 30 are synchronously formed;

[0068] A metal post 300 is provided. The metal post 300 is located on the reference metal connector 211 and the detection metal connector 221. One end of the metal post 300 is connected to the corresponding reference metal connector 211 and detection metal connector 221;

[0069] A pad 400 is provided. The pad 400 is located on the metal post 300. The pad 400 is connected to the other end of the metal post 300;

[0070] A dielectric layer 500 is provided. The dielectric layer 500 is located on the substrate 100 to cover the substrate 100, the reference metal layer, the detection metal layer and the metal post 300. Moreover, a dielectric layer detection window 511 exposing the pad 400 and a dielectric layer detection window 512 exposing the detection metal resistor 222 are provided in the dielectric layer 500.

[0071] Specifically, referring to Figure 1 , during the preparation process of the wafer 10, usually several to thousands or even tens of thousands of chips are included on one wafer 10. Scribing lanes are provided between adjacent chips to facilitate subsequent chip separation. In this embodiment, the area occupied by the chips in the wafer 10 is called the wafer active area 20, the area occupied by the scribing lanes is called the wafer dicing area 30. Moreover, the detection structure involved in this application is preferably located in the wafer dicing area 30 to reduce the occupation of the effective area of the wafer.

[0072] Among them, during the preparation process of the wafer 10, referring to Figures 2 to 4 , pads (PADs) 400 and electronic fuses (e-fuses) 202 are provided in the wafer active area 20. The pads 400 are used for electrical connection. The electronic fuses 202 use metal wires as fuses and are connected in series in the circuit to play a role in protecting the circuit. The pads 400 are usually composed of the top metal layer of the wafer 10. The electronic fuses 202 usually use the metal layer one layer below the top metal layer. Moreover, the electronic fuses 202 are connected to the pads 400 through metal connectors 201 and metal posts 300 located on the metal connectors 201.

[0073] During the manufacturing process, the same photomask is often used for the electronic fuse 202 and the pad 400. Therefore, the opening window of the electronic fuse 202, i.e., the etching window located in the dielectric layer 500, is carried out synchronously with the opening window of the pad 400, as Figure 3 , and in order to ensure the complete exposure of the pad 400 in the manufacturing process for subsequent electrical connection, the pad 400 is over-etched in the existing manufacturing process. During this etching process, the metal wires of the electronic fuse 202 will be damaged to a certain extent, and the dielectric layer 500 will be over-etched on both sides of the metal wires, as Figure 4 , which affects the performance of the electronic fuse 202. Therefore, it is necessary to detect the etching condition of the electronic fuse 202.

[0074] Referring to Figures 5 to 8 , in this embodiment, to improve the detection of the etching condition of the e-fuse, the reference metal layer and the detection metal layer are prepared in the wafer dicing area 30 while the e-fuse is being prepared. Among them, the reference metal layer includes two spaced reference metal connectors 211 and a reference metal resistor 212 correspondingly connected to the reference metal connectors 211. The detection metal layer includes two spaced detection metal connectors 221 and a detection metal resistor 222 correspondingly connected to the detection metal connectors 221. And above the reference metal connectors 211 and the detection metal connectors 221, there are correspondingly connected metal posts 300 and pads 400 for electrical testing. Thus, during the etching process, since there is a dielectric layer detection window 512 above the detection metal resistor 222, the detection metal resistor 222 is etched, causing the resistance value of the detection metal resistor 222 to change. Therefore, by exposing the dielectric layer detection window 511 of the pad 400, the electrical performance data of the detection metal resistor 222 and the reference metal resistor 212 can be collected, that is, the change in the resistance value of the detection metal resistor 222 and the reference metal resistor 212 can be monitored, which can reflect the etching condition of the e-fuse, thus avoiding the need for slice confirmation.

[0075] During the etching process to expose the pad 400, the dielectric layer 500 has a greater loss. For example, the dielectric layer 500 may include a silicon oxide dielectric layer, but is not limited thereto. During the etching process, the detection metal resistor 222 exposed in the dielectric layer detection window 512 will also be etched. Thus, according to the resistance principle, the resistance value of the detection metal resistor 222 will change. Since the dielectric layer 500 above the reference metal resistor 212 in the reference metal layer does not have the dielectric layer detection window 512, that is, the reference metal resistor 212 is covered by the dielectric layer 500, and the dielectric layer 500 above the reference metal resistor 212 is not etched during the etching process, the resistance value of the reference metal resistor 212 will not change. Therefore, by comparing the resistance values corresponding to the reference metal resistor 212 and the detection metal connector 222, the etching situation of the e-fuse can be known. Thus, the etching of the e-fuse can be monitored through the change of electrical performance data, that is, the resistance value, and the slicing operation can be avoided.

[0076] In this embodiment, the structure of the substrate 100 is not limited, and active or passive devices can be provided in the substrate 100 according to needs, and no excessive limitation is made here.

[0077] As an example, the reference metal layer and the detection metal layer can be simultaneously located in the wafer edge cutting area, simultaneously located in the wafer center cutting area, or simultaneously distributed in the entire wafer cutting area.

[0078] Specifically, for the need to detect the etching of the e-fuse located in different regions on the wafer 10, the reference metal layer and the detection metal layer can be simultaneously provided in the wafer edge cutting area, or simultaneously provided in the wafer center cutting area, or simultaneously distributed in the entire wafer cutting area, and no excessive limitation is made here.

[0079] Furthermore, to improve the detection accuracy of the detection structure for the e-fuse etching, it is preferred that the reference metal layer, the detection metal layer, and the e-fuse to be detected are arranged adjacent to each other. For example, the reference metal layer and the detection metal layer are located in the wafer cutting area (scribe line) of adjacent chips to be detected, and the specific spacing can be set according to needs, and no excessive limitation is made here.

[0080] Furthermore, when comparing the detected resistance values of the detection metal resistors 222 located in different wafer cutting areas 30, the differences in the wafer manufacturing process in different regions, such as processing differences, etc., can also be reflected, so as to facilitate the optimization of the wafer manufacturing process.

[0081] As an example, the morphology of the detection metal resistor 222 can be linear or curved.

[0082] Specifically, referring to Figure 5 and Figure 7 , in this embodiment, for the convenience of the processing technology and to improve the accuracy of detection, both the reference metal resistor 212 and the detection metal resistor 222 are in a curved shape. However, the morphologies of the reference metal resistor 212 and the detection metal resistor 222 are not limited thereto, and a straight shape or the like can also be adopted, and no excessive limitation is made here.

[0083] As an example, the dielectric layer detection window 512 can completely expose the detection metal resistor 222 or expose a part of the detection metal resistor 222.

[0084] Specifically, according to needs, the dielectric layer detection window 512 can completely expose the detection metal resistor 222 or partially expose the detection metal resistor 222, and specific selection can be made according to needs, and no excessive limitation is made here. For example Figure 7 , the dielectric layer detection windows 512 are arranged at intervals and expose a part of the detection metal resistor 222. However, it is not limited thereto, and the detection resistance value of the detection metal resistor 222 can be changed by changing one or a combination of the morphologies of the detection metal resistor 222 and the dielectric layer detection window 512, and specific settings can be made according to needs.

[0085] Embodiment 2

[0086] For example Figure 9 , this embodiment provides a preparation method for an e-fuse etching detection structure. This method can be used to prepare the detection structure in Embodiment 1, but the preparation process of the detection structure is not limited thereto. In this embodiment, the above detection structure is prepared by the following preparation process. Therefore, all statements about the detection structure can refer to Embodiment 1, and no further elaboration is made here.

[0087] Specifically, the preparation method may include the following steps:

[0088] S1: Provide a substrate, and the substrate includes a wafer active region and a wafer dicing region;

[0089] S2: Form a reference metal layer and a detection metal layer with the same morphology on the wafer dicing region of the substrate. Among them, the reference metal layer includes two reference metal connectors arranged at intervals and a reference metal resistor correspondingly connected to the reference metal connectors, the detection metal layer includes two detection metal connectors arranged at intervals and a detection metal resistor correspondingly connected to the detection metal connectors, and the reference metal layer and the detection metal layer are formed synchronously with the e-fuse located in the wafer active region;

[0090] S3: Form metal pillars, pads, and a dielectric layer on the substrate, where the metal pillars are located on the reference metal connectors and the detection metal connectors, and one end of each metal pillar is connected to the corresponding reference metal connector and detection metal connector; the pads are located on the metal pillars, and the pads are connected to the other ends of the metal pillars; the dielectric layer is located on the substrate to cover the substrate, the reference metal layer, the detection metal layer, and the metal pillars;

[0091] S4: Form a mask layer on the dielectric layer and pattern the mask layer;

[0092] S5: Etch the dielectric layer to form a dielectric layer detection window exposing the pads and a dielectric layer inspection window exposing the detection metal resistors.

[0093] Wherein, active or passive devices can be provided on the substrate as needed, which is not overly restricted here, and the dielectric layer can include a silicon oxide layer, but is not limited thereto.

[0094] Regarding the materials, dimensions, and specific preparation processes of the reference metal layer, the detection metal layer, the metal pillars, the pads, and the dielectric layer, selection can be made with reference to existing conventional applications, which is not overly restricted here.

[0095] Example Three

[0096] As Figure 7 , this example provides a detection method for e-fuse etching, specifically including the following steps:

[0097] Sa: Provide the detection structure in Example One;

[0098] Sb: Combine with the dielectric layer detection window to obtain the reference resistance value of the reference metal resistor and the detection resistance value of the detection metal resistor through the pads;

[0099] Sc: Compare the obtained reference resistance value with the detection resistance value to detect the etching of the e-fuse.

[0100] As an example, the method of changing the detection resistance value includes changing one or a combination of the morphologies of the detection metal resistor and the dielectric layer inspection window. For details, refer to Example One, which will not be elaborated here.

[0101] As an example, it may further include the step of comparing the detection resistance values of the detection metal resistors in different wafer dicing areas to reflect the differences in the wafer manufacturing process in different areas.

[0102] As described above, the detection structure, preparation and detection method for e-fuse etching according to the present invention form a reference metal layer and a detection metal layer in the wafer dicing area that are synchronously formed with the e-fuse located in the active area of the wafer. Among them, the reference metal layer includes two reference metal connectors arranged at intervals and a reference metal resistor connected corresponding to the reference metal connectors. The detection metal layer includes two detection metal connectors arranged at intervals and a detection metal resistor connected corresponding to the detection metal connectors. And metal columns and pads for electrical testing are correspondingly provided above the reference metal connectors and the detection metal connectors and are connected to each other. Therefore, during the etching process, since there is a dielectric layer detection window above the detection metal resistor, the detection metal resistor is etched, causing a change in the resistance value of the detection metal resistor. Therefore, by monitoring the electrical performance data, that is, the change in the resistance value, of the detection metal resistor and the reference metal resistor, the situation of e-fuse etching can be reflected, eliminating the need for slice confirmation.

[0103] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A detection structure for e-fuse etching, characterized in that, the detection structure includes: a substrate, the substrate includes a wafer active region and a wafer dicing region; a reference metal layer, the reference metal layer is located on the wafer dicing region of the substrate, the reference metal layer includes 2 spaced reference metal connectors and reference metal resistors correspondingly connected to the reference metal connectors, and the reference metal resistors are formed synchronously with the e-fuse located in the wafer active region; a detection metal layer, the detection metal layer is located on the wafer dicing region of the substrate, the detection metal layer has the same morphology as the reference metal layer, the detection metal layer includes 2 spaced detection metal connectors and detection metal resistors correspondingly connected to the detection metal connectors, and the detection metal resistors are formed synchronously with the e-fuse located in the wafer active region; metal pillars, the metal pillars are located on the reference metal connectors and the detection metal connectors, and one end of the metal pillars is connected to the corresponding reference metal connectors and detection metal connectors; bond pads, the bond pads are located on the metal pillars, and the bond pads are connected to the other ends of the metal pillars; a dielectric layer, the dielectric layer is located on the substrate to cover the substrate, the reference metal layer, the detection metal layer and the metal pillars, and there is a dielectric layer detection window exposing the bond pads and a dielectric layer detection window exposing the detection metal resistors in the dielectric layer.

2. The detection structure for e-fuse etching according to claim 1, characterized in that: the reference metal layer and the detection metal layer are both located in the wafer edge dicing region, both located in the wafer center dicing region, or distributed across the entire wafer dicing region.

3. The detection structure for e-fuse etching according to claim 1, characterized in that: the reference metal layer and the detection metal layer are located in the wafer dicing regions of adjacent chips.

4. The detection structure for e-fuse etching according to claim 1, characterized in that: the morphology of the detection metal resistor is linear or curved.

5. The detection structure for e-fuse etching according to claim 1, characterized in that: the dielectric layer detection window completely exposes the detection metal resistor or exposes a part of the detection metal resistor.

6. A preparation method for a detection structure for e-fuse etching, characterized in that, includes the following steps: providing a substrate, the substrate includes a wafer active region and a wafer dicing region; forming a reference metal layer and a detection metal layer with the same morphology on the wafer dicing region of the substrate, wherein, the reference metal layer includes 2 spaced reference metal connectors and reference metal resistors correspondingly connected to the reference metal connectors, the detection metal layer includes 2 spaced detection metal connectors and detection metal resistors correspondingly connected to the detection metal connectors, and the reference metal layer and the detection metal layer are formed synchronously with the e-fuse located in the wafer active region; Form metal pillars, pads, and a dielectric layer on the substrate, wherein the metal pillars are located on the reference metal connectors and the detection metal connectors, and one end of each metal pillar is connected to the corresponding reference metal connector and detection metal connector; the pads are located on the metal pillars, and the pads are connected to the other ends of the metal pillars; the dielectric layer is located on the substrate to cover the substrate, the reference metal layer, the detection metal layer, and the metal pillars; Form a mask layer on the dielectric layer and pattern the mask layer; Etch the dielectric layer to form a dielectric layer detection window exposing the pads and a dielectric layer detection window exposing the detection metal resistors.

7. The preparation method for the e-fuse etching detection structure according to claim 6, characterized in that: The dielectric layer includes a silicon oxide layer.

8. A detection method for e-fuse etching, characterized in that, comprising the following steps: Provide the detection structure according to any one of claims 1 to 5; Combined with the dielectric layer detection window, obtain the reference resistance value of the reference metal resistor and the detection resistance value of the detection metal resistor through the pads; Compare the obtained reference resistance value with the detection resistance value to detect the etching of the e-fuse.

9. The detection method for e-fuse etching according to claim 8, characterized in that: The method of changing the detection resistance value includes changing one or a combination of the morphology of the detection metal resistor and the dielectric layer detection window.

10. The detection method for e-fuse etching according to claim 8, characterized in that: It further includes the step of comparing the detection resistance values of the detection metal resistors located in different wafer dicing areas to reflect the differences in the wafer manufacturing process in different areas.

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