Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present invention provide a semiconductor device capable of improving leakage current characteristics and a manufacturing method thereof. According to one embodiment of the present invention, a capacitor includes a lower electrode, a dielectric layer over the lower electrode, and an upper electrode over the dielectric layer, the upper electrode including a carbon-containing conductive layer, wherein a carbon content in the carbon-containing conductive layer is greater than 5 at% and equal to or less than 10 at%.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0057713, filed on May 4, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device comprising an electrode having a conductive carbon-containing layer and a method for manufacturing the same. Background Technology

[0004] Due to advancements in electronic technology, semiconductor devices have undergone rapid miniaturization in recent years, resulting in more intricate patterns that constitute these devices. Consequently, even when forming a relatively thin dielectric layer in a capacitor with fine dimensions, it is necessary to develop a structure that can reduce leakage current in the capacitor while maintaining the desired electrical characteristics. Summary of the Invention

[0005] Various embodiments of the present invention provide a semiconductor device and a method for manufacturing the same that can improve the leakage current characteristics of a capacitor.

[0006] According to one embodiment of the present invention, a capacitor includes: a lower electrode; a dielectric layer above the lower electrode; and an upper electrode above the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein the carbon content in the conductive carbon-containing layer is greater than 5 at% and equal to or less than 10 at%.

[0007] According to one embodiment of the present invention, a method for manufacturing a capacitor includes: forming a molded structure on a substrate; forming an opening by etching the molded structure; forming a lower electrode disposed in the opening; exposing the outer wall of the lower electrode by removing the molded structure; forming a dielectric layer over the lower electrode; and forming an upper electrode over the dielectric layer, the upper electrode comprising a conductive carbon-containing layer, wherein the carbon content in the conductive carbon-containing layer is greater than 5 at% and equal to or less than 10 at%.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a dielectric layer on a substrate; and a metal electrode on the dielectric layer, the metal electrode including a conductive carbon-containing layer, wherein the carbon content in the conductive carbon-containing layer is greater than 5 at% and equal to or less than 10 at%.

[0009] This invention improves the reliability of semiconductor devices by improving the leakage current characteristics of the capacitors in semiconductor devices.

[0010] Because the present invention can omit the interface layer that is usually located between the dielectric layer and the top electrode of a semiconductor device, the present invention is effective in simplifying the manufacturing process of semiconductor devices.

[0011] This invention can maximize the polarization efficiency of semiconductor devices by applying electrodes with low crystallinity on the dielectric layer, thereby reducing the stress on the dielectric layer. Attached Figure Description

[0012] Figure 1 This is a view showing a capacitor according to an embodiment of the present invention.

[0013] Figure 2 It shows the formation Figure 1 The flowchart shows the method for the upper electrode 103.

[0014] Figure 3A and Figure 3B This is a view illustrating a semiconductor device according to an embodiment of the present invention.

[0015] Figures 4A to 4I This is a view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0016] The various embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams, which serve as schematic diagrams of the invention. Therefore, the structure of the drawings can be modified by manufacturing techniques and / or tolerances. Embodiments of the invention are not limited to the specific structures shown in the drawings, but include any variations in structure that may result from manufacturing processes. Furthermore, the shapes of any regions shown in the schematic drawings are intended to illustrate specific examples of the structure of various elements and are not intended to limit the scope of the invention.

[0017] Figure 1 This is a view showing a capacitor according to an embodiment of the present invention.

[0018] like Figure 1 As shown, capacitor 100 may include a lower electrode 101, a dielectric layer 102, and an upper electrode 103, which are stacked on top of each other in the listed order in a first direction (also referred to below as the stacking direction).

[0019] The lower electrode 101 may be made of a conductive material. For example, the lower electrode 101 may be made of a metal-based conductive material, hereinafter simply referred to as a metal-based material. A metal-based material may also be referred to as a metal-containing material. For example, a metal-based material may be a metal, a metal nitride, a conductive metal oxide, or a combination thereof. The metal-based material of the lower electrode 101 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), or a combination thereof. In another embodiment, the lower electrode 101 may include a silicon-based material. A silicon-based material may also be referred to as a silicon-containing material and may include a silicon substrate, a silicon layer, a silicon-germanium layer, or a combination thereof. In one embodiment, the lower electrode 101 may include a stack of metal-containing and silicon-containing materials.

[0020] The dielectric layer 102 may include a single-layer structure, a multilayer structure, and a laminated structure. The dielectric layer 102 may have a doped structure or a hybrid structure. The dielectric layer 102 may include a high-k material. The dielectric layer 102 may have a higher dielectric constant than silicon oxide (SiO2). Silicon oxide may have a dielectric constant of approximately 3.9, and the dielectric layer 102 may include materials with a dielectric constant of 4 or greater. High-k materials may have a dielectric constant of approximately 20 or greater. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer 102 may be formed of a composite layer comprising two or more layers formed from the aforementioned high-k materials. The dielectric layer 102 may be formed of a zirconium (Zr)-based oxide. The dielectric layer 102 may have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) may include ZA (ZrO2 / Al2O3) or ZAZ (ZrO2 / Al2O3 / ZrO2). The ZA structure may have a structure in which alumina is stacked on top of zirconium oxide. The ZAZ structure may have a structure in which zirconium oxide, alumina, and zirconium oxide are stacked sequentially. ZrO2, ZA, and ZAZ structures are generally referred to as zirconium oxide (ZrO2)-based layers. In another embodiment, the dielectric layer 102 may be formed from a hafnium (Hf)-based oxide. The dielectric layer 102 may have a stacked structure including hafnium oxide (HfO2). The stacked structure including hafnium oxide (HfO2) may include HA (HfO2 / Al2O3) or HAH (HfO2 / Al2O3 / HfO2). The HA structure may have a structure in which alumina is stacked on top of hafnium oxide. The HAH structure can have a structure in which hafnium oxide, aluminum oxide, and hafnium oxide are stacked sequentially. The HfO2, HA, and HAH structures can be referred to as hafnium oxide (HfO2) based layers.

[0021] In the ZA, ZAZ, HA, and HAH structures, alumina (Al2O3) can have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Alumina (Al2O3) can also have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer 102 can include a stack of high-k materials and high-bandgap materials with band gaps larger than those of the high-k materials. The dielectric layer 102 can include silicon oxide (SiO2) other than alumina as a high-bandgap material. Because the dielectric layer 102 includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be very thin. The high-bandgap material can be thinner than the high-k material.

[0022] In another embodiment, the dielectric layer 102 may include a laminated structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the laminated structure may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In the above laminated structures, the alumina (Al2O3) can be very thin.

[0023] The upper electrode 103 may include a conductive carbon-containing layer. The carbon content in the conductive carbon-containing layer may be greater than 5 at% and equal to or less than 10 at%. This is because if the carbon content in the membrane exceeds 10 at%, the membrane quality may be affected by carbon fume.

[0024] The upper electrode 103 may include a carbon-doped and oxygen-doped metal nitride. The upper electrode 103 may include a carbon-doped and oxygen-doped titanium nitride. For example, the upper electrode 103 may include titanium carbonitride (TiCON).

[0025] Compared to titanium nitride (TiN) that does not contain carbon and oxygen, the upper electrode 103 can exhibit high work function characteristics and low crystallinity. The work function of carbon (4.8 eV) is higher than that of titanium nitride (TiN) without carbon and oxygen (4.5 eV). In this embodiment, by forming a conductive carbon-containing layer, for example, carbon-doped and oxygen-doped titanium nitride, the upper electrode 103 can have higher work function characteristics than carbon-free titanium nitride (TiN). In the upper electrode 103, carbon can exist in the film in the form of the formula CH.

[0026] In another embodiment, the upper electrode 103 may have a varying carbon content. For example, the upper electrode 103 may have a carbon content that varies with its distance from the dielectric layer 102. More generally, the upper electrode 103 may have a carbon content that varies with its distance from the outermost surface of the upper electrode 103. For example, the upper electrode 103 may have a low carbon content in the portion adjacent to the dielectric layer 102, and the carbon content may increase with increasing distance from the dielectric layer 102. In another example, the upper electrode 103 may have a high carbon content in the portion adjacent to the dielectric layer 102, and the carbon content may decrease with increasing distance from the dielectric layer 102.

[0027] In another embodiment, the upper electrode 103 may have an oxygen content in the film that varies with distance from the dielectric layer 102. In yet another embodiment, the upper electrode 103 may have a carbon content and an oxygen content in the film that vary with distance from the dielectric layer 102.

[0028] The upper electrode 103 can be formed by atomic layer deposition (ALD). ALD can be performed under conditions that mitigate the reducing properties of the dielectric layer 102. ALD can be performed at low temperatures of 150°C to 350°C in an atmosphere free of chlorine (Cl) and ammonia (NH3) that would cause reduction of the dielectric layer 102.

[0029] As described above, due to the high work function characteristics of the upper electrode 103, the leakage current characteristics of the capacitor can be improved by generating a Schottky barrier at the interface with the dielectric layer 102 through the work function deviation.

[0030] Furthermore, since the formation of the upper electrode 103 is carried out under conditions that reduce the reducibility of the dielectric layer 102, the interface layer that has been typically used to suppress the reduction of the dielectric layer 102 can be omitted, thereby simplifying the process.

[0031] Furthermore, the upper electrode 103 can maximize polarization efficiency by reducing the stress on the dielectric layer due to its low crystallinity.

[0032] Figure 2 It shows the formation Figure 1 A flowchart of the method for using the upper electrode 103. Figure 2 The dielectric layer and upper electrode mentioned in the flowchart refer to Figure 1 The dielectric layer 102 and the upper electrode 103.

[0033] exist Figure 2 In operation P101, a metal precursor layer is formed by supplying a metal precursor, including a metal, onto the dielectric layer in the reaction space. For example, the metal may include titanium, but is not limited to this. The metal precursor in this embodiment may not contain chlorine (Cl) and ammonia (NH3). The metal precursor may include, for example, TDMAT (tetra(dimethylamino)titanium), but is not limited to this. The time period for supplying the metal precursor may include, for example, a period of 1 second to 10 seconds.

[0034] exist Figure 2 In operation P102, unwanted byproducts on the dielectric layer 102 can be removed by supplying purge gas onto the dielectric layer. The duration of supplying the purge gas can include, for example, a period of 1 to 10 seconds.

[0035] exist Figure 2In operation P103, a first reactive gas can be supplied to the dielectric layer to form a carbon-doped metal nitride. The reactive gas may include nitrogen (N2) remote plasma. The time period for supplying the reactive gas can be adjusted according to the desired amount of carbon in the film, and for example, this time period may be within 30 seconds. In one embodiment, the carbon content in the carbon-doped metal nitride film can be adjusted to be greater than 5 at% and equal to or less than 10 at%.

[0036] exist Figure 2 In operation P104, unwanted byproducts can be removed by supplying purge gas to the dielectric layer. The time for supplying the purge gas can include, for example, a period of 1 to 10 seconds.

[0037] exist Figure 2 In operation P105, carbon-doped and oxygen-doped metal nitrides can be formed by supplying a second reactant gas onto the dielectric layer. The second reactant gas may include O2 or O3. The time period for supplying the reactant gas can be adjusted to within 5 seconds.

[0038] exist Figure 2 In operation P106, purge gas can be supplied to dielectric layer 102 (see...) Figure 1 This is to remove unwanted byproducts. The time for supplying purge gas can include, for example, a period of 1 to 10 seconds.

[0039] like Figure 2 As shown in operation P107, the unit cycle of operations P101 to P106 can be repeated multiple times until a metal nitride with doped carbon and oxygen of the desired thickness is formed.

[0040] The thickness of the upper electrode can be controlled by adjusting the number of cycles in the atomic layer deposition process to suit different applications. Figure 2 The atomic layer deposition process illustrated forms the upper electrode. Specifically, according to one embodiment of the invention, when forming the upper electrode using atomic layer deposition, the carbon and oxygen content in the film, as well as the deposition temperature, can be controlled. The atomic layer deposition process can be performed at a low temperature equal to or less than 350°C to reduce the crystallinity of the metal nitride and the reducing properties of the dielectric layer. For example, the deposition temperature in the atomic layer deposition process can be adjusted between 150°C and 350°C.

[0041] In another embodiment, the carbon-doped and oxygen-doped metal nitrides described above can be applied to a metal gate electrode of a gate pattern that has been covered with a high-dielectric insulating layer.

[0042] In another embodiment, the carbon-doped and oxygen-doped metal nitrides of the above embodiments can be applied to flash memory that has an ONO (oxide-nitride-oxide) tunneling insulating layer (i.e., control gate).

[0043] In another embodiment, carbon-doped and oxygen-doped metal nitrides from the above embodiments can be used instead of titanium nitride (TiN) as a barrier layer (e.g., a barrier layer for metal wires) in all processes.

[0044] The carbon-doped and oxygen-doped metal nitrides described in this embodiment can be applied to electrode processes that require low reducibility, low deposition temperature, and low stress.

[0045] Figure 3A and Figure 3B This is a view showing a semiconductor device according to an embodiment. Figure 3A The lower electrode 310 can be columnar, and Figure 3B The lower electrode 310 may be cylindrical.

[0046] refer to Figure 3A and Figure 3B The semiconductor device 200 may include a lower structure 201. The lower structure 201 may be a stacked structure including a substrate 202 and an insulating layer 203 formed on the substrate 202. The lower structure 201 may include a plurality of storage node contact structures. The storage node contact structures may penetrate the insulating layer 203 and connect to the substrate 202. The storage node contact structures may be a stack of a lower plug 204 and an upper plug 205. The lower plug 204 may include a silicon plug, and the upper plug 205 may include a metal plug. Buried word lines and bit lines may be further formed in the lower structure 201. The buried word lines may be formed in the substrate 202, and the bit lines may be formed between the storage node contact structures.

[0047] The semiconductor device 200 may also include a capacitor structure 300. The capacitor structure 300 may be referred to as the upper structure. The capacitor structure 300 may be formed on the lower structure 201. The capacitor structure 300 may include a lower electrode 310, a dielectric layer 320, and an upper electrode 330.

[0048] Figure 3AThe lower electrode 310 may be columnar. The lower electrode 310 may include a cylindrical electrode 301 and a columnar electrode 302. The columnar electrode 302 may be formed inside the cylindrical electrode 301. The cylindrical electrode 301 and the columnar electrode 302 may be made of the same material or different materials. Both the cylindrical electrode 301 and the columnar electrode 302 may be made of a metal-based material. A metal-based material can refer to a material containing metals. In another embodiment, the cylindrical electrode 301 may be a metal-based material, and the columnar electrode 302 may be a silicon-based material. A silicon-based material can refer to a silicon-containing material. For example, both the cylindrical electrode 301 and the columnar electrode 302 may be titanium nitride (TiN). The cylindrical electrode 301 may be titanium nitride (TiN), and the columnar electrode 302 may be doped polycrystalline silicon. Doped polycrystalline silicon can refer to polycrystalline silicon doped with conductive impurities. Figure 3B The lower electrode 310 may be cylindrical.

[0049] The outer walls of the plurality of lower electrodes 310 may be supported by a first support member 311 and a second support member 312. The first support member 311 and the second support member 312 may be referred to as multi-level supports. In another embodiment, the multi-level supports may have at least three or more levels. The first support member 311 and the second support member 312 may include silicon nitride (Si3N4) and silicon carbonitride (SiCN).

[0050] The dielectric layer 320 may include a single-layer structure, a multilayer structure, and a laminated structure. The dielectric layer 320 may have a doped structure or a hybrid structure. The dielectric layer 320 may include a high-k material. The dielectric layer 320 may have a higher dielectric constant than silicon oxide (SiO2). Silicon oxide may have a dielectric constant of approximately 3.9, and the dielectric layer 320 may include a material with a dielectric constant of 4 or greater. The high-k material may have a dielectric constant of approximately 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer 320 may be formed of a composite layer comprising two or more layers of the aforementioned high-k material. The dielectric layer 320 may be formed of a zirconium (Zr)-based oxide. The dielectric layer 320 may have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) may include ZA (ZrO2 / Al2O3) or ZAZ (ZrO2 / Al2O3 / ZrO2). ZA may have a structure in which alumina is stacked on zirconium oxide. ZAZ may have a structure in which zirconium oxide, alumina, and zirconium oxide are stacked sequentially in the listed order. ZrO2, ZA, and ZAZ may be referred to as zirconium oxide (ZrO2)-based layers. In another embodiment, the dielectric layer 320 may be formed of a hafnium (Hf)-based oxide. The dielectric layer 320 may have a stacked structure including hafnium oxide (HfO2). The stacked structure including hafnium oxide (HfO2) may include HA (HfO2 / Al2O3) or HAH (HfO2 / Al2O3 / HfO2). HA may have a structure in which alumina is stacked on hafnium oxide. HAH can have a structure in which hafnium oxide, aluminum oxide, and hafnium oxide are stacked sequentially in the listed order. HfO2, HA, and HAH can be referred to as hafnium oxide (HfO2) based layers.

[0051] In ZA, ZAZ, HA, and HAH structures, alumina (Al2O3) can have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Alumina (Al2O3) can also have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, dielectric layer 320 can include a stack of high-k materials and high-bandgap materials with band gaps larger than those of high-k materials. Dielectric layer 320 can include silicon oxide (SiO2) other than alumina as a high-bandgap material. Because dielectric layer 320 includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be very thin. The high-bandgap material can be thinner than the high-k material.

[0052] In another embodiment, the dielectric layer 320 may include a laminated structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the laminated structure may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In the above laminated structures, the alumina (Al2O3) can be very thin.

[0053] The upper electrode 330 may be single-layered or multi-layered. The upper electrode 330 may include a conductive carbon-containing layer. According to one embodiment of the invention, the upper electrode 330 may include a stacked structure of a first upper electrode 331 and a second upper electrode 332. The first upper electrode 331 may be conformally formed on the dielectric layer 320. The second upper electrode 332 may be formed to fill the space between the capacitor structures 300.

[0054] To mitigate the reduction characteristics of the dielectric layer 320, the first upper electrode 331 may comprise a material with low crystallinity and a higher work function than titanium nitride (TiN). The first upper electrode 331 can be... Figure 2 The atomic layer deposition process shown in the flowchart is used to form the layer. That is, the atomic layer deposition process can be carried out at a low temperature of 150°C to 350°C in an atmosphere that does not contain chlorine (Cl) and NH3, which would cause the dielectric layer 320 to be reduced.

[0055] The first upper electrode 331 may include a conductive carbon-containing layer. The carbon content in the conductive carbon-containing layer may be greater than 5 at% and equal to or less than 10 at%. This is because if the carbon content in the membrane exceeds 10 at%, the membrane quality may be affected by carbon soot.

[0056] The first upper electrode 331 may include a carbon-doped and oxygen-doped metal nitride. The first upper electrode 331 may include carbon-doped and oxygen-doped titanium nitride. The first upper electrode 331 may include TiCON.

[0057] Compared to titanium nitride that does not contain carbon and oxygen, the first upper electrode 331 can exhibit high work function characteristics and low crystallinity. The work function of carbon (4.8 eV) is higher than that of titanium nitride (TiN) that does not contain carbon and oxygen (4.5 eV). According to one embodiment of the invention, by forming a conductive carbon-containing layer, such as carbon-doped and oxygen-doped titanium nitride, the first upper electrode 331 can have higher work function characteristics than carbon-free titanium nitride. In the first upper electrode 331, carbon can exist in the film in the form of CH.

[0058] In another embodiment, the first upper electrode 331 may have a varying carbon content. For example, the first upper electrode 331 may have a carbon content that varies with its distance from the dielectric layer 320. More generally, the first upper electrode 331 may have a carbon content that varies with its distance from the outermost surface of the first upper electrode 331. For example, the first upper electrode 331 may have a low carbon content in the portion adjacent to the dielectric layer 320, and the carbon content may increase with increasing distance from the dielectric layer 320. In another example, the first upper electrode 331 may have a high carbon content in the portion adjacent to the dielectric layer 320, and the carbon content may decrease with increasing distance from the dielectric layer 320.

[0059] The first upper electrode 331 may have an oxygen content that varies with its distance from the dielectric layer 320. More generally, the first upper electrode 331 may have an oxygen content that varies with its distance from the outermost surface of the first upper electrode 331. In another embodiment, the first upper electrode 331 may have a carbon and oxygen content in the film that varies with its thickness. For example, the first upper electrode 331 may have a carbon and oxygen content that varies with its distance from the dielectric layer 320.

[0060] The second upper electrode 332 may include a silicon-containing material, a germanium-containing material, a metal-containing material, or a combination thereof. The second upper electrode 332 may include a metal, a metal nitride, a metal carbide, a conductive metal oxide, or a combination thereof. The second upper electrode 332 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbon nitride (TiCN), tantalum carbon nitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), or a combination thereof. The second upper electrode 332 may include a silicon layer (Si layer), a germanium layer (Ge layer), a silicon-germanium layer (SiGe layer), or a combination thereof. The second upper electrode 332 can be formed by stacking a silicon-germanium layer (Si / SiGe) on a silicon layer. The second upper electrode 332 can be formed by stacking a silicon-germanium layer (Ge / SiGe) on a germanium layer. The second upper electrode 332 may include a stack of silicon-containing materials and metal-containing materials. The second upper electrode 332 can be formed by stacking a silicon-germanium layer and a tungsten nitride layer (SiGe / WN).

[0061] According to one embodiment, the second upper electrode 332 may include a gap-filling material and a low-resistance material. The gap-filling material may include silicon germanium (SiGe), and the low-resistance material may include tungsten (W). The gap-filling material can fill the narrow gap between the lower electrodes 310 without leaving voids. The low-resistance material can reduce the resistance of the upper electrode 330.

[0062] Figures 4A to 4IThis is a view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0063] like Figure 4A As shown, a lower structure 11L can be formed. The lower structure 11L may include a semiconductor substrate, a semiconductor device, and an interlayer insulating layer. The lower structure 11L may include a region in which memory cells are disposed. The lower structure 11L may correspond to... Figure 3A and Figure 3B The lower structure 201. The lower structure 11L may include a substrate 11 and storage node contact plugs formed on the substrate 11. The storage node contact plugs may be a stack of a lower plug L1 and an upper plug L2. The storage node contact plugs may be connected to the substrate 11 through an interlayer insulating layer L3.

[0064] A molded structure M10 may be formed on the lower structure 11L. The molded structure M10 may include a first molding layer 12, a first support layer 13', a second molding layer 14, and a second support layer 15' sequentially stacked on the lower structure 11L. The first molding layer 12 and the second molding layer 14 may be, for example, silicon oxide (SiO2). The first molding layer 12 and the second molding layer 14 may be formed using a vapor deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0065] The first support layer 13' and the second support layer 15' may be formed of a material that is etch-selective relative to the first molding layer 12 and the second molding layer 14. The first support layer 13' and the second support layer 15' may include silicon nitride or silicon carbonitride (SiCN). The second support layer 15' may be thicker than the first support layer 13'. The first support layer 13' and the second support layer 15' may be thinner than the first molding layer 12 and the second molding layer 14.

[0066] like Figure 4B As shown, multiple openings 16 can be formed. The openings 16 can be formed by etching the molding structure M10 using a mask layer (not shown). To form the openings 16, the mask layer can be used as an etching barrier layer to sequentially etch the first support layer 15', the second molding layer 14, the first support layer 13', and the first molding layer 12. Dry etching, wet etching, or a combination thereof can be used to form the openings 16. The opening 16 can be referred to as a hole in which the lower electrode (or storage node) is to be formed. The opening 16 can have a high aspect ratio. The opening 16 can have an aspect ratio of at least 1:1. For example, the opening 16 can have a high aspect ratio of 1:10 or greater. Aspect ratio as used herein refers to the ratio of width to height.

[0067] The molded structure M10, which includes multiple openings 16, can be formed by a series of etching processes as described above.

[0068] like Figure 4C As shown, a first conductive material 17' can be formed in the opening 16. The first conductive material 17' can be conformally formed on the molded structure M10 in which the opening 16 is formed. A second conductive material 18' can be formed on the first conductive material 17'. The second conductive material 18' can fill the opening 16.

[0069] The first conductive material 17' and the second conductive material 18' may comprise polycrystalline silicon, metal, metal nitride, conductive metal nitride, metal silicide, noble metal, or combinations thereof. The first conductive material 17' and the second conductive material 18' may comprise at least one selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W) or tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and combinations thereof. In one embodiment, both the first conductive material 17' and the second conductive material 18' may comprise titanium nitride (TiN). The first conductive material 17' and the second conductive material 18' may comprise titanium nitride (ALD-TiN) formed by atomic layer deposition (ALD).

[0070] In another embodiment, the first conductive material 17' and the second conductive material 18' may respectively comprise titanium nitride and tungsten. In another embodiment, the first conductive material 17' and the second conductive material 18' may respectively comprise titanium nitride and polycrystalline silicon.

[0071] In another embodiment, the first conductive material 17' and the second conductive material 18' can be the same material and formed as a single layer. That is, the opening 16 can be filled with either the first conductive material 17' or the second conductive material 18'.

[0072] like Figure 4D As shown, a lower electrode BE can be formed. A lower electrode separation process can be performed to form the lower electrode BE. The lower electrode separation process may include an etch-back process and / or a CMP process. The first conductive material 17' and the second conductive material 18' disposed on the second support layer 15' can be removed by the lower electrode separation process.

[0073] The lower electrode BE may include a cylindrical electrode 17 and a cylindrical electrode 18. The cylindrical electrode 17 may be formed by etching a first conductive material 17′, and the cylindrical electrode 18 may be formed by etching a second conductive material 18′.

[0074] like Figure 4EAs shown, a second support member 15 can be formed. To form the second support member 15, a portion of the second support member layer 15' can be etched using a support member mask layer SM. The support member opening S1 and the second support member 15 can be formed by etching the second support member layer 15'.

[0075] The second support 15 can contact the upper sidewall of the lower electrode BE. The upper surface of the second molding layer 14 can be exposed by the second support 15. The second support 15 can have a shape that surrounds a portion of the outer wall of the lower electrode BE. In this way, the second support 15 can prevent the lower electrode BE, which has a large aspect ratio, from collapsing in subsequent processes such as removing the second molding layer 14.

[0076] like Figure 4F As shown, the second molding layer 14 can be removed. For example, the second molding layer 14 can be removed by a wet leaching process. The wet chemicals used to remove the second molding layer 14 can be supplied through the support opening S1. As wet chemicals, one or more chemicals such as HF, NH4F / NH4OH, H2O2, HCl, HNO3, and H2SO4 can be used.

[0077] For example, when the second molding layer 14 is formed of silicon oxide, the second molding layer 14 can be removed by a wet leaching process using chemicals containing hydrofluoric acid. When the second molding layer 14 is removed, the second support 15, which has etching selectivity for the second molding layer 14, can be retained without being removed. Therefore, since the adjacent lower electrode BE is supported by the second support 15, the lower electrode BE can be prevented from collapsing.

[0078] like Figure 4G As shown, a first support member 13 can be formed. A portion of the first support member layer 13' can be etched using a support member mask layer SM. The first support member 13 can be formed by etching the first support member layer 13'.

[0079] After the first support 13 is formed, the first molding layer 12 can be removed. For example, the first molding layer 12 can be removed by a wet leaching process. The wet chemical used to remove the first molding layer 12 can be supplied through the support opening S1. As the wet chemical, one or more chemicals selected from, for example, HF, NH4F / NH4OH, H2O2, HCl, HNO3, and H2SO4 can be used.

[0080] For example, when the first molding layer 12 is formed of silicon oxide, the first molding layer 12 can be removed by a wet leaching process. When the first molding layer 12 is removed, the lower electrode BE is prevented from collapsing because it is supported by the second support 15 and the first support 13, which have etching selectivity relative to the first molding layer 12.

[0081] With the removal of the second molding layer 14 and the first molding layer 12, the outer wall of the lower electrode BE, except for the portion in contact with the first support member 13 and the second support member 15, can be exposed. The upper part of the lower electrode BE can be supported by the second support member 15. The middle part of the lower electrode BE can be supported by the first support member 13.

[0082] Subsequently, the support mask layer SM can be removed.

[0083] like Figure 4H As shown, a dielectric layer 19 can be formed. The dielectric layer 19 can be formed on the lower electrode BE and the first support 13 and the second support 15. A portion of the dielectric layer 19 can cover the lower structure 11L. The dielectric layer 19 can include a high-k material having a dielectric constant higher than silicon oxide. High-k materials can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer 19 can be formed from a composite layer comprising two or more layers of the aforementioned high-k material. The dielectric layer 19 can be formed from a zirconium (Zr)-based oxide. The dielectric layer 19 can have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) can include ZA (ZrO2 / Al2O3) or ZAZ (ZrO2 / Al2O3 / ZrO2). ZA can have a structure in which alumina is stacked on zirconium oxide. ZAZ can have a structure in which zirconium oxide, alumina, and zirconium oxide are sequentially stacked. ZrO2, ZA, and ZAZ can be referred to as zirconium oxide (ZrO2)-based layers. In another embodiment, dielectric layer 19 can be formed of a hafnium (Hf)-based oxide. Dielectric layer 19 can have a stacked structure including hafnium oxide (HfO2). The stacked structure including hafnium oxide (HfO2) can include HA (HfO2 / Al2O3) or HAH (HfO2 / Al2O3 / HfO2). HA can have a structure in which alumina is stacked on hafnium oxide. HAH can have a structure in which hafnium oxide, alumina, and hafnium oxide are sequentially stacked. HfO2, HA, and HAH can be referred to as hafnium oxide (HfO2) based layers.

[0084] In the ZA, ZAZ, HA, and HAH structures, alumina (Al2O3) can have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Alumina (Al2O3) has a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, dielectric layer 102 can include a stack of high-k materials and high-bandgap materials with larger band gaps than high-k materials. Dielectric layer 19 can include silicon oxide (SiO2) other than alumina as a high-bandgap material. Because dielectric layer 19 contains a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be very thin. The high-bandgap material can be thinner than the high-k material.

[0085] In another embodiment, the dielectric layer 19 may include a laminated structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the laminated structure may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In the above laminated structures, the alumina (Al2O3) can be very thin.

[0086] like Figure 4I As shown, the upper electrode SE can be formed on the dielectric layer 19. The upper electrode SE can include a stacked structure of a first upper electrode 20 and a second upper electrode 21. The first upper electrode 20 can be conformally formed on the dielectric layer 19. The second upper electrode 21 can fill the space between adjacent lower electrodes BE.

[0087] To mitigate the reduction properties of the dielectric layer 19, the first upper electrode 20 may comprise a material with lower crystallinity and higher work function properties than titanium nitride (TiN). The first upper electrode 20 may be made of... Figure 2 The atomic layer deposition process shown in the flowchart is formed. That is, the atomic layer deposition process can be performed at low temperatures of 150°C to 350°C in an atmosphere that does not contain chlorine (Cl) and NH3, which would cause reduction of the dielectric layer 19.

[0088] The first upper electrode 20 may include a conductive carbon-containing layer. The carbon content in the conductive carbon-containing layer may be greater than 5 at% and equal to or less than 10 at%. This is because if the carbon content in the membrane exceeds 10 at%, the membrane quality may be affected by carbon soot.

[0089] The first upper electrode 20 may include a carbon-doped and oxygen-doped metal nitride. The first upper electrode 20 may include carbon-doped and oxygen-doped titanium nitride. The first upper electrode 20 may include TiCON.

[0090] Compared to titanium nitride that does not contain carbon and oxygen, the first upper electrode 20 can exhibit high work function characteristics and low crystallinity. The work function of carbon (4.8 eV) is higher than that of titanium nitride (TiN) that does not contain carbon and oxygen (4.5 eV). In one embodiment, by forming a conductive carbon-containing layer, such as carbon-doped and oxygen-doped titanium nitride, the first upper electrode 20 can have higher work function characteristics than carbon-free titanium nitride. In the first upper electrode 20, carbon can exist in the film in the form of CH.

[0091] In another embodiment, the first upper electrode 20 may have a carbon content in the film that varies with its distance from the dielectric layer 19. For example, the first upper electrode 20 may have a low carbon content in the portion adjacent to the dielectric layer 19, and the carbon content may increase with increasing distance from the dielectric layer 19. In another example, the first upper electrode 20 may have a high carbon content in the portion adjacent to the dielectric layer 19, and the carbon content may decrease with increasing distance from the dielectric layer 19.

[0092] In another embodiment, the first upper electrode 20 may have an oxygen content in the film that varies depending on its distance from the dielectric layer 19. In another embodiment, the first upper electrode 20 may have a carbon content and oxygen content in the film that vary depending on its thickness.

[0093] The first upper electrode 20 can be formed by atomic layer deposition (ALD). ALD can be performed under conditions that reduce the reducing properties of the dielectric layer 19. ALD can be performed at low temperatures of 150°C to 350°C in an atmosphere free of chlorine (Cl) and NH3, which would cause reduction of the dielectric layer 19. The first upper electrode 20 can be formed by… Figure 2 The atomic layer deposition process shown in the flowchart is formed.

[0094] The second upper electrode 21 may include a silicon-containing material, a germanium-containing material, a metal-containing material, or a combination thereof. The second upper electrode 21 may include a metal, a metal nitride, a metal carbide, a conductive metal oxide, or a combination thereof. The second upper electrode 21 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbon nitride (TiCN), tantalum carbon nitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), or a combination thereof. The second upper electrode 21 may include a silicon layer (Si layer), a germanium layer (Ge layer), a silicon-germanium layer (SiGe layer), or a combination thereof. The second upper electrode 21 can be formed by stacking a silicon-germanium layer (Si / SiGe) on a silicon layer. The second upper electrode 21 can be formed by stacking a silicon-germanium layer (Ge / SiGe) on a germanium layer. The second upper electrode 21 may include a stack of silicon-containing materials and metal-containing materials. The second upper electrode 21 can be formed by stacking a silicon-germanium layer and a tungsten nitride layer (SiGe / WN). The silicon-germanium layer can be doped with boron. For example, the metal-containing material can be a stack of tungsten nitride and tungsten (WN / W).

[0095] In one embodiment, the second upper electrode 21 may include a gap-filling material and a low-resistance material. The gap-filling material may include silicon germanium (SiGe), and the low-resistance material may include tungsten (W). The gap-filling material can fill the narrow gap between the lower electrodes BE without leaving voids. The low-resistance material can reduce the resistance of the upper electrode SE.

[0096] Various embodiments have been described above in response to the problem to be solved; however, it will be readily understood by those skilled in the art that various changes and modifications may be made thereto without departing from the scope of this disclosure.

Claims

1. A semiconductor device, comprising: Lower electrode; The dielectric layer above the lower electrode; as well as An upper electrode is located above the dielectric layer, the upper electrode comprising a conductive carbon-containing layer, wherein... The carbon content in the conductive carbon-containing layer is greater than 5 at% and equal to or less than 10 at%. The conductive carbon-containing layer is a titanium carbon nitride oxide with a lower crystallinity than titanium nitride (TiN).

2. The semiconductor device as claimed in claim 1, wherein, The conductive carbon-containing layer has a carbon content that varies depending on its distance from the dielectric layer.

3. The semiconductor device as claimed in claim 1, wherein, The upper electrode also includes a semiconductor material layer formed on the conductive carbon-containing layer.

4. The semiconductor device as claimed in claim 1, wherein, The upper electrode further includes a stacked structure of silicon-germanium layers and tungsten layers on the conductive carbon-containing layer.

5. The semiconductor device as claimed in claim 1, wherein, The lower electrode is cylindrical or tubular.

6. The semiconductor device of claim 1, further comprising: A support member that supports the outer wall of the lower electrode.

7. A method for manufacturing a semiconductor device, the method comprising: A molded structure is formed on the substrate; An opening is formed by etching the molded structure; A lower electrode is formed in the opening; The outer wall of the lower electrode is exposed by removing the molded structure. A dielectric layer is formed on the lower electrode; as well as An upper electrode is formed on the dielectric layer, the upper electrode comprising a conductive carbon-containing layer. The carbon content in the conductive carbon-containing layer is greater than 5 at% and equal to or less than 10 at%. The conductive carbon-containing layer is titanium carbon nitride. The step of forming the upper electrode is performed using an atomic layer deposition process. The atomic layer deposition process includes: Supplying nitrogen (N2) remote plasma as the first reactant gas; and Oxygen (O2) or ozone (O3) is supplied as the second reactant gas.

8. The method of claim 7, wherein, The conductive carbon-containing layer has a carbon content that varies depending on its distance from the dielectric layer.

9. The method of claim 7, wherein, The upper electrode also includes a semiconductor material layer formed on the conductive carbon-containing layer.

10. The method of claim 7, wherein, The upper electrode further includes a stacked structure of silicon-germanium layers and tungsten layers on the conductive carbon-containing layer.

11. The method of claim 7, wherein, The atomic layer deposition process is performed in an atmosphere that does not contain chlorine (Cl) or ammonia (NH3).

12. The method of claim 7, wherein, The atomic layer deposition process is performed in a low-temperature atmosphere ranging from 150°C to 350°C.

13. The method of claim 7, wherein, The atomic layer deposition process uses TDMAT as the source gas, where TDMAT stands for tetra(dimethylamino)titanium.

14. The method of claim 7, wherein, The lower electrode is cylindrical or tubular.

15. The method of claim 7, wherein, The molded structure includes at least one molded structure and at least one support layer.

16. A semiconductor device, comprising: A dielectric layer on top of the substrate; as well as A metal electrode is placed above the dielectric layer, the metal electrode comprising a conductive carbon-containing layer. The carbon content in the conductive carbon-containing layer is greater than 5 at% and equal to or less than 10 at%. The conductive carbon-containing layer is a titanium carbon nitride oxide with a lower crystallinity than titanium nitride (TiN).

17. The semiconductor device of claim 16, wherein, The dielectric layer comprises a high-k material.

18. The semiconductor device of claim 16, wherein, The conductive carbon-containing layer has a carbon content that varies depending on its distance from the dielectric layer.

19. The semiconductor device of claim 16, wherein, The dielectric layer includes a tunneling dielectric layer with an ONO structure, where ONO represents oxide-nitride-oxide.

20. The semiconductor device of claim 16, wherein, The dielectric layer includes an interlayer insulating layer, and the interlayer insulating layer includes an inlaid pattern.

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