Driving substrate and display panel

Abstract

The application provides a driving substrate and a display panel. The driving substrate comprises a substrate, a source electrode, a drain electrode and an active layer arranged on the substrate. The source electrode and the drain electrode have a first interval therebetween. The active layer is arranged on the source electrode and the drain electrode. The active layer comprises a channel and source and drain regions located on both sides of the channel. The source region covers at least part of the source electrode. The drain region covers at least part of the drain electrode. The channel corresponds to the first interval. Thus, the length of the channel of the active layer is defined by the interval between the source electrode and the drain electrode. The length of the channel of the active layer is reduced. The electron mobility of the channel of the active layer is improved. The problem that the improvement of the electron mobility of the existing thin film transistor is limited is solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a driving substrate and a display panel. Background Technology

[0002] Thin-film transistors (TFTs) are widely used in driving active-matrix displays, and as display sizes continue to increase, driving frequencies are also constantly rising. For TFTs, the electron mobility in the channel region of the active layer affects the device's operating frequency, and improving electron mobility is beneficial to improving device performance.

[0003] To improve the electron mobility of thin-film transistors (TFTs), the semiconductor material can be changed or the channel width of the TFT can be increased. However, increasing the channel width of the TFT leads to an increase in the overall size of the TFT, which is detrimental to achieving high-resolution displays. This limits the improvement of the electron mobility of TFTs. Summary of the Invention

[0004] This application provides a driving substrate and a display panel to alleviate the technical problem that limits the improvement of electron mobility in existing thin-film transistors.

[0005] To solve the above problems, the technical solution provided in this application is as follows:

[0006] This application provides a driving substrate, which includes:

[0007] Substrate;

[0008] A source and a drain are disposed on the substrate, and a first gap is formed between the source and the drain;

[0009] An active layer is disposed on the substrate and the source and the drain. The active layer includes a channel and source and drain regions located on both sides of the channel. The source regions cover at least a portion of the source and the drain regions cover at least a portion of the drain. The channel corresponds to the first interval.

[0010] The gate is disposed on the side of the active layer away from the source and the drain, and is disposed corresponding to the active layer.

[0011] In the driving substrate provided in the embodiments of this application, the orthogonal projection of the gate on the substrate covers the orthogonal projection of the channel of the active layer on the substrate, and also covers the orthogonal projection of at least a portion of the source region of the active layer on the substrate and the orthogonal projection of at least a portion of the drain region of the active layer on the substrate.

[0012] In the driving substrate provided in the embodiments of this application, the driving substrate further includes an auxiliary source located between the source and the substrate and an auxiliary drain located between the drain and the substrate. The auxiliary source is electrically connected to the source and the auxiliary drain is electrically connected to the drain.

[0013] In the driving substrate provided in the embodiments of this application, the driving substrate further includes a conductive layer located on the side of the gate away from the active layer and insulated from the gate. The conductive layer includes a first electrode and a connection trace disposed at intervals. The first electrode is electrically connected to the source and the auxiliary source, and the connection trace is electrically connected to the drain and the auxiliary drain.

[0014] In the driving substrate provided in the embodiments of this application, the orthogonal projection of the first electrode on the substrate at least covers the orthogonal projection of the channel on the substrate.

[0015] In the driving substrate provided in the embodiments of this application, the driving substrate further includes a buffer layer located between the auxiliary source and the auxiliary drain. The source and the drain are located on the buffer layer, and the source and the drain are electrically connected to the corresponding source auxiliary electrode and the drain auxiliary electrode through the vias of the buffer layer, respectively.

[0016] In the driving substrate provided in the embodiments of this application, in the direction perpendicular to the substrate, the thickness of the source electrode is less than the thickness of the auxiliary source electrode, and the thickness of the drain electrode is less than the thickness of the auxiliary drain electrode.

[0017] In the driving substrate provided in the embodiments of this application, the orthogonal projection of the auxiliary source on the substrate at least covers the orthogonal projection of the channel on the substrate.

[0018] In the driving substrate provided in the embodiments of this application, the driving substrate further includes an auxiliary source and an auxiliary drain located on the side of the gate away from the active layer and insulated from the gate. The auxiliary source is electrically connected to the source, and the auxiliary drain is electrically connected to the drain.

[0019] In the driving substrate provided in the embodiments of this application, the materials of the source electrode and the drain electrode both include metal oxides.

[0020] This application also provides a display panel that includes a driving substrate from one of the foregoing embodiments.

[0021] The beneficial effects of this application are as follows: In the driving substrate and display panel provided by this application, the driving substrate includes a substrate and a source electrode, a drain electrode, and an active layer disposed on the substrate. There is a first gap between the source electrode and the drain electrode. The active layer is disposed on the source electrode and the drain electrode. The active layer includes a channel and a source region and a drain region located on both sides of the channel. The source region covers at least a portion of the source electrode, and the drain region covers at least a portion of the drain electrode. The channel corresponds to the first gap. In this way, the length of the active layer channel is limited by the gap between the source electrode and the drain electrode, so as to reduce the length of the active layer channel and thereby improve the electron mobility of the active layer channel, solving the problem that the improvement of electron mobility of existing thin film transistors is limited. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a cross-sectional structural diagram of a driving substrate provided in an embodiment of this application.

[0024] Figure 2 This is a schematic diagram of another cross-sectional structure of the driving substrate provided in an embodiment of this application.

[0025] Figure 3 This is a schematic cross-sectional view of another driving substrate provided in an embodiment of this application.

[0026] Figure 4 This is a schematic flowchart of the driving substrate fabrication method provided in the embodiments of this application.

[0027] Figure 5 This is a schematic cross-sectional view of the substrate provided in an embodiment of this application.

[0028] Figure 6 In order to be in Figure 5 A schematic diagram of the cross-sectional structure of the auxiliary source and auxiliary drain fabricated on the substrate.

[0029] Figure 7 In order to be in Figure 6 A schematic diagram of the cross-sectional structure of the source and drain electrodes fabricated on the structure.

[0030] Figure 8 In order to be in Figure 7 A schematic diagram of the cross-sectional structure of the active layer fabricated on the structure.

[0031] Figure 9In order to be in Figure 8 A schematic diagram of the cross-sectional structure of the gate fabricated on the structure.

[0032] Figure 10 In order to be in Figure 9 A schematic diagram of the cross-sectional structure on which the passivation layer is prepared. Detailed Implementation

[0033] The following descriptions of the embodiments are based on the accompanying illustrations, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of this application, and not for limiting this application. In the figures, structurally similar units are denoted by the same reference numerals. In the figures, the thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thicknesses of each component shown in the figures are arbitrarily shown, but this application is not limited thereto.

[0034] Please refer to Figure 1 , Figure 1 This is a cross-sectional view of a driving substrate provided in an embodiment of this application. The driving substrate 100 includes a substrate 10 and a source electrode 20, a drain electrode 30, an active layer 40, and a gate electrode 50 disposed on the substrate 10. A first gap exists between the source electrode 20 and the drain electrode 30. The active layer 40 is disposed on the substrate 10 and the source electrode 20 and the drain electrode 30. The active layer 40 includes a channel 41 and a source region 42 and a drain region 43 located on both sides of the channel 41. The source region 42 covers at least a portion of the source electrode 20, and the drain region 43 covers at least a portion of the drain electrode 30. The channel 41 corresponds to the first gap. The gate electrode 50 is disposed on the side of the active layer 40 away from the source electrode 20 and the drain electrode 30, and is disposed correspondingly to the active layer 40.

[0035] In this embodiment, the length of the active layer 40 channel 41 is defined by the first interval between the source 20 and the drain 30 to achieve a smaller channel 41 length. This reduces the length of the active layer 40 channel 41 and improves the electron mobility of the active layer 40 channel 41, solving the problem that the improvement of electron mobility in existing thin-film transistors is limited.

[0036] In one embodiment, the driving substrate 100 further includes an auxiliary source 21 located between the source 20 and the substrate 10, and an auxiliary drain 31 located between the drain 30 and the substrate 10. The auxiliary source 21 is electrically connected to the source 20 to reduce the resistance of the source 20; the auxiliary drain 31 is electrically connected to the drain 30 to reduce the resistance of the drain 30.

[0037] Optionally, the substrate 10 can be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, it can include rigid substrates such as glass substrates and plastic substrates; when the substrate 10 is a flexible substrate, it can include flexible substrates such as polyimide (PI) films and ultra-thin glass films.

[0038] The auxiliary source 21 and the auxiliary drain 31 are disposed on the substrate 10, with a gap between them, and are insulated from each other. Optionally, the materials of the auxiliary source 21 and the auxiliary drain 31 include one or more combinations of low resistivity metals such as Mo, Al, Cu, and Ti, for example, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, or Mo / Cu / ITO.

[0039] The auxiliary source 21 and the auxiliary drain 31 are covered with a buffer layer 11, the source 20 and the drain 30 are disposed on the side of the buffer layer 11 away from the substrate 10, and the active layer 40 covers at least a portion of the source 20, at least a portion of the drain 30 and the buffer layer 11.

[0040] Specifically, the buffer layer 11 covers the auxiliary source 21, the auxiliary drain 31, and the substrate 10. The buffer layer 11 prevents unwanted impurities or contaminants (such as moisture, oxygen, etc.) from diffusing from the substrate 10 into the device that may be damaged by these impurities or contaminants. Optionally, the material of the buffer layer 11 includes silicon oxide (SiO2). x ), silicon nitride (SiN) x (or a stack of silicon oxide and silicon nitride.)

[0041] Meanwhile, the buffer layer 11 can also provide a flat top surface to facilitate the formation of the source 20, the drain 30 and the active layer 40 on the buffer layer 11. The flat top surface is more conducive to the formation of good interface characteristics of the active layer 40.

[0042] The source electrode 20 and the drain electrode 30 are formed on the buffer layer 11, and a first gap exists between the source electrode 20 and the drain electrode 30. The materials of the source electrode 20 and the drain electrode 30 both include metals such as ITO, IZO, and ANCL, or metal oxides with low resistivity. For example, if the source electrode 20 and the drain electrode 30 are made of metal oxides such as ITO, the etching size difference in the photolithography process is small. Under the limitations of the exposure machine, the distance of the first gap between the source electrode 20 and the drain electrode 30 can be smaller, which further allows the active layer 40 to form a channel 41 of shorter length, thereby improving the electron mobility of the channel 41 of the active layer 40.

[0043] Furthermore, in a direction perpendicular to the substrate 10 and pointing from the substrate 10 to the source 20, the thickness of the auxiliary source 21 is greater than the thickness of the source 20, and the thickness of the auxiliary drain 31 is greater than the thickness of the drain 30, so as to further reduce the resistance of the auxiliary source 21 and the auxiliary drain 31.

[0044] The active layer 40 covers at least a portion of the source electrode 20, at least a portion of the drain electrode 30, and the buffer layer 11. By forming the active layer 40 on the source electrode 20 and the drain electrode 30, the influence of the etching solution on the active layer 40 during the etching process is avoided. For example, when the etching solution comes into contact with the active layer 40, it will not only erode the film layer of the active layer 40 but also cause changes in the concentration of In, Ga, Zn ions on the surface of the active layer 40, affecting the stability and reliability of the device. Optionally, the material of the active layer 40 includes semiconductor metal oxides such as IGZO, IGZTO, IGTO, IGO, and AZTO.

[0045] The channel 41 of the active layer 40 is disposed corresponding to the first interval. In a direction perpendicular to the substrate 10 and pointing from the substrate 10 to the source 20, the thickness of the active layer 40 is greater than the thickness of the source 20 or the thickness of the drain 30, such that the channel 41 of the active layer 40 is located within the first interval and extends beyond the height of the source 20 or the drain 30. The source region 42 of the active layer 40 covers the source 20, and the drain region 43 of the active layer 40 covers the drain 30. Thus, the surface of the active layer 40 away from the buffer layer 11 is horizontal.

[0046] The orthographic projection of the channel 41 of the active layer 40 onto the substrate 10 falls within the range of the orthographic projection of the auxiliary source 21 onto the substrate 10, thus enabling the auxiliary source 21 to also have a light-shielding function to prevent light from illuminating the channel 41 of the active layer 40. Of course, the orthographic projection of the auxiliary source 21 onto the substrate 10 can also cover the entire orthographic projection of the active layer 40 onto the substrate 10; that is, the orthographic projections of the source region 42 and the drain region 43 of the active layer 40 onto the substrate 10 also fall within the range of the orthographic projection of the auxiliary source 21 onto the substrate 10.

[0047] Furthermore, the orthogonal projection of the source electrode 20 onto the substrate 10 falls within the orthogonal projection range of the auxiliary source electrode 21 onto the substrate 10, and the orthogonal projection area of ​​the source electrode 20 onto the substrate 10 is smaller than the orthogonal projection area of ​​the auxiliary source electrode 21 onto the substrate 10. At the same time, the orthogonal projection area of ​​the drain electrode 30 onto the substrate 10 is smaller than the orthogonal projection area of ​​the auxiliary drain electrode 31 onto the substrate 10.

[0048] The following will explain in detail how to electrically connect the source 20 and the drain 30 to the auxiliary source 21 and the auxiliary drain 31, respectively:

[0049] In one embodiment, the driving substrate 100 further includes a gate 50 located on and insulated from the active layer 40, the gate 50 being disposed corresponding to the active layer 40. Specifically, a gate insulating layer 12 is disposed between the gate 50 and the active layer 40, the gate insulating layer 12 covering the active layer 40, and the gate 50 being disposed on the gate insulating layer 12.

[0050] The gate insulating layer 12 is also disposed corresponding to the active layer 40, and the orthographic projection of the gate insulating layer 12 on the substrate 10 overlaps with the orthographic projection of the active layer 40 on the substrate 10. Optionally, the material of the gate insulating layer 12 includes SiO2. x SiN x A combination of one or more of Al2O3, such as Al2O3 / SiN x / SiO x SiO x / SiN x / SiO x wait.

[0051] The gate 50 is disposed on the gate insulating layer 12. Optionally, the material of the gate 50 is the same as the material of the auxiliary source 21. The orthogonal projection of the gate 50 on the substrate 10 covers the orthogonal projection of the channel 41 of the active layer 40 on the substrate 10, and also covers the orthogonal projection of at least a portion of the source region 42 of the active layer 40 on the substrate 10 and the orthogonal projection of at least a portion of the drain region 43 of the active layer 40 on the substrate 10, so that in the direction perpendicular to the substrate 10, the gate 50 overlaps with both the source 20 and the drain 30.

[0052] Understandably, when a driving voltage is applied to the gate 50, an electric field is formed between the gate 50 and the corresponding source 20. This electric field can transform the source region 42 of the active layer 40 between the gate 50 and the source 20 from a semiconductor to a conductor. Correspondingly, when a driving voltage is applied to the gate 50, an electric field is formed between the gate 50 and the corresponding drain 30. This electric field can transform the drain region 43 of the active layer 40 between the gate 50 and the drain 30 from a semiconductor to a conductor. Therefore, it is unnecessary to use conductive methods such as plasma to conductiveize the source region 42 and drain region 43 of the active layer 40.

[0053] In one embodiment, the driving substrate 100 further includes a conductive layer 60 located on the side of the gate 50 away from the active layer 40 and insulated from the gate 50. The conductive layer 60 includes a first electrode 61 and a connection trace 62 spaced apart. The first electrode 61 is electrically connected to the source 20 and the auxiliary source 21 to achieve an electrical connection between the source 20 and the auxiliary source 21, and simultaneously achieves an electrical connection between the first electrode 61 and the source 20. The connection trace 62 is electrically connected to the drain 30 and the auxiliary drain 31 to achieve an electrical connection between the drain 30 and the auxiliary drain 31.

[0054] Optionally, a passivation layer 13 is disposed between the conductive layer 60 and the gate 50. The passivation layer 13 covers the gate 50, a portion of the source 20, a portion of the drain 30, and the buffer layer 11. A plurality of first vias 131 and a plurality of second vias 132 are formed on the passivation layer 13. The first vias 131 penetrate the passivation layer 13, with a portion of the first vias 131 exposing a portion of the source 20 and another portion exposing a portion of the drain 30. The second vias 132 penetrate the passivation layer 13 and the buffer layer 11, with a portion of the second vias 132 exposing a portion of the auxiliary source 21 and another portion exposing a portion of the auxiliary drain 31.

[0055] The first electrode 61 is electrically connected to the source electrode 20 through a portion of the conductive layer 60 within the first via 131, and is also electrically connected to the auxiliary source electrode 21 through a portion of the conductive layer 60 within the second via 132. The connection trace 62 is electrically connected to the drain electrode 30 through a portion of the conductive layer 60 within the first via 131, and is also electrically connected to the auxiliary drain electrode 31 through a portion of the conductive layer 60 within the second via 132. Thus, the electrical connections between the source electrode 20 and the drain electrode 30 and their corresponding auxiliary source electrode 21 and auxiliary drain electrode 31, as well as the electrical connection between the first electrode 61 and the source electrode 20, can be achieved using a single photomask, which helps save costs.

[0056] In one embodiment, the orthographic projection of the first electrode 61 on the substrate 10 at least covers the orthographic projection of the channel 41 on the substrate 10. By providing a larger area for the first electrode 61, it is possible to block moisture from the environment from diffusing into the channel 41 region of the active layer 40, thereby improving the reliability of the device.

[0057] Optionally, in order to achieve a better effect of blocking moisture in the environment, the orthogonal projection of the first electrode 61 on the substrate 10 may also cover the entire orthogonal projection of the gate 50 on the substrate 10, so as to form a larger area of ​​the first electrode 61.

[0058] In one embodiment, please refer to the reference. Figure 1 and Figure 2 , Figure 2 This is a schematic cross-sectional view of another driving substrate provided in an embodiment of this application. Unlike the embodiments described above, the driving substrate 101 further includes a buffer layer 11 located between the auxiliary source 21 and the auxiliary drain 31. The source 20 and the drain 30 are located on the buffer layer 11, and the source 20 and the drain 30 are electrically connected to the corresponding auxiliary electrodes of the source 20 and the drain 30 through vias in the buffer layer 11.

[0059] Specifically, a third via 111 and a fourth via 112 are formed on the buffer layer 11. The third via 111 penetrates the buffer layer 11 and exposes a portion of the auxiliary source 21. The fourth via 112 penetrates the buffer layer 11 and exposes a portion of the auxiliary drain 31. The source 20 is electrically connected to the auxiliary source 21 through the conductive material within the third via 111, and the drain 30 is electrically connected to the auxiliary drain 31 through the conductive material within the fourth via 112. Other details are provided in the above embodiment and will not be repeated here.

[0060] In one embodiment, please refer to the reference. Figure 1and Figure 3 , Figure 3 This is a schematic cross-sectional view of another driving substrate provided in an embodiment of this application. Unlike the above embodiment, the driving substrate 102 further includes an auxiliary source 21 and an auxiliary drain 31 located on the side of the gate 50 away from the active layer 40 and insulated from the gate 50. The auxiliary source 21 is electrically connected to the source 20, and the auxiliary drain 31 is electrically connected to the drain 30.

[0061] Specifically, the auxiliary source 21 and the auxiliary drain 31 are disposed on the passivation layer 13, and a via is formed on the passivation layer 13, penetrating the passivation layer 13 and exposing a portion of the source 20 and the drain 30. The auxiliary source 21 is electrically connected to the source 20 through the conductive material in the via on the passivation layer 13, and the auxiliary drain 31 is electrically connected to the drain 30 through the conductive material in the via on the passivation layer 13.

[0062] The auxiliary source electrode 21 and the auxiliary drain electrode 31 are covered with a planarization layer 14. The first electrode 61 is disposed on the planarization layer 14. A via is formed on the planarization layer 14, penetrating the planarization layer 14 and exposing part of the auxiliary source electrode 21. The first electrode 61 is electrically connected to the auxiliary source electrode 21 through the conductive material in the via on the planarization layer 14. Other descriptions are provided in the above embodiment and will not be repeated here.

[0063] In one embodiment, a method for fabricating a driving substrate is also provided, please refer to... Figures 4 to 10 , Figure 4 This is a schematic flowchart of the driving substrate fabrication method provided in the embodiments of this application. Figure 5 This is a schematic cross-sectional view of the substrate provided in an embodiment of this application. Figure 6 In order to be in Figure 5 A schematic diagram of the cross-sectional structure of the auxiliary source and auxiliary drain fabricated on the substrate. Figure 7 In order to be in Figure 6 A schematic diagram of the cross-sectional structure of the source and drain electrodes fabricated on the structure. Figure 8 In order to be in Figure 7 A schematic diagram of the cross-sectional structure of the active layer fabricated on the structure. Figure 9 In order to be in Figure 8 A schematic diagram of the cross-sectional structure of the gate fabricated on the structure. Figure 10 In order to be in Figure 9 A cross-sectional structural diagram of the passivation layer fabricated on the structure. The method for fabricating the driving substrate includes the following steps:

[0064] S301: Provides substrate 10;

[0065] Specifically, a substrate 10 is provided, such as Figure 5As shown, the substrate 10 can be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, it can include rigid substrates such as glass substrates and plastic substrates; when the substrate 10 is a flexible substrate, it can include flexible substrates such as polyimide (PI) films and ultra-thin glass films.

[0066] S302: A source electrode 20 and a drain electrode 30 are formed on the substrate 10, and a first gap is formed between the source electrode 20 and the drain electrode 30;

[0067] Specifically, a first metal thin film is prepared on the substrate 10 using deposition processes such as physical vapor deposition, and the first metal thin film is patterned to form an auxiliary source 21 and an auxiliary drain 31, such as... Figure 6 As shown. Optionally, the material of the first metal thin film includes one or more combinations of low resistivity metals such as Mo, Al, Cu, and Ti, for example, it can be a combination of Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, or Mo / Cu / ITO.

[0068] Next, a buffer layer 11 is deposited on the auxiliary source 21, the auxiliary drain 31, and the substrate 10 using deposition processes such as chemical vapor deposition. The material of the buffer layer 11 includes silicon oxide (SiO2). x ), silicon nitride (SiN) x (or a stack of silicon oxide and silicon nitride.)

[0069] Then, a source electrode 20 and a drain electrode 30 are fabricated on the buffer layer 11, with a first gap 201 between the source electrode 20 and the drain electrode 30, such as... Figure 7 As shown. The materials of the source electrode 20 and the drain electrode 30 both include metals such as ITO, IZO, and ANCL, or metal oxides with low resistivity. For example, if the source electrode 20 and the drain electrode 30 are made of metal oxides such as ITO, the etching size difference of metal oxides such as ITO in the photolithography process is small. Under the limit of the exposure machine, the distance of the first gap between the source electrode 20 and the drain electrode 30 can be smaller, which can further enable the active layer 40 to form a channel 41 with a shorter length, thereby improving the electron mobility of the channel 41 of the active layer 40.

[0070] S303: An active layer 40 is formed on the substrate 10, the source electrode 20, and the drain electrode 30. The active layer 40 includes a channel 41 and a source region 42 and a drain region 43 located on both sides of the channel 41. The source region 42 covers at least a portion of the source electrode 20, and the drain region 43 covers at least a portion of the drain electrode 30. The channel 41 corresponds to the first interval.

[0071] Specifically, a metal oxide semiconductor thin film is deposited on the substrate 10, the source electrode 20, and the drain electrode 30. The metal oxide semiconductor thin film is patterned to form an active layer 40. The active layer 40 includes a channel 41 and a source region 42 and a drain region 43 located on both sides of the channel 41. The source region 42 covers at least a portion of the source electrode 20, and the drain region 43 covers at least a portion of the drain electrode 30. The channel 41 corresponds to the first interval, such as... Figure 8 As shown.

[0072] Optionally, the active layer 40 may be made of semiconductor metal oxides such as IGZO, IGZTO, IGTO, IGO, and AZTO.

[0073] S304: A gate 50 is formed on the side of the active layer 40 away from the substrate 10, wherein the orthogonal projection of the gate 50 on the substrate 10 covers the orthogonal projection of the channel 41 of the active layer 40 on the substrate 10, and also covers the orthogonal projection of at least a portion of the source region 42 of the active layer 40 on the substrate 10 and covers the orthogonal projection of at least a portion of the drain region 43 of the active layer 40 on the substrate.

[0074] Specifically, inorganic thin films are deposited on the active layer 40, the source electrode 20, the drain electrode 30, and the buffer layer 11 using deposition processes such as chemical vapor deposition. The material of the inorganic thin film includes SiO2. x SiN x A combination of one or more of Al2O3, such as Al2O3 / SiN x / SiO x SiO x / SiN x / SiO x wait.

[0075] Next, a second metal thin film is deposited on the inorganic thin film using a deposition process such as physical vapor deposition. The second metal thin film is then patterned to form a gate 50, which is disposed corresponding to the active layer 40. Optionally, the material of the second metal thin film may be the same as that of the first metal thin film.

[0076] Then, using the gate 50 as a shield, a self-aligned process is employed to pattern the inorganic thin film to form the gate insulating layer 12, such as... Figure 9 As shown.

[0077] The method for preparing the driving substrate further includes the following steps:

[0078] A conductive layer 60 is formed on the side of the gate 50 away from the active layer 40. The conductive layer 60 includes a first electrode 61 and a connecting line 62 spaced apart. The first electrode 61 is electrically connected to the source 20 and the auxiliary source 21, and the connecting line 62 is electrically connected to the drain 30 and the auxiliary drain 31.

[0079] Specifically, a passivation layer 13 is deposited on the gate 50, the source 20, the drain 30, and the buffer layer 11 using a deposition process such as chemical vapor deposition. The material of the passivation layer 13 includes silicon oxide, silicon nitride, or a stack of silicon oxide and silicon nitride.

[0080] The passivation layer 13 is patterned to form a plurality of first vias 131 and a plurality of second vias 132 on the passivation layer 13, such as Figure 10 As shown. The first via 131 penetrates the passivation layer 13, with a portion of the first via 131 exposing a portion of the source electrode 20, and another portion of the first via 131 exposing a portion of the drain electrode 30. The second via 132 penetrates the passivation layer 13 and the buffer layer 11, with a portion of the second via 132 exposing a portion of the auxiliary source electrode 21, and another portion of the second via 132 exposing a portion of the auxiliary drain electrode 31.

[0081] Next, a conductive layer 60 is fabricated on the passivation layer 13, and the conductive layer 60 is patterned to form a first electrode 61 and a connecting trace 62, as shown below. Figure 1 As shown. The first electrode 61 is electrically connected to the source electrode 20 through a portion of the conductive layer 60 within the first via 131, and simultaneously, the first electrode 61 is also electrically connected to the auxiliary source electrode 21 through a portion of the conductive layer 60 within the second via 132. The connection trace 62 is electrically connected to the drain electrode 30 through a portion of the conductive layer 60 within the first via 131, and simultaneously, the connection trace 62 is also electrically connected to the auxiliary drain electrode 31 through a portion of the conductive layer 60 within the second via 132. Thus, the electrical connections of the source electrode 20 and the drain electrode 30 to the auxiliary source electrode 21 and the auxiliary drain electrode 31, respectively, as well as the electrical connection of the first electrode 61 to the source electrode 20, can be achieved using a single photomask, which helps to save costs.

[0082] Optionally, the conductive layer 60 is a layer formed of metal oxide electrode materials such as IZO and ITO, or a three-layer metal anti-reflection structure of IZO / Mo / Cu can be used to reduce the influence of the light-emitting unit on the channel 41 of the active layer 40.

[0083] Based on the same inventive concept, this application also provides a display panel, which includes a driving substrate of one of the foregoing embodiments. The display panel can be a liquid crystal display panel, an OLED display panel, or an LED direct-view display panel, etc. For example, when the display panel is an LED direct-view display panel, it further includes an LED chip, which is bonded to the driving substrate 100. Specifically, the driving substrate 100 also has a second electrode on the same layer as the first electrode 61. The LED chip is electrically connected to the first electrode 61 and the second electrode on the driving substrate 100 to achieve bonding between the LED chip and the driving substrate 100.

[0084] As can be seen from the above embodiments:

[0085] This application provides a driving substrate and a display panel. The driving substrate includes a substrate and a source electrode, a drain electrode, and an active layer disposed on the substrate. A first gap exists between the source electrode and the drain electrode. The active layer is disposed on the source electrode and the drain electrode. The active layer includes a channel and a source region and a drain region located on both sides of the channel. The source region covers at least a portion of the source electrode, and the drain region covers at least a portion of the drain electrode. The channel corresponds to the first gap. Thus, the length of the active layer channel is limited by the gap between the source electrode and the drain electrode, thereby reducing the length of the active layer channel and improving the electron mobility of the active layer channel. This solves the problem that the improvement of electron mobility in existing thin-film transistors is limited.

[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0087] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A driving substrate, characterized in that, include: Substrate; A source and a drain are disposed on the substrate, and a first gap is formed between the source and the drain; An active layer is disposed on the substrate and the source and the drain. The active layer includes a channel and source and drain regions located on both sides of the channel. The source regions cover at least a portion of the source and the drain regions cover at least a portion of the drain. The channel corresponds to the first interval. A gate is disposed on the side of the active layer away from the source and the drain, and is disposed corresponding to the active layer; An auxiliary source electrode is located between the source electrode and the substrate, the auxiliary source electrode is electrically connected to the source electrode, and the orthogonal projection of the auxiliary source electrode on the substrate at least covers the orthogonal projection of the channel on the substrate. A conductive layer is disposed on the side of the gate away from the substrate. The conductive layer includes a first electrode electrically connected to the source and the auxiliary source. The orthogonal projection of the first electrode on the substrate at least covers the orthogonal projection of the channel on the substrate. Wherein, the orthogonal projection of the gate on the substrate covers the orthogonal projection of the channel of the active layer on the substrate, and also covers the orthogonal projection of at least a portion of the source region of the active layer on the substrate and the orthogonal projection of at least a portion of the drain region of the active layer on the substrate.

2. The driving substrate according to claim 1, characterized in that, The driving substrate further includes an auxiliary drain located between the drain and the substrate, and the auxiliary drain is electrically connected to the drain.

3. The driving substrate according to claim 2, characterized in that, The driving substrate further includes a conductive layer that is insulated from the gate. The conductive layer includes connection traces spaced apart from the first electrode, and the connection traces are electrically connected to the drain and the auxiliary drain.

4. The driving substrate according to claim 2, characterized in that, The driving substrate further includes a buffer layer located between the auxiliary source and the auxiliary drain, the source and the drain being located on the buffer layer, and the source and the drain being electrically connected to the corresponding source auxiliary electrode and the drain auxiliary electrode through vias in the buffer layer, respectively.

5. The driving substrate according to claim 2, characterized in that, In a direction perpendicular to the substrate, the thickness of the source electrode is less than the thickness of the auxiliary source electrode, and the thickness of the drain electrode is less than the thickness of the auxiliary drain electrode.

6. The driving substrate according to claim 1, characterized in that, Both the source electrode and the drain electrode are made of metal oxides.

7. A display panel, characterized in that, Includes the driving substrate as described in any one of claims 1-6.

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