A sensing pixel cell, array and structure

Abstract

The embodiment of the application discloses a sensing pixel unit, array and structure, which comprises a first switch transistor, a second switch transistor and a sensing transistor; the first switch transistor serves as a conduction switch of the sensing transistor; and the second switch transistor serves as a gating switch of a third gate of the sensing transistor. Through the embodiment scheme, the active addressing function is realized, so that the working electrode of a specific pixel can be selected for probe modification in the electrode modification stage of the microarray chip, and the detection function is not affected, and the detection accuracy is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to thin film transistor design technology, and in particular to a sensing pixel unit, array and structure. BACKGROUND

[0002] In order to meet the detection of multiple target molecules by a thin film transistor sensing array chip, a micro working electrode in each sensing pixel needs to be selectively modified with a specific probe. Generally, in a low-resolution array, a micro droplet reagent is spotted on a local site by using a spotting technology, so as to modify the working electrode site in the sensing pixel. However, in a microarray chip with better high throughput and higher resolution, the working electrode is not only small in size, but also arranged very densely, so that it is difficult to achieve accurate spotting on a local site. Meanwhile, considering that the working electrode of the extended gate sensing transistor is in a suspended state, there will be charge accumulation after a period of work, which causes signal drift and affects the accuracy of detection. SUMMARY

[0003] Embodiments of the present application provide a sensing pixel unit, array and structure, which can realize active addressing function, so that the working electrode of a specific pixel can be modified with a probe as needed in the electrode modification stage of a microarray chip, and the detection function is not affected, thereby improving the detection accuracy.

[0004] Embodiments of the present application provide a sensing pixel unit, which can include a first switch transistor, a second switch transistor and a sensing transistor.

[0005] The first switch transistor serves as a conduction switch of the sensing transistor.

[0006] The second switch transistor serves as a gating switch of a third gate of the sensing transistor.

[0007] In exemplary embodiments of the present application, the first switch transistor can include a first pin, a second pin and a third pin; the third pin is a first gate.

[0008] The second switch transistor can include a fourth pin, a fifth pin and a sixth pin; the sixth pin is a second gate.

[0009] The sensing transistor can include a seventh pin, an eighth pin and a ninth pin; the ninth pin is a third gate; the third gate is in a suspended state.

[0010] The second pin is connected to the seventh pin, and the fourth pin is connected to the ninth pin.

[0011] The first pin and the eighth pin are configured to output a readout signal.

[0012] The third pin is configured to input the startup voltage of the first switching transistor;

[0013] The sixth pin is configured to input the startup voltage of the second switching transistor;

[0014] The fifth pin is configured as the input drive voltage.

[0015] This application embodiment also provides a sensing pixel array, which may include:

[0016] The aforementioned sensing pixel unit;

[0017] Sensor signal readout circuit;

[0018] Row selection circuit;

[0019] Drive circuit; and,

[0020] Reference electrode;

[0021] Wherein, the second pin of the first switching transistor included in the sensing pixel unit is connected to the seventh pin of the sensing transistor included in the sensing pixel unit, and the fourth pin of the second switching transistor included in the sensing pixel unit is connected to the ninth pin of the sensing transistor, wherein the ninth pin is the third gate; the third gate is in a floating state.

[0022] The first pin of the first switching transistor is connected to the sensing signal readout circuit;

[0023] The eighth pin of the sensing transistor is connected to the sensing signal readout circuit.

[0024] The fifth pin of the second switching transistor is connected to the drive circuit;

[0025] The third pin of the first switching transistor is connected to the row selection circuit; the third pin is the first gate.

[0026] The sixth pin of the second switching transistor is connected to the row selection circuit; the sixth pin is the second gate.

[0027] The reference electrode is connected to the sensing signal readout circuit.

[0028] This application embodiment also provides a sensing pixel structure, which is the structure of the sensing pixel unit, and may include: a first switching transistor structure, a second switching transistor structure and a sensing transistor structure;

[0029] The first switching transistor structure, the sensing transistor structure, and the second switching transistor structure are arranged sequentially in the horizontal direction.

[0030] In an exemplary embodiment of this application, the sensing pixel structure may further include a substrate;

[0031] The first switching transistor structure, the sensing transistor structure, and the second switching transistor structure are all disposed on the substrate;

[0032] The first switching transistor structure, the sensing transistor structure, and the second switching transistor structure are all embedded between the interlayer dielectric.

[0033] In an exemplary embodiment of this application, the first switching transistor structure may include:

[0034] The first source and drain are disposed on the substrate;

[0035] The second source / drain electrode is disposed on the substrate;

[0036] A first organic semiconductor is disposed on the substrate, located between the first source drain and the second source drain, and extends upward above the first source drain and the second source drain. The portion above the first source drain and the second source drain extends a portion toward one side of the first source drain and the second source drain, respectively.

[0037] A first gate dielectric is disposed above the first organic semiconductor;

[0038] A first gate is disposed above the first gate dielectric;

[0039] The first gate contact electrode is disposed in the first gate via in the interlayer medium, connected to the upper surface of the first gate, and extends to the upper surface of the interlayer medium, with a portion extending around the upper surface of the interlayer medium.

[0040] In an exemplary embodiment of this application, the second switching transistor structure may include:

[0041] The third source / drain is disposed on the substrate;

[0042] The fourth source / drain electrode is disposed on the substrate;

[0043] A second organic semiconductor is disposed on the substrate, located between the third source drain and the fourth source drain, and extends upward above the third source drain and the fourth source drain. The portion above the third source drain and the fourth source drain extends a portion toward one side of the third source drain and the fourth source drain, respectively.

[0044] A second gate dielectric is disposed above the second organic semiconductor;

[0045] The second gate is disposed above the second gate dielectric;

[0046] The second gate contact electrode is disposed in the second gate via in the interlayer medium, connected to the upper surface of the second gate, and extends to the upper surface of the interlayer medium, with a portion extending around the upper surface of the interlayer medium.

[0047] In an exemplary embodiment of this application, the sensing transistor structure may include:

[0048] The fifth source / drain electrode is disposed on the substrate;

[0049] The sixth source and drain are disposed on the substrate and share the same source and drain as the second source and drain of the first switching transistor structure.

[0050] A third organic semiconductor is disposed on the substrate, located between the fifth source drain and the sixth source drain, and extends upward above the fifth source drain and the sixth source drain. The portion above the fifth source drain and the sixth source drain extends a portion toward one side of the fifth source drain and the sixth source drain, respectively.

[0051] A third gate dielectric is disposed above the third organic semiconductor;

[0052] A third gate is disposed above the third gate dielectric;

[0053] The third gate contact electrode is disposed in the third gate via in the interlayer dielectric, connected to the upper surface of the third gate, and extends to the upper surface of the interlayer dielectric. A portion of the electrode extends around the upper surface of the interlayer dielectric, and the extended portion connects with the fourth source and drain of the second switching transistor structure.

[0054] In an exemplary embodiment of this application, the sensing pixel structure may further include: an encapsulation layer and a reference electrode, wherein the encapsulation layer is disposed above the interlayer medium; and the reference electrode is disposed on the upper surface of the interlayer medium.

[0055] The first gate contact electrode of the first switching transistor structure, the second gate contact electrode of the second switching transistor structure, the third gate contact electrode of the sensing transistor structure, and the reference electrode are all embedded in the encapsulation layer.

[0056] In an exemplary embodiment of this application, a working electrode via is provided in the encapsulation layer above the third gate contact electrode, and a reference electrode via is provided in the encapsulation layer above the reference electrode.

[0057] A modification probe is formed in the working electrode via, and the modification probe is connected to the third gate contact electrode.

[0058] A reference functional film is formed in the through-hole of the reference electrode, and the reference functional film is connected to the reference electrode.

[0059] Compared with related technologies, the sensing pixel unit in this application embodiment may include: a first switching transistor, a second switching transistor, and a sensing transistor; the first switching transistor serves as the on switch of the sensing transistor; and the second switching transistor serves as the selection switch of the third gate of the sensing transistor. This embodiment achieves active addressing, allowing for selective probe modification of the working electrode of a specific pixel during the electrode modification stage of the microarray chip, without affecting the detection function. Selective conduction of the first and second switching transistors provides a discharge path for accumulated charge, thereby avoiding signal drift and improving detection accuracy.

[0060] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0061] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0062] Figure 1 This is a schematic diagram of a sensing pixel unit according to an embodiment of this application;

[0063] Figure 2 This is a schematic diagram of the sensor pixel matrix connection according to an embodiment of this application;

[0064] Figure 3 This is a schematic diagram of the sensor pixel structure according to an embodiment of this application. Detailed Implementation

[0065] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0066] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0067] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0068] This application provides a sensing pixel unit A, such as Figure 1 As shown, it may include: a first switching transistor A1, a second switching transistor A2, and a sensing transistor A3;

[0069] The first switching transistor A1 serves as the on / off switch for the sensing transistor A3;

[0070] The second switching transistor A2 serves as the gate switch for the third gate of the sensing transistor A3.

[0071] In an exemplary embodiment of this application, the first switching transistor A1 may include: a first pin P1, a second pin P2, and a third pin P3; the third pin P3 is a first gate G1;

[0072] The second switching transistor A2 may include: a fourth pin P4, a fifth pin P5, and a sixth pin P6; the sixth pin P6 is the second gate.

[0073] The sensing transistor A3 may include: a seventh pin P7, an eighth pin P8, and a ninth pin P9; the ninth pin P9 is the third gate; the third gate is in a floating state.

[0074] The second pin P2 is connected to the seventh pin P7, and the fourth pin P4 is connected to the ninth pin P9;

[0075] The first pin P1 and the eighth pin P8 are configured as readout signals;

[0076] The third pin P3 is configured to input the start-up voltage of the first switching transistor A1;

[0077] The sixth pin P6 is configured to input the start-up voltage of the second switching transistor A2;

[0078] The fifth pin P5 is set as the input drive voltage.

[0079] To enable thin-film transistor (TFT) sensor array chips to detect a variety of target molecules, the micro-working electrodes within each sensing pixel need to be selectively modified with specific probes. Typically, in low-resolution arrays, spotting techniques are used to apply microdroplets of reagent to local sites, thus modifying the working electrode sites within that sensing pixel. However, in high-throughput and high-resolution microarray chips, the working electrodes are not only small in size but also densely packed, making precise spotting of local sites impractical. Furthermore, considering that the working electrodes of extended-gate TFTs are suspended, charge accumulation after a period of operation can cause signal drift, thus affecting detection accuracy.

[0080] In an exemplary embodiment of this application, in order to solve the above-mentioned modification and detection problems, additional thin-film transistors are added as switches within the sensing pixels. For example, a first switching transistor A1 and a second switching transistor A2 are added to realize active addressing function, so that probe modification of the working electrode of a specific sensing pixel unit can be selected as needed during the electrode modification stage of the microarray (i.e., sensing pixel array) chip.

[0081] In an exemplary embodiment of this application, the first switching transistor A1 can be a thin-film transistor, which serves as the selection switch for the sensing transistor A3 to complete the reading of the sensing signal. The second switching transistor A2 can be a thin-film transistor, which serves as the selection switch for the floating gate (third gate) of the sensing transistor A3 to complete the electrode modification and charge reset operations.

[0082] In an exemplary embodiment of this application, during the detection phase of the sensing transistor A3, the first switching transistor A1 is closed and the second switching transistor A2 is turned on, thereby putting the current sensing pixel unit in a maintenance state, which does not affect the detection function and does not affect the read and write operations of sensing pixel units A in other rows.

[0083] In an exemplary embodiment of this application, after the sensing pixel unit A has been working for a period of time, the first switching transistor A1 and the second switching transistor A2 can be selectively turned on to form a release channel for the charge accumulated on the working electrode, thereby improving drift characteristics and ultimately improving the accuracy of detection.

[0084] In an exemplary embodiment of this application, the first switching transistor A1, the first switching transistor A1, and the sensing transistor A3 can all be selected as N-type MOS transistors or P-type MOS transistors. There is no limitation on the specific selection of the first switching transistor A1, the first switching transistor A1, and the sensing transistor A3, and the corresponding pins are set as source or drain according to different selections.

[0085] This application also provides a sensing pixel array B, such as Figure 2 As shown, it may include:

[0086] The aforementioned sensing pixel unit A;

[0087] Sensor signal readout circuit 401;

[0088] Row selection circuit 400;

[0089] Drive circuit 402; and,

[0090] Reference electrode 204;

[0091] Wherein, the second pin P2 of the first switching transistor A1 included in the sensing pixel unit A is connected to the seventh pin P7 of the sensing transistor A3 included in the sensing pixel unit A, and the fourth pin P4 of the second switching transistor A2 included in the sensing pixel unit A is connected to the ninth pin P9 of the sensing transistor A3, wherein the ninth pin P9 is the third gate; the third gate is in a floating state.

[0092] The first pin P1 of the first switching transistor A1 is connected to the sensing signal readout circuit 401;

[0093] The eighth pin P8 of the sensing transistor A3 is connected to the sensing signal readout circuit 401;

[0094] The fifth pin P5 of the second switching transistor A2 is connected to the drive circuit 402;

[0095] The third pin P3 of the first switching transistor A2 is connected to the row selection circuit 400; the third pin P3 is the first gate.

[0096] The sixth pin of the second switching transistor A2 is connected to the row selection circuit 400; the sixth pin P6 is the second gate.

[0097] The reference electrode 204 is connected to the sensing signal readout circuit 401.

[0098] In an exemplary embodiment of this application, the first switching transistor A1 can be a thin-film transistor, which serves as the selection switch for the sensing transistor A3 to complete the reading of the sensing signal. The second switching transistor A2 can be a thin-film transistor, which serves as the selection switch for the floating gate (third gate) of the sensing transistor A3 to complete the electrode modification and charge reset operations.

[0099] In an exemplary embodiment of this application, after working for a period of time, the first switching transistor A1 and the second switching transistor A2 can be selectively turned on by the row selection circuit B2 and the driving circuit B3, thereby forming a release channel for the charge accumulated on the working electrode, improving drift characteristics, and ultimately improving the accuracy of detection.

[0100] This application also provides a sensing pixel structure, such as Figure 3 The structure of the sensing pixel unit A shown is included, which may include: a first switching transistor structure 101, a second switching transistor structure 102 and a sensing transistor structure 103.

[0101] The first switching transistor structure 101, the sensing transistor structure 103, and the second switching transistor structure 103 are arranged sequentially in the horizontal direction.

[0102] In an exemplary embodiment of this application, the first switching transistor structure 101 is the structure of the first switching transistor A1, the second switching transistor structure 102 is the structure of the first switching transistor A2, and the sensing transistor structure 103 is the structure of the sensing transistor A3.

[0103] In an exemplary embodiment of this application, the sensing pixel structure may further include a substrate 100 and an interlayer medium 150;

[0104] The first switching transistor structure 101, the sensing transistor structure 102 and the second switching transistor structure 103 are all disposed on the substrate 100;

[0105] The first switching transistor structure 101, the sensing transistor structure 102 and the second switching transistor structure 103 are all embedded between the interlayer dielectric 150.

[0106] In an exemplary embodiment of this application, starting from the upper surface of the substrate 100, the main components (e.g., drain-source, organic semiconductor, gate dielectric, and gate) of the first switching transistor structure 101, the sensing transistor structure 102, and the second switching transistor structure 103 can be sequentially arranged from bottom to top. After the main components are arranged, the interlayer dielectric 150 is arranged, and the first switching transistor structure 101, the sensing transistor structure 102, and the second switching transistor structure 103 are all embedded in the interlayer dielectric 150.

[0107] In an exemplary embodiment of this application, the first switching transistor structure 101 may include:

[0108] The first source / drain electrode 111 is disposed on the substrate 100;

[0109] The second source / drain 141 is disposed on the substrate 100;

[0110] A first organic semiconductor 112 is disposed on the substrate, located between the first source / drain 111 and the second source / drain 141, and extends upward above the first source / drain 111 and the second source / drain 141. The portion above the first source / drain 111 and the second source / drain 141 extends a portion toward one side of the first source / drain 111 and the second source / drain 141, respectively.

[0111] The first gate dielectric 113 is disposed above the first organic semiconductor 112;

[0112] The first gate 114 is disposed above the first gate dielectric 113;

[0113] The first gate contact electrode 201 is disposed in the first gate via 161 in the interlayer medium 150, connected to the upper surface of the first gate 114, and extends to the upper surface of the interlayer medium 150, with a portion extending around the upper surface of the interlayer medium 150.

[0114] In an exemplary embodiment of this application, the fabrication process of the first switching transistor structure 101 may include: performing the following processes from bottom to top based on the substrate 100:

[0115] 1. A first source / drain electrode 111 and a second source / drain electrode 141 are formed on the substrate 100;

[0116] 2. On the substrate 100, a first organic semiconductor 112 is embedded between the first source / drain 111 and the second source / drain 141, and extends upward above the first source / drain 111 and the second source / drain 141. The portion above the first source / drain 111 and the second source / drain 141 extends to one side of the first source / drain 111 and the second source / drain 141, respectively.

[0117] 3. A first gate dielectric 113 is disposed on the first organic semiconductor 112;

[0118] 4. A first gate 114 is disposed on the first gate dielectric 113;

[0119] 5. An interlayer dielectric 150 is provided, in which the first source / drain 111, the second source / drain 141, the first organic semiconductor 112, the first gate dielectric 113, and the first gate 114 are all encapsulated;

[0120] 6. A first gate via 161 is provided in the interlayer dielectric 150 above the first gate 114. A first gate contact electrode 201 is provided in the first gate via 161. One end of the first gate contact electrode 201 is connected to the first gate 114, and the other end extends to the upper surface of the interlayer dielectric 150, with a portion extending around the upper surface of the interlayer dielectric 150.

[0121] In an exemplary embodiment of this application, the second switching transistor structure 102 may include:

[0122] The third source drain 121 is disposed on the substrate 100;

[0123] The fourth source / drain 142 is disposed on the substrate 100;

[0124] The second organic semiconductor 122 is disposed on the substrate 100, located between the third source / drain 121 and the fourth source / drain 142, and extends upward above the third source / drain 121 and the fourth source / drain 142. The portion of the semiconductor that extends above the third source / drain 121 and the fourth source / drain 142 extends to one side of the third source / drain 121 and the fourth source / drain 142, respectively.

[0125] The second gate dielectric 123 is disposed above the second organic semiconductor 122;

[0126] The second gate 124 is disposed above the second gate dielectric 123;

[0127] The second gate contact electrode is disposed in the second gate via in the interlayer medium, connected to the upper surface of the second gate, and extends to the upper surface of the interlayer medium, with a portion extending around the upper surface of the interlayer medium.

[0128] In an exemplary embodiment of this application, the fabrication process of the second switching transistor structure 102 may include: performing the following processes from bottom to top based on the substrate 100:

[0129] 1. A third source / drain electrode 121 and a fourth source / drain electrode 142 are formed on the substrate 100;

[0130] 2. On the substrate 100, a second organic semiconductor 122 is embedded between the third source drain 121 and the fourth source drain 142, and extends upward above the third source drain 121 and the fourth source drain 142. The portion above the third source drain 121 and the fourth source drain 142 extends a portion toward one side of the third source drain 121 and the fourth source drain 142, respectively.

[0131] 3. A second gate dielectric 123 is disposed on the second organic semiconductor 122;

[0132] 4. A second gate 124 is disposed on the second gate dielectric 123;

[0133] 5. An interlayer dielectric 150 is provided, in which the third source / drain 121, the fourth source / drain 142, the second organic semiconductor 122, the second gate dielectric 123, and the second gate 124 are all encapsulated;

[0134] 6. A second gate via 162 is provided in the interlayer dielectric 150 above the second gate 124. A second gate contact electrode 202 is provided in the second gate via 162. One end of the second gate contact electrode 202 is connected to the second gate 124, and the other end extends to the upper surface of the interlayer dielectric 150, extending a portion around the upper surface of the interlayer dielectric 150.

[0135] In an exemplary embodiment of this application, the sensing transistor structure 103 may include:

[0136] The fifth source / drain 131 is disposed on the substrate 100;

[0137] The sixth source and drain are disposed on the substrate 100 and share the same source and drain as the second source and drain 141 of the first switching transistor structure 101.

[0138] A third organic semiconductor 132 is disposed on the substrate, located between the fifth source drain 131 and the sixth source drain 141, and extends upward above the fifth source drain 131 and the sixth source drain 141. The portion above the fifth source drain 131 and the sixth source drain 141 extends a portion toward one side of the fifth source drain 131 and the sixth source drain 141, respectively.

[0139] The third gate dielectric 133 is disposed above the third organic semiconductor 132;

[0140] The third gate 134 is disposed above the third gate dielectric 133;

[0141] The third gate contact electrode is disposed in the third gate via in the interlayer dielectric, connected to the upper surface of the third gate, and extends to the upper surface of the interlayer dielectric. A portion of the electrode extends around the upper surface of the interlayer dielectric, and the extended portion connects with the fourth source and drain of the second switching transistor structure.

[0142] In an exemplary embodiment of this application, the fabrication process of the sensing transistor structure 103 may include: performing the following processes from bottom to top based on the substrate 100:

[0143] 1. A fifth source / drain electrode 131 is formed on the substrate 100;

[0144] 2. On the substrate 100, a third organic semiconductor 132 is embedded between the fifth source drain 131 and the sixth source drain 141 (i.e., the second source drain), and extends upward above the fifth source drain 131 and the sixth source drain 141. The portion above the fifth source drain 131 and the sixth source drain 141 extends a portion toward one side of the fifth source drain 131 and the sixth source drain 141, respectively.

[0145] 3. A third gate dielectric 133 is disposed on the third organic semiconductor 132;

[0146] 4. A third gate 134 is disposed on the third gate dielectric 133;

[0147] 5. An interlayer dielectric 150 is provided, in which the fifth source / drain 131, the sixth source / drain 141, the third organic semiconductor 132, the third gate dielectric 133, and the third gate 134 are all encapsulated;

[0148] 6. A third gate via 163 is provided in the interlayer dielectric 150 above the third gate 134. A third gate contact electrode 203 is provided in the third gate via 163. One end of the third gate contact electrode 203 is connected to the third gate 134, and the other end extends to the upper surface of the interlayer dielectric 150. A portion extends around the upper surface of the interlayer dielectric 150, and the extended portion connects with the fourth source-drain electrode 142 of the second switching transistor structure 102.

[0149] In an exemplary embodiment of this application, in the actual process flow, the first switching transistor A1, the second switching transistor A2, and the sensing transistor A3 are uniformly arranged and can be sequentially arranged from bottom to top as follows:

[0150] 1. Configure the first source-drain 111, the second source-drain 141, the fifth source-drain 131, the fourth source-drain 142, and the third source-drain 121;

[0151] 2. A first organic semiconductor 112, a third organic semiconductor 132, and a second organic semiconductor 122 are provided;

[0152] 3. Set the first gate medium 113, the third gate medium 133, and the second gate medium 123;

[0153] 4. Set the first gate medium 113, the third gate medium 133, and the second gate medium 123;

[0154] 5. Set the first gate 114, the third gate 134, and the second gate 124;

[0155] 6. Set the interlayer medium to 150;

[0156] 7. Provide a first gate via 161, a third gate via 163, and a second gate via 162;

[0157] 8. Set a first gate contact electrode 201, a third gate contact electrode 203, and a second gate contact electrode 202.

[0158] In an exemplary embodiment of this application, an encapsulation layer 210 and a reference electrode 204 are provided, wherein the encapsulation layer 210 is disposed above the interlayer medium 150; and the reference electrode 204 is disposed on the upper surface of the interlayer medium 150.

[0159] The first gate contact electrode 201 of the first switching transistor structure 101, the second gate contact electrode 202 of the second switching transistor structure 102, the third gate contact electrode 203 of the sensing transistor structure 103, and the reference electrode 204 are all embedded in the encapsulation layer 210.

[0160] In an exemplary embodiment of this application, a working electrode via 301 is provided in the encapsulation layer 210 above the third gate contact electrode 203, and a reference electrode via 302 is provided in the encapsulation layer 210 above the reference electrode 204.

[0161] A modification probe 310 is formed in the working electrode through hole 301, and the modification probe 310 is connected to the third gate contact electrode 203;

[0162] A reference functional film 320 is formed in the reference electrode through-hole 302, and the reference functional film 320 is connected to the reference electrode 204.

[0163] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A sensing pixel unit, characterized in that, include: First switching transistor, second switching transistor, sensing transistor, working electrode, and reference electrode; The first switching transistor serves as the on / off switch for the sensing transistor; The second switching transistor serves as a gate switch for the third gate of the sensing transistor; The first switching transistor includes: a first pin, a second pin, and a third pin; the third pin is the first gate. The second switching transistor includes a fourth pin, a fifth pin, and a sixth pin; the sixth pin is a second gate. The sensing transistor includes a seventh pin, an eighth pin, and a ninth pin; the ninth pin is the third gate; the third gate is in a floating state. The second pin is connected to the seventh pin, and the fourth pin is connected to the ninth pin; The first pin and the eighth pin are configured as readout signals; The third pin is configured to input the startup voltage of the first switching transistor; The sixth pin is configured to input the startup voltage of the second switching transistor; The fifth pin is configured as the input drive voltage; The working electrode is connected to the third gate and has a modification probe; The reference electrode is connected to the eighth pin.

2. A sensing pixel array, characterized in that, include: The sensing pixel unit as described in claim 1; Sensor signal readout circuit; Row selection circuit; Drive circuit; The first pin of the first switching transistor is connected to the sensing signal readout circuit; The eighth pin of the sensing transistor is connected to the sensing signal readout circuit. The fifth pin of the second switching transistor is connected to the driving circuit; The third pin of the first switching transistor is connected to the row selection circuit; The sixth pin of the second switching transistor is connected to the row selection circuit; The reference electrode is connected to the sensing signal readout circuit.

3. A sensing pixel structure, characterized in that, The structure of the sensing pixel unit according to claim 1 includes: a first switching transistor structure, a second switching transistor structure, and a sensing transistor structure; The first switching transistor structure, the sensing transistor structure, and the second switching transistor structure are arranged sequentially in the horizontal direction.

4. The sensing pixel structure according to claim 3, characterized in that, It also includes the substrate; The first switching transistor structure, the sensing transistor structure, and the second switching transistor structure are all disposed on the substrate; The first switching transistor structure, the sensing transistor structure, and the second switching transistor structure are all embedded between the interlayer dielectric.

5. The sensing pixel structure according to claim 4, characterized in that, The first switching transistor structure includes: The first source and drain are disposed on the substrate; The second source / drain electrode is disposed on the substrate; A first organic semiconductor is disposed on the substrate, located between the first source drain and the second source drain, and extends upward above the first source drain and the second source drain. The portion above the first source drain and the second source drain extends a portion toward one side of the first source drain and the second source drain, respectively. A first gate dielectric is disposed above the first organic semiconductor; The first gate is disposed above the first gate dielectric; The first gate contact electrode is disposed in the first gate via in the interlayer medium, connected to the upper surface of the first gate, and extends to the upper surface of the interlayer medium, with a portion extending around the upper surface of the interlayer medium.

6. The sensing pixel structure according to claim 4, characterized in that, The second switching transistor structure includes: The third source / drain is disposed on the substrate; The fourth source / drain electrode is disposed on the substrate; A second organic semiconductor is disposed on the substrate, located between the third source drain and the fourth source drain, and extends upward above the third source drain and the fourth source drain. The portion above the third source drain and the fourth source drain extends a portion toward one side of the third source drain and the fourth source drain, respectively. A second gate dielectric is disposed above the second organic semiconductor; The second gate is disposed above the second gate dielectric; The second gate contact electrode is disposed in the second gate via in the interlayer medium, connected to the upper surface of the second gate, and extends to the upper surface of the interlayer medium, with a portion extending around the upper surface of the interlayer medium.

7. The sensing pixel structure according to claim 4, characterized in that, The sensing transistor structure includes: The fifth source / drain electrode is disposed on the substrate; The sixth source and drain are disposed on the substrate and share the same source and drain as the second source and drain of the first switching transistor structure. A third organic semiconductor is disposed on the substrate, located between the fifth source drain and the sixth source drain, and extends upward above the fifth source drain and the sixth source drain. The portion above the fifth source drain and the sixth source drain extends a portion toward one side of the fifth source drain and the sixth source drain, respectively. A third gate dielectric is disposed above the third organic semiconductor; The third gate is disposed above the third gate dielectric; The third gate contact electrode is disposed in the third gate via in the interlayer dielectric, connected to the upper surface of the third gate, and extends to the upper surface of the interlayer dielectric. A portion of the electrode extends around the upper surface of the interlayer dielectric, and the extended portion connects with the fourth source and drain of the second switching transistor structure.

8. The sensing pixel structure according to claim 4, characterized in that, Also includes: The encapsulation layer and the reference electrode, wherein the encapsulation layer is disposed above the interlayer dielectric; The reference electrode is disposed on the upper surface of the interlayer medium; The first gate contact electrode of the first switching transistor structure, the second gate contact electrode of the second switching transistor structure, the third gate contact electrode of the sensing transistor structure, and the reference electrode are all embedded in the encapsulation layer.

9. The sensing pixel structure according to claim 8, characterized in that, A working electrode via is provided in the encapsulation layer above the third gate contact electrode, and a reference electrode via is provided in the encapsulation layer above the reference electrode. A modification probe is formed in the working electrode via, and the modification probe is connected to the third gate contact electrode. A reference functional film is formed in the through-hole of the reference electrode, and the reference functional film is connected to the reference electrode.

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