A schottky diode and a method of manufacturing the same

Abstract

A Schottky diode and a manufacturing method thereof, the Schottky diode comprising a first metal layer, a semiconductor layer, a second metal layer, a passivation layer and a metal sidewall; the first metal layer is formed on a substrate, and the first metal layer is a high work function metal; the semiconductor layer is formed on the first metal layer, or the semiconductor layer is partially formed on the first metal layer and partially formed on the substrate; the metal sidewall is in contact with a sidewall of the semiconductor layer, the metal sidewall is a high work function metal, and a Schottky contact is formed between the metal sidewall and the semiconductor layer; the passivation layer covers the metal sidewall, the semiconductor layer and the first metal layer; an ohmic contact is formed between the second metal layer and the semiconductor layer, and the second metal layer is a low work function metal. By arranging the metal sidewall on the sidewall of the semiconductor layer, the sidewall of the semiconductor layer is depleted by the Schottky contact between the metal sidewall and the semiconductor layer, the edge electric field is weakened, and the leakage current under reverse voltage is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Schottky diode, in particular to a Schottky diode and a manufacturing method thereof. BACKGROUND

[0002] The existing Schottky diode can realize close ideal factor and high Schottky barrier, but has serious leakage when reverse voltage is applied, and the off-state current rises rapidly with the increase of reverse voltage, which also makes the device easy to be broken down. SUMMARY

[0003] The present application mainly solves the technical problem of reverse voltage leakage and breakdown of the existing Schottky diode.

[0004] According to the first aspect, a Schottky diode is provided in an embodiment, comprising: a first metal layer, a semiconductor layer, a second metal layer, a passivation layer and a metal side wall;

[0005] The first metal layer is formed on the substrate, and the first metal layer is a high work function metal;

[0006] The semiconductor layer is formed on the first metal layer, or the semiconductor layer is partially formed on the first metal layer and partially formed on the substrate; the Schottky contact is formed between the semiconductor layer and the first metal layer;

[0007] The metal side wall is in contact with the sidewall of the semiconductor layer, the metal side wall is a high work function metal, and the Schottky contact is formed between the metal side wall and the semiconductor layer;

[0008] The passivation layer covers the metal side wall, the semiconductor layer and the first metal layer;

[0009] The second metal layer penetrates the passivation layer, the Ohmic contact is formed between the second metal layer and the semiconductor layer, and the second metal layer is a low work function metal.

[0010] According to the second aspect, a manufacturing method of a Schottky diode is provided in an embodiment, comprising:

[0011] Forming a first metal layer on the substrate, the first metal layer being a high work function metal;

[0012] Forming a semiconductor layer on the first metal layer, or on part of the first metal layer and the substrate;

[0013] Forming a metal side wall in contact with the sidewall of the semiconductor layer; the metal side wall is a high work function metal, and the Schottky contact is formed between the metal side wall and the semiconductor layer;

[0014] Forming a passivation layer covering the metal side wall, the semiconductor layer and the first metal layer, and performing a patterned treatment on the passivation layer to form a first window penetrating the passivation layer;

[0015] A second metal layer is formed on the first window, the second metal layer is in contact with the semiconductor layer and forms an ohmic contact, and the second metal layer is a low work function metal.

[0016] According to the Schottky diode and the manufacturing method thereof, by disposing the metal sidewall on the sidewall of the semiconductor layer, the sidewall of the semiconductor layer is depleted by the Schottky contact between the metal sidewall and the semiconductor layer, the edge electric field is weakened, and the leakage under reverse voltage is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 Fig. 1 is a schematic diagram of the structure of a prior art Schottky diode;

[0018] Figure 2 Fig. 2 is a schematic diagram of the electrical characteristic curves of the prior art Schottky diode under different defect states;

[0019] Figure 3 Fig. 3 is a schematic diagram of the structure of a Schottky diode according to an embodiment;

[0020] Figure 4 Fig. 4 is a schematic diagram of the structure of another Schottky diode according to an embodiment;

[0021] Figure 5 Fig. 5 is a schematic diagram of the electrical characteristic curves of the Schottky diode shown in Fig. 3; Figure 1 Fig. 6 is a schematic diagram of the electrical characteristic curves of the Schottky diode shown in Fig. 3 compared with the Schottky diode shown in Fig. 1 (I); Figure 3

[0022] Figure 6 Fig. 7 is a schematic diagram of the electrical characteristic curves of the Schottky diode shown in Fig. 4 compared with the Schottky diode shown in Fig. 1 (II); Figure 1 Figure 3

[0023] Figure 7 Fig. 8 is a schematic diagram of the structure of another Schottky diode according to an embodiment;

[0024] Figure 8 Fig. 9 is a schematic diagram of the structure of another Schottky diode according to an embodiment;

[0025] Figure 9 Fig. 10 is a schematic diagram of the structure of another Schottky diode according to an embodiment;

[0026] Figure 10 Fig. 11 is a flowchart of a manufacturing method of a Schottky diode according to an embodiment;

[0027] Figure 11 Fig. 12 is a schematic diagram of a process of a manufacturing method of a Schottky diode according to an embodiment (I);

[0028] Figure 12 ​​​Process diagram of the manufacturing method of the Schottky diode provided in one embodiment (two);

[0029] Figure 13 Process diagram of the manufacturing method of the Schottky diode provided in one embodiment (three);

[0030] Figure 14 Process diagram of the manufacturing method of the Schottky diode provided in one embodiment (four);

[0031] Figure 15 Process diagram of the manufacturing method of the Schottky diode provided in one embodiment (five);

[0032] Figure 16 Process diagram of the manufacturing method of the Schottky diode provided in one embodiment (six);

[0033] Figure 17 Process diagram of the manufacturing method of the Schottky diode provided in one embodiment (seven).

[0034] Fig. 1 is a process diagram of the manufacturing method of the Schottky diode provided in one embodiment (one); DETAILED DESCRIPTION

[0035] The application will be further described below in conjunction with the drawings. Like elements in different embodiments are denoted by like reference numerals. In the following embodiments, many details are described in order to provide a more thorough description of the application. However, it will be apparent to those skilled in the art that some features can be omitted, or replaced by other elements, materials, methods, etc. in different situations. In some cases, some operations related to the application are not shown or described in the specification in order to avoid the core of the application being obscured by too much description, and it is not necessary to describe these operations in detail for those skilled in the art based on the description in the specification and general knowledge in the art.

[0036] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. Meanwhile, the steps or actions in the method description can also be sequentially adjusted or changed in a manner that is apparent to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing one embodiment, and do not mean that the sequence is necessary, unless otherwise stated that a certain sequence must be followed.

[0037] The numbers of components in this paper, such as "first", "second", etc., are only used to distinguish the described objects, and have no technical meaning. Unless otherwise specified, "connection" and "coupling" in this application include direct and indirect connections (couplings).

[0038] As shown in Figure 1 The existing vertical structure Schottky diode can achieve an ideal factor close to 1 and a higher Schottky barrier, but when reverse voltage is applied, the Schottky diode will have a large leakage current, and even be broken down. Some existing Schottky diodes can reduce leakage by adding a guard ring or field plate structure. On the one hand, the material selection of the guard ring or field plate is difficult, and polycrystalline silicon is generally used. On the other hand, it increases the process complexity and makes the carrier transport mechanism complex, and the process temperature is generally relatively high. When the semiconductor layer 3 is N-type semiconductor, the field plate can use nickel oxide or P-type polycrystalline silicon, in which nickel oxide is unstable, and P-type polycrystalline silicon is generally used. The forming temperature of P-type polycrystalline silicon is higher than 350 degrees, which does not belong to the low-temperature process in the semiconductor field, and the polycrystalline silicon also needs to be doped to form a guard ring, which requires an additional process. The field plate needs to be set on the top of the passivation layer and needs to have a certain width along the left-right direction shown in the figure, which will increase the lateral size of the device, and the field plate generally needs to be used with a field limiting ring to obtain better electric field modulation effect. The field limiting ring needs to be formed by an additional process (ion implantation), which will also increase the volume of the device. It should be noted that the additional process refers to the process not involved in the conventional Schottky diode, such as deposition and doping of polycrystalline silicon, and specifically refers to the process type, which can also include different process parameters of the same type of process if necessary.

[0039] This application analyzes the forming process of the Schottky diode, as shown in Figure 1 The conventional Schottky diode forms a first metal layer 2, a semiconductor layer 3, a passivation layer 4 and a second metal layer 5 on a substrate 1 in sequence. This application believes that the semiconductor layer 3 needs to be patterned after being formed by using dry etching or wet etching, and the side wall 31 of the semiconductor layer 3 is formed under the condition of etching or ion bombardment. Therefore, the semiconductor layer 3 side wall 31 has a large number of defect states. This application believes that it is these defect states that cause the device to have a leakage current. Through further analysis, this application believes that a large number of electrons will tunnel into the semiconductor layer 3 through the defect states under the action of the electric field provided by the negative bias, causing serious leakage at the edge of the semiconductor layer 3 (corresponding to the position of the side wall 31).

[0040] As shown in Figure 2As shown, the application firstly adopts TCAD simulation, and the simulation is carried out for different defect states. It can be seen that the larger the defect state density (DOS) of the edge of the semiconductor layer 3 is, the larger the leakage current under negative voltage is, and the more obvious the upwarping is.

[0041] In the embodiment of the application, by increasing a metal side wall 6 on the side wall 31 of the semiconductor layer 3, a Schottky contact is formed between the metal side wall 6 and the side wall 31 of the semiconductor layer 3 to deplete the edge electric field of the semiconductor layer 3, and finally the technical effect of reducing the leakage current is achieved.

[0042] Embodiment one:

[0043] Please refer to Figure 3 and Figure 4 , the embodiment provides a Schottky diode, which can include a first metal layer 2, a semiconductor layer 3, a second metal layer 5, a passivation layer 4 and a metal side wall 6. The Schottky diode provided by the application can be a vertical structure Schottky diode as shown in Figure 3 , or can be a horizontal structure Schottky diode as shown in Figure 4 .

[0044] The first metal layer 2 is formed on the substrate 1, and the first metal layer 2 is a high work function metal. The substrate 1 can be a hard material such as silicon, silicon dioxide, etc.; or can be a flexible substrate such as plastic, paper, etc. Common high work function metals include platinum, palladium, gold or silver oxide. Common semiconductor layers 3, such as metal oxides, carbon nanotubes, perovskites, amorphous silicon or single crystal silicon, can all use the above metals. The thickness of the first metal layer 2 can be the same as or different from that of the semiconductor layer 3.

[0045] As shown in Figure 3 , the semiconductor layer 3 is formed on the first metal layer 2; or as shown in Figure 4 , the semiconductor layer 3 is partially formed on the first metal layer 2 and partially formed on the substrate 1; a Schottky contact is formed between the semiconductor layer 3 and the first metal layer 2. The semiconductor layer 3 can include at least one layer of semiconductor material layer arranged in a stack; the material of the semiconductor layer 3 can be metal oxide (such as gallium nitride, gallium arsenide, generally amorphous), single crystal silicon or amorphous silicon.

[0046] The metal side wall 6 is in contact with the side wall 31 of the semiconductor layer 3, and the metal side wall 6 corresponds to a high work function metal, and a Schottky contact is formed between the metal side wall 6 and the semiconductor layer 3. For example, the metal side wall 6 can adopt the same material as the first metal layer 2. The side wall 31 of the semiconductor layer 3 is formed by etching.

[0047] The passivation layer 4 covers the metal side wall 6, the semiconductor layer 3 and the first metal layer 2. The passivation layer 4 can adopt at least one insulating layer material, such as silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, etc.

[0048] The second metal layer 5 penetrates the passivation layer 4, and an ohmic contact is formed between the second metal layer 5 and the semiconductor layer 3. The second metal layer 5 is a low work function metal. The thickness of the second metal layer 5 can be the same as or different from that of the semiconductor layer 3.

[0049] As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 5 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 6 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 3 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 1 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 2 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 3 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 5 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. 5 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. 5 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3.

[0050] As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 6 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 3 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. -8 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. 2 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 1 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. -5 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. 2 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 3 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3.

[0051] As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3. Figure 3 As shown in FIG. 1, the semiconductor layer 3 is formed on the first metal layer 2, and the metal side wall 6 is formed on the sidewall 31 of the semiconductor layer 3.

[0052] In one embodiment, as shown in Figure 4 The semiconductor layer 3 is formed on the substrate 1 and part of the first metal layer 2, and the metal sidewall 6 is formed on one sidewall 31 of the semiconductor layer 3 close to the first metal layer 2; the second metal layer 5 is arranged on the semiconductor layer 3 away from the first metal layer 2.

[0053] In one embodiment, as shown in Figure 3 and 7 In the case of a vertical structure, as shown in the metal sidewall 6 can have an overlapping portion 61 in contact with the top surface of the semiconductor layer 3, and the metal sidewall 6 has a sidewall portion 62 in contact with the sidewall 31 of the semiconductor layer 3. The thickness of the overlapping portion 61 (the up-down direction shown in the figure) generally cannot be too thin, and is generally greater than or equal to 1 / 3 of the thickness of the semiconductor layer 3, for example, when the thickness of the semiconductor layer 3 is 60 nm, the thickness of the overlapping portion 61 is not less than 20 nm. The thickness of the sidewall portion 62 (the left-right direction shown in the figure) corresponds to not less than 20 nm.

[0054] In one embodiment, as shown in Figure 8 and 9 In the case of a vertical structure, as shown in the metal sidewall 6 can not have an overlapping portion 61 in contact with the top surface of the semiconductor layer 3, and the metal sidewall 6 only has a sidewall portion 62 in contact with the sidewall 31 of the semiconductor layer 3.

[0055] For example, the metal sidewall 6 with the overlapping portion 61 can have better edge electric field shielding effect when the Schottky diode is applied to a larger negative bias. Without the metal sidewall 6, a certain shielding effect of the edge electric field can also be achieved to reduce the leakage effect, but only when the negative bias is small, and the shielding effect will be weakened under a larger negative bias.

[0056] For example, as shown in Figure 7 and Figure 8 The sidewall portion 62 is arranged along the sidewall 31 of the semiconductor layer 3 and can not be in contact with the first metal layer 2; as shown in Figure 3 and Figure 9 The sidewall portion 62 can be arranged along the sidewall 31 of the semiconductor layer 3 and in contact with the first metal layer 2.

[0057] For example, when the sidewall is in contact with the first metal layer 2, the bias of the metal sidewall 6 is always at the same potential as the first metal layer 2, which can provide better edge electric field shielding effect.

[0058] Embodiment two:

[0059] Please refer to Figure 10 The embodiment provides a manufacturing method of a Schottky diode, and the Schottky diode prepared by the manufacturing scheme can be compatible with low-temperature process, and the method can comprise:

[0060] Step 1: As Figure 11 As shown, a first metal layer 2 is formed on the substrate 1, and the first metal layer 2 is a high work function metal.

[0061] For example, substrate 1 can be a rigid substrate or a flexible substrate. The rigid substrate 1 can be conventional single-crystal silicon, silicon dioxide, or SOI, while the flexible substrate can be plastic or paper. In this embodiment, the example of substrate 1 being plastic is used, such as a PET or PI substrate.

[0062] For example, the first metal layer 2 is palladium, which is formed by sputtering at room temperature and has a thickness of 60 nm.

[0063] Step 2: Form a semiconductor layer 3 on the first metal layer 2, or on a portion of the first metal layer 2 and the substrate 1; in this embodiment, the semiconductor layer 3 is described as a single-layer amorphous metal oxide. The use of an amorphous metal oxide is primarily for its low processing temperature, ensuring compatibility with low-temperature processes. If low-temperature requirements are not present, single-crystal silicon and other available semiconductor materials can also be used.

[0064] In this embodiment, a Schottky diode with a vertical structure is used as an example for illustration. Step 2 includes:

[0065] Step 201: As Figure 11 As shown, a semiconductor layer 3 is formed on the first metal layer 2, and the thickness of the semiconductor layer 3 can be 60 nm. For example, a sputtering process can be used, and the process temperature is room temperature.

[0066] Step 202: As Figure 12 As shown, the semiconductor layer 3 is patterned by wet etching, and the etched semiconductor layer 3 forms two sidewalls 31.

[0067] Step 3: Form a metal sidewall 6 that contacts the sidewall 31 of the semiconductor layer 3; the metal sidewall 6 is a high work function metal, and a Schottky contact is formed between the metal sidewall 6 and the semiconductor layer 3.

[0068] Correspondence formation Figure 3 When using the Schottky diode shown, step 3 may include:

[0069] Step 301: As Figure 13 As shown, a third metal layer 60 is formed covering the semiconductor layer 3 and the first metal layer 2. The material of the third metal layer 60 can be the same as that of the first metal layer 2. In this application, the material and molding process of the third metal layer 60 can be the same as those of the first metal layer 2, thereby saving the cost of different material molding processes and reducing process complexity. The thickness of the third metal layer 60 is not less than 20 nm.

[0070] Step 302: As shown, the third metal layer 60 is patterned to obtain the metal side wall 6. The third metal layer 60 can be etched by wet etching. Specifically, the third metal layer 60 is patterned to retain the portion of the third metal layer 60 on the top surface of the semiconductor layer 3 close to the side wall 31 of the semiconductor layer 3, thereby forming the overlapping portion 61 of the metal side wall 6; and retain the portion of the third metal layer 60 covering the side wall 31 of the semiconductor layer 3, thereby forming the side wall portion 62 of the metal side wall 6, which is in contact with the first metal layer 2. Figure 14

[0071] If it is required to form the structure as shown in Figure 7 or Figure 8 , specifically, the metal side wall 6 is not connected to the first metal layer 2, a passivation layer 4 is formed before the deposition of the third metal layer 60 to isolate the third metal layer 60 from the first metal layer 2. Figure 8 or Figure 9 , specifically, the metal side wall 6 does not have the overlapping portion 61 on the top surface of the semiconductor layer 3, the mask in step 302 needs to be changed to change the patterned shape.

[0072] Step 4: As shown, the passivation layer 4 covering the metal side wall 6, the semiconductor layer 3 and the first metal layer 2 is formed, and the passivation layer 4 is patterned to form the first window 41 penetrating through the passivation layer 4. The material of the passivation layer 4 can be silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide or other commonly used insulating materials, which can be a single layer structure or a laminated structure. In this application, the passivation layer 4 can be silicon dioxide or silicon nitride, for example, silicon dioxide, which can be formed by plasma enhanced chemical vapor deposition at a process temperature below 300°C. Figure 15

[0073] Step 5: As shown, the second metal layer 5 is formed on the first window 41, which is in contact with the semiconductor layer 3 and forms an ohmic contact, and the second metal layer 5 is a low work function metal. For example, the second metal layer 5 is molybdenum, titanium and indium tin oxide, which is formed by a room temperature sputtering process or a low temperature evaporation process (below 350°C) to a thickness of 60 nm. Figure 16 By the above manufacturing method, the vertical structure Schottky diode as shown in

[0074] and Figure 3 can be manufactured. If it is required to manufacture the horizontal structure Schottky diode as shown in Figure 17 , only the mask needs to be adjusted to adjust the patterned shape of each structure layer, and the specific forming process and process temperature can be referred to the corresponding process in each step above. Figure 4

[0075] ​​​It can be seen that each of the above process temperatures belongs to a low-temperature process (not more than 350 DEG C), and can be compatible with flexible technology, for example, a flexible diode manufactured on a flexible substrate, and can be applied to a flexible screen such as a curved screen or a folding screen. The existing technical solutions using a guard ring and a field plate all require a high-temperature process (more than 350 DEG C), and are not compatible with flexible technology. The metal side wall 6 is made of the same material as the first metal layer 2, and can be formed by using the same process, without introducing new processes and materials, thereby reducing manufacturing cost.

[0076] In summary, the metal side wall 6 can shield the Schottky contact of the semiconductor layer 3 edge difference, thereby greatly reducing the off-state current, ensuring that the off-state current is approximately constant under a larger reverse voltage, improving the breakdown voltage, and reducing the off-state current, thereby improving the application potential of the Schottky diode in the photoelectric direction. At the same time, the on-state current is more in line with the theoretical formula of thermionic emission, and the ideal factor and barrier height of the on-state are closer to the theoretical value. The electrical stress stability test and environmental stability of the structure are also better than those of the unimproved structure. Moreover, the process difficulty is low, and the compatibility is stronger than that of the traditional guard ring and other structures. Since the process temperature is lower than 350 DEG C throughout, the structure can be applied to a flexible substrate.

[0077] The above application of specific examples is used to illustrate the present application, and is only used to help understand the present application, and does not limit the present application. For those skilled in the art to which the present application belongs, according to the idea of the present application, a number of simple deductions, deformations or substitutions can be made.

Claims

1. A Schottky diode, characterized in that, include: The structure comprises a first metal layer (2), a semiconductor layer (3), a second metal layer (5), a passivation layer (4), and a metal sidewall (6); The first metal layer (2) is formed on the substrate (1), and the first metal layer (2) is a high work function metal; The semiconductor layer (3) is formed on the first metal layer (2), or the semiconductor layer (3) is partially formed on the first metal layer (2) and partially formed on the substrate (1); a Schottky contact is formed between the semiconductor layer (3) and the first metal layer (2); The metal sidewall (6) is in contact with the sidewall (31) of the semiconductor layer (3), the metal sidewall (6) is a high work function metal, and a Schottky contact is formed between the metal sidewall (6) and the semiconductor layer (3); The passivation layer (4) covers the metal sidewall (6), the semiconductor layer (3), and the first metal layer (2); The second metal layer (5) penetrates the passivation layer (4), and an ohmic contact is formed between the second metal layer (5) and the semiconductor layer (3). The second metal layer (5) is a low work function metal. The material of the metal sidewall (6) is the same as the material of the first metal layer (2).

2. The Schottky diode as described in claim 1, characterized in that, The Schottky diode is a vertically oriented Schottky diode; The semiconductor layer (3) is formed on the first metal layer (2), and the metal sidewalls (6) are symmetrically formed on the two sidewalls (31) of the semiconductor layer (3); The second metal layer (5) is centrally disposed on the semiconductor layer (3).

3. The Schottky diode as described in claim 1, characterized in that, The Schottky diode is a horizontally structured Schottky diode; The semiconductor layer (3) is formed on the substrate (1) and a portion of the first metal layer (2), and the metal sidewall (6) is formed on a sidewall (31) of the semiconductor layer (3) near the first metal layer (2); The second metal layer (5) is disposed on the semiconductor layer (3) away from the first metal layer (2).

4. The Schottky diode as described in any one of claims 1 to 3, characterized in that, The metal sidewall (6) has an overlap (61) that contacts the top surface of the semiconductor layer (3).

5. The Schottky diode as described in any one of claims 1 to 3, characterized in that, The metal sidewall (6) has a sidewall portion (62) that contacts the sidewall (31) of the semiconductor layer (3), the sidewall portion (62) being disposed along the sidewall (31) of the semiconductor layer (3) and in contact with the first metal layer (2).

6. The Schottky diode as described in any one of claims 1 to 3, characterized in that, The semiconductor layer (3) includes at least one stacked semiconductor material layer; And / or, the semiconductor layer (3) is made of metal oxide, single crystal silicon or amorphous silicon; the metal sidewall (6) is made of platinum, palladium or gold; And / or, the substrate (1) is a flexible substrate.

7. A method for manufacturing a Schottky diode, characterized in that, include: A first metal layer (2) is formed on a substrate (1), wherein the first metal layer (2) is a high work function metal; A semiconductor layer (3) is formed on the first metal layer (2), or on a portion of the first metal layer (2) and the substrate (1); A metal sidewall (6) is formed in contact with the sidewall (31) of the semiconductor layer (3); the metal sidewall (6) is a high work function metal, and a Schottky contact is formed between the metal sidewall (6) and the semiconductor layer (3); A passivation layer (4) is formed covering the metal sidewall (6), the semiconductor layer (3) and the first metal layer (2). The passivation layer (4) is patterned to form a first window (41), which penetrates the passivation layer (4). A second metal layer (5) is formed on the first window (41), the second metal layer (5) is in contact with the semiconductor layer (3) and forms an ohmic contact, and the second metal layer (5) is a low work function metal; The material of the metal sidewall (6) is the same as the material of the first metal layer (2).

8. The manufacturing method as described in claim 7, characterized in that, The semiconductor layer (3) is formed on the first metal layer (2); A metal sidewall (6) is formed in contact with the sidewall (31) of the semiconductor layer (3), comprising: A third metal layer (60) is formed covering the semiconductor layer (3) and the first metal layer (2), wherein the material of the third metal layer (60) is the same as that of the first metal layer (2); The third metal layer (60) is patterned to obtain the metal sidewall (6).

9. The manufacturing method as described in claim 8, characterized in that, The third metal layer (60) is patterned to obtain the metal sidewall (6), comprising: The third metal layer (60) is patterned, and a portion of the third metal layer (60) near the sidewall (31) of the semiconductor layer (3) is retained, and the overlapping portion (61) of the metal sidewall (6) is formed accordingly. The third metal layer (60) retains a portion of the sidewall (31) covering the semiconductor layer (3), and a corresponding sidewall portion (62) is formed of the metal sidewall (6), which is in contact with the first metal layer (2).

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