Power supply clamping circuit and chip

Abstract

The application provides a power supply clamping circuit and a chip. The power supply clamping circuit comprises a first PMOS tube, a source end of the first PMOS tube being connected with a power supply line, a gate end of the first PMOS tube being connected with a ground line; a capacitor, one end of the capacitor being connected with a drain end of the first PMOS tube, the other end of the capacitor being connected with the ground line; a second PMOS tube, a source end of the second PMOS tube being connected with the power supply line, a gate end of the second PMOS tube being connected with a drain end of the first PMOS tube; a first NMOS tube, a drain end of the first NMOS tube being connected with a drain end of the second PMOS tube, a gate end of the first NMOS tube being connected with a drain end of the first PMOS tube, a source end of the first NMOS tube being connected with the ground line; and a second NMOS tube, a drain end of the second NMOS tube being connected with the power supply line, a gate end of the second NMOS tube being connected with a drain end of the second PMOS tube, a source end of the second NMOS tube being connected with the ground line.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip circuit design technical field, and particularly to a power clamp circuit and a chip. BACKGROUND

[0002] With the development of integrated circuit technology, the integration of devices on a single chip is becoming higher and higher, which makes the requirement of the chip on the electrical overstress (EOS) protection is increasing. The EOS of integrated circuits is usually caused by the discharge of a large voltage on the pins of the chip by an external source in a very short time, so this discharge phenomenon can easily damage the chip without EOS protection design. Specifically, EOS events can be divided into two categories, the first category is the nanosecond level fast transient discharge event, such as electrostatic discharge (ESD), and the second category is the micro-millisecond level slow transient discharge event, such as surge. Therefore, when designing the EOS protection circuit, both electrostatic discharge protection and surge protection need to be considered. SUMMARY

[0003] The present application provides a power clamp circuit and a chip, which can enhance the surge protection capability.

[0004] In one aspect, the present application provides a power clamp circuit, comprising: a driving sub-circuit and a discharge sub-circuit, wherein,

[0005] The driving sub-circuit comprises:

[0006] A first PMOS tube, the source end of the first PMOS tube is connected with a power supply line, and the gate end of the first PMOS tube is connected with a ground line;

[0007] A capacitor, one end of the capacitor is connected with the drain end of the first PMOS tube, and the other end of the capacitor is connected with the ground line;

[0008] A second PMOS tube, the source end of the second PMOS tube is connected with the power supply line, and the gate end of the second PMOS tube is connected with the drain end of the first PMOS tube;

[0009] A first NMOS tube, the drain end of the first NMOS tube is connected with the drain end of the second PMOS tube, the gate end of the first NMOS tube is connected with the drain end of the first PMOS tube, and the source end of the first NMOS tube is connected with the ground line;

[0010] The discharge sub-circuit comprises:

[0011] A second NMOS tube, the drain end of the second NMOS tube is connected with the power supply line, the gate end of the second NMOS tube is connected with the drain end of the second PMOS tube, and the source end of the second NMOS tube is connected with the ground line.

[0012] Optionally, the driving sub-circuit further comprises:

[0013] a third NMOS tube, a drain end of the third NMOS tube is connected with a drain end of the first PMOS tube, a gate end and a source end of the third NMOS tube are connected with a ground wire;

[0014] a resistor, one end of the resistor is connected with a drain end of the second PMOS tube, and the other end of the resistor is connected with the ground wire.

[0015] Optionally, if a 5-volt NMOS is selected, a primary breakdown voltage of the third NMOS tube is not more than 10 volts, when a surge voltage is greater than the primary breakdown voltage of the third NMOS tube, the third NMOS tube is suddenly returned, so that the second NMOS tube is turned on to discharge the surge current.

[0016] Optionally, a resistance of the resistor satisfies: when the second PMOS tube is turned on, a voltage on the resistor is greater than a threshold voltage of the second NMOS tube, so that the second NMOS tube is turned on.

[0017] Optionally, the second NMOS tube is a large-size NMOS tube, and a width size of the second NMOS tube is greater than 500 microns.

[0018] In another aspect, the application provides a chip, the chip comprising the power clamp circuit.

[0019] The power clamp circuit provided by the embodiment of the application can keep the transistor of the discharge sub-circuit turned on when the electrostatic discharge and the surge occur, discharge the electrostatic discharge current and the surge current, and thus protect the chip. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 FIG. 1 is a circuit structure schematic diagram of a power clamp circuit according to an embodiment of the application;

[0021] Figure 2 FIG. 2 is a circuit structure schematic diagram of a power clamp circuit according to another embodiment of the application;

[0022] Figure 3 FIG. 3 is a schematic diagram of a sudden return characteristic of an NMOS tube;

[0023] Figure 4 FIG. 4 is a comparison schematic diagram of anti-surge abilities of various protection schemes;

[0024] Figure 5 FIG. 5 is a comparison schematic diagram of leakage conditions of two power clamp circuits according to embodiments of the application. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0026] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0027] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] The embodiments of the present application provide a power clamp circuit for chip electro-overshoot (EOS) protection, as shown in the figure, the power clamp circuit comprises: Figure 1

[0029] The driving sub-circuit comprises a first PMOS tube PM2, a capacitor C1, a second PMOS tube PM1 and a first NMOS tube NM1, the source end of PM2 is connected with a power supply line VDD, the gate end of PM2 is connected with a ground line GND, one end of C1 is connected with the drain end of PM2, and the other end of C1 is connected with the ground line GND. The source end of PM1 is connected with the power supply line VDD, the gate end of PM1 is connected with the drain end of PM2, the drain end of NM1 is connected with the drain end of PM1, the gate end of NM1 is connected with the drain end of PM2, and the source end of NM1 is connected with the ground line GND.

[0030] The discharge sub-circuit comprises a second NMOS tube NM2, the drain end of NM2 is connected with the power supply line VDD, the gate end of NM2 is connected with the drain end of PM1, and the source end of NM2 is connected with the ground line GND.

[0031] ​In the embodiment, the first PMOS transistor PM2 functions as a resistor, and PM2 and the capacitor C1 form an RC circuit. The resistor of the RC delay circuit is a PMOS transistor for saving layout area. The second NMOS transistor NM2 functions as a discharge of ESD current and surge current, and NM2 needs to be a large-size NMOS transistor, for example, the width size can be greater than 500 microns.

[0032] When the nanosecond-level ESD comes, VDD is high, and because the RC circuit has a delay charging characteristic, initially, the gate end of PM1 is low, PM1 is turned on, the gate end of NM2 is high, NM2 is turned on, and thus NM2 discharges the ESD current. Therefore, the power clamp circuit provided by the embodiment of the application can effectively protect against ESD.

[0033] However, because the surge is a micro-millisecond-level overvoltage phenomenon, its duration is generally longer than the RC charging time in the prior art, and at this time, the capacitor C1 has been charged, the gate end of NM1 is high, NM1 is turned on, and the gate end of NM2 is low, so that NM2 cannot be effectively turned on during the surge, and it is difficult to reduce the surge voltage on the power line. Therefore, the power clamp circuit shown in the prior art has less-than-ideal effect in protecting against surges. Figure 1 Figure 1

[0034] In order to better solve the surge protection problem, another embodiment of the application provides a power clamp circuit, as shown in the accompanying drawings, which is compared with the power clamp circuit shown in the prior art. Figure 2 Figure 1 The driving sub-circuit part of the power clamp circuit is increased with a third NMOS transistor NM3 and a resistor R1. NM3 is a grounded-gate NMOS (GGNMOS), the drain end of NM3 is connected with the drain end of PM2, and the gate end and the source end of NM3 are connected with the ground wire GND. One end of the resistor R1 is connected with the drain end of PM1, and the other end is connected with the ground wire GND.

[0035] Figure 2 The power clamp circuit shown in the embodiment can enhance the surge protection capability of the circuit and improve the surge protection voltage without affecting the ESD protection. The specific analysis is as follows.

[0036] ​​​When a nanosecond-level ESD occurs, VDD is high, and due to the delay charging characteristics of the RC circuit composed of PM2 and C1, before the RC charging is completed, the gate of PM1 is low, PM1 is on, the gate of NM2 is high, and NM2 is on, so that NM2 discharges the ESD current. It is worth noting that although the resistance R1 is additionally added, by properly adjusting the resistance ratio of PM1 and R1, it can still be ensured that when PM1 is normally turned on, the voltage on the resistance R1 is greater than the threshold voltage of the second NMOS tube NM2, and the gate of NM2 is high. Then wait until the RC charging is completed, the gate of PM1 is high, PM1 is off, NM1 is on, the gate of NM2 is low, and NM2 is off, completing the clamping of the power supply potential. During the entire period of discharging the ESD current, since the gate of NM3 is always grounded and the power supply voltage is clamped, the drain voltage Vd of NM3 is always not higher than the primary breakdown voltage V t1 of the device, so that NM3 does not snapback and is always off, and the existence of NM3 has little effect on ESD discharge. The snapback mentioned here refers to the following situation: taking NMOS as an example, when the gate and source are connected to a low voltage, and the drain voltage is high to a certain extent, the drain and source of NMOS will be conductive, and will exhibit negative resistance characteristics, and then the drain voltage will be clamped to a lower potential. Figure 3 A schematic diagram of the snapback characteristics of the NMOS tube. As Figure 3 shown, when the drain voltage Vd of the NMOS reaches the primary breakdown voltage V t1 of the device, the NMOS snaps back, and the drain voltage Vd is clamped to a lower potential V hold In this embodiment, if the power line VDD is 5V, the third NMOS tube NM3 can be selected as a 5-volt NMOS, and the primary breakdown voltage of the third NMOS tube NM3 can be 10 volts (for a 152-nanometer 5-volt NMOS of TSMC).

[0037] When a micro-millisecond-level surge occurs, VDD is high, and the RC circuit delay charging effect can be ignored, and the gate of PM1 follows the voltage of VDD in real time. When the surge voltage is lower than the primary breakdown voltage V t1 of NM3, the gate of PM1 is high, PM1 is off, NM1 is on, the gate of NM2 is low, and NM2 is off. However, as the surge voltage increases to V t1 , NM3 snaps back and clamps the drain voltage of NM3 to a lower potential V hold , at which time the gate of PM1 is low, PM1 is on, the gate of NM2 is high, and NM2 is on to discharge the surge current. And because NM3 has a clamping effect when it snaps back, this also makes the gate oxide of PM1 and NM1 not easy to be broken down during the surge.

[0038] In addition, it should be noted that,Figure 1 In the absence of NM3, the power clamping circuit can directly cause NM2 to undergo a quick return during a surge, discharging a certain current to suppress high voltage. However, this type of discharge has two main drawbacks: firstly, NM2 is often a high-voltage transistor, and secondly, the voltage V required for the quick return is high. t1 Firstly, the voltage is too high. Secondly, NM2 is a large-size tube, and there is a problem with uniform conduction during the sudden return process. Therefore, relying solely on the sudden return of NM2 for surge protection is not very effective.

[0039] Figure 4 This article summarizes the test results of surge protection capabilities for four protection schemes using TSMC's 152nm process. For example... Figure 4 As shown, the horizontal axis represents the number of power clamping circuits, and 60normal indicates 60. Figure 1 The power clamping circuit shown, 40normal indicates 40 Figure 1 The power clamping circuit shown. 20normal+20ggnmos represents 20 Figure 1 The power clamping circuit shown and 20 Figure 2 The power clamping circuit shown, 15normal+15ggnmos represents 15... Figure 1 The power clamping circuit shown and 15 Figure 2 The power clamping circuits shown are evenly distributed throughout the power supply loop. The vertical axis represents surge voltage resistance.

[0040] As can be seen, for those using only 40 and 60... Figure 1 For the chip with surge protection provided by the power clamping circuit shown, the maximum surge voltages it can withstand are 14 volts and 15 volts, respectively. Although the latter has 50% more power clamping circuits than the former, the surge protection capability is not significantly improved. This is mainly due to the non-uniform conduction of the large-size transistor NM2.

[0041] Next, when 40 Figure 1 The 20 in the power clamping circuit shown are replaced with Figure 2 After implementing the power clamping circuit of the GGNMOS architecture, it can be found that the surge voltage of the chip can be rapidly increased to 23 volts, and the surge resistance is significantly enhanced, with an increase of 64%.

[0042] Furthermore, when the number of the two power clamping circuits is reduced to 15 each, the chip can still withstand a 22-volt surge voltage.

[0043] In summary, the power clamping circuit provided in this embodiment of the invention adds an NM3 with its gate grounded in the driving sub-circuit. By utilizing the quick-return characteristic of NM3, the NM2 of the discharge sub-circuit is turned on to discharge surge current. This circuit has both ESD protection and surge protection capabilities, enhancing the surge protection capability between the chip's power line and ground line.

[0044] In addition to the above anti-surge ability of the reinforcement, Figure 2 The power supply clamping circuit also solves the problem of leakage when the power supply is normally powered. Figure 2 The resistor R1 connected to the NM2 gate end and GND can effectively reduce the leakage current through the discharge sub-circuit when the power supply is normally powered. The main source of leakage of the power supply clamping circuit during power-on is the large current passing through the low-resistance path formed after the large-size discharge tube NM2 is mistakenly turned on, so here the switching condition of NM2 during normal power-on is mainly analyzed. Figure 5 The simulation results of NM2 leakage under TSMC 152nm process conditions are shown. The simulation tool used here is Cadence Spectre. Figure 5 (a) of shows the voltage change at the gate end of NM2 during normal power-on, and the power-on time of the simulation is set to 30 microseconds, as shown by the solid line. V1 represents Figure 2 The voltage change at the gate end of NM2 in the power supply clamping circuit is shown, V2 represents Figure 1 The voltage change at the gate end of NM2 in the power supply clamping circuit is shown. It can be seen that during normal power-on, the highest potential of V1 is not higher than 0.8 volts, while the highest potential of V2 can reach 2.3 volts, which is far beyond the threshold voltage of NM2.

[0045] Figure 5 (b) of shows the leakage current change during normal power-on, I1 represents Figure 2 The leakage current change in the power supply clamping circuit is shown, I2 represents Figure 1 The leakage current change in the power supply clamping circuit is shown. It can be seen that during power-on, I2 can reach 55mA, while I1 is always below 1mA, and the leakage suppression ability is obvious.

[0046] On the other hand, the embodiment of the present application also provides a chip, which comprises the power supply clamping circuit provided by the above-mentioned embodiment.

[0047] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any changes or replacements within the technical range disclosed by the present application can be easily thought of by those skilled in the art, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A power clamping circuit, characterized in that, include: The driver sub-circuit and the discharge sub-circuit, wherein, The driving sub-circuit includes: The first PMOS transistor has its source terminal connected to the power supply line and its gate terminal connected to the ground line. A capacitor, one end of which is connected to the drain terminal of the first PMOS transistor, and the other end of which is connected to ground. The second PMOS transistor has its source connected to the power supply line and its gate connected to the drain of the first PMOS transistor. The first NMOS transistor has its drain connected to the drain of the second PMOS transistor, its gate connected to the drain of the first PMOS transistor, and its source connected to ground. And, a third NMOS transistor, the drain of which is connected to the drain of the first PMOS transistor, and the gate and source of which are connected to ground. A resistor, one end of which is connected to the drain of the second PMOS transistor, and the other end of which is connected to ground. The discharge sub-circuit includes: The second NMOS transistor has its drain connected to the power supply line, its gate connected to the drain of the second PMOS transistor, and its source connected to the ground line.

2. The power clamping circuit according to claim 1, characterized in that, If a 5V NMOS is selected, the first breakdown voltage of the third NMOS transistor does not exceed 10V. When the surge voltage is greater than the first breakdown voltage of the third NMOS transistor, the third NMOS transistor will undergo a sudden return, causing the second NMOS transistor to conduct and discharge the surge current.

3. The power clamping circuit according to claim 1, characterized in that, The resistance value satisfies the following condition: when the second PMOS transistor is turned on, the voltage across the resistor is greater than the threshold voltage of the second NMOS transistor, causing the second NMOS transistor to turn on.

4. The power clamping circuit according to claim 1, characterized in that, The second NMOS transistor is a large-size NMOS transistor with a width greater than 500 micrometers.

5. A chip, characterized in that, The chip includes a power clamping circuit as described in any one of claims 1-4.

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