A high-speed W transformation method, secure hash algorithm and electronic device

Abstract

The present invention discloses a high-speed W transformation method, a secure hash algorithm, and an electronic device. The high-speed W transformation method utilizes high- and low-bit decomposition and pipeline operations, converting 64-bit additions into 32-bit additions and performing the operations in steps. Multiple pipelines operate in parallel, significantly improving the efficiency of the W transformation. Furthermore, the design of the high-speed W transformation method shortens the circuit operation path, simplifies the required hardware circuitry, and thus enables higher frequency operation, enhancing the circuit's data processing performance.

Description

Technical Field

[0001] The present invention relates to the field of data security, and in particular to a high-speed W transformation method, a secure hash algorithm, and an electronic device. Background Art

[0002] The Secure Hash Algorithm (SHA) is a family of cryptographic hash functions. It is a FIPS-certified secure hash algorithm that can calculate the fixed-length string (also known as a message digest) corresponding to a digital message. If the input messages are different, the probability of the corresponding strings being different is high.

[0003] SHA was designed by the U.S. National Institute of Standards and Technology (NIST) and published in 1993 as SHA-0. Security vulnerabilities were soon discovered, leading to the release of SHA-1 in 1995. In 2002, NIST released SHA-256, SHA-384, and SHA-512, collectively known as SHA-2. In 2008, SHA-224 was added. As SHA-1 became less secure, various SHA-2 versions have become the mainstream.

[0004] SHA512 is currently the most commonly used hash algorithm, but its operational efficiency is low, primarily due to two factors: the W transform method and the hash wheel transform method. Existing technologies for the W transform method require complex hardware circuits with long operational paths, resulting in low efficiency. However, high-performance security gateways currently need to provide clients with a variety of services, including data provenance verification, data integrity verification, and data encryption. These services require support for high-speed cryptographic computation. Clearly, the existing W transform method is no longer suitable and requires a redesign. Summary of the Invention

[0005] To address the above issues, the present invention provides a high-speed W transformation method, a secure hash algorithm, and an electronic device, which greatly improve the efficiency of W transformation. The specific technical solutions of the present invention are as follows:

[0006] A high-speed W transformation method is applied to a secure hash algorithm. The method specifically comprises the following steps: step S1, performing high- and low-bit disassembly on known data used for W transformation, and then performing low-bit operations and high-bit operations; step S2, respectively disassembling the low-bit operations and the high-bit operations into several addition operations, and then performing pipeline operations, and finally merging the results of the low-bit operations and the high-bit operations to obtain a complete W transformation result; wherein the low-bit operations and the high-bit operations are performed in parallel.

[0007] Furthermore, the secure hash algorithm is the SHA512 algorithm.

[0008] Furthermore, the W transformation method of the SHA512 algorithm is as follows:

[0009]

[0010] Among them, W t (0≤t≤79) is 64-bit data; M t (0≤t≤15) is the known data used for W transformation, with a size of 64 bits; EP0 and EP1 are W transformation functions.

[0011] Furthermore, the specific calculation process of EP0 and EP1 is as follows:

[0012] EP0(x)=(x<<<1)^(x<<<8)^(x>>7),

[0013] EP1(x)=(x<<<19)^(x<<<61)^(x>>6),

[0014] Among them, x is known data, <<< represents a circular left shift operation, ^ represents an exclusive OR operation, and >> represents a right shift operation.

[0015] Furthermore, in step S1, the specific method of performing high-low bit separation on the known data used for W transformation includes: taking the known data M used for W transformation t The data on the lower 32 bits of (0≤t≤15) is stored in the low register and the known data M used for W transformation is obtained. t The data on the upper 32 bits of (0≤t≤15) is stored in the high-order register; wherein, the number of the low-order registers is 16, each of which can store 32-bit data, and the number of the high-order registers is 16, each of which can store 32-bit data.

[0016] Furthermore, in step S2, the specific method of decomposing the low-order operation into several addition operations includes: step S21, based on the W transformation function, calculating W t `[31:0]=EP0(W t-15 )[31:0]+W t-16 [31:0], and generate the first carry W of 1 bit at the same time t `_c, recorded as the first stage pipeline, then enter step S22; step S22, calculate W t ``[31:0]=W t `[31:0]+W t-7 [31:0], and generate the second carry W of 1 bit at the same timet ``_c, recorded as the second stage pipeline, then enter step S23; step S23, calculate W t [31:0]=W t ``[31:0]+EP1(W t-2 )[31:0], and generate the 1-bit third carry W at the same time t _c, recorded as the third-level pipeline.

[0017] Furthermore, in step S2, the specific method of decomposing the high-order operation into several addition operations includes: step S24, based on the W transformation function, calculating W t `[63:32]=EP0(W t-15 )[63:32]+W t-16 [63:32], recorded as the first stage pipeline, then enter step S25; step S25, calculate W t ``[63:32]=W t `[63:32]+W t-7 [63:32]+W t `_c, recorded as the second stage pipeline, then enter step S26; step S26, calculate W t ```[63:32]=W t ``[63:32]+EP1(W t-2 )[63:32]+W t ``_c, recorded as the third stage pipeline, then enter step S27; step S27, calculate W t [63:32]=W t ```[63:32]+W t _c, recorded as the fourth stage pipeline.

[0018] Furthermore, in step S2, after the low-order operation is disassembled into several addition operations, the specific method of performing pipeline operation includes: step S31, when t=1, based on the data in the low-order register of the previous clock cycle, calculate W 16 Low 32-bit first-stage pipeline W 16 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 16 The first carry W 16 `[31:0]_c; Step S32, when t=2, calculate W based on the data in the low-order register of the previous clock cycle 16 Low 32-bit second-stage pipeline W 16``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 17 Low 32-bit first-stage pipeline W 17 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 16 The second carry W 16 ``[31:0]_c and W 17 The first carry W 17 `[31:0]_c; Step S33, when t=3, calculate W based on the data in the low-order register of the previous clock cycle 16 Low 32-bit third-stage pipeline W 16 [31:0], and store it in the fourteenth low register, and at the same time, calculate W 17 Low 32-bit second-stage pipeline W 17 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 18 Low 32-bit first-stage pipeline W 18 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 16 The third carry W 16 [31:0]_c、W 17 The second carry W 17 ``[31:0]_c and W 18 The first carry W 18 `[31:0]_c; Step S34, when t=4, calculate W based on the data in the low-order register of the previous clock cycle 17 Low 32-bit third-stage pipeline W 17 [31:0], and store it in the fourteenth low register, and at the same time, calculate W 18 Low 32-bit second-stage pipeline W 18 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 19 Low 32-bit first-stage pipeline W 19 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 17 The third carry W 17 [31:0]_c、W 18The second carry W 18 ``[31:0]_c and W 19 The first carry W 19 `[31:0]_c; Step S35, when t=5, calculate W based on the data in the low-order register of the previous clock cycle 18 Low 32-bit third-stage pipeline W 18 [31:0], and store it in the fourteenth low register, and at the same time, calculate W 19 Low 32-bit second-stage pipeline W 19 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 20 Low 32-bit first-stage pipeline W 20 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 18 The third carry W 18 [31:0]_c、W 19 The second carry W 19 ``[31:0]_c and W 20 The first carry W 20 `[31:0]_c; Step S36, and so on, based on the data in the low register of the previous clock cycle, the third pipeline, the second pipeline and the first pipeline of the current clock cycle are calculated in parallel until W is obtained 79 Low 32-bit third-stage pipeline W 79 [31:0] and W 79 The third carry W 79 [31:0]_c.

[0019] Furthermore, in step S2, after the high-order operation is decomposed into several addition operations, the specific method of performing pipeline operation includes: step S41, when t=1, based on the data in the high-order register of the previous clock cycle, calculate W 16 High 32bit first stage pipeline W 16 `[63:32], and store it in the sixteenth high register, then shift the data in the high register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline and the third-stage pipeline left by 32 bits; step S42, when t=2, calculate W based on the data in the high register of the previous clock cycle 16 High 32bit second stage pipeline W 16 ``[63:32], and store it in the fifteenth high register, at the same time, calculate W 17 High 32bit first stage pipeline W17 `[63:32], and store it in the sixteenth high register, then shift the data in the high register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline and the third-stage pipeline left by 32 bits; step S43, when t=3, calculate W based on the data in the high register of the previous clock cycle 16 High 32-bit third-stage pipeline W 16 ```[63:32], and store it in the fourteenth high register, at the same time, calculate W 17 High 32bit second stage pipeline W 17 ``[63:32], and store it in the fifteenth high register, and at the same time, calculate W 18 High 32bit first stage pipeline W 18 `[63:32], and store it in the sixteenth high register, then shift the data in the high register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline and the third-stage pipeline left by 32 bits; step S44, when t=4, calculate W based on the data in the high register of the previous clock cycle 16 High 32-bit fourth-stage pipeline W 16 [63:32], and store it in the 13th high register, and at the same time, calculate W 17 High 32-bit third-stage pipeline W 17 ```[63:32], and store it in the fourteenth high register, at the same time, calculate W 18 High 32bit second stage pipeline W 18 ``[63:32], and store it in the fifteenth high register, and at the same time, calculate W 19 High 32bit first stage pipeline W 19 `[63:32], and store it in the sixteenth high register, then shift the data in the high register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline and the third-stage pipeline left by 32 bits; step S45, when t=5, calculate W based on the data in the high register of the previous clock cycle 17 High 32-bit fourth-stage pipeline W 17 [63:32], and store it in the 13th high register, and at the same time, calculate W 18 High 32-bit third-stage pipeline W 18 ```[63:32], and store it in the fourteenth high register, at the same time, calculate W 19 High 32bit second stage pipeline W 19 ``[63:32], and store it in the fifteenth high register, and at the same time, calculate W 20High 32bit first stage pipeline W 20 `[63:32], and store it in the sixteenth high register, then shift the data in the high register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline and the third-stage pipeline left by 32 bits; step S46, and so on, based on the data in the high register of the previous clock cycle, parallelly calculate the fourth-stage pipeline, the third pipeline, the second pipeline and the first pipeline of the current clock cycle until W is obtained 79 High 32-bit fourth-stage pipeline W 79 [63:32].

[0020] A secure hash algorithm includes the high-speed W transformation method. The secure hash algorithm performs a secure hash operation on a W transformation result calculated by the high-speed W transformation method to obtain a secure hash value.

[0021] Furthermore, the secure hash algorithm performs a hash operation based on the W transformation result calculated by the high-speed W transformation method to obtain a secure hash value. Specifically, the method includes: when t=0, merging the data in the first low-order register and the first high-order register of the current clock cycle, and then using them for the secure hash operation; whenever t increases by 1, the data in the low-order register except the first-stage pipeline and the second-stage pipeline are shifted left by 32 bits, and the data in the high-order register except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline are shifted left by 32 bits, so that in each clock cycle, the data in the first low-order register and the first high-order register are the data required for the subsequent secure hash operation after being merged; wherein the low-order register is used to store the known data M t (0≤t≤15) The data on the lower 32 bits and the corresponding W transformation results, the high register is used to store the known data M t (0≤t≤15) The data on the upper 32 bits and the corresponding W transformation result; wherein the W transformation method includes low-bit operations and high-bit operations, and the low-bit operations and high-bit operations run in parallel; wherein the low-bit operations include the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline, and the high-bit operations include the first-stage pipeline, the second-stage pipeline, the third-stage pipeline, and the fourth-stage pipeline.

[0022] An electronic device runs the secure hash algorithm, so that the electronic device can achieve high-speed confidential data transmission.

[0023] The present invention offers the following advantages: Compared to existing technologies, the high-speed W transform method described herein significantly improves W transform efficiency by utilizing high- and low-bit decomposition and pipeline operations. Specifically, it converts 64-bit additions into 32-bit additions and performs these operations in steps, while simultaneously running multiple pipelines in parallel. Furthermore, the design of this high-speed W transform method shortens the circuit operation path, simplifies the required hardware circuitry, and thus enables higher frequency operation, enhancing the circuit's data processing performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of a flow chart of a high-speed W conversion method according to an embodiment of the present invention.

[0025] Figure 2 This is a partial pipeline operation process in the low-bit operation described in an embodiment of the present invention.

[0026] Figure 3 This is a partial pipeline operation process in high-bit operations described in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0028] It should be understood that when used in this application, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their collections. It should also be understood that the term "and / or" used in this application refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0029] As used in this application, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0030] In addition, in the description of the present application, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance. References to "one embodiment" or "some embodiments" etc. described in the specification of the present application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0031] SHA512 is a commonly used hash algorithm, but its operational efficiency is low, primarily due to two factors: the W transform method and the hash wheel transform method. Existing technologies for implementing the W transform method require complex hardware circuits with long operational paths, resulting in low efficiency. However, high-performance security gateways currently need to provide clients with a variety of services, including data provenance verification, data integrity verification, and data encryption. These services require support for high-speed cryptographic computation. Clearly, the existing W transform method is no longer suitable and requires a redesign.

[0032] In order to solve the above problems, the embodiment of the present invention provides a high-speed W conversion method, which greatly improves the operating efficiency of W conversion. Figure 1 As shown, the method specifically includes the following steps:

[0033] Step S1, separating the known data used for W transformation into high and low bits, and then performing low-bit operations and high-bit operations;

[0034] In step S2, the low-order operation and the high-order operation are respectively decomposed into several addition operations, and then pipelined, and finally the results of the low-order operation and the high-order operation are merged to obtain a complete W transformation result; wherein the low-order operation and the high-order operation are run in parallel.

[0035] It's important to note that the W transform processes the input data to be authenticated by a hash algorithm (also known as a hash algorithm) into a format suitable for the hash round transformation. Simply put, it formats the input data into the format required by the algorithm. The overall processing flow of a hash algorithm is as follows: input data -> padding -> W transform -> HASH transform -> HASH result. This article focuses on improvements to the W transform method.

[0036] As one of the preferred implementations, the secure hash algorithm is the SHA512 algorithm. The W transformation method of the SHA512 algorithm is as follows:

[0037]

[0038] Among them, W t (0≤t≤79) is 64-bit data; M t (0≤t≤15) is the known data or padded data used for W transformation, with a size of 64 bits; EP0 and EP1 are W transformation functions. The specific calculation process of EP0 and EP1 is as follows:

[0039] EP0(x)=(x<<<1)^(x<<<8)^(x>>7),

[0040] EP1(x)=(x<<<19)^(x<<<61)^(x>>6),

[0041] Among them, x is known data, <<< represents a circular left shift operation, ^ represents an exclusive OR operation, and >> represents a right shift operation.

[0042] In the process of executing step S1, the specific method of performing high and low bit separation of the known data used for W transformation includes: taking the known data M used for W transformation t The data on the lower 32 bits of (0≤t≤15) is stored in the low register and the known data M used for W transformation is obtained. t The data on the upper 32 bits of (0≤t≤15) is stored in the high-order register; there are 16 low-order registers, each of which can store 32 bits of data, and there are 16 high-order registers, each of which can store 32 bits of data. Separating the high and low-order data for calculation cuts the difficulty of each calculation in half, greatly improving efficiency.

[0043] Specifically, refer to Figure 2 as well as Figure 3 The low-order registers include the first low-order register w0_l_reg, the second low-order register w1_l_reg, ..., and so on, until the sixteenth low-order register w15_l_reg, and at t=0, W0[31:0] to W 15 [31:0]. Similarly, the high registers include the first high register w0_h_reg, the second high register w1_h_reg, ..., the sixteenth high register w15_h_reg, and at t=0, W0[63:32] to W 15 [63:32].

[0044] In the process of executing step S2, the specific method of decomposing the low-order operation into several addition operations includes: step S21, based on the W transformation function, calculating W t `[31:0]=EP0(W t-15 )[31:0]+W t-16 [31:0], and generate the first carry W of 1 bit at the same time t `_c, recorded as the first stage pipeline, then enter step S22; step S22, calculate W t ``[31:0]=W t `[31:0]+W t-7 [31:0], and generate the second carry W of 1 bit at the same time t ``_c, recorded as the second stage pipeline, then enter step S23; step S23, calculate W t [31:0]=W t ``[31:0]+EP1(W t-2 )[31:0], and generate the 1-bit third carry W at the same time t _c, recorded as the third-level pipeline.

[0045] As shown in the above steps S21 to S23, the low-order operation is decomposed into a number of addition operations, that is, the W transformation function EP1 (W t-2 )+W t-7 +EP0(W t-15 )+W t-16 The three addition operations in the algorithm are divided into three-stage pipelines for calculation, which reduces the computational complexity of each calculation and improves the computational efficiency.

[0046] In the process of executing step S2, the specific method of decomposing the high-order operation into several addition operations includes: step S24, based on the W transformation function, calculating W t `[63:32]=EP0(W t-15 )[63:32]+W t-16 [63:32], recorded as the first stage pipeline, then enter step S25; step S25, calculate W t ``[63:32]=W t `[63:32]+W t-7 [63:32]+W t `_c, recorded as the second stage pipeline, then enter step S26; step S26, calculate W t ```[63:32]=W t ``[63:32]+EP1(W t-2 )[63:32]+W t``_c, recorded as the third stage pipeline, then enter step S27; step S27, calculate W t [63:32]=W t ```[63:32]+W t _c, recorded as the fourth stage pipeline.

[0047] As shown in the above steps S24 to S27, the low-order operation is decomposed into a number of addition operations, that is, the W transformation function EP1 (W t-2 )+W t-7 +EP0(W t-15 )+W t-16 The three addition operations plus one carry calculation are divided into a four-stage pipeline for calculation, which reduces the computational complexity of each calculation and improves the computational efficiency.

[0048] Reference Figure 2 In step S2, after the low-order operation is decomposed into several addition operations, the specific method of performing pipeline operation includes:

[0049] Step S31, when t=1, based on the data in the low-order register of the previous clock cycle, that is, the known data M t (0≤t≤15), calculate W 16 Low 32-bit first-stage pipeline W 16 `[31:0], and store it in the sixteenth low register. According to the W transformation function and the calculation rules of the first-level pipeline, W 16 `[31:0]=EP0(W1)[31:0]+W0[31:0], at this time, W1[31:0] and W0[31:0] are distributed and stored in the second low-order register w1_l_reg and the first low-order register w0_l_reg, so the sixteenth low-order register w15_l_reg=W 16 `[31:0]=EP0(w1_l_reg)+w0_l_reg. Then the data in the low register of the previous clock cycle except the first and second stage pipelines are shifted left by 32 bits. In the calculation process, W is also generated 16 The first carry W 16 `[31:0]_c, used for the second-level pipeline calculation participating in high-order operations.

[0050] Step S32, when t=2, based on the data in the low-order register of the previous clock cycle, that is, the known data M t (1≤t≤15) and W 16 `[31:0], calculate W 16 Low 32-bit second-stage pipeline W 16``[31:0], and store it in the fifteenth low register. According to the W transformation function and the calculation rules of the second-stage pipeline, W 16 ``[31:0]=W 16 `[31:0]+W9[31:0], at this time W9[31:0] is stored in the seventh low register w8_l_reg (because it is shifted left once), so the fifteenth low register w14_l_reg=W 16 ``[31:0]=w15_l_reg+w8_l_reg. At the same time, in the current clock cycle, W is also calculated 17 Low 32-bit first-stage pipeline W 17 `[31:0], and store it in the sixteenth low register. The calculation process is the same as that of calculating W 16 The process of `[31:0] is the same and will not be repeated here. Then the data in the low register of the previous clock cycle except the first and second stage pipelines are shifted left by 32 bits. In the calculation process, W is also generated. 16 The second carry W 16 ``[31:0]_c and W 17 The first carry W 17 `[31:0]_c. It should be noted that at t=2, W 16 The lower 32-bit second-stage pipeline and W 17 The low 32-bit first-stage pipeline performs simultaneous calculations, which improves the computing efficiency.

[0051] Step S33, when t=3, based on the data in the low-order register of the previous clock cycle, that is, the known data M t (2≤t≤15), W 16 ``[31:0] and W 17 `[31:0], calculate W 16 Low 32-bit third-stage pipeline W 16 [31:0] and store it in the fourteenth low register. According to the W conversion function and the calculation rules of the second-stage pipeline, W 16 [31:0]=W 16 ``[31:0]+EP1(W 14 )[31:0], at this time W 14 [31:0] is stored in the eleventh low-order register w12_l_reg, so the fourteenth low-order register w13_l_reg=W 16 [31:0]=w14_1_reg+w12_1_reg, so far, W 16 The lower 32 bits of W transformation calculation are completed. At the same time, calculate W 17 Low 32-bit second-stage pipeline W17 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 18 Low 32-bit first-stage pipeline W 18 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits. In the calculation process, W is also generated 16 The third carry W 16 [31:0]_c、W 17 The second carry W 17 ``[31:0]_c and W 18 The first carry W 18 `[31:0]_c. It should be noted that at t=3, W 16 Low 32-bit third-stage pipeline, W 17 The lower 32-bit second-stage pipeline and W 18 The low 32-bit first-stage pipeline performs simultaneous calculations, which improves the computing efficiency.

[0052] Step S34, when t=4, calculate W based on the data in the low-order register of the previous clock cycle 17 Low 32-bit third-stage pipeline W 17 [31:0], and store it in the fourteenth low register, and at the same time, calculate W 18 Low 32-bit second-stage pipeline W 18 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 19 Low 32-bit first-stage pipeline W 19 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 17 The third carry W 17 [31:0]_c、W 18 The second carry W 18 ``[31:0]_c and W 19 The first carry W 19 `[31:0]_c. Similarly, the pipelines of three different data are calculated simultaneously, which improves the calculation efficiency. I will not go into details later.

[0053] Step S35, when t=5, calculate W based on the data in the low-order register of the previous clock cycle 18 Low 32-bit third-stage pipeline W 18[31:0], and store it in the fourteenth low register, and at the same time, calculate W 19 Low 32-bit second-stage pipeline W 19 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 20 Low 32-bit first-stage pipeline W 20 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 18 The third carry W 18 [31:0]_c、W 19 The second carry W 19 ``[31:0]_c and W 20 The first carry W 20 `[31:0]_c.

[0054] Step S36, and so on, based on the data in the low-order register of the previous clock cycle, the third pipeline, the second pipeline and the first pipeline of the current clock cycle are calculated in parallel until W is obtained. 79 Low 32-bit third-stage pipeline W 79 [31:0] and W 79 The third carry W 79 [31:0]_c. It should be noted that when t=64, the calculation of W 79 The first stage pipeline of the lower 32 bits calculates W at t=65. 79 The second stage pipeline of the lower 32 bits only needs to calculate W according to the formula of W transformation. 79 , so there will be no new first-stage pipeline calculation at this time. At t=66, calculate W 79 The third stage pipeline of the lower 32 bits, at this point, the low-bit calculation is completed.

[0055] Reference Figure 2 In step S2, after the high-order operation is decomposed into several addition operations, the specific method of performing pipeline operation includes:

[0056] Step S41, when t=1, calculate W based on the data in the high-order register of the previous clock cycle 16 High 32bit first stage pipeline W 16 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits;

[0057] Step S42: When t=2, calculate W based on the data in the high-order register of the previous clock cycle. 16 High 32bit second stage pipeline W 16 ``[63:32], and store it in the fifteenth high register, at the same time, calculate W 17 High 32bit first stage pipeline W 17 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits;

[0058] Step S43, when t=3, calculate W based on the data in the high-order register of the previous clock cycle 16 High 32-bit third-stage pipeline W 16 ```[63:32], and store it in the fourteenth high register, at the same time, calculate W 17 High 32bit second stage pipeline W 17 ``[63:32], and store it in the fifteenth high register, and at the same time, calculate W 18 High 32bit first stage pipeline W 18 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits;

[0059] Step S44, when t=4, calculate W based on the data in the high-order register of the previous clock cycle 16 High 32-bit fourth-stage pipeline W 16 [63:32], and store it in the thirteenth high register. So far, W 16 The high 32bit W transformation is completed, which also means the complete W 16 [63:0] W transformation is completed. At the same time, calculate W 17 High 32-bit third-stage pipeline W 17 ```[63:32], and store it in the fourteenth high register, at the same time, calculate W 18 High 32bit second stage pipeline W 18 ``[63:32], and store it in the fifteenth high register, and at the same time, calculate W 19 High 32bit first stage pipeline W 19 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits;

[0060] Step S45, when t=5, calculate W based on the data in the high register of the previous clock cycle 17 High 32-bit fourth-stage pipeline W 17 [63:32], and store it in the 13th high register, and at the same time, calculate W 18 High 32-bit third-stage pipeline W 18 ```[63:32], and store it in the fourteenth high register, at the same time, calculate W 19 High 32-bit second-stage pipeline W 19 ``[63:32], and store it in the fifteenth high register, and at the same time, calculate W 20 High 32bit first stage pipeline W 20 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits;

[0061] Step S46, and so on, based on the data in the high register of the previous clock cycle, the fourth pipeline, the third pipeline, the second pipeline and the first pipeline of the current clock cycle are calculated in parallel until W is obtained. 79 High 32-bit fourth-stage pipeline W 79 [63:32] It should be noted that at t=64, the calculation of W 79 The first stage pipeline of the upper 32 bits calculates W at t=65. 79 The second-stage pipeline of the high 32 bits only needs to calculate W according to the formula of W transformation. 79 , so there will be no new first-stage pipeline calculation at this time. At t=66, calculate W 79 The third stage pipeline of the upper 32 bits calculates W at t=67. 79 The fourth stage pipeline of the upper 32 bits, at this point, the high-bit calculation is completed.

[0062] Based on the calculation process of the above low-bit operation and high-bit operation, it can be seen that the high-bit operation consumes one more clock cycle than the low-bit operation. It should be emphasized that the low-bit operation and the high-bit operation are run in parallel, not calculating the low 32 bits first and then calculating the high 32 bits. For example, in step S31, the calculation of W 16 Low 32-bit first-stage pipeline W 16 `[31:0] and W calculated in step S41 16 High 32bit first stage pipeline W 16`[63:32] is carried out at the same time, and so on. In the fourth clock cycle, the complete W 16 The W transformation of [63:0] is fully completed. Compared with the existing technology, the high-speed W transformation method of the present invention greatly improves the efficiency of the W transformation by disassembling high and low bits and performing pipeline operations. Specifically, it converts 64-bit addition into 32-bit addition and performs the operation step by step. At the same time, multiple pipelines run in parallel.

[0063] An embodiment of the present invention further provides a secure hash algorithm that performs a secure hash operation based on the W transformation result calculated by the high-speed W transformation method to obtain a secure hash value. Specifically, the secure hash algorithm includes:

[0064] When t=0, the data in the first low-order register and the first high-order register of the current clock cycle are merged and then used for secure hash operation; whenever t increases by 1, the data in the low-order register except the first-stage pipeline and the second-stage pipeline are shifted left by 32 bits, and the data in the high-order register except the first-stage pipeline, the second-stage pipeline and the third-stage pipeline are shifted left by 32 bits, so that in each clock cycle, the data in the first low-order register and the first high-order register are the data required for subsequent secure hash operation after merging; wherein, the low-order register is used to store known data M t (0≤t≤15) The data on the lower 32 bits and the corresponding W transformation results, the high register is used to store the known data M t The data on the upper 32 bits of (0≤t≤15) and the corresponding W transformation result; wherein the W transformation method includes low-bit operations and high-bit operations, and the low-bit operations and high-bit operations are performed in parallel; wherein the low-bit operations include a first-stage pipeline, a second-stage pipeline, and a third-stage pipeline, and the high-bit operations include a first-stage pipeline, a second-stage pipeline, a third-stage pipeline, and a fourth-stage pipeline. Compared with the prior art, the secure hash algorithm optimizes the calculation process of the W transformation, thereby greatly improving the operating efficiency of the secure hash algorithm.

[0065] An embodiment of the present invention further provides an electronic device that runs the secure hash algorithm, enabling high-speed, secure data transmission. Compared to existing technologies, the W transformation method employed in the electronic device shortens the circuit operation path, simplifies the required hardware circuitry, and thus enables higher frequency operation, enhancing the circuit's data processing performance.

[0066] It should be understood that various parts of the present invention can be implemented using hardware, software, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having logic gate circuits for implementing logical functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc. References to memory, storage, databases, or other media used in the various embodiments provided herein may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable memory (PROM), electrically programmable memory (DPROM), electrically erasable programmable memory (DDPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory.

[0067] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The above embodiments merely represent several embodiments of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the concept of the present application, and these modifications and improvements are all within the scope of protection of the present application.

Claims

1. A high-speed W transformation method, applied to a secure hash algorithm, characterized in that: The method specifically comprises the following steps: Step S1, separating the known data used for W transformation into high and low bits, and then performing low-bit operations and high-bit operations; Step S2: Decompose the low-order operation and the high-order operation into several addition operations respectively, then perform pipeline operations, and finally merge the results of the low-order operation and the high-order operation to obtain a complete W transformation result; Among them, low-order operations and high-order operations are run in parallel; In step S2, the specific method of decomposing the low-order operation into several addition operations includes: Step S21, based on the W transformation function, calculate W t `[31:0]=EP0(W t-15 )[31:0]+W t-16 [31:0], and generate the first carry W of 1 bit at the same time t `_c, recorded as the first stage of the pipeline, and then enter step S22; Step S22, calculate W t ``[31:0]=W t `[31:0]+W t-7 [31:0], and generate the second carry W of 1 bit at the same time t ``_c, recorded as the second stage pipeline, and then enters step S23; Step S23, calculate W t [31:0]=W t ``[31:0]+EP1(W t-2 )[31:0], and generate the 1-bit third carry W at the same time t _c, recorded as the third-level pipeline.

2. A high-speed W conversion method according to claim 1, characterized in that: The secure hash algorithm is the SHA512 algorithm.

3. A high-speed W conversion method according to claim 2, characterized in that: The W transformation method of the SHA512 algorithm is as follows: Among them, W t (0≤t≤79) is 64-bit data; M t (0≤t≤15) is the known data used for W transformation, with a size of 64 bits; EP0 and EP1 are W transformation functions.

4. A high-speed W conversion method according to claim 3, characterized in that: The specific calculation process of EP0 and EP1 is as follows: EP0(x)=(x<<<1)^(x<<<8)^(x>>7), EP1(x)=(x<<<19)^(x<<<61)^(x>>6), Among them, x is known data, <<< represents a circular left shift operation, ^ represents an exclusive OR operation, and >> represents a right shift operation.

5. A high-speed W conversion method according to claim 3, characterized in that: In step S1, the specific method of performing high- and low-bit decomposition of the known data used for W transformation includes: Take the known data M for W transformation t The data on the lower 32 bits of (0≤t≤15) is stored in the low register. Take the known data M for W transformation t The data on the upper 32 bits of (0≤t≤15) is stored in the high register; There are 16 low-order registers, each of which can store 32-bit data. The number of the high-order registers is 16, and each high-order register can store 32-bit data.

6. A high-speed W conversion method according to claim 5, characterized in that: In step S2, the specific method of decomposing the high-order operation into several addition operations includes: Step S24, based on the W transformation function, calculate W t `[63:32]=EP0(W t-15 )[63:32]+W t-16 [63:32], recorded as the first stage pipeline, and then enters step S25; Step S25, calculate W t ``[63:32]=W t `[63:32]+W t-7 [63:32]+W t `_c, recorded as the second stage pipeline, and then enters step S26; Step S26, calculate W t ```[63:32]=W t ``[63:32]+EP1(W t-2 )[63:32]+W t ``_c, recorded as the third stage pipeline, and then enters step S27; Step S27, calculate W t [63:32]=W t ```[63:32]+W t _c, recorded as the fourth stage pipeline.

7. A high-speed W conversion method according to claim 6, characterized in that: In step S2, after the low-order operation is decomposed into several addition operations, the specific method of performing pipeline operation includes: Step S31, when t=1, calculate W based on the data in the low-order register of the previous clock cycle 16 Low 32-bit first-stage pipeline W 16 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 16 The first carry W 16 `[31:0]_c; Step S32: When t=2, calculate W based on the data in the low-order register of the previous clock cycle. 16 Low 32-bit second-stage pipeline W 16 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 17 Low 32-bit first-stage pipeline W 17 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 16 The second carry W 16 ``[31:0]_c and W 17 The first carry W 17 `[31:0]_c; Step S33, when t=3, calculate W based on the data in the low-order register of the previous clock cycle 16 Low 32-bit third-stage pipeline W 16 [31:0], and store it in the fourteenth low register, and at the same time, calculate W 17 Low 32-bit second-stage pipeline W 17 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 18 Low 32-bit first-stage pipeline W 18 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 16 The third carry W 16 [31:0]_c、W 17 The second carry W 17 ``[31:0]_c and W 18 The first carry W 18 `[31:0]_c; Step S34, when t=4, calculate W based on the data in the low-order register of the previous clock cycle 17 Low 32-bit third-stage pipeline W 17 [31:0], and store it in the fourteenth low register, and at the same time, calculate W 18 Low 32-bit second-stage pipeline W 18 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 19 Low 32-bit first-stage pipeline W 19 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 17 The third carry W 17 [31:0]_c、W 18 The second carry W 18 ``[31:0]_c and W 19 The first carry W 19 `[31:0]_c; Step S35, when t=5, calculate W based on the data in the low-order register of the previous clock cycle 18 Low 32-bit third-stage pipeline W 18 [31:0], and store it in the fourteenth low register, and at the same time, calculate W 19 Low 32-bit second-stage pipeline W 19 ``[31:0], and store it in the fifteenth low register, and at the same time, calculate W 20 Low 32-bit first-stage pipeline W 20 `[31:0], and store it in the sixteenth low register, and then shift the data in the low register of the previous clock cycle except the first and second stage pipelines left by 32 bits; in the calculation process, W is also generated 18 The third carry W 18 [31:0]_c、W 19 The second carry W 19 ``[31:0]_c and W 20 The first carry W 20 `[31:0]_c; Step S36, and so on, based on the data in the low-order register of the previous clock cycle, the third pipeline, the second pipeline and the first pipeline of the current clock cycle are calculated in parallel until W is obtained. 79 Low 32-bit third-stage pipeline W 79 [31:0] and W 79 The third carry W 79 [31:0]_c.

8. A high-speed W conversion method according to claim 7, characterized in that: In step S2, after the high-order operation is decomposed into several addition operations, the specific method of performing pipeline operation includes: Step S41, when t=1, calculate W based on the data in the high-order register of the previous clock cycle 16 High 32bit first stage pipeline W 16 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits; Step S42: When t=2, calculate W based on the data in the high-order register of the previous clock cycle. 16 High 32-bit second-stage pipeline W 16 ``[63:32], and store it in the fifteenth high register, at the same time, calculate W 17 High 32bit first stage pipeline W 17 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits; Step S43, when t=3, calculate W based on the data in the high-order register of the previous clock cycle 16 High 32-bit third-stage pipeline W 16 ```[63:32], and store it in the fourteenth high register, at the same time, calculate W 17 High 32-bit second-stage pipeline W 17 ``[63:32], and store it in the fifteenth high register, and at the same time, calculate W 18 High 32bit first stage pipeline W 18 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits; Step S44, when t=4, calculate W based on the data in the high-order register of the previous clock cycle 16 High 32-bit fourth-stage pipeline W 16 [63:32], and store it in the 13th high register, and at the same time, calculate W 17 High 32-bit third-stage pipeline W 17 ```[63:32], and store it in the fourteenth high register, at the same time, calculate W 18 High 32-bit second-stage pipeline W 18 ``[63:32], and store it in the fifteenth high register, and at the same time, calculate W 19 High 32bit first stage pipeline W 19 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits; Step S45, when t=5, calculate W based on the data in the high register of the previous clock cycle 17 High 32-bit fourth-stage pipeline W 17 [63:32], and store it in the 13th high register, and at the same time, calculate W 18 High 32-bit third-stage pipeline W 18 ```[63:32], and store it in the fourteenth high register, at the same time, calculate W 19 High 32-bit second-stage pipeline W 19 ``[63:32], and store it in the fifteenth high register, and at the same time, calculate W 20 High 32bit first stage pipeline W 20 `[63:32], and store it in the sixteenth high-order register, and then shift the data in the high-order register of the previous clock cycle except the first-stage pipeline, the second-stage pipeline, and the third-stage pipeline left by 32 bits; Step S46, and so on, based on the data in the high register of the previous clock cycle, the fourth pipeline, the third pipeline, the second pipeline and the first pipeline of the current clock cycle are calculated in parallel until W is obtained. 79 High 32-bit fourth-stage pipeline W 79 [63:32].

9. A method for implementing a secure hash algorithm, characterized in that: The implementation method includes the high-speed W transformation method according to any one of claims 1 to 8, and the implementation method performs a secure hash operation on the W transformation result calculated by the high-speed W transformation method to obtain a secure hash value.

10. The implementation method according to claim 9, characterized in that: The implementation method performs a hash operation on the W transformation result calculated by the high-speed W transformation method to obtain a secure hash value, specifically comprising: When t=0, the data in the first low-order register and the first high-order register of the current clock cycle are merged and then used for the secure hash operation. Whenever t increases by 1, the data in the low-order register except the first and second pipeline stages are shifted left by 32 bits, and the data in the high-order register except the first, second, and third pipeline stages are shifted left by 32 bits. In this way, in each clock cycle, the data in the first low-order register and the first high-order register, after being merged, are the data required for the subsequent secure hash operation. Among them, the low register is used to store known data M t (0≤t≤15) The data on the lower 32 bits and the corresponding W transformation results, the high register is used to store the known data M t (0≤t≤15) The data on the upper 32 bits and the corresponding W transformation result; The W transformation method includes low-order operations and high-order operations, and the low-order operations and high-order operations are run in parallel; Among them, low-order operations include the first-level pipeline, the second-level pipeline and the third-level pipeline, and high-order operations include the first-level pipeline, the second-level pipeline, the third-level pipeline and the fourth-level pipeline.

11. An electronic device, characterized in that: The electronic device runs the implementation method described in any one of claims 9 to 10, so that the electronic device can achieve high-speed and confidential data transmission.

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