boosted back-porch voltage

Abstract

The dynamic memory array of a DRAM device operates using at least two voltages. A first voltage is the operating (i.e., switching) voltage of most of the digital logic circuitry of the DRAM device, which is used to power sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write). A second voltage is greater than the operating (i.e., switching) voltage of most of the digital logic circuitry of the DRAM device, which determines the voltage written to the capacitor of a DRAM cell (i.e., the bit line voltage). The digital logic circuitry operates using a supply voltage, which is lower than the voltage written to the capacitor of the DRAM array. This allows lower voltage swing digital logic to be used for most of the logic on the DRAM device, while a larger voltage is written to the DRAM cell.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0001] Figure 1 is a block diagram illustrating a dynamic random access memory (DRAM) system according to one embodiment.

[0002] Figure 2 is a diagram illustrating an example boost readback sense amplifier.

[0003] Figure 3 is a diagram illustrating elements of an offset compensated boost readback sense amplifier.

[0004] Figures 4A-4C is a diagram illustrating a boost readback operation.

[0005] Figure 5 is a diagram illustrating a boost voltage write operation.

[0006] Figure 6 is a flowchart diagram illustrating a boost readback method.

[0007] Figure 7 is a flowchart diagram illustrating a boost write method.

[0008] Figure 8 is a method of operating a memory device.

[0009] Figure 9 is a method of adjusting a readback voltage.

[0010] Figure 10 is a block diagram of a processing system. DETAILED DESCRIPTION

[0011] Reducing power consumption of electronic devices and computer systems is an ongoing goal. As such, reducing power consumption of dynamic random access memory (DRAM) devices is part of this effort. A major factor contributing to DRAM device power consumption is associated with the formula P = CV 2 f, where P is power consumption, C is capacitance, V is switching voltage, and f is switching frequency. As such, reducing switching voltage has a significant impact on reducing power consumption since voltage is squared in the above formula.

[0012] In one embodiment, the dynamic memory array(s) of the DRAM device operate using at least two voltages. A first voltage is the operating (i.e., switching) voltage of most of the digital logic circuitry of the DRAM device, the first voltage is used to power sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write). A second voltage that determines the voltage (i.e., bit line voltage) written to the capacitors of the DRAM cells is greater than the operating (i.e., switching) voltage of most of the digital logic circuitry of the DRAM device. In other words, the digital logic circuitry operates using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for most of the logic on the DRAM device, while writing a larger voltage to the DRAM cells for retention time purposes. The lower voltage swing used by most of the logic reduces the power consumption of the sense amplifiers of the DRAM array and other digital logic of the DRAM, which in turn reduces the power consumption of the overall DRAM device.

[0013] Figure 1 is a block diagram illustrating a dynamic random access memory (DRAM) system according to one embodiment. In Figure 1 the memory system 100 includes a DRAM memory device 110 and a controller 180. The controller 180 and the memory device 110 are integrated circuit type devices, such as are commonly referred to as “chips.” A memory controller such as the controller 180 manages the flow of data to and from a memory device. The memory controller can be a separate, independent chip, or can be integrated into another chip. For example, the memory controller can be included on a single die with a microprocessor, or included as part of a more complex integrated circuit system, such as a block of a system on a chip (SOC).

[0014] The controller 180 includes a physical interface 185. The physical interface 185 includes a command / address (CA) interface 181 and a bidirectional data (DQ) interface 182. The memory device 110 includes physical interface circuitry 175. The physical interface circuitry 175 includes a command / address (CA) interface 171 and a bidirectional data (DQ) interface 172. The command / address interface 181 of the controller 180 is operably coupled to the CA interface 171 of the memory device 110 to send commands and addresses to the memory device 110. The controller 180 is operably coupled to the memory device 110 via the bidirectional data interface 182. The controller 180 is operably coupled to the memory device 110 to communicate data with the memory device 110. The memory device 110 transfers data via the bidirectional data interface 172.

[0015] In Figure 1In particular embodiments, DRAM memory device 110 includes a plurality of memory banks / sub-banks, control circuitry 160, and interface circuitry 175. DRAM memory device 110 can be, on, or include at least one integrated circuit. A DRAM memory bank includes a sub-array (e.g., sub-array 128), a sense amplifier strip (e.g., sense amplifier strip 135), a column decoder 140, and word line control circuitry 150. Sense amplifier strip 135 includes a sense amplifier (e.g., sense amplifier 130) and a local-global switch (e.g., local-global switch 127). A sub-array includes memory bit cells (e.g., cell 123). Memory bit cell 123 is connected to a word line 122, a bit line 121, and a column select line 124. Sense amplifier 130 is connected to bit line 121 and a local data line 125. Local-global switch 127 is connected to local data line 125 and a global data line 126.

[0016] Control circuitry 160 is operatively coupled to the DRAM memory banks to at least process column addresses, row addresses, and / or commands received via CA interface 171. Control circuitry 160 includes digital logic circuitry that operates in a normal mode of operation using a selected (e.g., selected by a manufacturer of DRAM memory device 110) digital logic supply voltage (also referred to as VDD). Control circuitry 160 can include a majority of the circuitry in the circuitry using complementary metal-oxide-semiconductor (CMOS) type logic gates. Control circuitry 160 can include circuitry implemented using CMOS logic implemented in a high-K / metal gate (HKMG) CMOS fabrication process. The range of signal swing (i.e., between logic ‘1’ and logic ‘0’) for a full-swing CMOS logic gate can range from a minimum value corresponding to a negative supply / reference / substrate voltage to a maximum voltage corresponding to the digital logic supply voltage.

[0017] In one embodiment, in a normal mode of operation (i.e., not a test mode), DRAM memory device 110 (and in particular, sense amplifier 130) senses the state of a memory bit cell (e.g., cell 123) using the digital logic supply and / or maximum signal swing level of a majority of the digital logic on DRAM memory device 110 (relative to the same negative supply / reference / substrate voltage referenced by the bit line voltage).

[0018] However, when writing data to a memory bitcell (e.g., cell 123), the DRAM device (and in particular, sense amplifier 130) can charge the bitline to a voltage (i.e., a maximum voltage relative to a negative supply / reference / substrate voltage) that is higher than the digital logic supply and / or maximum signal swing level of most digital logic on the DRAM memory device 110 (relative to the same negative supply / reference / substrate voltage to which the bitline voltage is referenced). In particular, during write and readback operations, bitline 121 can be charged using a maximum voltage that is greater than control circuitry 160. For brevity, this boosted bitline voltage can be referred to herein as VBLHI.

[0019] Normal operation (non-test) mode includes an intended mode of operation of DRAM memory device 110 in memory system 100 used in non-production and non-test environments. For example, DRAM memory device 110 can be tested or otherwise operated in one or more test modes before being included in a larger system (e.g., a complete computer system, consumer electronic device, etc.). These test modes can be used during various manufacturing processes and / or stages, and are typically not used when the system is in use by an end user (e.g., a consumer, a data center, etc.).

[0020] For example, sometimes, such as during burn-in, test modes can be used to ‘stress’ DRAM device 110 to confirm functionality and / or reliability of DRAM device 110. Also, during testing, the digital logic supply voltage can be lowered below the boosted bitline voltage to confirm functionality and / or reliability of DRAM memory device 110. However, test modes are typically not used during ‘normal’ operation, as functionality, performance, longevity, and / or reliability of DRAM device 110 can degrade when operated in one or more test modes (as opposed to ‘normal’ operation mode).

[0021] In a normal mode of operation, the sense amplifier strips 135 and the sense amplifiers therein (e.g., sense amplifier 130) can operate using a selected (e.g., selected by the manufacturer) boosted bit line voltage (and / or bit line voltage range). In the normal mode of operation, the word line control circuitry 150 can operate using a digital logic supply voltage and / or a separate program supply voltage (VPP) that can be present to support word line voltage requirements that are compatible with the boosted bit line voltage. In the normal mode of operation, the column decoders 140 can operate using a digital logic supply voltage. In the normal mode of operation, the control circuitry (and included data path circuitry) 160 can operate using a digital logic supply voltage. In the normal mode of operation, the interface circuitry 175 can operate using an input / output (I / O) supply voltage and / or a digital logic supply voltage.

[0022] In one embodiment, the control circuitry 160, column decoders 140, and row decoders 150 collectively process at least column addresses and row addresses to retrieve data stored in at least the subarray 128. The control circuitry 160, column decoders 140, and row decoders 150 operate using a digital logic supply voltage. During sensing operations and column operations, the sense amplifiers 130 also operate using the digital logic supply voltage. During a write back operation, the sense amplifiers 130 also operate using a boosted bit line voltage that is greater than the first digital logic supply voltage. The control circuitry 160, column decoders 140, and / or row decoders 150 can be implemented using a high-k metal gate process.

[0023] The sense amplifiers 130 include a pair of cross-coupled inverters configured as a bistable flip-flop coupled to a respective bit line of a dynamic memory array. The cross-coupled inverters each have a negative supply node and a positive supply node. During a write back operation, a boosted bit line voltage can be selectively coupled to the positive supply node of the cross-coupled inverters. This causes the sense amplifier circuit to charge the cells 123 of the array to the boosted bit line voltage, rather than the digital logic supply voltage. Increasing the voltage at which the cells 123 are charged increases the data retention time of the cells 123 compared to charging the cells 123 with the digital logic supply voltage.

[0024] In one embodiment, during a sense operation and a column operation, a digital logic supply voltage is selectively coupled to a positive supply node of the cross-coupled inverters. During a write-back operation, the digital logic supply voltage is selectively decoupled from the positive supply node of the cross-coupled inverters. In this manner, a drive conflict between the digital logic supply voltage and the boosted bit line voltage is avoided. In one embodiment, during a refresh operation, the boosted bit line voltage is selectively coupled to the positive supply node of the cross-coupled inverters. In particular, during a sense operation, the boosted bit line voltage is selectively coupled to the positive supply node of the cross-coupled inverters without first using the digital logic supply voltage for sensing. In this manner, the refresh operation can be completed without waiting for the cross-coupled inverters to reach a steady state using the digital logic supply voltage before beginning to charge the bit line with the boosted bit line voltage. This can allow the refresh operation to be completed in less time as compared to a separate (boosted) write-back operation following a separate sense operation.

[0025] In one embodiment, the boosted bit line voltage can be based on a command received from the controller 180. For example, the controller 180 can write a value to a register in the control circuitry 160 that sets the boosted bit line voltage. In another example, a command (e.g., refresh, write, etc.) can indicate the boosted bit line voltage (e.g., write with boost, refresh without boost, etc.). In another example, the controller 180 can use a combination of a register in the control circuitry 160 and a command that indicates the boosted bit line voltage to indicate the boosted bit line voltage. In one embodiment, the controller 180 can select the boosted bit line voltage based on a temperature of the memory device 110. In one embodiment, the controller can select the boosted bit line voltage based on a use of the sensed data. For example, if the controller 180 knows that the data will not be stored in the memory device 110 again, the controller 180 can indicate a “read without boost write back” command. The “read without boost write back” or “refresh without boost write back” command can select a bit line voltage for write back that is equal to the digital logic supply voltage. These commands can affect (e.g., reduce) a processing time of the command as compared to always using the boosted bit line voltage, thereby increasing a throughput of the memory device 110.

[0026] In one embodiment, the memory device 110 can select the boosted bit line voltage. The memory device 110 can select the boosted bit line voltage based on a temperature of the memory device 110. In one embodiment, the memory device 110 can select the boosted bit line voltage based on a temperature of the memory device 110 and one or more indicators (e.g., register values or commands) received from the controller 180. For example, the memory device 110 can select the boosted bit line voltage based on a temperature of the memory device 110 and a temperature and boosted bit line voltage coefficient indicator received from the controller 180.

[0027] Figure 2 is a diagram illustrating an example boosted back-write sense amplifier. Sense amplifier 200 can be part of DRAM memory device 110 and / or sense amplifier strip 135 (i.e., in particular, as sense amplifier 130). In Figure 2 , sense amplifier 200 includes functional blocks 210, 220, 225, 230, 240, 250, and 250. While illustrated in Figure 2 as part of one sense amplifier 200, functional blocks 220, 225, 230, 240, and 250 can be shared with multiple amplifier blocks 210 to form multiple sense amplifiers. Similarly, while illustrated in Figure 2 as proximate to amplifier block 210, functional blocks 220, 225, 230, 240, and 250 can be located at various locations within the DRAM array that are relatively far from amplifier block 210.

[0028] Sense amplifier 200 performs an evaluation of the voltage difference on true (BLt) and complement (BLc) bit lines. Sense amplifier 200 also performs a write and / or back-write of data to a memory cell (e.g., cell 123) by forcing (charging) the true bit line (BLt) and complement bit line (BLc) to a digital logic supply voltage (VDD) and / or a boosted bit line voltage (VBLHI).

[0029] Amplifier block 210 includes a cross-coupled inverter pair that is turned on by evaluation control block 220. The cross-coupled inverters of amplifier block 210 include n-channel field effect transistors (NFETs) 211 and 212, and p-channel field effect transistors (PFETs) 213 and 214. NFET 211 and PFET 214 form a first inverter that is cross-coupled to a second inverter formed using NFET 212 and PFET 214. The output of each inverter is provided to the input of the other inverter (i.e., cross-coupled). The negative and positive supplies to the inverters of amplifier block 210 are selectively provided by evaluation control block 220 and / or boosted bit line control block 225.

[0030] The supply voltages SAN and SAP to these inverters are selectively (switchably) provided to the amplifier block 210 by the evaluation control block 220. The supply voltage SAP is selectively (switchably) provided to the amplifier block 210 by the boosted bit line control block 225. The supply voltages SAN and SAP to these inverters are selectively (switchably) provided to the amplifier block 210 by the evaluation control block 220 in order to allow the internal nodes of the amplifier block 210 / external nodes to the amplifier block 210 (including the bit lines BLt and BLc, and the supply voltages SAN and SAP) to be equalized, and then activated to evaluate the voltages on the bit lines BLt and BLc. The supply voltage SAP is selectively (switchably) provided to the amplifier block 210 by the boosted bit line control block 225 in order to charge the voltage on one of the bit lines BLt and BLc depending on the state of the amplifier block 210 to the boosted bit line voltage VBLHI.

[0031] The evaluation control block 220 includes an NFET 221 and a PFET 222. The NFET 221 switchably connects a negative (reference) supply voltage (which is the negative supply for the amplifier block 210) to the node SAN and disconnects it under the control of a signal on the NSET node. The PFET 222 switchably connects a digital logic supply voltage (which is the positive supply for the amplifier block 210) to the node SAP and disconnects it under the control of a signal on the PSET node. The signal provided to the NSET node (i.e., the gate of the NFET 221) can have a swing that is less than the boosted bit line voltage. Thus, in normal operation, the control circuitry coupled to the evaluation control block 220 (e.g., the control circuitry 160) can include circuitry that can provide a signal to the NSET node that reaches the digital logic supply voltage, but does not reach VBLHI (or even VBLHI minus the threshold voltage of the PFET 222).

[0032] In one embodiment, in normal non-write-back operation, the digital logic supply voltage connected to SAP by the PFET 222 is less than the boosted bit line voltage VBLHI. The swing of the signal on the PSET (i.e., the gate of the PFET 222) can be equal to (or less than the digital logic supply voltage (e.g., VDD) to be connected to SAP by less than the threshold voltage of the PFET 222). Thus, in normal non-write-back operation, the control circuitry coupled to the evaluation control block 220 can include circuitry that can provide a signal to the PSET node that reaches the digital logic supply voltage VDD, but does not reach VBLHI (or even VBLHI minus the threshold voltage of the PFET 222).

[0033] The sense amplifier equalization block 230 connects the SAP and SAN together and to the equalization supply voltage VBLEQ when activated via a signal on the node SNS AMP EQ. The sense amplifier equalization block 230 includes NFETs 231-233. The gates of the NFETs 231-233 are operably coupled together and to the node SNS AMP EQ. The source node and the drain node of the NFET 231 are connected to the SAN and the SAP, respectively. The source node and the drain node of the NFET 232 are connected to the SAN and VBLEQ, respectively. The source node and the drain node of the NFET 233 are connected to VBLEQ and the SAP, respectively. The signal provided to SNS AMP EQ can have a swing that is less than the boosted bit line voltage VBLHI. Thus, in normal operation, the control circuitry (e.g., control circuitry 160) coupled to the sense amplifier equalization block 230 can include circuitry that can provide a signal to the SNS AMP EQ node that reaches the digital logic supply voltage, but does not reach VBLHI (or even VBLHI minus the threshold voltage of the PFET 222).

[0034] The bit line equalization block 240 connects the bit line BLt and the bit line BLc together and to the equalization supply voltage VBLEQ when activated via a signal on the node EQL. The bit line equalization block 240 includes NFETs 241-243. The gates of the NFETs 241-243 are operably coupled together and to the node EQL. The source node and the drain node of the NFET 241 are connected to the BLt and the BLc, respectively. The source node and the drain node of the NFET 242 are connected to the BLt and VBLEQ, respectively. The source node and the drain node of the NFET 243 are connected to VBLEQ and the BLc, respectively. The signal provided to EQL can have a swing that is less than the boosted bit line voltage VBLHI. Thus, in normal operation, the control circuitry (e.g., control circuitry 160) coupled to the bit line equalization block 240 can include circuitry that can provide a signal to the EQL node that reaches the digital logic supply voltage but does not reach VBLHI (or even VBLHI minus the threshold voltage of the PFET 222).

[0035] Column connection block 250 selectively (switchably) connects (also known as gates) bit lines BLT and BLC to local data lines LDQt and LDQc, respectively. Column connection block 250 includes NFETs 251-252. The gates of NFETs 251-252 are operatively coupled together and coupled to node CSL. The source and drain nodes of NFET 251 are connected to BLT and LDQt, respectively. The source and drain nodes of NFET 252 are connected to BLC and LDQt, respectively. The swing of the signal on CSL (i.e., the gates of NFETs 251-252) can be equal to the digital logic supply voltage.

[0036] In one embodiment, under the control of signals on the PSETH node, PFET 226 can switchably connect and disconnect the boost bit line voltage VBLHI from node SAP. When PFET 226 connects the boost bit line voltage VBLHI to node SAP, PFET 222 can switchably disconnect the digital logic supply voltage VDD from node SAP under the control of signals on the PSET node. To disconnect the digital logic supply voltage VDD from node SAP, the voltage on the PSET node can be boosted to VBLHI. Disconnecting the digital logic supply voltage VDD from node SAP avoids drive conflicts between the boost bit line voltage VBLHI and the digital logic supply voltage VDD. When PFET 226 connects the boost bit line voltage VBLHI to node SAP, one of the bit lines BLt and BLc selected by the amplifier block 210 state is charged to the boost bit line voltage VBLHI. In one embodiment, PFET 226 connects the boost bit line voltage VBLHI to node SAP to evaluate the voltages on bit lines BLt and BLc. In this embodiment, the PFET 226 can connect the boost bit line voltage VBLHI to the node SAP without first connecting the digital logic supply voltage VDD to the node SAP.

[0037] Figure 3 This is a diagram illustrating the components of an offset-compensated boost write-back sense amplifier. The sense amplifier 300 may be part of the DRAM memory device 110 and / or sense amplifier bar 135 (i.e., specifically, as sense amplifier 130). Figure 3 In the sensor amplifier 300, functional blocks 310, 320, and 340 are included. For simplicity, from... Figure 3Other functional blocks of the sense amplifier 300 are omitted. The sense amplifier 300 performs an evaluation of the voltage difference on the true (BLt) and complement (BLc) bit lines. The sense amplifier 300 also performs a write and / or a write back of data to a memory cell (e.g., cell 123) by forcing (charging) the true (BLt) and complement (BLc) bit lines to a digital logic supply voltage (VDD) and / or a boosted bit line voltage (VBLHI).

[0038] The amplifier block 310 includes a cross-coupled inverter pair that is turned on by the evaluation control block 320. The cross-coupled inverters of the amplifier block 310 include n-channel field effect transistors (NFETs) 311 and 312, and p-channel field effect transistors (PFETs) 313 and 314. The NFET 311 and the PFET 314 form a first inverter that is cross-coupled to a second inverter formed using the NFET 312 and the PFET 314. The output of each inverter is provided to the input of the other inverter (i.e., cross-coupled). The negative and positive supplies to the inverters of the amplifier block 310 are selectively provided by the evaluation control block 320.

[0039] The supplies SAN and SAP to these inverters are selectively (switchably) provided to the amplifier block 310 by the evaluation control block 320 in order to allow the internal nodes of the amplifier block 310 / external nodes to the amplifier block 310 (including the bit lines BLt, BLc, internal nodes SABLt, SABLc, and the supplies SAN and SAP) to be equalized, and then activated to evaluate the voltages on the bit line BLt and the bit line BLc. The supply SAP is selectively (switchably) provided to the amplifier block 310 by the boosted bit line control block 325. The supply SAP is selectively (switchably) provided to the amplifier block 310 by the boosted bit line control block 325 in order to charge the voltage on one of the bit lines BLt and BLc that depends on the state of the amplifier block 310 to the boosted bit line voltage VBLHI.

[0040] The evaluation control block 320 includes an NFET 321 and a PFET 322. The NFET 321 can switchably connect a negative (reference) supply voltage (which is a negative supply for the amplifier block 310) to, and disconnect it from, the node SAN under control of a signal on the NSET node. The PFET 322 can switchably connect a digital logic supply voltage VDD (which is a positive supply for the amplifier block 310) to, and disconnect it from, the node SAP under control of a signal on the PSET node. The NFET 321 can switchably connect a negative (reference) supply voltage (which is a negative / reference supply for the amplifier block 310) to, and disconnect it from, the node SAN under control of a signal on the NSET node. The signal provided to the NSET node (i.e., the gate of the NFET 321) can have a swing that is less than the bit line voltage. Thus, in normal operation, control circuitry (e.g., control circuitry 160) coupled to the evaluation control block 320 can include circuitry that can provide a signal to the NSET node that reaches the digital logic supply voltage VDD, but does not reach VBLHI (or even VBLHI minus the threshold voltage of the PFET 322).

[0041] In one embodiment, in normal operation, the positive supply voltage connected to SAP by the PFET 322 is less than the boosted bit line voltage VBLHI. The swing of the signal on the PSET (i.e., the gate of the PFET 322) can be equal to (or less than the digital logic supply voltage (e.g., VDD) to be connected to SAP by less than the threshold voltage of the PFET 322). Thus, in normal non-write-back operation, control circuitry coupled to the evaluation control block 320 can include circuitry that can provide a signal to the PSET node that reaches the digital logic supply voltage VDD, but does not reach VBLHI (or even VBLHI minus the threshold voltage of the PFET 322).

[0042] The offset compensation switch block 340, when activated via signals on nodes ISO and OC, disconnects the bit line BLt and the bit line BLc from the node SABLt and the node SABLc, respectively, of the internal amplifier block 310; connects the BLt to the SABLc; and connects the BLc to the SABLt. The offset compensation switch block 340 includes NFETs 341-544. The gates of the NFETs 341-542 are operatively coupled together and to the node ISO (also referred to as isolation). The source node and the drain node of the NFET 341 are connected to the BLt and the SABLt, respectively. The source node and the drain node of the NFET 342 are connected to the BLc and the SABLc, respectively. The source node and the drain node of the NFET 343 are connected to the BLt and the SABLc, respectively. The source node and the drain node of the NFET 344 are connected to the BLc and the SABLt, respectively. The swing of the signal on the OC (i.e., the gates of the NFETs 343-344) can be equal to the digital logic supply voltage VDD. Thus, in normal operation, the control circuitry coupled to the offset compensation switch block 340 can include circuitry that can provide a signal to the OC node that is at least VDD, but not VBLHI.

[0043] In one embodiment, the PFET 326 switchably connects the boosted bit line voltage VBLHI to the node SAP and disconnects it therefrom under control of a signal on the PSETH node. When the PFET 326 connects the boosted bit line voltage VBLHI to the node SAP, the PFET 322 switchably disconnects the digital logic supply voltage from the node SAP under control of a signal on the PSET node. To disconnect the digital logic supply voltage VDD from the node SAP, the voltage on the PSET node can be boosted to VBLHI. The disconnection of the digital logic supply voltage VDD from the node SAP avoids a drive conflict between the boosted bit line voltage VBLHI and the digital logic supply voltage VDD. When the PFET 326 connects the boosted bit line voltage VBLHI to the node SAP, one of the bit lines BLt and BLc that is selected by the amplifier block 310 is charged to the boosted bit line voltage VBLHI. In one embodiment, the PFET 326 connects the boosted bit line voltage VBLHI to the node SAP to evaluate the voltage on the bit lines BLt and BLc. In this embodiment, the PFET 326 can connect the boosted bit line voltage VBLHI to the node SAP without first connecting the digital logic supply voltage VDD to the node SAP.

[0044] Figures 4A-4Cis a diagram illustrating a boost read operation. Typically, during a boost read operation, PSET should be at VBLHI to completely disconnect VBLHI from VDD. This can be achieved in one of two ways: (1) a two-level operation, where PSET toggles between VSS and VBLHI; or (2) a three-level operation, where PSET toggles between 0 and VDD during non-read operations, and is boosted to VBLHI during read operations. Figure 4A An example three-level operation is illustrated in Figure 4B , Figure 4C and Figure 5 An example two-level operation is illustrated in

[0045] In Figure 4A , a sense (read) operation is performed, followed by a read-while-write operation. In Figure 4A , waveforms 401 and 402 represent the voltage on a bit line (e.g., bit line BLt and bit line BLc of sense amplifier 200). In a first phase (precharge operation), waveforms 401-402 illustrate that the bit lines are precharged to the same voltage level VBLEQ. In some embodiments, VBLEQ can be approximately equal to VDD / 2. During this first precharge phase, PSET is driven to VDD, and PSETH is driven to the boosted bit line voltage VBLHI. This is to allow the bit lines to be charged to VBLEQ, which is less than both VDD and VBLHI in Figure 4A .

[0046] The next (second) phase is signal development. Signal development begins when the equalization circuitry (e.g., sense amplifier equalization block 230 and bit line equalization block 240) is turned off and the word line is disconnected, while the sense amplifier has not yet been switched to sense. Signal development shares the charge of the bit line cell, and slightly separates the true and complement bit lines to create a signal, which is then amplified in the sense phase.

[0047] In a third phase (sense operation), PSET is driven to a negative reference voltage VSS, and PSETH remains at VBLHI. When PSET is driven to the negative reference voltage, the positive supply node SAP of the amplifier block (e.g., amplifier block 210) of the sense amplifier is connected to VDD. This, along with the negative node (not shown in Figure 4A , which is connected to VSS, causes the cross-coupled inverters (e.g., amplifier block 210) of the sense amplifier to evaluate the voltage difference on the bit lines. In evaluating the voltage difference, the cross-coupled inverters feed back on each other to drive the bit lines according to the voltage difference on the bit lines. This is illustrated in Figure 4A by waveforms 401 charging to VDD and waveforms 402 discharging to VSS.

[0048] In the fourth phase (write-back operation), PSET is driven to the boosted bit line voltage VBLHI and PSETH is driven to the negative reference voltage VSS. This causes VBLHI to be applied to the positive supply node SAP. In response, waveform 401 illustrates the bit line charged to VDD is further charged to VBLHI. Waveform 402 illustrates the bit line discharged to VSS remains at VSS. Thus, from Figure 4A As can be seen, waveform 401 illustrates the bit line is "boosted" to VBLHI which is higher than VDD. The voltage on the bit line illustrated by waveform 401 determines the voltage on the capacitor in the DRAM cell (e.g., cell 123). Thus, the voltage on the capacitor in the DRAM cell is also "boosted."

[0049] In the fifth phase (pre-charge operation), PSETH is driven to the boosted bit line voltage VBLHI and PSET is lowered to VDD. This allows the bit line to be pre-charged back to the starting voltage level VBLEQ. This is illustrated in Figure 4A by waveforms 401-402 returning to VBLEQ.

[0050] In Figure 4B , a sense (read) operation is performed followed by a write-back operation. In Figure 4B , waveforms 403 and 404 represent the voltage on the bit lines (e.g., bit line BLt and bit line BLc of sense amplifier 200). In the first phase (pre-charge operation), waveforms 403-404 illustrate the bit lines being pre-charged to the same voltage level VBLEQ. In some embodiments, VBLEQ can be approximately equal to VDD / 2. During this first pre-charge phase, PSET and PSETH are driven to the boosted bit line voltage VBLHI. This is to allow the bit lines to be charged to VBLEQ, which in Figure 4B , VBLEQ is less than both VDD and VBLHI.

[0051] The next (second) phase is signal development. In the third phase (sense operation), PSET is driven to the negative reference voltage VSS and PSETH remains at VBLHI. When PSET is driven to the negative reference voltage, the positive supply node SAP of the amplifier block (e.g., amplifier block 210) of the sense amplifier is connected to VDD. This along with the negative node (not shown in Figure 4B ) connected to VSS causes the cross-coupled inverters (e.g., amplifier block 210) of the sense amplifier to evaluate the voltage difference on the bit lines. In evaluating the voltage difference, the cross-coupled inverters feed back on each other to drive the bit lines according to the voltage difference on the bit lines. This is illustrated in Figure 4B by waveform 403 charging to VDD and waveform 404 discharging to VSS.

[0052] In the fourth phase (a read operation), PSET is driven to VBLHI and PSETH is driven to a negative reference voltage VSS. This causes the boosted bit line voltage VBLHI to be applied to the positive supply node SAP. In response, waveform 403 illustrates the bit line charged to VDD further charging to VBLHI. Waveform 404 illustrates the bit line discharged to VSS remaining at VSS. Thus, from Figure 4B As can be seen, waveform 403 illustrates the bit line being "boosted" to a voltage higher than VDD to VBLHI. The voltage on the bit line illustrated by waveform 403 determines the voltage on the capacitor in the DRAM cell (e.g., cell 123). Thus, the voltage on the capacitor in the DRAM cell is also "boosted."

[0053] In the fifth phase (a pre-charge operation), PSETH and PSET are driven to the boosted bit line voltage VBLHI. This allows the bit lines to be pre-charged back to the starting voltage level VBLEQ. This is illustrated in Figure 4B by waveforms 403-404 returning to VBLEQ.

[0054] Figure 4C A boosted bit line voltage refresh operation is illustrated. In Figure 4C waveforms 405 and 406 represent the voltage on the bit lines (e.g., bit line BLt and bit line BLc of sense amplifier 200). In a first phase (a pre-charge operation), waveforms 405-406 illustrate the bit lines being pre-charged to the same voltage level VBLEQ. In some embodiments, VBLEQ can be approximately equal to VDD / 2. During this first pre-charge phase, PSET and PSETH are driven to VBLHI. Waveforms 405-406 illustrate the bit lines both being charged to VBLEQ, in Figure 4C which VBLEQ is less than both VDD and VBLHI.

[0055] The next (second) phase is signal development. In a third phase (a combined sense and read operation), PSET is still driven to VBLHI and PSETH is driven to a negative reference voltage VSS. This causes VBLHI to be applied to the positive supply node SAP. When PSET is driven to the negative reference voltage, the positive supply node SAP of the amplifier block (e.g., amplifier block 210) of the sense amplifier is connected to VBLHI. This along with the negative node (not shown in Figure 4C causes the cross-coupled inverters (e.g., amplifier block 210) of the sense amplifier to evaluate the voltage difference on the bit lines. In evaluating the voltage difference, the cross-coupled inverters feed back on each other to drive waveforms 405-406 according to the voltage difference on the bit lines. This is illustrated in Figure 4C by waveform 405 charging to VBLHI and waveform 406 discharging to VSS.

[0056] Thus, from Figure 4C It can be seen that in one operation, waveform 405 is "boosted" to be higher than VDD to VBLHI. The voltage on the bit line illustrated by waveform 405 determines the voltage on the capacitor in the DRAM cell (e.g., cell 123). Thus, the voltage on the capacitor in the DRAM cell is also "boosted." In the fourth phase (precharge operation), PSETH is driven to the boosted bit line voltage VBLHI, and PSET remains at VBLHI. This allows waveforms 405-406 to be precharged back to the starting voltage level VBLEQ.

[0057] Figure 5 is a diagram illustrating a boosted voltage write operation. In Figure 5 waveforms 501 and 502 represent the voltage on a bit line (e.g., bit line BLt and bit line BLc of sense amplifier 200). In the first phase (end of sense operation), waveforms 501-502 illustrate the bit lines being charged to VSS and VDD, respectively. The state of the bit lines can have been determined by a previous sense operation or write operation that set the state of the inverters in the amplifier block (e.g., amplifier block 210). At the end of this phase, PSET is driven to VSS, PSETH is driven to VBLHI, and column select line CSL is driven to VSS. This is to allow the bit lines illustrated by waveform 501 to be charged up to VDD, but not as high as VBLHI. This also prevents the voltage on the local data line from rewriting the state of the inverters in the amplifier block.

[0058] In the second phase (write operation), PSET remains at VSS, and PSETH remains at VBLHI, and column select line (CSL) is driven to VDD. When CSL is driven to VDD, the voltage on the local data line rewrites the state of the inverters in the amplifier block. This is illustrated in Figure 5 by waveform 501 charging to VDD and waveform 502 discharging to VSS.

[0059] In the third phase (write-back operation), PSET is driven to VBLHI, PSETH is driven to negative reference voltage VSS, and CSL is driven to VSS. This causes VBLHI to be applied to the positive supply node SAP. In response, waveform 501, which was charged to VDD, is further charged to VBLHI. Waveform 502, which was discharged to VSS, remains at VSS. Thus, from Figure 5 It can be seen that in one operation, waveform 405 is "boosted" to be higher than VDD to VBLHI. The voltage on the bit line illustrated by waveform 405 determines the voltage on the capacitor in the DRAM cell (e.g., cell 123). Thus, the voltage on the capacitor in the DRAM cell is also "boosted." In the fourth phase (precharge operation), PSETH is driven to the boosted bit line voltage VBLHI, and PSET remains at VBLHI. This allows waveforms 405-406 to be precharged back to the starting voltage level VBLEQ. It can be seen that in one operation, waveform 405 is "boosted" to be higher than VDD to VBLHI. The voltage on the bit line illustrated by waveform 405 determines the voltage on the capacitor in the DRAM cell (e.g., cell 123). Thus, the voltage on the capacitor in the DRAM cell is also "boosted." In the fourth phase (precharge operation), PSETH is driven to the boosted bit line voltage VBLHI, and PSET remains at VBLHI. This allows waveforms 405-406 to be precharged back to the starting voltage level VBLEQ.

[0060] In the fourth phase (precharge operation), PSETH is driven to the boosted bit line voltage VBLHI, PSET is held at VBLHI, and CSL is held at VSS. This allows the bit line illustrated by waveforms 501-502 to be precharged back to the starting voltage level VBLEQ.

[0061] Figure 6 is a flowchart illustrating a boosted read method. Figure 6 One or more steps illustrated in are performed by, for example, memory system 100, sense amplifier 200, sense amplifier 300, and / or components thereof. A digital value is sensed from a voltage difference between two bit lines of a dynamic memory array using a digital logic supply voltage level to power cross-coupled inverters (602). For example, using a digital logic supply voltage VDD to power the cross-coupled inverters of amplifier block 210, sense amplifier 200 can sense a digital value corresponding to a voltage difference between true (BLt) and complement (BLc) bit lines connected to sense amplifier 200 using the voltage difference.

[0062] A digital value is written to a dynamic memory array using a bit line voltage greater than the digital logic supply voltage level (604). For example, the boosted bit line control block of sense amplifier 200 can couple a boosted bit line voltage VBLHI greater than VDD to the positive supply node SAP of amplifier block 210. This allows one of the cross-coupled inverters of amplifier block 210 to drive the boosted bit line voltage VBLHI into a dynamic memory array (e.g., subarray 128), where the boosted bit line voltage VBLHI will charge a capacitor of a dynamic memory array cell (e.g., cell 123).

[0063] Figure 7 is a flowchart illustrating a boosted write method. Figure 7 One or more steps illustrated in are performed by, for example, memory system 100, sense amplifier 200, sense amplifier 300, and / or components thereof. A state of a pair of cross-coupled inverters of a sense amplifier of a dynamic memory array is set using a digital logic supply voltage level to power the cross-coupled inverters (702). For example, during a write operation that sets their state based on voltages on local data lines LDQt and LDQc, the cross-coupled inverters of amplifier block 210 of sense amplifier 200 can be powered by a VDD level voltage from evaluation control block 320.

[0064] Write the state of the cross-coupled inverter pair of the sense amplifier to the dynamic memory array using a bit line voltage greater than a digital logic supply voltage level (704). For example, based on the state of the cross-coupled inverters, the sense amplifier 200 can drive a boosted bit line voltage VBLHI greater than VDD to one of the true (BLt) and complement (BLc) bit lines corresponding to the state of the cross-coupled inverters. This allows the sense amplifier 200 to drive the boosted bit line voltage VBLHI into the dynamic memory array (e.g., subarray 128), where the boosted bit line voltage VBLHI will charge the capacitor of a dynamic memory array cell (e.g., cell 123).

[0065] Figure 8 is a method of operating a memory device. Figure 8 One or more steps illustrated in the middle can be performed by, for example, the memory system 100 and / or components thereof. Transmit a first command to the memory device to operate a plurality of sense amplifier circuits as part of a dynamic memory array of the memory device to use a digital logic supply voltage level during sensing operations and column operations (802). For example, the controller 180 can transmit a command (and / or set a register value) via the interface 185 that causes the memory device 110 to configure the sense amplifiers 130 to sense the state of a memory bit cell (e.g., cell 123) using a digital logic supply voltage level (e.g., VDD) and / or a maximum signal swing level (relative to the same negative supply / reference / substrate voltage referenced by the bit line voltage) used by most digital logic on the DRAM memory device 110.

[0066] During a write back operation, the memory device is controlled to use a bit line voltage greater than a digital logic supply voltage (804). For example, the controller 180 can transmit a command (and / or set a register value) via the interface 185 that causes the memory device 110 to configure the sense amplifiers 130 to write back the state of a memory bit cell (e.g., cell 123) using a boosted bit line supply (e.g., VBLHI) and / or a maximum signal swing level (relative to the same negative supply / reference / substrate voltage referenced by the digital logic supply voltage level) greater than a digital logic supply voltage level used by most digital logic on the DRAM memory device 110.

[0067] Figure 9 is a method of adjusting a write back voltage. Figure 9One or more of the steps illustrated in FIG. 12 can be performed, for example, by the memory system 100 and / or components thereof. Transmit a first command to a memory device to operate a plurality of sense amplifier circuits as part of a dynamic memory array of the memory device to use a digital logic supply voltage level during a sense operation and a column operation (1202). For example, the controller 180 can transmit a register value (and / or command) via the interface 185 that causes the memory device 110 to configure the sense amplifiers 130 to sense a state of a memory bit cell (e.g., cell 123) using a digital logic supply voltage level (e.g., VDD) and / or a maximum signal swing level that is used by most digital logic on the DRAM memory device 110.

[0068] Transmit a second indicator to the memory device to operate the plurality of sense amplifier circuits at a first bit line voltage during a write back operation (1204). For example, the controller 180 can transmit a register value (and / or command) via the interface 185 that causes the memory device 110 to configure the sense amplifiers 130 to write back a state of a memory bit cell (e.g., cell 123) using a boosted bit line supply (e.g., VBLHI) and / or a maximum signal swing level.

[0069] Transmit a third indicator to the memory device to operate the plurality of sense amplifier circuits at a second bit line voltage during the write back operation, wherein the second bit line voltage is not equal to the first bit line voltage (1204). For example, the controller 180 can transmit a register value (and / or command) via the interface 185 that causes the memory device 110 to configure the sense amplifiers 130 to write back a state of a memory bit cell (e.g., cell 123) using a different boosted bit line supply and / or a maximum signal swing level. In another example, the controller 180 can transmit a register value (and / or command) via the interface 185 that causes the memory device 110 to change a voltage level of VBLHI.

[0070] The above-described methods, systems, and devices can be implemented in or stored by a computer system. The above-described methods can also be stored on a non-transitory computer-readable medium. The devices, circuits, and systems described herein can be implemented using computer-aided design tools available in the art and can be embodied by computer-readable files containing a software description of such circuits. This includes, but is not limited to, memory system 100, sense amplifier 200, sense amplifier 300, and their components. These software descriptions can be: behavioral, register transfer, logic component, transistor, and layout geometry level descriptions. Furthermore, the software descriptions can be stored on storage media or communicated by carrier waves.

[0071] Data formats in which such descriptions can be implemented include, but are not limited to: formats supporting behavioral languages such as C, formats supporting register transfer level (RTL) languages such as Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other appropriate formats and languages. Furthermore, the transfer of such files in data on machine- readable media can be performed electronically over the Internet through various media or, for example, via email. Note that physical files can be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy disk media, CDs, DVDs, etc.

[0072] Figure 10 is a block diagram illustrating one embodiment of a processing system 1000 for including, processing, or generating a representation of a circuit component 1020. The processing system 1000 includes one or more processors 1002, a memory 1004, and one or more communication devices 1006. The processor 1002, the memory 1004, and the communication device 1006 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1008.

[0073] The processor 1002 executes instructions for one or more processes 1012 stored in the memory 1004 to process and / or generate the circuit component 1020 in response to user input 1014 and parameters 1016. The processes 1012 can be any suitable electronic design automation (EDA) tool or portion thereof for designing, simulating, analyzing, and / or verifying electronic circuitry and / or generating a photomask for electronic circuitry. The representation 1020 includes data describing the memory system 100, the sense amplifier 200, the sense amplifier 300, and their components, as shown in the figures.

[0074] The representation 1020 can include one or more of behavioral, register transfer, logic component, transistor, and layout geometry level descriptions. Furthermore, the representation 1020 can be stored on storage media or communicated by carrier waves.

[0075] Data formats that can implement the representation 1020 include, but are not limited to, formats for behavior languages that support such as C, formats for register transfer level (RTL) languages that support such as Verilog and VHDL, formats that support geometry description languages such as GDSII, GDSIII, GDSIV, CIF, and MEBES, and other appropriate formats and languages. Moreover, such file transfers of data on machine- readable media can be performed electronically over the Internet through various mediums or, for example, via email.

[0076] The user input 1014 can include input parameters from a keyboard, a mouse, a voice recognition interface, a microphone and speaker, a graphical display, a touch screen, or other types of user interface devices. The user interface can be distributed among multiple interface devices. The parameters 1016 can include specifications and / or characteristics that are input to assist in defining the representation 1020. For example, the parameters 1016 can include information that defines device types (e.g., NFET, PFET, etc.), topologies (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, supply voltages, simulation temperatures, simulation models, etc.).

[0077] The memory 1004 includes non-transitory computer-readable storage media of any appropriate type, number, and / or configuration that stores the processes 1012, the user input 1014, the parameters 1016, and the circuit component 1020.

[0078] The communication devices 1006 include any appropriate type, number, and / or configuration of wired and / or wireless devices that transmit information from the processing system 1000 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, the communication devices 1006 can transmit the circuit component 1020 to another system. The communication devices 1006 can receive the processes 1012, the user input 1014, the parameters 1016, and / or the circuit component 1020 and can cause the processes 1012, the user input 1014, the parameters 1016, and / or the circuit component 1020 to be stored in the memory 1004.

[0079] The implementations discussed herein include, but are not limited to, the following examples:

[0080] Example 1 : A dynamic random access memory (DRAM) device comprising: digital logic circuitry to at least process a column address and a row address to retrieve data stored in a dynamic memory array, the digital logic circuitry operating using a first digital logic supply voltage level; and sense amplifier circuitry, as part of the dynamic memory array, to operate using the first digital logic supply voltage level during a sense operation and a column operation, and to operate using a boosted bit line voltage during a write back operation, the boosted bit line voltage being greater than the first digital logic supply voltage level.

[0081] Example 2: The DRAM device of example 1, wherein the digital logic circuitry is implemented using a high-k metal gate process.

[0082] Example 3: The DRAM device of example 1, wherein the sense amplifier circuitry comprises a cross-coupled inverter pair in a bistable flip-flop configuration, the cross-coupled inverter pair being coupled to a respective bit line of the dynamic memory array, the cross-coupled inverter pair each having a negative supply node and a positive supply node.

[0083] Example 4: The DRAM device of example 3, wherein during a write back operation, the boosted bit line voltage is selectively coupled to the positive supply node of the cross-coupled inverter pair.

[0084] Example 5: The DRAM device of example 4, wherein during a sense operation and a column operation, the first digital logic supply voltage level is selectively coupled to the positive supply node of the cross-coupled inverter pair.

[0085] Example 6: The DRAM device of example 4, wherein during a refresh operation, the boosted bit line voltage is selectively coupled to the positive supply node of the cross-coupled inverter pair.

[0086] Example 7: The DRAM device of example 4, wherein the boosted bit line voltage is selectively coupled to the positive supply node of the cross-coupled inverter pair using a p-channel field effect transistor (PFET) having a PFET gate node controlled using a logic that applies a voltage to the PFET gate node that is at least the boosted bit line voltage minus a threshold voltage of the PFET.

[0087] Example 8: A dynamic random access memory (DRAM) device comprising: a sense amplifier circuit, as part of a dynamic memory array, to operate using a first digital logic supply voltage level during a first plurality of sense operations and a first plurality of column operations, and to operate using a first bit line voltage during a first plurality of write back operations occurring after respective ones of the first plurality of sense operations to write back data sensed by the respective ones of the first plurality of sense operations, the first bit line voltage being greater than the first digital logic supply voltage level; and digital logic to process at least received commands, column addresses, and row addresses to retrieve data stored in the dynamic memory array, the digital logic operating using the first digital logic supply voltage level.

[0088] Example 9: The DRAM of example 8, wherein the first bit line voltage is based on a first received command.

[0089] Example 10: The DRAM of example 9, wherein the sense amplifier circuit is to operate using a second bit line voltage to write back data sensed by a sense operation during a write back operation occurring after the sense operation based on a second received command, the second bit line voltage being equal to the first digital logic supply voltage level.

[0090] Example 11: The DRAM of example 9, wherein the sense amplifier circuit is to operate using a second bit line voltage to write back data sensed by a sense operation during a write back operation occurring after the sense operation based on a second received command, the second bit line voltage not being equal to the first bit line voltage and being greater than or equal to the first digital logic supply voltage level.

[0091] Example 12: The DRAM of example 10, wherein the second bit line voltage is based on a temperature of the DRAM.

[0092] Example 13: The DRAM of example 8, wherein the sense amplifier circuit is to precharge respective bit lines of the dynamic memory array to a precharge voltage derived from the first digital logic supply voltage level based on a first received command.

[0093] Example 14: The DRAM of example 8, wherein the sense amplifier circuit is to perform a refresh operation using a second bit line voltage equal to the first digital logic supply voltage level based on a first received command.

[0094] Example 15: A memory controller comprising: a command interface to communicate a first indicator and a second indicator to a memory device, based at least on the first indicator, the memory device to operate a plurality of sense amplifier circuits using a first digital logic supply voltage level during a first sense operation and a first column operation, the plurality of sense amplifier circuits being part of a dynamic memory array of the memory device, and the memory device to operate using a first bit line voltage during a first write back operation occurring after the first sense operation to write back data sensed by the first sense operation, the first bit line voltage being greater than the first digital logic supply voltage level; based at least on the second indicator, the memory device to operate using a second bit line voltage during a second write back operation occurring after a second sense operation to write back data sensed by the second sense operation, the second bit line voltage being equal to the first digital logic supply voltage level; and a data interface to receive data sensed by respective ones of the first plurality of sense operations.

[0095] Example 16: The memory controller of example 15, wherein the first indicator is command based.

[0096] Example 17: The memory controller of example 15, wherein the command interface is to communicate a third indicator to the memory device, the memory device to operate the plurality of sense amplifier circuits using a third bit line voltage to write back data sensed by a third sense operation during a third write back operation occurring after the third sense operation based on the third indicator, the third bit line voltage not being equal to the first bit line voltage and being greater than or equal to the first digital logic supply voltage level.

[0097] Example 18: The memory controller of example 15, wherein the third indicator is command based.

[0098] Example 19: The memory controller of example 15, wherein the first bit line voltage is based on a temperature of the memory device.

[0099] Example 20: The memory controller of example 17, wherein the third bit line voltage is based on a temperature of the memory device.

[0100] The foregoing description of the present application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed, and other modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of the application and its practical application and to thereby enable others skilled in the art to best utilize the application in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the following claims be interpreted to include all such embodiments and equivalents thereto as fall within the true scope of the application.

Claims

1. A dynamic random access memory (DRAM) device, comprising: A digital logic circuit system for processing at least column addresses and row addresses to retrieve data stored in a dynamic memory array, the digital logic circuit system operating using a first digital logic supply voltage level; as well as A sense amplifier circuit, as part of the dynamic memory array, is configured to operate using the first digital logic supply voltage level during column operations and sense operations until the cross-coupled inverter pair of the sense amplifier circuit reaches a stable state using the first digital logic supply voltage, and to operate using a boost bit line voltage greater than the first digital logic supply voltage level during write-back operations after the cross-coupled inverter pair reaches the stable state using the first digital logic supply voltage.

2. The dynamic random access memory (DRAM) device of claim 1, wherein the digital logic circuit system is implemented using a high-k metal gate process.

3. The dynamic random access memory (DRAM) device of claim 1, wherein the cross-coupled inverter pair is configured as a bistable trigger, the cross-coupled inverter pair is coupled to a corresponding bit line of the DRAM array, and each of the cross-coupled inverter pairs has a negative power supply node and a positive power supply node.

4. The dynamic random access memory (DRAM) device of claim 3, wherein during a write-back operation, the boost bit line voltage is selectively coupled to the positive power supply node of the cross-coupled inverter pair.

5. The dynamic random access memory (DRAM) device of claim 4, wherein during sensing and column operations, the first digital logic supply voltage level is selectively coupled to the positive supply node of the cross-coupled inverter pair.

6. The dynamic random access memory (DRAM) device of claim 4, wherein during a refresh operation, the boost bit line voltage is selectively coupled to the positive power supply node of the cross-coupled inverter pair.

7. The dynamic random access memory (DRAM) device of claim 4, wherein the boost bit line voltage is selectively coupled to the positive power supply node of the cross-coupled inverter pair using a p-channel field-effect transistor (PFET), the p-channel field-effect transistor (PFET) having a PFET gate node controlled by logic that applies a voltage to the PFET gate node at least equal to the boost bit line voltage minus a threshold voltage of the p-channel field-effect transistor (PFET).

8. A dynamic random access memory (DRAM) device, comprising: A sense amplifier circuit, as part of a dynamic memory array, is configured to operate using a first digital logic supply voltage level during a first plurality of column operations and a first plurality of sense operations, during which time it lasts at least until the cross-coupled inverter pair of the sense amplifier circuit reaches a stable state using the first digital logic supply voltage, and is configured to operate using a first bit line voltage during a first plurality of write-back operations occurring after a corresponding sense operation in the first plurality of sense operations, to write back data sensed by the corresponding sense operation in the first plurality of sense operations, wherein the first bit line voltage is greater than the first digital logic supply voltage level; as well as Digital logic, used to process at least the received commands, column addresses, and row addresses to retrieve data stored in the dynamic memory array, operates using the first digital logic power supply voltage level.

9. The dynamic random access memory (DRAM) device of claim 8, wherein the first bit line voltage is based on the first receive command.

10. The dynamic random access memory (DRAM) device of claim 9, wherein the sense amplifier circuit is configured to: operate using a second bit line voltage to write back data sensed by the sense operation based on a second receive command and during a write-back operation occurring after the sense operation, the second bit line voltage being equal to the first digital logic supply voltage level.

11. The dynamic random access memory (DRAM) device of claim 9, wherein the sense amplifier circuit is configured to: operate using a second bit line voltage to write back data sensed by the sense operation based on a second receive command and during a write-back operation occurring after the sense operation, the second bit line voltage being not equal to the first bit line voltage and greater than or equal to the first digital logic supply voltage level.

12. The dynamic random access memory (DRAM) device of claim 10, wherein the second bit line voltage is based on the temperature of the dynamic random access memory (DRAM).

13. The dynamic random access memory (DRAM) device of claim 8, wherein the sense amplifier circuit is configured to: precharge a corresponding bit line of the DRAM array to a precharge voltage derived from the first digital logic supply voltage level based on a first receive command.

14. The dynamic random access memory (DRAM) device of claim 8, wherein the sense amplifier circuit is configured to: perform a refresh operation using a second bit line voltage based on a first receive command, the second bit line voltage being equal to the first digital logic supply voltage level.

15. A memory controller, comprising: A command interface is provided for transmitting a first indicator and a second indicator to a memory device, at least based on the first indicator. The memory device is configured to operate a plurality of sense amplifier circuits using a first digital logic supply voltage level during a first column operation and a first sensing operation, during which time the cross-coupled inverters of the plurality of sense amplifier circuits reach a steady state using the first digital logic supply voltage, the plurality of sense amplifier circuits being part of a dynamic memory array of the memory device. The memory device is also configured to operate using a first bit line voltage during a first write-back operation occurring after the first sensing operation reaches the steady state using the first digital logic supply voltage, to write back data sensed by the first sensing operation, the first bit line voltage being greater than the first digital logic supply voltage level. At least based on the second indicator, the memory device is configured to operate using a second bit line voltage during a second write-back operation that occurs after the second sensing operation reaches the steady state using the first digital logic supply voltage, in order to write back the data sensed by the second sensing operation, the second bit line voltage being equal to the level of the first digital logic supply voltage; as well as A data interface for receiving data sensed by the corresponding sensing operation in the first sensing operation.

16. The memory controller of claim 15, wherein the first indicator is command-based.

17. The memory controller of claim 15, wherein the command interface is configured to transmit a third indicator to the memory device, the memory device being configured to: based on the third indicator, and during a third write-back operation occurring after the third sensing operation has reached the stable state using the first digital logic supply voltage, operate the plurality of sense amplifier circuits to write back data sensed by the third sensing operation using a third bit line voltage, the third bit line voltage being not equal to the first bit line voltage and greater than or equal to the first digital logic supply voltage level.

18. The memory controller of claim 17, wherein the third indicator is command-based.

19. The memory controller of claim 15, wherein the first line voltage is based on the temperature of the memory device.

20. The memory controller of claim 17, wherein the third bit line voltage is based on the temperature of the memory device.

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