Etchless algan gan triple gate transistor

Abstract

Apparatuses and methods for field effect transistor devices including a source, a gate, and a drain. The transistor includes a semiconductor region positioned below the source, the gate, and the drain. The semiconductor region can include a gallium nitride (GaN) layer and a group III-nitride (III-N) layer. The GaN layer includes a bandgap and the III-N layer includes a bandgap. The III-N layer bandgap is higher than the GaN layer bandgap. A sub-region of the semiconductor region is positioned below the gate and is doped with Mg ions at selected locations in the sub-region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices, and in particular to transistors incorporating etch-less processing. BACKGROUND

[0002] In view of today's advanced technology systems, there is a need for improvements in power transistors to provide more robust energy delivery networks and efficient methods of power generation and conversion. Conventional power transistor applications can include power supplies, electronic applications in many technology industries, such as high voltage direct current (HVDC) electronics, lamp ballasts, telecommunication circuits, and display drivers. These types of technology systems rely on efficient converters to step up or step down voltages and use power transistors that are capable of blocking large voltages and / or carrying large currents.

[0003] Conventional power transistors used in such applications are made of silicon. However, the limited critical electric field of silicon and its relatively high electrical resistance result in commercially available devices, circuits, and systems that are very large and heavy and operate at low frequencies. Thus, such commercially available devices are not suitable for many different types of applications in future generations.

[0004] For example, conventional power semiconductor devices require many characteristics, i.e., high breakdown voltage and low on-resistance. There is a trade-off relationship between the breakdown voltage and the on-resistance in power semiconductor devices that is determined by the device material. Among others, low on-resistance that approaches the limit of the primary device material, such as silicon, can be achieved in power semiconductor devices. Some conventional power semiconductor devices using wide bandgap semiconductors have been designed without considering the characteristics unique to power devices, i.e., considering the electron avalanche tolerance capability. This is because GaN-based devices are based on radio frequency (RF) device designs.

[0005] Therefore, in view of the above utility and difficulty, there is an unaddressed need for devices and circuits that improve the performance of group III nitride semiconductor structures. SUMMARY

[0006] The present disclosure relates generally to semiconductor devices, and in particular to transistors incorporating etch-less processing.

[0007] Some embodiments generally relate to device structures and fabrication methods for constructing electronic devices including transistor devices such as field effect transistors. The field effect transistor can include a source, a gate, and a drain. The transistor has a semiconductor region located below the source, the gate, and the drain. The semiconductor region can include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is a gallium nitride (GaN) material and includes a bandgap, and the second semiconductor layer is a group III-nitride (III-N) material and includes a bandgap. The second semiconductor bandgap is higher than the first semiconductor layer bandgap. A sub-region of the semiconductor region is located below the gate and is doped with Mg ions at selected locations in the sub-region.

[0008] During the experiment, high electron mobility transistors (HEMTs) based on AlGaN / GaN heterostructures were tested and found to be excellent candidates for high power, high voltage, and high temperature applications. The performance of the tested depletion mode (D-mode) HEMTs appeared to be very good, which seemed to be advantageous for digital IC applications as well as radio frequency integrated circuit (RFIC) or monolithic microwave integrated circuit (MMIC) designs, while enhancement mode (E-mode) device testing also appeared to play a more important role in the future. For the digital IC applications being tested, circuit configurations can be implemented using direct coupled FET logic (DCFL) with integrated features of both D-mode and E-mode HEMTs.

[0009] At the same time, for large IC designs, E-mode devices that do not require a negative voltage supply were tested and it was believed that this could greatly reduce the complexity of circuit design. Enhancement mode devices based on AlGaN / GaN material systems were further tested. Enhancement mode devices based on AlGaN / GaN material systems and E-mode GaN HEMTs, including FinFET devices, were also tested.

[0010] Some implementations of the present disclosure obtained from experiments include testing with E-mode AlGaN GaN HEMTs, particularly in tri-gate (FinFET). Among other things, depending on the fin width, the threshold voltage of the tri-gate (FinFET) was found to be between 0.2V-1.5V. It was learned that narrow fin width can provide more E-mode behavior, and vice versa. However, it was later discovered that narrow fin width reduces the on-current of the transistor device, another reason being due to lack of active channel area. It was also learned that selective etching of the fin fabricated with AlGaN GaN can have negative impacts. For example, such etched tri-gate transistors have reliability issues due to dangling bonds formed during the etching process. One of the many challenges to overcome for aspects of the present disclosure is to find solutions to these problems. In facing approaches to overcome these challenges, one realization includes exploring possible fabrication approaches for tri-gate devices without etching.

[0011] TECHNICAL PROBLEM

[0012] Some problems discovered from experiments with etching are that many dangling bonds on the (Al)GaN surface seem to cause surface depletion band bending due to surface pinning effect. For example, the lateral channel surface can show depletion regions from the sidewall gates in the tri-gate structure. A dangling bond is an unsatisfied valence on a fixed atom. An atom with a dangling bond is also called a fixed radical or a fixed free radical, referring to its structural and chemical similarity to a free radical. Some other experiments tested include etching p-GaN outside the gate region using dry etching while maintaining the integrity of the thickness of the underlying epitaxial layers. However, it was later learned that if the underlying epitaxial layers are etched too much, the two-dimensional electron gas (2DEG) will not form at the interface of AlGaN / GaN of the N-face p-GaN gate E-mode HEMT structure. This means that using dry etching can be challenging because the etch depth is difficult to control and there is still thickness non-uniformity in each epitaxial layer of the epitaxial wafer. Furthermore, such epitaxial structures have issues related to current collapse, such as buffer traps and surface traps, which need to be further addressed.

[0013] SOLUTIONS TO THE PROBLEMS

[0014] Accordingly, based on what was learned from the experiments, no further testing of the etching was performed. Among other things, further experiments resulted in the fabrication of a three-gate device without etching. At least one major difference between the AlGaN GaN HEMT device and the transistor device of the present disclosure is in the gate region. In the transistor device of the present disclosure, the region under the gate is selectively implanted with Mg ions and then annealed. As such, the Mg implant converts the AlGaN and GaN to p-AlGaN and p-GaN, respectively, and creates holes in the implanted region. These implanted regions deplete the 2-DEG and provide E-mode operation for the device. By way of non-limiting example, some features and characteristics of the transistor device of the present disclosure include:

[0015] (a) a threshold voltage higher than a three-gate AlGaN GaN HEMT;

[0016] (b) better gate control compared to a gate injection transistor;

[0017] (c) higher breakdown voltage due to super junction; and

[0018] (d) higher reliability due to no etching process.

[0019] Practical Applications

[0020] Applications of the transistor device of the present disclosure can be used with many technologies, non-limiting examples of which include: microwave, millimeter wave communications, imaging, radar, and radio astronomy, among others. In fact, any application that can require high gain and low noise at high frequencies. Other applications of the transistor device of the present disclosure can be in many types of equipment, from cellular phones and DBS receivers to electronic systems such as radar and for radio astronomy. Other applications of the transistor device of the present disclosure can be used as power switching transistors for voltage converter applications.

[0021] The transistor of the present disclosure provides unique characteristics as described above that are critical for active components in almost all modern electronic devices. The transistor of the present disclosure can be produced as integrated circuits (ICs) and microchips, as well as diodes, resistors, capacitors, and other electronic components to produce complete electronic circuits. The transistor of the present disclosure can be manufactured at low cost (when compared to conventional transistors) and is reliable, which are properties that make it a ubiquitous device to a large extent. Transistor electromechanical integrated circuits have replaced electromechanical devices that control appliances and machinery. It is often easier and cheaper to use a standard microcontroller and write a computer program to perform the control function than to design an equivalent mechanical system to control the same function.

[0022] According to one embodiment of the present invention, a field effect transistor is provided that includes a source, a gate, and a drain. A semiconductor region is located under the source, the gate, and the drain. The semiconductor region is caused to include a gallium nitride (GaN) layer and a group-III nitride (III-N) layer. The GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap. A sub-region of the semiconductor region under the gate is doped with Mg ions at selected locations in the sub-region.

[0023] According to another embodiment of the present invention, a transistor is provided that includes a source, a gate, and a drain. A semiconductor region is located under the source, the gate, and the drain. The semiconductor region is caused to include a gallium nitride (GaN) layer and a group-III nitride (III-N) layer. The GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap. The GaN layer and the III-N layer are undoped. A sub-region of the semiconductor region under the gate is doped with Mg ions at selected locations in the sub-region.

[0024] According to another embodiment of the present invention, a transistor is provided that includes a source, a gate, and a drain. A semiconductor region is located under the source, the gate, and the drain. The semiconductor region is caused to include a gallium nitride (GaN) layer and a group-III nitride (III-N) layer. The GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap. The III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the GaN layer. A sub-region of the semiconductor region under the gate is doped with Mg ions at selected locations in the sub-region. BRIEF DESCRIPTION OF DRAWINGS

[0025] The presently disclosed embodiments will be further explained with reference to the drawings. The depicted drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the presently disclosed embodiments.

[0026] [ FIG. 1A ]

[0027] FIG. 1A is a schematic diagram showing a three-dimensional (3D) view of a transistor device according to embodiments of the present disclosure.

[0028] [ FIG. 1B ]

[0029] FIG. 1B is a schematic diagram showing a cross-sectional view of FIG. 1A , showing structures and thicknesses of gate stacks and other structures and thicknesses of transistor devices according to some embodiments of the present disclosure.

[0030] [ FIG. 1C ]

[0031] FIG. 1C is a schematic diagram showing a cross-sectional view of FIG. 1A , showing the structure and thickness of the gate stack, and other structures and thicknesses of the transistor device, according to some embodiments of the present disclosure.

[0032] [ FIG. 1D ]

[0033] FIG. 1D is a schematic diagram showing a cross-sectional view of FIG. 1A , showing the structure and thickness of the gate stack, and other structures and thicknesses of the transistor device, according to some embodiments of the present disclosure.

[0034] [ FIG. 2A ]

[0035] FIG. 2A is a schematic diagram showing a cross-section of the transistor device of FIG. 1A , showing the Mg implant region, according to some embodiments of the present disclosure, below the gate region.

[0036] [ FIG. 2B ]

[0037] FIG. 2B is a schematic diagram showing another cross-section of the gate of the transistor device of FIG. 1A , showing selected locations of Mg implantation, with different spacing between the selected locations and different width along the width direction from the A location to the B location (see FIG. 1A ), at the location of the sub-region, according to some embodiments of the present disclosure, below the gate region.

[0038] [ FIG. 2C ]

[0039] FIG. 2C is a schematic diagram showing a cross-section of the transistor device of FIG. 1A , showing selected locations of selected Mg implantation, which can include varying vertical length along the vertical direction from the C location to the D location (see FIG. 1A ), according to some embodiments of the present disclosure, below the gate region.

[0040] [ FIG. 2D ]

[0041] FIG. 2D is a schematic diagram showing another cross-section of the transistor device of FIG. 1A , showing selected locations of selected Mg implantation, which can vary in the range of 90 degrees to about 80 degrees along the width direction from the A location to the B location (see FIG. 1A ), according to some embodiments of the present disclosure, below the gate region.

[0042] [ FIG. 3 ]

[0043] FIG. 3 is a block diagram illustrating a manufacturing process of a transistor device according to some embodiments of the present disclosure.

[0044] While the above figures set forth embodiments of the presently disclosed technology, other embodiments can also be contemplated as indicated in the discussion. The present disclosure presents illustrative embodiments by way of representation and not by limitation. Those skilled in the art can devise many other modifications and embodiments that fall within the principles and scope of the presently disclosed technology. DETAILED DESCRIPTION

[0045] The present disclosure relates generally to semiconductor devices, and in particular to transistors incorporating an etch-less process.

[0046] FIG. 1A is a schematic diagram illustrating a three-dimensional (3D) view of a transistor device according to embodiments of the present disclosure. For example, FIG. 1A A field effect transistor 100A is shown, which includes a source 104, a gate 111, and a drain 105. A semiconductor region is underneath the source 104, the gate 111, and the drain 105, and includes a base layer, a buffer layer above the base layer. A gallium nitride (GaN) layer is above the buffer layer, and a group-III nitride (III-N) layer is above the GaN layer. The vertical thickness of the GaN layer is greater than the vertical thickness of the III-N layer. For example, the vertical thickness of the GaN layer can be 10 times the vertical thickness of the III-N layer, or the vertical thickness of the GaN layer can be 1000% of the vertical thickness of the III-N layer. A sub-region R sub of the semiconductor region underneath the gate 111 is doped with Mg ions at a selective location 113 in the sub-region R sub . FIG. 2A to FIG. 2D ).

[0047] It is contemplated that the gap distance between the source 104 and the gate 111, and the gap distance between the gate 111 and the drain 105 can be one of symmetric or asymmetric. Among others, the gap distance between the gate and the drain is related to the breakdown voltage of the field effect transistor.

[0048] Further, the III-N layer can be aluminum gallium nitride (AlGaN). The III-N layer can also be Al x In y Ga 1-x-yN, such that the values of x and y are between 0 and 1 (0 < x < 1), (0 < y < 1). Wherein, the III-N layer has a higher spontaneous polarization charge than the spontaneous polarization charge of the GaN layer. Wherein, the GaN layer comprises a bandgap, and the III-N layer comprises a bandgap, such that the III-N layer bandgap is higher than the GaN layer bandgap.

[0049] Still referring to FIG. 1A , a first end of the device width A extends to another device width end B, and represents the width direction W. Further, from the other device width end B to a location C represents the direction of transport of the electron flow. In addition, from the location C to a location D represents the device vertical direction V. The source 104 comprises the ground 103, and the drain 105 applies a voltage between the source 104 and the drain 105 of the device 100A to read the state of the device 100A connected to the ground 108. V DS 106 is the read voltage and can be positive or negative with respect to the ground 108.I DS 107 is the source-to-drain current flowing out of the device 100A.I DS 107 is the resistive state of the device 100A. It can be a high resistive state or a low resistive state, depending on the polarity of the applied voltage.

[0050] FIG. 1B 、 FIG. 1C and FIG. 1D is a schematic diagram showing a cross-sectional view of FIG. 1A , which shows the structure and thickness of the gate 111 stack, and other structures and thicknesses of the source 104 stack and the drain 105 stack of the field transistor device, according to some embodiments of the present disclosure. FIG. 1B shows the source 104 disposed over a portion of the III-N layer (or AlGaN layer), while FIG. 1D shows the drain 105 located over a portion of the III-N layer (or AlGaN layer). FIG. 1C shows the location of the gate 111 over the entire III-N layer (or AlGaN layer), such that the selective Mg implantation locations 113 convert AlGaN to p-AlGaN and GaN to p-GaN, respectively, and create holes in the implanted regions.

[0051] FIG. 2A is a schematic diagram showing a cross-section of FIG. 1A the transistor device, according to some embodiments of the present disclosure, under the gate region at the location of the sub-region R sub , shows selected locations 213 of Mg implantation. For example, FIG. 2A shows the bottom edge B GaN of the GaN layer, and the top edge T GaNThe sub-region R below gate 211, at selected location 213 sub Mg is implanted and then annealed. In this way, Mg implantation converts AlGaN to p-AlGaN and p-GaN respectively, and creates holes in the implanted regions. These implanted regions deplete the 2-DEG and provide E-mode operation for the device. The depth of each selected Mg implantation site can extend across the top edge of the GaN (TGaN) and into the GaN layer. It is expected that each selected Mg implantation site can extend into approximately 10% of the GaN layer.

[0052] FIG. 2B This illustrates some embodiments according to the present disclosure. FIG. 1A A schematic diagram of another cross-section of the gate of a transistor device, below the gate region in sub-region R. sub At the location shown, the selected locations 213 for Mg injection have varying spacing between them and varying width along the width direction from location A to location B (see [reference]). FIG. 1A ).For example, FIG. 2B The top edge T of the III-N layer (the second layer above the GaN layer) is shown. second and bottom edge B second The second layer (III-N layer) can be aluminum gallium nitride (AlGaN). Each selected location in the sub-region doped with Mg ions can have a T-axis extending from the top edge of the III-N layer. second Crossing the bottom edge B of layer III-N second The interface extends to the top edge T of the GaN layer. GaN The depth of the selected Mg injection sites. The spacing between the selected Mg injection sites can be symmetrical or asymmetrical. The width of the selected Mg injection sites can be symmetrical or asymmetrical.

[0053] FIG. 2C This illustrates some embodiments according to the present disclosure. FIG. 1A A schematic diagram of another cross-section of the gate of a transistor device, below the gate region, shows that selected locations for Mg implantation may include a vertical length varying along a vertical direction from location C to location D (see [reference]). FIG. 1A ).exist FIG. 2A subregion R sub Doped with Mg ions FIG. 2A Each selected position 213 has a contour, such that the contour includes FIG. 2B The vertical profile lengths L1 and L2 and the profile widths W1 and W2. One aspect may be that each profile at the selected location includes... FIG. 2B The constant profile width (W1 = W2) FIG. 2Bone or a combination of variable profile width (W1≠W2), constant vertical profile length (L1=L2), or variable vertical profile length (L1≠L2).

[0054] wherein an aspect can be that the profile forms a pattern such that a profile width of the profile increases along a direction from a first width end A of the field effect transistor to a second width end B of the field effect transistor, resulting in higher linearity compared to a profile having a constant profile width in a direction from the first width end to the second width end of the field effect transistor. An aspect can be that each profile is equally spaced along the width of the field effect transistor, or wherein each profile is unequally spaced and varies along the width of the field effect transistor. FIG. 1A FIG. 1A wherein an aspect can be that each profile is equally spaced along the width of the field effect transistor, or wherein each profile is unequally spaced and varies along the width of the field effect transistor.

[0055] FIG. 2D is a schematic diagram showing another cross section of a transistor device of FIG. 1A under the gate region, showing that a selected Mg implantation at a selected location can have a varying angle A1, A2 from 90 degrees to about 80 degrees along a width direction from A location to B location (see FIG. 1A ).

[0056] FIG. 3 is a block diagram showing a manufacturing process of a transistor device according to some embodiments of the present disclosure.

[0057] Step 305 shows the manufacturing of a field transistor device starting with growing an epitaxial structure. The process starts with a Si / Sapphire / SiC / GaN wafer. The size of the wafer can be 2 / 4 / 6 / 12 inches.

[0058] Step 310 shows growing a buffer layer to address the lattice mismatch between the wafer material and III-N semiconductors if the wafer is not a GaN wafer.

[0059] Then, step 315 shows growing a GaN semiconductor on the buffer layer. The layer thickness can be in the range of 450 nm to a few microns. Ideally, the layer thickness is a thicker layer of GaN as a thicker layer helps to reduce the defect density in the III-N layer, which in turn helps to achieve the best device performance.

[0060] ​Then, step 320 shows growing a III-N layer on the GaN layer. However, the III-N layer bandgap needs to be higher than the GaN layer. Typically, the thickness of the III-N layer can be 5 nm to 30 nm. The buffer layer, GaN layer, and III-N layer can be grown by any growth method using one or a combination of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or remote plasma chemical vapor deposition (RPCVD), pulsed laser deposition (PLD), sputtering, etc.

[0061] Step 325 shows a Ni hard mask formation step. E-beam lithography is required to form the Ni hard mask. After e-beam lithography, 50 nm thick nickel metal is deposited using e-beam evaporation method. Then, lift-off is performed to create the fin pattern.

[0062] Step 330 shows a Mg implantation step. Mg implantation is required to convert GaN and AlGaN to p-type.

[0063] Step 335 shows an annealing step. Annealing is performed to activate Mg ions and create holes.

[0064] Step 340 shows the formation of source and drain terminals. Photolithography is performed and Ti-20 nm / Al-100 nm / Ni-25 nm / Au-50 nm metal is deposited, and lift-off is performed to form metal contacts at the source and drain regions. Then, the contacts are annealed at high temperature in N2, forming ohmic contacts.

[0065] Step 345 shows the formation of gate terminal. Photolithography is performed and Ni-20 nm / Au-80 nm metal is deposited, and lift-off is performed to form metal contacts at the gate region.

[0066] Features

[0067] One embodiment of the present disclosure includes a field effect transistor comprising a source, a gate, and a drain. A semiconductor region is located below the source, the gate, and the drain. The semiconductor region is caused to include a gallium nitride (GaN) layer and a group-III-nitride (III-N) layer. Wherein, the GaN layer includes a bandgap, and the III-N layer includes a bandgap, such that the III-N layer bandgap is higher than the GaN layer bandgap. A sub-region of the semiconductor region below the gate is doped with Mg ions at selected locations in the sub-region. Wherein, the following aspects are considered to configure a modified embodiment of the above-mentioned embodiment.

[0068] One aspect can include, wherein the semiconductor region includes a base layer, a buffer layer above the base layer, and wherein the GaN layer is located above the buffer layer. Another aspect can be that the III-N layer is Al x In yGa 1-x-y N, such that the values of x and y are between 0 and 1 (0 < x < 1), (0 < y < 1). Further, an aspect can be that the III-N layer has a higher spontaneous polarization charge than the spontaneous polarization charge of the GaN layer.

[0069] An aspect can be that the vertical thickness of the GaN layer is greater than the vertical thickness of the III-N layer. An aspect can be that the vertical thickness of the GaN layer is 10 times the vertical thickness of the III-N layer, or the vertical thickness of the GaN layer is 1000% thicker than the vertical thickness of the III-N layer. Another aspect can be that the gap distance between the source and the gate and the gap distance between the gate and the drain are one of symmetric or asymmetric.

[0070] Another aspect can be that each selected location in the sub-region doped with Mg ions has a profile such that the profile includes a vertical profile length and a profile width. An aspect can be that each profile of the selected locations includes one or a combination of a constant profile width, a variable profile width, a constant vertical profile length, or a variable vertical profile length. As such, an aspect can be that the profile forms a pattern such that the profile width of the profile increases along a direction from a first width end to a second width end of the field effect transistor, resulting in a higher linearity than a profile having a constant profile width in a direction from a first width end to a second width end of the field effect transistor. An aspect can be that each profile is equally spaced along the width of the field effect transistor, or where each profile is unequally spaced and varies along the width of the field effect transistor.

[0071] An aspect can include that the selected locations in the sub-region doped with Mg ions have a profile such that the profile is arranged at an angle in a range of about 90 degrees to 80 degrees. Another aspect can be that there is an accumulation of a two-dimensional gas (2-DEG) at the interface of the GaN layer and the III-N layer. An aspect can be that the accumulation of the 2-DEG is depleted by the III-N layer, resulting in an enhancement-mode (E-mode) operation for the field effect transistor. Another aspect can be that the sub-region is annealed in a nitrogen environment after the doping of the Mg ions in the selected locations in the sub-region is completed. Further, an aspect can be that the III-N layer is aluminum gallium nitride (AlGaN), and where the selected locations in the sub-region doped with Mg ions convert the AlGaN layer to p-AlGaN and convert the GaN layer to p-GaN, which results in the creation of holes at the selected locations of the Mg ion implantation of the sub-region.

[0072] An aspect can be that each selected location in the sub-region doped with Mg ions has a profile that extends from a top edge of the III-N layer across an interface of a bottom edge of the III-N layer into a top edge of the GaN layer.

[0073] One aspect can be where the GaN layer and the III-N layer are grown using one or a combination of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or remote plasma chemical vapor deposition (RPCVD), and where the selected locations in the sub-region that are doped with Mg ions are formed by Mg ion implantation.

[0074] Definitions

[0075] In accordance with aspects of the present disclosure, and based on experimentation, the following definitions have been established, and are of course not complete definitions of every phrase or term. Among other things, based on learning from experimentation, the provided definitions are provided by way of example only, where other interpretations, definitions, and other aspects can be involved. However, such definitions have been provided for at least a basic preview of the phrase or term presented, but the definitions presented below can in no way be applied as prior art as this is simply knowledge gained from experimentation.

[0076] Two layers in direct contact : Two layers in direct contact can be understood as an arrangement where the two contacting layers are absent other intermediate layers. That is, direct physical contact between the two layers.

[0077] Two-dimensional (2D) semiconductor layer : A two-dimensional (2D) semiconductor layer refers to a semiconductor layer that includes a 2D material layer. Such materials have interesting properties in terms of anisotropic mobility, which can allow for the extension of transistor performance in the future. For example, in some embodiments, a 2D material layer can have a dimension in one direction that is smaller than a dimension in other orthogonal directions, such that at least one physical property in one direction can be different compared to the physical property in the other orthogonal directions. For example, direction-dependent physical properties can include bandgap, electrical and / or thermal conductivity, state density, carrier mobility, etc. For example, when a 2D material layer is formed as a sheet in a plane formed by x and y directions and has a sufficiently smaller dimension in the orthogonal z direction compared to the dimensions in the x and y directions, the 2D material layer can have a bandgap that is different from the bandgap in the x and / or y directions, e.g., a larger bandgap. Further, in some embodiments, a 2D material layer can be a material that has a layered structure, where the atoms of the 2D material layer can have one type of bonding in the x and y directions, and a different type of bonding in the z direction. For example, the atoms of the 2D material layer can be covalently bonded in the x and y directions, and weakly bonded in the z direction, e.g., through Van der Waals forces.

[0078] Gallium nitride (GaN)GaN is a binary III / V direct bandgap semiconductor used in light emitting diodes. The compound is a very hard material with a wurtzite crystal structure. Its wide bandgap of 3.4 eV provides special properties for its use in optoelectronics, high power, and high frequency devices. For example, GaN is the substrate that makes possible violet (405 nm) laser diodes without the need for nonlinear optical frequency doubling. It is very low in sensitivity to ionizing radiation (as are other III-nitrides), which makes it a suitable material for solar cell arrays for satellites. Space applications can also benefit since the devices exhibit stability in a radiation environment. GaN transistors are ideal power amplifiers at microwave frequencies since they can operate at much higher temperatures and at much higher voltages than gallium arsenide (GaAs) transistors. In addition, GaN offers promising properties for THz devices.

[0079] The very high breakdown voltage, high electron mobility, and saturation velocity of GaN also make it an ideal candidate for high power and high temperature microwave applications, as evidenced by its high Johnson figure of merit. Potential markets for GaN-based high power / high frequency devices include microwave radio frequency power amplifiers (such as those used in high speed wireless data transmission) and high voltage switching devices for power grids. A potential mass market application for GaN-based radio frequency transistors is as the microwave source for microwave ovens, replacing the magnetrons currently in use. The large bandgap means that the performance of GaN transistors remains constant at higher temperatures (~400 °C) than silicon transistors (~150 °C) because it reduces the effects of thermal generation of any semiconductor's intrinsic charge carriers. Enhancement mode GaN transistors, which are just n-channel transistors, are designed to replace power MOSFETs in applications where switching speed or power conversion efficiency is critical. These transistors, also known as eGaN FETs, can be built by growing a thin layer of GaN on a standard silicon wafer. This enables eGaN FETs to maintain similar costs to silicon power MOSFETs but with the superior electrical performance of GaN. GaN transistors can be depletion mode devices, i.e., turned on / resistive when the gate-source voltage is zero.

[0080] Aluminum gallium nitride (AlGaN): AlGaN is a semiconductor material and is any alloy of aluminum nitride and gallium nitride. Al x Ga 1-xThe bandgap of N can be tuned from 3.4 eV (xAl = 0) to 6.2 eV (xAl = 1). In addition, AlGaN can be used to make light emitting diodes that work in the blue to ultraviolet region, where wavelengths as low as 250 nm (far UV) can be achieved. AlGaN can be used in blue semiconductor lasers, in ultraviolet radiation detectors, and in AlGaN / GaN high electron mobility transistors. AlGaN can be used with gallium nitride or aluminum nitride to form a heterojunction. AlGaN layers can be grown on gallium nitride, sapphire, or Si, sometimes with an additional GaN layer.

[0081] Digital IC applications : The simplest circuit configuration can be achieved using direct coupled FET logic (DCFL) which has the integrated characteristics of both D-mode and E-mode HEMTs.

[0082] RFIC design : RFIC is an abbreviation for radio frequency integrated circuit. Applications of RFICs include radar and communications, but the term RFIC can apply to any electronic integrated circuit that operates in a frequency range suitable for wireless transmission. RFICs have the potential cost advantage of moving as many wireless transceivers as possible to a single technology, which in turn will allow system-on-a-chip solutions rather than the more common system-in-package.

[0083] MMIC design : A monolithic microwave integrated circuit or MMIC is a type of integrated circuit (IC) device that operates at microwave frequencies (300 MHz to 300 GHz). These devices perform functions such as microwave mixing, power amplification, low-noise amplification, and high-frequency switching. Inputs and outputs on MMIC devices are often matched to a 50-ohm impedance characteristic. This makes them easier to use, as cascading of MMICs does not require external matching networks. In addition, most microwave test equipment is designed to operate in a 50-ohm environment. MMICs are small in size (from about 1 mm 2 to 10 mm 2) and can be mass produced, which makes high frequency devices such as cellular phones possible. MMICs have two fundamental advantages over silicon (Si), the traditional material for IC implementation, device (transistor) speed and semi-insulating substrates. Both of these factors contribute to the ability to design high frequency circuit functions. However, as transistor feature sizes decrease, the speed of silicon-based technology is gradually increasing, and MMICs can also be fabricated with silicon technology. The main advantage of Si technology over GaAs is its lower manufacturing cost. Silicon wafers are larger in diameter (typically 8" to 15" vs. 4" to 8" for GaAs) and the wafer cost is lower, which contributes to lower IC cost. Gallium nitride (GaN) is an option for MMICs. Since GaN transistors can operate at much higher temperatures and much higher voltages than GaAs transistors, they are ideal power amplifiers at microwave frequencies.

[0084] High electron mobility transistor (HEMT) : Also known as heterostructure FET (HFET) or modulation doped FET (MODFET), is a type of field-effect transistor that incorporates a junction between two materials with different bandgaps (i.e., a heterojunction) instead of a doped region (as is typically the case for MOSFETs) into the channel. The material combination can be GaAs and AlGaAs, but varies greatly depending on the application of the device. Devices incorporating more indium generally exhibit better high-frequency performance, and gallium nitride HEMTs have high power performance. Like other FETs, HEMTs are used as digital switches in integrated circuits. FETs can also be used as amplifiers for large currents using a small voltage as a control signal. The unique current-voltage characteristics of FETs make both of these uses possible. HEMT transistors are capable of operating at higher frequencies than ordinary transistors, up to millimeter wave frequencies, and are used in high-frequency products such as cellular phones, satellite television receivers, voltage converters, and radar equipment. They are used in satellite receivers, low-power amplifiers, and the defense industry. Some advantages of HEMTs can be that they have high gain, which makes them useful as amplifiers; high switching speed, because the majority carrier is the primary charge carrier in MODFETs, and the minority carrier does not participate significantly; and extremely low noise values, because the current in these devices varies very little compared to other FETs. HEMTs are heterojunctions. This means that the semiconductors used have different bandgaps. For example, the bandgap of silicon is 1.1 electron volts (eV), while the bandgap of germanium is 0.67 eV. When a heterojunction is formed, the conduction and valence bands of the entire material must be bent to form a continuous energy level.

[0085] The superior carrier mobility and switching speed of HEMTs comes from the condition that a wide band element is doped with donor atoms; thus, it has excess electrons in its conduction band. Due to the availability of states with lower energy, these electrons will diffuse to the conduction band of the adjacent narrow band material. The movement of the electrons will cause a change in potential, thus creating an electric field between the materials. The electric field will push the electrons back to the conduction band of the wide band element. The diffusion process continues until the electron diffusion and electron drift are balanced with each other, thus creating a balanced junction similar to a p-n junction. Note that the undoped narrow band gap material now has an excess of majority charge carriers. The fact that the charge carriers are majority carriers results in high switching speed, while the fact that the low band gap semiconductor is not doped means that there are no donor atoms causing scattering, thus resulting in high mobility.

[0086] An important aspect of HEMTs is that the band discontinuity across the conduction and valence bands can be modified separately. This allows control of the type of carriers that go into and out of the device. Since HEMTs require electrons as the primary carriers, it is possible to apply graded doping in one material, thus making the conduction band discontinuity smaller and keeping the valence band discontinuity the same. This diffusion of carriers results in the accumulation of electrons along the boundary of the two regions within the narrow band gap material. The accumulation of electrons results in very high current in these devices. The accumulated electrons are also called 2DEG or two-dimensional electron gas. The term "modulation doping" refers to the fact that the dopant is spatially in a different region from the charge carriers.

[0087] To allow conduction, semiconductors are doped with impurities that provide mobile electrons or holes. However, these electrons are slowed down by collisions with the impurities (dopants) that were originally used to create them. HEMTs avoid this by using the high mobility electrons that are created by the heterojunction of a highly doped wide band gap n-type donor supply layer (AlGaAs in our example) and an undoped narrow band gap channel layer (GaAs) with no dopant impurities. The electrons created in the thin n-type AlGaAs layer fall completely into the GaAs layer, forming a depleted AlGaAs layer, because the heterojunction created by the different band gap materials forms a quantum well (steep canyon) in the conduction band on the GaAs side, where the electrons can move fast without colliding with any impurities, because the GaAs layer is not doped and they cannot escape from it. The effect of this is to form a very thin layer of highly mobile conducting electrons with a very high concentration, making the resistivity of the channel very low (or in other words, "high electron mobility"). Furthermore, HEMTs based on AlGaN / GaN heterostructures are excellent candidates for high power, high voltage, and high temperature applications.

[0088] Depletion mode (D-mode) HEMTIn field effect transistors (FETs), depletion mode and enhancement mode are two main transistor types, corresponding to whether the transistor is in an on state or an off state at zero gate-source voltage. Enhancement mode MOSFETs (metal oxide semiconductor FETs) are common switching elements in most integrated circuits. These devices turn off at zero gate-source voltage. NMOS can be turned on by pulling the gate voltage above the source voltage, and PMOS can be turned on by pulling the gate voltage below the source voltage. In most circuits, this means that pulling the gate voltage of an enhancement mode MOSFET toward its drain voltage turns it on. In depletion mode MOSFETs, the device is normally on at zero gate-source voltage. Such devices are used as load "resistors" in logic circuits (e.g., in depletion load NMOS logic). For N-type depletion load devices, the threshold voltage can be about -3V, so it can be turned off by pulling the gate negative 3V (by contrast, in NMOS, the drain is more positive than the source). In PMOS, the polarity is reversed. The type can be determined by the sign of the threshold voltage (the gate voltage relative to the source voltage at the point in the channel just forming an inversion layer): for N-type FETs, enhancement mode devices have a positive threshold, depletion mode devices have a negative threshold; for P-type FETs, enhancement mode is negative, depletion mode is positive.

[0089] Large scale IC design Very large scale integration (VLSI) is the process of creating integrated circuits (ICs) by combining millions of MOS transistors onto a single chip. Structured VLSI design is a modular approach that is used to save microchip area by minimizing interconnect structure area. This is obtained by repeating an arrangement of rectangular macroblocks that can be interconnected using abutting wiring. An example is the division of a layout of adders into a row of equal bit-slice cells. In complex designs, this structure can be achieved by hierarchical nesting.

[0090] Two-dimensional electron gas (2-DEG) 2DEG is a scientific model in solid state physics. It is a gas of electrons that can move freely in two dimensions but is strictly confined in the third. This strict confinement leads to quantized energy levels for motion in the third direction, which can then be neglected for most problems. Thus, the electrons appear to be embedded in a 2D sheet in a 3D world. A similar hole construction is called a two-dimensional hole gas (2DHG), and such systems have many useful and interesting properties.

[0091] Most 2DEGs are found in transistor-like structures made of semiconductors. The most common 2DEG is the electron layer in a MOSFET (metal-oxide-semiconductor field-effect transistor). When the transistor is in inversion mode, the electrons under the gate oxide are confined to the semiconductor-oxide interface, thus occupying a well-defined energy level. For sufficiently thin potential wells and not too high temperatures, only the lowest energy level is occupied (see figure caption), so electron motion perpendicular to the interface can be neglected. However, electrons can move freely parallel to the interface, hence they are quasi-two-dimensional.

[0092] For engineering, 2DEGs are high electron mobility transistors (HEMTs) and rectangular quantum wells. HEMTs are field-effect transistors that use a heterojunction between two semiconductor materials to confine electrons in a triangular quantum well. Electrons confined in the heterojunction of a HEMT exhibit higher mobility than those in a MOSFET because the former device uses an intentionally undoped channel, thus mitigating the deleterious effects of ionized impurity scattering. Two closely spaced heterojunction interfaces can be used to confine electrons in a rectangular quantum well. Careful selection of materials and alloy composition allows control of the carrier density within the 2DEG.

[0093] Electrons can also be confined to the surface of a material. For example, free electrons will float on the surface of liquid helium, can move freely along the surface, but will stick to the helium; some of the earliest work on 2DEGs was done using this system. In addition to liquid helium, there are solid insulators (such as topological insulators) that support surface conduction electron states.

[0094] Dangling bond In chemistry, a dangling bond is an unsatisfied valency on a fixed atom. Atoms with dangling bonds are also called fixed radicals or fixed free radicals, referring to their structural and chemical similarity to free radicals. To get enough electrons to fill their valence shell (see also octet rule), many atoms will form covalent bonds with other atoms. In the simplest case, in the case of a single bond, two atoms each contribute one unpaired electron, and the resulting electron pair is shared between them. Atoms with too few bonding partners to satisfy their valency and with unpaired electrons are called "free radicals"; thus, it is usually a molecule that contains such an atom. When a free radical exists in a fixed environment (for example, a solid), it is called a "fixed free radical" or "dangling bond".

[0095] Both free radicals and fixed radicals exhibit very different chemical properties from atoms and molecules that contain only complete bonds. In general, they are very reactive. Fixed radicals, like their mobile counterparts, are highly unstable, but they gain some kinetic stability due to limited mobility and steric hindrance. While the lifetime of a free radical is usually short, fixed radicals often exhibit longer lifetimes due to the reduction in reactivity.

[0096] Ferroelectricity : A property of certain materials that have a spontaneous electric polarization that can be reversed by the application of an external electric field. All ferroelectrics are pyroelectrics, the additional property that their natural polarization is reversible. The term is used by analogy with ferromagnetism, where materials exhibit a permanent magnetic moment.

[0097] Polarization : When most materials are polarized, the resulting polarization P is almost proportional to the applied external electric field E; so the polarization is a linear function. Some materials, called paraelectric materials, exhibit a stronger non-linear polarization. The dielectric constant, which corresponds to the slope of the polarization curve, is not constant like in a dielectric, but a function of the external electric field. In addition to the non-linearity, ferroelectric materials exhibit a spontaneous, non-zero polarization even when the applied field E is zero. The distinguishing feature of ferroelectrics is that the spontaneous polarization can be reversed by the application of a suitably strong electric field in the opposite direction. Thus, the polarization depends not only on the current electric field, but also on its history, giving rise to a hysteresis loop. They are called ferroelectrics, analogous to ferromagnetic materials, which have a spontaneous magnetization and exhibit similar hysteresis loops. Usually, a material exhibits ferroelectricity only below a certain phase transition temperature, called the Curie temperature (TC), and above this temperature it is paraelectric: the spontaneous polarization disappears and the ferroelectric crystal transforms into a paraelectric state. Many ferroelectrics completely lose their piezoelectric properties above TC, because their paraelectric phase has a centrosymmetric crystal structure. The non-linear properties of ferroelectric materials can be used to make capacitors whose capacitance is adjustable. Usually, a ferroelectric capacitor consists of only a pair of electrodes sandwiching a layer of ferroelectric material. The dielectric constant of a ferroelectric is not only adjustable, but also usually very high, especially close to the phase transition temperature. For this reason, ferroelectric capacitors have a small physical size compared to dielectric (non-adjustable) capacitors of similar capacitance.

[0098] Spontaneous polarization : The spontaneous polarization of ferroelectric materials implies a hysteresis effect that can be used as a memory function, and ferroelectric capacitors are indeed used to make ferroelectric RAM for computers and RFID cards. In these applications, thin films of ferroelectric material are usually used, because this allows the field needed to switch the polarization to be achieved at moderate voltages. However, when using thin films, great care needs to be taken of the interfaces, electrodes and sample quality for the device to work reliably.

[0099] Metal organic chemical vapor deposition (MOCVD) MOCVD, also known as metal-organic vapor phase epitaxy (MOVPE) or organometallic vapor phase epitaxy (OMVPE), is a chemical vapor deposition method used to produce single-crystal or polycrystalline thin films. MOCVD is a process that grows crystalline layers to create complex semiconductor multilayer structures. In contrast to molecular beam epitaxy (MBE), the growth of the crystal is by chemical reaction rather than physical deposition. This does not occur in a vacuum, but in a gas phase at moderate pressure (10 Torr to 760 Torr).

[0100] Molecular beam epitaxy (MBE) MBE is an epitaxy method for the deposition of single-crystal thin films. MBE processes are used to manufacture semiconductor devices including transistors and to manufacture diodes.

[0101] Remote plasma chemical vapor deposition (RPCVD) RPCVD is a low-temperature growth technique developed by BluGlass Limited for high-brightness LED applications. The unique growth conditions of RPCVD have been shown to produce activated as-grown (AAG) buried p-GaN to enable GaN-based tunnel junctions (TJs) for potential use in current spreading and cascaded LED and LD applications.

[0102] Sputtering Sputter deposition is a physical vapor deposition (PVD) method of thin film deposition by sputtering. This involves ejecting material from a "target" as a source onto a "substrate" such as a silicon wafer. Resputtering is the re-emission of deposited material by ion or atom bombardment in a deposition process. The sputtered atoms ejected from the target have a wide energy distribution, often up to tens of eV (100,000 K). The ions of the sputtering (usually only a small fraction of the ejected particles are ionized - about 1%) can fly out of the target in straight-line trajectories and strongly impact the substrate or the vacuum chamber (causing resputtering).

[0103] Pulsed laser deposition (PLD)PLD is a physical vapor deposition (PVD) technique in which a high-power pulsed laser beam is focused inside a vacuum chamber to impinge on a target of the material to be deposited. This material is evaporated from the target (in a plasma plume) to deposit as a thin film on a substrate (such as a silicon wafer facing the target). This process can be performed in ultra-high vacuum or in the presence of a background gas (such as oxygen, which is commonly used when depositing oxides) to fully oxidize the deposited thin film. While the basic setup is simple compared to many other deposition techniques, the physical phenomena of the laser-target interaction and thin film growth are quite complex. When the laser pulse is absorbed by the target, the energy is first converted into electronic excitation and then into thermal, chemical, and mechanical energy, resulting in evaporation, ablation, plasma formation, and even spallation. The ejected material expands into the surrounding vacuum in a plume containing many high-energy species, including atoms, molecules, electrons, ions, clusters, particulates, and molten spheres, before being deposited on a usually hot substrate.

[0104] Embodiments

[0105] The following description provides exemplary embodiments only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the following description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing one or more exemplary embodiments. Various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the subject matter disclosed in the appended claims.

[0106] In the following description, specific details are set forth to provide a thorough understanding of the embodiments. However, persons having ordinary skill in the art will appreciate that the embodiments can be practiced without the specific details. For example, the systems, processes, and other elements in the disclosed subject matter can be shown as elements in block diagram form, in order not to obscure the embodiments in unnecessary detail. In other instances, well-known processes, structures, and techniques have not been shown in detail in order not to obscure the embodiments.

[0107] Also, various embodiments can be described as a process depicted as a flowchart, flow diagram, data flow diagram, structure diagram, or block diagram. Although a flowchart can describe operations as a sequential process, many of the operations can be performed in parallel, or concurrently. In addition, the order of the operations can be re-arranged. A process can be terminated when its operations are completed, but could have additional steps not discussed or included in a figure. Further, not all operations in any described process need take place in the process. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.

[0108] Furthermore, implementations of the disclosed subject matter can be implemented, at least in part, manually or automatically. Manual or automatic implementations can be executed or at least assisted with the use of machines, hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks can be stored in a machine readable medium. Processors can perform the necessary tasks.

[0109] Furthermore, the embodiments of the present disclosure and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structural equivalents of such software, firmware, and hardware, or in combinations of one or more of them. Further embodiments of the present disclosure can be implemented as one or more computer program(s) i.e., one or more modules of computer program instructions encoded on a tangible non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. Furthermore, program instructions can be encoded on a propagated signal that is generated by one or more computer program instructions executed on a machine, such as a processor, or a computer. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0110] According to embodiments of the present disclosure, the term "data processing apparatus" can encompass all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers.

[0111] A computer program, which can also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub programs, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and are interconnected by a communication network. Computers suitable for the execution of a computer program include, by way of example, can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a central processing unit for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

[0112] While the present disclosure has been described with reference to certain preferred embodiments thereof, a variety of other modifications and variations are possible in light of the disclosure. Therefore, it is intended that the appended claims cover all such changes and modifications that fall within the true spirit and scope of this disclosure.

Claims

1. A field effect transistor, the field effect transistor comprising: a source; a gate; a drain; a semiconductor region underlying the source, the gate, and the drain, such that the semiconductor region comprises a gallium nitride (GaN) layer and a group-III nitride (III-N) layer, wherein the GaN layer comprises a bandgap and the III-N layer comprises a bandgap, such that the III-N layer bandgap is higher than the GaN layer bandgap; and a sub-region of the semiconductor region underlying the gate is doped with Mg ions at selected locations in the sub-region, wherein each selected location in the sub-region doped with Mg ions has a profile, such that the profile comprises a vertical profile length and a profile width, wherein the profile forms a pattern, such that the profile width increases along a direction from a first width end to a second width end of the field effect transistor, resulting in a higher linearity than a profile having a constant profile width in a direction from the first width end to the second width end of the field effect transistor.

2. The field effect transistor of claim 1, wherein, the semiconductor region comprises a base layer, a buffer layer over the base layer, wherein the GaN layer is over the buffer layer.

3. The field effect transistor of claim 1, wherein, The III-N layer is Al x In y Ga 1-x-y N, such that the values of x and y are between 0 and 1, 0 < x < 1, 0 < y < 1.

4. The field effect transistor of claim 1, wherein, the III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the GaN layer.

5. The field effect transistor of claim 1, wherein, a vertical thickness of the GaN layer is greater than a vertical thickness of the III-N layer.

6. The field effect transistor of claim 1, wherein, the vertical thickness of the GaN layer is 10 times the vertical thickness of the III-N layer.

7. The field effect transistor of claim 1, wherein, a gap distance between the source and the gate and a gap distance between the gate and the drain are symmetrical or asymmetrical.

8. The field effect transistor of claim 1, wherein, a gap distance between the gate and the drain is related to a breakdown voltage of the field effect transistor.

9. The field effect transistor of claim 1, wherein, each profile is equally spaced along a width of the field effect transistor, or wherein each profile is unequally spaced and varies along a width of the field effect transistor.

10. The field effect transistor of claim 1, wherein, the selected locations in the sub-region doped with Mg ions have a profile, such that the profile is arranged at an angle in a range of 90 degrees to 80 degrees.

11. The field effect transistor of claim 1, wherein, a build-up of a two-dimensional electron gas (2-DEG) exists at an interface of the GaN layer and III-N layer, such that the build-up of the 2-DEG is depleted by the III-N layer, resulting in an enhancement-mode (E-mode) operation for the field effect transistor.

12. The field effect transistor of claim 1, wherein, the doping of the Mg ions in the selected locations in the sub-region is followed by annealing the sub-region in a nitrogen environment.

13. The field effect transistor of claim 1, wherein, the III-N layer is an aluminum gallium nitride (AlGaN) layer, and wherein the selected locations in the sub-region doped with Mg ions convert the AlGaN layer to p-AlGaN and the GaN layer to p-GaN, which results in a generation of holes in the selected locations of the sub-region implanted with Mg ions.

14. The field effect transistor of claim 1, wherein, each selected location in the sub-region doped with Mg ions has a depth extending from a top edge of the III-N layer across an interface of a bottom edge of the III-N layer to a top edge of a GaN layer.

15. A transistor, the transistor comprising: a source; a gate; a drain; A semiconductor region is located under the source, the gate, and the drain such that the semiconductor region includes a gallium nitride, GaN, layer and a group-III nitride, III-N, layer, where the GaN layer includes a bandgap and the III-N layer includes a bandgap such that the III-N layer bandgap is higher than the GaN layer bandgap, where the GaN layer and the III-N layer are undoped; and A sub-region of the semiconductor region under the gate is doped with Mg ions at selected locations in the sub-region, where each selected location in the sub-region that is doped with Mg ions has a profile such that the profile includes a vertical profile length and a profile width, where the profile forms a pattern such that the profile width of the profile increases along a direction from a first width end to a second width end of the transistor resulting in a higher linearity than a profile having a constant profile width in a direction from the first width end to the second width end of the transistor.

16. The transistor of claim 15, wherein, The GaN layer and the III-N layer are grown using one or a combination of metal-organic chemical vapor deposition, MOCVD, molecular beam epitaxy, MBE, or remote plasma chemical vapor deposition, RPCVD, and where the selected locations in the sub-region that are doped with Mg ions are formed by Mg ion implantation.

17. A transistor, the transistor comprising: a source; a gate; a drain; a semiconductor region is located under the source, the gate, and the drain such that the semiconductor region includes a gallium nitride, GaN, layer and a group-III nitride, III-N, layer, where the GaN layer includes a bandgap and the III-N layer includes a bandgap such that the III-N layer bandgap is higher than the GaN layer bandgap, where the III-N layer has a higher spontaneous polarization charge than the GaN layer; and A sub-region of the semiconductor region under the gate is doped with Mg ions at selected locations in the sub-region, where each selected location in the sub-region that is doped with Mg ions has a profile such that the profile includes a vertical profile length and a profile width, where the profile forms a pattern such that the profile width of the profile increases along a direction from a first width end to a second width end of the transistor resulting in a higher linearity than a profile having a constant profile width in a direction from the first width end to the second width end of the transistor.

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