High-speed real-time transmission implementation system and method based on RapidIO protocol

Abstract

The present invention discloses a high-speed real-time transmission implementation system and method based on the RapidIO protocol, comprising a data exchange module that is simultaneously connected to a source device and a destination device, the data exchange module comprising an FPGA chip, the source device and the data exchange module exchanging data via a serial transceiver, the data exchange module and the destination device exchanging data via a RapidIO interface, and the serial transceiver and the RapidIO interface both being connected to the FPGA chip via a cache module. The system of the present invention is highly flexible, highly scalable, and easy to transplant. The present invention can increase or decrease the interface between the source device and the data exchange module FPGA, and the interface between the data exchange module FPGA and the destination device according to system requirements, and adjust the data transmission bandwidth by increasing or decreasing the interface. The present invention takes into account both high bandwidth and real-time performance, adopts multi-channel transmission, increases the transmission speed, and improves the transmission efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a system and method for realizing high-speed real-time transmission based on the RapidIO protocol. Background Art

[0002] The RapidIO bus is a high-performance interconnect bus based on packet switching. It is an interconnection protocol suitable for chip-to-chip and chassis-to-chassis connections. It has the advantages of high bandwidth, high reliability and low latency, and is suitable for the internal interconnection construction of real-time signal processing systems. Currently, most signal processing devices using the VPX architecture use the RapidIO bus as the system interconnection bus.

[0003] In high-speed digital signal processing systems, as sampling rates and channel counts increase, the amount of signal processing data increases, and the requirements for data transmission become increasingly stringent. Faced with digital signal streams of tens or even hundreds of Gbps, how to achieve high-speed, real-time transmission has become a bottleneck restricting the overall performance improvement of the signal processing system.

[0004] To meet the demand for real-time processing of high-bandwidth digital signals, existing signal processing systems using DSP / FPGA as core processing devices are widely used in fields such as radar signal processing and communication base station signal processing. FPGA chips, with their rich peripheral I / O interfaces and powerful parallel processing capabilities, enable the development of dedicated FPGA programs within systems composed of large-scale FPGA and DSP nodes to achieve real-time transmission of high-bandwidth signal data streams. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a high-speed real-time transmission implementation system and method based on the RapidIO protocol to solve the problem of high-speed real-time data transmission.

[0006] To achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is: a high-speed real-time transmission implementation system based on the RapidIO protocol, including a data exchange module that is simultaneously connected to a source device and a destination device, the data exchange module including an FPGA chip, the source device and the data exchange module exchanging data via a serial transceiver, the data exchange module and the destination device exchanging data via a RapidIO interface, and the serial transceiver and the RapidIO interface are both connected to the FPGA chip via a cache module.

[0007] Furthermore: there are three serial transceivers and two RapidIO interfaces.

[0008] A method for implementing high-speed real-time transmission based on the RapidIO protocol includes the following steps:

[0009] S1. The source device splits the data stream to be transmitted according to the bandwidth of the data stream to be transmitted and the rate and number of serial transceivers, and sends it to the data exchange module through the serial transceiver;

[0010] S2: After receiving the data, the FPGA chip on the data exchange module writes it into the asynchronous cache for clock domain isolation. When all asynchronous caches are not empty, the system clock and control unit synchronously read the data from all asynchronous caches and splice the data into one data stream according to the splitting rules of the source device.

[0011] S3. The FPGA chip on the data exchange module performs bit width conversion on the spliced ​​data stream according to the bus data bit width and the number of RapidIO interfaces. The converted data bus bit width is equal to the number of RapidIO interfaces N*64 bits.

[0012] S4, split the data stream after bit width conversion into N channels of 64-bit bus data and write them into the asynchronous cache;

[0013] S5: The RapidIO interface reads the corresponding asynchronous cache status. If the cache is not empty, it encapsulates the data based on the idle state of the RapidIO interface and sends it out.

[0014] S6. The destination device restores the data stream according to the pre-agreed RapidIO interface sequence. The destination device splits the high-speed data stream according to the bandwidth of the data to be transmitted and the rate and number of RapidIO interfaces, and sends the data to the data exchange module through the RapidIO interface.

[0015] S7: The FPGA chip on the data exchange module verifies the RapidIO message and writes the correct data into the respective asynchronous buffers for clock domain isolation.

[0016] S8. When all asynchronous cache data are not empty, data is synchronously read from all asynchronous caches through the system clock and control unit, the data is spliced ​​into one data stream, and the bit width of the spliced ​​bus data is converted according to the bus data bit width and the serial transceiver rate and number. The data is split and sent to the serial transceiver interface processing cache. Finally, the data is read and packaged according to the serial transceiver status and sent to the source device.

[0017] Furthermore: the bandwidth of the data stream to be transmitted is 192 bits.

[0018] Furthermore: the rate of the serial transceiver is 64 bits, and the number of the serial transceivers is 3.

[0019] Furthermore, the number N of RapidIO interfaces is 2.

[0020] Furthermore: the FPGA chip adopts the AURORA protocol, and the FPGA chip receives data through the AURORA interface.

[0021] The beneficial effects of the present invention are:

[0022] 1. The system of the present invention is highly flexible, scalable, and easy to transplant. The present invention can increase or decrease the interfaces between the source device and the data exchange module FPGA, and between the data exchange module FPGA and the destination device, according to system requirements. By increasing or decreasing the interfaces, the data transmission bandwidth can be adjusted.

[0023] 2. The present invention takes into account both high bandwidth and real-time performance, adopts multi-channel transmission, increases transmission speed, and improves transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a block diagram of the system composition of the present invention;

[0025] Figure 2 Schematic diagram of bit width conversion in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0027] like Figure 1 and Figure 2 As shown, a high-speed real-time transmission implementation system based on the RapidIO protocol includes a data exchange module that is simultaneously connected to a source device and a destination device. The data exchange module includes an FPGA chip. The source device and the data exchange module exchange data via a serial transceiver. The data exchange module and the destination device exchange data via a RapidIO interface. The serial transceiver and the RapidIO interface are both connected to the FPGA chip via a cache module.

[0028] A method for implementing high-speed, real-time data transmission based on the RapidIO protocol includes: a data exchange module that is simultaneously connected to a source device and a destination device, the source device and the data exchange module exchanging data via three serial transceivers, the data exchange module and the destination device exchanging data via two RapidIO interfaces, the data exchange module including an FPGA chip, the data stream to be sent in the source device has a bit width of 192 bits, the data is split into three 64-bit data streams of equal bit width, and the data is sent to the data exchange module via serial transceivers respectively, and the protocol can adopt the AURORA protocol; after receiving data via the AURORA interface, the data exchange module FPGA writes the data into the corresponding asynchronous cache for clock domain isolation; when all asynchronous cache data are not empty, the system clock and control unit synchronously read data from all asynchronous caches, and merge the three 64-bit data streams into one 192-bit data stream; the data exchange module FPGA performs bit width conversion on the data stream, converts it into one 128-bit data stream, and then splits it into two 64-bit data streams of equal bit width and writes it into the cache; the RapidIO interface reads the corresponding cache status, and when it finds that the cache is not empty, the data is blocked according to the idle state of the interface. The destination device can write two RapidIO data streams into their respective corresponding asynchronous caches. When all asynchronous cache data is not empty, the system clock and control unit synchronously read data from the two asynchronous caches, merge the two 64-bit data streams into one 128-bit data stream, and finally perform bit width conversion, thereby achieving complete reception of the data stream sent by the source device. At the same time, the destination device converts the data to be sent into one 128-bit data stream, then splits it into two 64-bit data streams and writes them into the cache. The destination device RapidIO interface reads the corresponding cache status. If the cache is not empty, it encapsulates the data according to the interface idle state and sends it out. The data exchange module FPGA writes the received two RapidIO data streams into their respective corresponding caches. When all asynchronous cache data is not empty, the system clock and control unit synchronously read data from the two asynchronous caches, merge the two 64-bit data streams into one 128-bit data stream. The data exchange module FPGA performs bit width conversion on the data stream, converts it into one 192-bit data stream, and then splits it into three 64-bit data streams of equal bit width and writes them into the cache. The AURORA interface reads the corresponding cache status. When it finds that the cache is not empty, it encapsulates the data according to the idle state of the interface and sends it out. After the source device serial transceiver receives the data, it writes it into the cache. When all asynchronous cache data are not empty, the system clock and control unit synchronously read data from the three caches, merge the three 64-bit data streams into one 192-bit data stream, and finally perform bit width conversion, thereby realizing the complete reception of the data stream sent by the destination device.

Claims

1. A method for implementing high-speed real-time transmission based on RapidIO protocol, characterized in that: The following steps are involved: S1. The source device splits the data stream to be transmitted according to the bandwidth of the data stream to be transmitted and the rate and number of serial transceivers, and sends it to the data exchange module through the serial transceiver; S2: After receiving the data, the FPGA chip on the data exchange module writes it into the asynchronous cache for clock domain isolation. When all asynchronous caches are not empty, the system clock and control unit synchronously read the data from all asynchronous caches and splice the data into one data stream according to the splitting rules of the source device. S3. The FPGA chip on the data exchange module performs bit width conversion on the spliced ​​data stream according to the bus data bit width and the number of RapidIO interfaces. The converted data bus bit width is equal to the number of RapidIO interfaces N*64 bits. S4, split the data stream after bit width conversion into N channels of 64-bit bus data and write them into the asynchronous cache; S5: The RapidIO interface reads the corresponding asynchronous cache status. If the cache is not empty, it encapsulates the data based on the idle state of the RapidIO interface and sends it out. S6. The destination device restores the data stream according to the pre-agreed RapidIO interface sequence. The destination device splits the high-speed data stream according to the bandwidth of the data to be transmitted and the rate and number of RapidIO interfaces, and sends the data to the data exchange module through the RapidIO interface. S7: The FPGA chip on the data exchange module verifies the RapidIO message and writes the correct data into the respective asynchronous buffers for clock domain isolation. S8. When all asynchronous cache data are not empty, data is synchronously read from all asynchronous caches through the system clock and control unit, the data is spliced ​​into one data stream, and the bit width of the spliced ​​bus data is converted according to the bus data bit width and the serial transceiver rate and number. The data is split and sent to the serial transceiver interface processing cache. Finally, the data is read and packaged according to the serial transceiver status and sent to the source device.

2. The method for implementing high-speed real-time transmission based on the RapidIO protocol according to claim 1, wherein: The bandwidth of the data stream to be transmitted is 192 bits.

3. The method for implementing high-speed real-time transmission based on the RapidIO protocol according to claim 1, wherein: The serial transceiver has a rate of 64 bits and is 3 in number.

4. The method for implementing high-speed real-time transmission based on the RapidIO protocol according to claim 1, wherein: The number N of RapidIO interfaces is 2.

5. The method for implementing high-speed real-time transmission based on the RapidIO protocol according to claim 1, wherein: The FPGA chip adopts the AURORA protocol, and the FPGA chip receives data through the AURORA interface.

6. A high-speed real-time transmission implementation system based on RapidIO protocol, characterized in that: The system is used to implement the high-speed real-time transmission implementation method according to any one of claims 1 to 5; the system includes a data exchange module that is simultaneously connected to a source device and a destination device, the data exchange module includes an FPGA chip, the source device and the data exchange module exchange data via a serial transceiver, the data exchange module and the destination device exchange data via a RapidIO interface, and the serial transceiver and the RapidIO interface are both connected to the FPGA chip via a cache module.

7. The high-speed real-time transmission implementation system based on RapidIO protocol according to claim 6, characterized in that: There are three serial transceivers and two RapidIO interfaces.

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