Stacked package structure based on organic carrier board and rdl and method of manufacture

Abstract

The organic carrier board and RDL-based stacked packaging structure and the preparation method have the advantages that the organic carrier board is combined with the first RDL composite layer and the second RDL composite layer, the first chip is accommodated in the organic carrier board and electrically connected with the first RDL composite layer, the second chip is electrically connected with the first RDL composite layer, and the first RDL composite layer is combined with the organic carrier board and electrically connected with the second RDL composite layer to perform electrical lead-out through tin balls. The application is suitable for large-area manufacturing, can improve production capacity, reduce cost, improve design flexibility, improve packaging reliability, reduce packaging thickness, reduce thermal resistance, shorten interconnection path, realize densification, fine packaging, flexible packaging, make signal transmission faster, and improve the application range.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of packaging, and relates to a stacked packaging structure based on an organic carrier board and RDL and a preparation method thereof. BACKGROUND

[0002] With the development of electronic products towards high density and miniaturization, the packaging feature size is getting smaller and smaller and gradually approaching the limit. The way of continuously improving the integration by reducing the feature size is no longer applicable. Electronic packaging begins to develop in the vertical direction (Z direction) on the basis of previous 2D packaging, forming 3D packaging technology represented by stacked package and through-silicon-via (TSV). Packaging thus enters the era of three-dimensional high-density packaging. At present, 2.5D and 3D high-density packaging gradually replace traditional 2D packaging (such as QFP, PQFN, BGA and CSP packaging), becoming the development trend of packaging technology.

[0003] As a widely used stacked three-dimensional packaging technology, PoP (Package-on-Package) packaging can flexibly stack chips in the vertical direction without increasing the product size on the basis of compatible existing standard surface mount technology (SMT) process. PoP packaging has strong assembly flexibility and expandability, can completely replace previous separate or parallel distributed packaging forms, realizes the mixed integration of a higher number of different devices, and is widely used in various mobile communication consumer electronic products such as smart phones, tablet computers and notebook computers.

[0004] The traditional PoP packaging structure, such as Figure 1 , usually adopts a BGA structure as the connection between the upper and lower two layers of packaging. This packaging structure makes the packaging cost larger, the packaging size larger, the interconnection density of the circuit lower, and the connection mode of the chip makes the transmission efficiency of current and signal low. The gap of the upper and lower packaging structures is large, and the upper and lower layers are separated by air. As a poor conductor, air will cause the problem of chip heat dissipation. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a stacked packaging structure based on an organic carrier board and RDL and a preparation method thereof, which solves the problem of stacked packaging in the prior art.

[0006] To achieve the above-mentioned purposes and other related purposes, the present application provides a stacked packaging structure based on an organic carrier board and RDL, which comprises:

[0007] An organic carrier plate, comprising a first surface and a second opposite surface, the organic carrier plate comprising an organic core layer and metal layers on opposite sides of the organic core layer and electrically connected to each other, the organic carrier plate having a through slot therein;

[0008] A first chip, disposed in the through slot, and a pad of the first chip being on the same side as the first surface of the organic carrier plate;

[0009] A first RDL composite layer, disposed on the first surface of the organic carrier plate, the first RDL composite layer comprising a first insulating medium layer and a first metal connection layer, and the first metal connection layer being electrically connected to the pad of the first chip and the metal layer of the organic carrier plate;

[0010] A second RDL composite layer, disposed on the second surface of the organic carrier plate, the second RDL composite layer comprising a second insulating medium layer and a second metal connection layer, the second insulating medium layer filling the through slot and covering the first chip and the second surface of the organic carrier plate, and the second metal connection layer being electrically connected to the metal layer of the organic carrier plate;

[0011] A second chip, disposed on the first RDL composite layer, and the second chip being electrically connected to the first metal connection layer;

[0012] A packaging layer, disposed on the first RDL composite layer, covering the first RDL composite layer and encapsulating the second chip;

[0013] A solder resist layer, disposed on the second RDL composite layer, covering the second RDL composite layer and having a recess in the solder resist layer exposing the second metal connection layer;

[0014] A solder ball, disposed in the recess, one end of the solder ball being electrically connected to the second metal connection layer and the other end of the solder ball being exposed from the solder resist layer.

[0015] Optionally, the packaging structure comprises a plurality of the first chips, and the pads corresponding to the first chips are on the same plane; and the packaging structure comprises a plurality of the second chips.

[0016] Optionally, the second chip is electrically connected to the first metal connection layer through a metal bump formed by electroplating.

[0017] Optionally, the first RDL composite layer comprises the first metal connection layer stacked and electrically connected; and the second RDL composite layer comprises the second metal connection layer stacked and electrically connected.

[0018] Optionally, the line width of the first metal connection layer is greater than or equal to 1 μm, and the line spacing of the first metal connection layer is greater than or equal to 1 μm; the line width of the second metal connection layer is greater than or equal to 1 μm, and the line spacing of the second metal connection layer is greater than or equal to 1 μm.

[0019] Optionally, the first insulating medium layer comprises a photosensitive medium layer or a non-photosensitive medium layer; and the second insulating medium layer comprises a photosensitive medium layer or a non-photosensitive medium layer.

[0020] Optionally, the packaging structure comprises a fan-out packaging structure or a fan-in packaging structure.

[0021] The present application also provides a preparation method of the packaging structure based on the organic carrier board and the RDL, comprising the following steps:

[0022] providing an organic carrier board, wherein the organic carrier board comprises a first surface and an opposite second surface, the organic carrier board comprises an organic core layer and metal layers located on opposite surfaces of the organic core layer and electrically connected to each other, and the organic carrier board has a through slot;

[0023] providing a support substrate, and bonding the support substrate to the first surface of the organic carrier board;

[0024] providing a first chip, and placing the first chip in the through slot, wherein the pads of the first chip face the support substrate;

[0025] removing the support substrate to form a first RDL composite layer and a second RDL composite layer, wherein the first RDL composite layer is located on the first surface of the organic carrier board, the first RDL composite layer comprises a first insulating medium layer and a first metal connection layer, and the first metal connection layer is electrically connected to the pads of the first chip and the metal layers of the organic carrier board; the second RDL composite layer is located on the second surface of the organic carrier board, the second RDL composite layer comprises a second insulating medium layer and a second metal connection layer, the second insulating medium layer fills the through slot and covers the first chip and the second surface of the organic carrier board, and the second metal connection layer is electrically connected to the metal layers of the organic carrier board;

[0026] forming a solder resist layer on the surface of the second RDL composite layer;

[0027] forming a groove in the solder resist layer, wherein the groove exposes the second metal connection layer;

[0028] forming a tin ball in the groove, and forming a second chip and a packaging layer on the first RDL composite layer, one end of the tin ball is electrically connected with the second metal connecting layer, and the other end is exposed on the solder mask layer; the second chip is located on the first RDL composite layer, and the second chip is electrically connected with the first metal connecting layer; the packaging layer is located on the first RDL composite layer, covering the first RDL composite layer and covering the second chip.

[0029] Optionally, the second chip is electrically connected with the first metal connecting layer through a metal bump, and the method for forming the metal bump comprises an electroplating method.

[0030] Optionally, the first insulating medium layer comprises a photosensitive medium layer or a non-photosensitive medium layer; the second insulating medium layer comprises a photosensitive medium layer or a non-photosensitive medium layer; when the insulating medium layer is a non-photosensitive medium layer, the method for patterning comprises laser, and when the insulating medium layer is a photosensitive medium layer, the method for patterning comprises dry etching or wet etching.

[0031] As described above, the organic carrier board and RDL-based stacked packaging structure and preparation method of the present application combines the organic carrier board with the first RDL composite layer and the second RDL composite layer, accommodates the first chip in the organic carrier board and electrically connects the first chip with the first RDL composite layer, and electrically connects the second chip with the first RDL composite layer, and electrically connects the first RDL composite layer with the organic carrier board and the second RDL composite layer, so as to electrically lead out through the tin ball.

[0032] The present application is suitable for large-area manufacturing, can improve production capacity and reduce cost; through the setting of the RDL composite layer, a part of the internal circuit of the chip can be replaced, and the stacked structure provides flexibility for chip design, can be flexibly mixed and connected, so as to meet the demand, reduce the complexity and cost of design; the first RDL composite layer is directly electrically connected with the pad of the first chip, and the second chip is electrically connected with the first RDL composite layer through a metal bump, so as to reduce stress and improve packaging reliability; the combination of the RDL composite layer can reduce the packaging thickness, shorten the conduction distance between chips, realize densification and fine of the circuit, meet the demand of thin and small packaging; the fan-out packaging structure can make the size of the packaged chip larger, and can also make the I / O contact pitch more flexible; thus, the organic carrier board and RDL-based stacked packaging structure and preparation method of the present application can reduce cost, reduce thermal resistance, improve reliability, shorten the interconnection path, realize densification, fine and flexibility of packaging, make signal transmission faster, improve the application range, and can meet the demand of future cloud infrastructure, 5G, automatic driving and artificial intelligence and the like. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A PoP packaging structure in the prior art is shown.

[0034] Figure 2 A flow chart of a preparation process of the organic carrier board and RDL based stacked package structure in the embodiment of the present application is shown.

[0035] Figures 3-20 A structural schematic diagram of the organic carrier board and RDL based stacked package structure in the embodiment of the present application in each step of the preparation process is shown.

[0036] Element number explanation

[0037] 100 organic carrier board

[0038] 101 organic core layer

[0039] 102 metal layer

[0040] 201 first chip

[0041] 202 second chip

[0042] 301 first sub-insulating medium layer

[0043] 3011 first sub-insulating medium layer opening

[0044] 302 second sub-insulating medium layer

[0045] 3021 second sub-insulating medium layer opening

[0046] 303 third sub-insulating medium layer

[0047] 3031 third sub-insulating medium layer opening

[0048] 401 first Ti / Cu metal deposition layer

[0049] 402 second Ti / Cu metal deposition layer

[0050] 403 third Ti / Cu metal deposition layer

[0051] 501 first resist layer

[0052] 502 second resist layer

[0053] 601 first sub-metal connection layer

[0054] 602 second sub-metal connection layer

[0055] 603 third sub-metal connection layer

[0056] 700 solder resist layer

[0057] 701 groove

[0058] 800 solder ball

[0059] 900 metal bump

[0060] 110 encapsulation layer DETAILED DESCRIPTION

[0061] Following, embodiments of the present application will be described in detail by way of specific examples. Other advantages and effects of the present application will be readily understood from this description by those skilled in the art. The present application can also be carried out or applied by other different embodiments, and various modifications or changes can be made based on different views and applications without departing from the spirit of the present application.

[0062] In describing embodiments of the present application, the cross-sectional views will be described with the components of the devices drawn in a general orientation, but will be shown in a partially enlarged manner for convenience of explanation, and the schematic views are only examples and should not limit the scope of the present application. In addition, three-dimensional spatial dimensions of length, width and depth should be included in actual fabrication.

[0063] For the convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatial relationship words are intended to include other orientations of the device in use or operation in addition to the orientations depicted in the drawings. In addition, when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0064] In the context of the present application, the structure described with the first feature "on" the second feature can include the embodiment in which the first and second features are formed in direct contact, and can also include the embodiment in which another feature is formed between the first and second features, so that the first and second features can not be in direct contact.

[0065] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be a random change in shape, number and proportion, and the layout pattern of the components can also be more complex.

[0066] Referring to Figure 2 The embodiment provides a preparation method of a stacked package structure based on an organic carrier board and RDL, including the following steps:

[0067] S1: Providing an organic carrier, the organic carrier comprising a first surface and an opposite second surface, the organic carrier comprising an organic core layer and metal layers located on two opposite surfaces of the organic core layer and electrically connected to each other, the organic carrier having a through groove;

[0068] S2: providing a supporting substrate, and attaching the supporting substrate to the first surface of the organic carrier;

[0069] S3: providing a first chip, and placing the first chip in the through-groove, with the pad of the first chip facing the supporting substrate;

[0070] S4: removing the supporting substrate to form a first RDL composite layer and a second RDL composite layer, wherein the first RDL composite layer is located on the first surface of the organic carrier, the first RDL composite layer includes a first insulating dielectric layer and a first metal connection layer, and the first metal connection layer is electrically connected to the pad of the first chip and the metal layer of the organic carrier; the second RDL composite layer is located on the second surface of the organic carrier, the second RDL composite layer includes a second insulating dielectric layer and a second metal connection layer, the second insulating dielectric layer fills the through groove and covers the first chip and the second surface of the organic carrier, and the second metal connection layer is electrically connected to the metal layer of the organic carrier;

[0071] S5: forming a solder resist layer on the surface of the second RDL composite layer;

[0072] S6: forming a groove in the solder resist layer, wherein the groove exposes the second metal connection layer;

[0073] S7: forming a solder ball in the groove, and forming a second chip and a packaging layer on the first RDL composite layer, wherein one end of the solder ball is electrically connected to the second metal connection layer, and the other end is exposed in the solder resist layer; the second chip is located on the first RDL composite layer, and the second chip is electrically connected to the first metal connection layer; the packaging layer is located on the first RDL composite layer, covering the first RDL composite layer and encapsulating the second chip.

[0074] The following is combined with Figures 3-20 , further introduces the preparation of stacked packaging structure based on organic carrier and RDL.

[0075] like Figure 3 First, step S1 is performed to provide an organic carrier 100, wherein the organic carrier 100 includes a first surface and an opposite second surface, the organic carrier 100 includes an organic core layer 101 and metal layers 102 located on two opposite surfaces of the organic core layer 101 and electrically connected to each other, and the organic carrier 100 has a through groove.

[0076] Specifically, the organic carrier board 100 can include the steps of drilling → electroplating → film pasting → exposure → development → etching when being prepared, so as to drill through holes on the organic core layer 101 and form the patterned and electrically connected metal layer 102 on the opposite two surfaces of the organic core layer 101, and then the through groove for placing the first chip 201 can be made on the area of the bare organic core layer 101 without the metal layer 102 by using, for example, laser, the size of the through groove is preferably similar to the size of the first chip 201 to be pasted subsequently, only needs to add 5 μm ~ 100 μm, such as 5 μm, 10 μm, 50 μm, 100 μm, etc. on each side of the size of the first chip 201, and the specific setting can be made according to the needs.

[0077] The organic carrier board 100 can be a glass fiber cloth coated with resin and copper clad board, and the resin can be epoxy resin, high-temperature-resistant epoxy resin, polyimide resin (PI), polytetrafluoroethylene resin (PTFE), bismaleimide modified triazine resin (BT), polypropylene resin (PPE), polyether ketone resin (PEK), polyetherimide resin (PEI), polyethylene (PE), polysulfone resin and polyphenyl ether resin (PPO), etc. The metal layer 102 can be copper foil including electrolytic copper and calendered copper, but is not limited thereto.

[0078] Then, steps S2 and S3 are performed to provide a support substrate (not shown) and adhere the support substrate to the first surface of the organic carrier board 100; provide the first chip 201 and place the first chip 201 in the through groove, and the pads of the first chip 201 face the support substrate.

[0079] Specifically, an organic adhesive tape can be pasted on the first surface of the organic carrier board 100 as the support substrate, and then the active surface of the first chip 201 with pads faces the support substrate and is placed in the through groove, but the type of the support substrate is not limited thereto.

[0080] Preferably, the pads of the first chip 201 are at the same height as the metal layer 102 on the first surface of the organic carrier board 100, i.e. on the same plane, so as to facilitate subsequent electrical connection.

[0081] Preferably, the pads corresponding to the plurality of first chips 201 are on the same plane, so as to facilitate subsequent electrical connection. The number and distribution of the first chips 201 are not limited here.

[0082] Then, step S4 is performed to remove the support substrate to form a first RDL composite layer and a second RDL composite layer, the first RDL composite layer is located on the first surface of the organic carrier 100, the first RDL composite layer comprises a first insulating medium layer and a first metal connection layer, and the first metal connection layer is electrically connected with the pads of the first chip 201 and the metal layer of the organic carrier 100; the second RDL composite layer is located on the second surface of the organic carrier 100, the second RDL composite layer comprises a second insulating medium layer and a second metal connection layer, the second insulating medium layer fills the through slot and covers the first chip 201 and the second surface of the organic carrier, and the second metal connection layer is electrically connected with the metal layer of the organic carrier 100.

[0083] For example, the first RDL composite layer comprises the first metal connection layer in stack and electrical connection; the second RDL composite layer comprises the second metal connection layer in stack and electrical connection.

[0084] Specifically, in the embodiment, the first RDL composite layer comprises two layers of the first metal connection layer, i.e. a first sub-metal connection layer 601 and a second sub-metal connection layer 602, and corresponding first and second sub-insulating medium layers 301 and 302, the second RDL composite layer comprises one layer of the second metal connection layer, i.e. a third sub-metal connection layer 603, and corresponding third sub-insulating medium layer 303, but the number of layers of the metal connection layer in the first RDL composite layer and the second RDL composite layer is not limited to this.

[0085] Participate Figures 3-18 Specifically, the preparation of the first RDL composite layer and the second RDL composite layer can comprise the following steps:

[0086] First, step S4-1 is performed to remove the support substrate to expose the pads of the first chip 201.

[0087] Next, step S4-2 is performed to first form a third sub-insulating dielectric layer 303. The third sub-insulating dielectric layer 303 fills the through-trench and covers the first chip 201 and the second surface of the organic carrier 100. The third sub-insulating dielectric layer 303 can fill the gap between the first chip 201 and the organic carrier 100 and then solidify to embed the first chip 201. The first chip 201 can have a thickness of 100 μm and dimensions of 10×10 mm. The third sub-insulating dielectric layer 303 is preferably made of ABF material, which has good fluidity, heat dissipation, and is convenient for subsequent processing. Of course, other organic materials can also be used to fill the remaining portion of the through-trench as needed. The thickness, type, and size of the first chip 201 can be selected as needed.

[0088] Next, see Figure 3 and Figure 4 , executing step S4-3, a first sub-insulating dielectric layer 301 can be formed on the first surface of the organic carrier 100 by coating or vacuum lamination, and then the first sub-insulating dielectric layer opening 3011 can be formed on the first sub-insulating dielectric layer 301 by exposure, development or laser processing.

[0089] As an example, the first insulating medium layer may include a non-photosensitive insulating medium layer or a photosensitive insulating medium layer; and the second insulating medium layer may include a non-photosensitive insulating medium layer or a photosensitive insulating medium layer.

[0090] Specifically, if the first sub-insulating dielectric layer 301 is a non-photosensitive dielectric layer, the first sub-insulating dielectric layer openings 3011 may be formed by laser etching. If the first sub-insulating dielectric layer 301 is a photosensitive dielectric layer, the first sub-insulating dielectric layer openings 3011 may be formed by dry or wet etching. The material of the first sub-insulating dielectric layer 301 may include PI, ABF, epoxy resin, etc. The thickness of the first sub-insulating dielectric layer 301 may be 5 μm, the diameter of the first sub-insulating dielectric layer openings 3011 may be 35 μm, and the opening spacing may be 60 μm. The thickness, opening size, and morphology of the first sub-insulating dielectric layer 301 are not excessively limited herein. The corresponding second sub-insulating dielectric layer 302 and third sub-insulating dielectric layer 303 may refer to the first sub-insulating dielectric layer 301 and will not be described in detail below.

[0091] In particular, the first sub-insulating medium layer 301 can be formed by the method of film pasting, exposure, development, UV curing and thermal curing under dry process. Under wet process, spin coating or slot coating process can be used. Under spin coating process, the patterning can be formed by the method of cold plate, spin coating, baking plate, cooling, exposure, post-baking, development and post-curing. Under slot coating process, the patterning can be formed by the process of plasma impurity removal, coating, VCD vacuum baking, pre-baking, exposure, development and post-curing.

[0092] Then, referring to Figure 5 , step S4-4 is performed to form the first Ti / Cu metal deposition layer 401.

[0093] In particular, the first Ti / Cu metal deposition layer 401 can be deposited by physical vapor deposition (PVD) in this step. The Ti / Cu layer deposited by PVD has good controllability and repeatability of thickness, wide application range, and good adhesion to the substrate. A layer of Ti metal is first deposited because the Ti metal layer has high conductivity and adhesion, and good thickness uniformity, so that the subsequently formed first sub-metal connection layer 601 can be firmly fixed on the first sub-insulating medium layer 301. The thickness of the first Ti / Cu metal deposition layer 401 after deposition can be 300-500 nm, with a thickness deviation of <5%.

[0094] Then, referring to Figure 6 , step S4-5 is performed to form the first resist layer 501 on the first Ti / Cu metal deposition layer 401.

[0095] Then, referring to Figure 7 , step S4-6 is performed to expose and develop the first resist layer 501 to form a patterned first resist layer 501.

[0096] In particular, the first resist layer 501 can be a photosensitive resist layer, which can be formed by film pasting, spin coating or slot coating. The material of the first resist layer 501 can include acrylic acid and polymer adhesive, etc. The first resist layer 501 can be manufactured by dry or wet process. In particular, under dry process, the patterning process includes film pasting, exposure, development, UV curing and thermal curing. Under wet process, spin coating or slot coating process can be used. Under spin coating process, the patterning process can include cold plate, spin coating, baking plate, cooling, exposure, post-baking, development and post-curing. Under slot coating process, the patterning process includes plasma impurity removal, coating, VCD vacuum baking, pre-baking, exposure, development and post-curing.

[0097] Then, referring to Figure 8After step S4-7, a first sub-metal connection layer 601, such as a Cu metal connection layer, can be formed between the patterned first resist layer 501 by electroplating.

[0098] Specifically, since high-speed electroplating has higher electroplating efficiency and mass transfer, a higher quality and more uniform Cu plating layer can be obtained, so that a Cu metal connection layer can be formed between the first resist layer 501 by high-speed electroplating as the first sub-metal connection layer 601. The manufacturing process of the Cu metal layer can include high-pressure water washing, high-pressure acid washing, electroplating, water washing, and drying. The RDL is ultra-fine line, so the ratio of Cu plating thickness to line width is preferably 1:1, the Cu plating layer material should include medium-high purity electroplated copper with elongation not less than 22% and sulfur content not higher than 9.6ppm, the Cu plating layer thickness deviation is <5%, and the thickness can be 5μm.

[0099] Referring back to Figure 9 and Figure 10 , step S4-8 is performed to form the first sub-metal connection layer 601 on the first sub-insulating medium layer 301 by film removal, flash etching, and Ti layer etching.

[0100] Specifically, the first resist layer 501, Cu, and Ti between the first sub-metal connection layer 601 are etched in sequence using the film removal, flash etching, and Ti etching process to complete the manufacturing of the first sub-metal connection layer 601. Wet or dry etching can be used for etching, and the chemical reagent for wet etching can include H2SO4+H2O2 and weak acid+H2O2, HF or non-HF (NaOH+H2O2), NaHCO3, NaOH, a mixture of NaHCO3 / H2O2, a mixture of NaHCO3 / NaOH / H2O2, or an aqueous solution of alkali metal hydroxide. The aqueous solution of alkali metal hydroxide can be NaOH, KOH, etc. Dry etching can be achieved by ion milling, reactive ion etching, and plasma etching, including but not limited to argon, nitrogen, fluorine-based gas, or a combination thereof as the process gas to perform etching.

[0101] As needed, referring to Figures 11-18 , the above steps S4-3 to S4-8 can be repeated to form the second sub-insulating medium layer 302, the second sub-insulating medium layer opening 3021, the second Ti / Cu metal deposition layer 402, the second resist layer 502, the second sub-metal connection layer 602, the third sub-insulating medium layer opening 3031, the third Ti / Cu metal deposition layer 403, and the third sub-metal connection layer 603 in sequence.

[0102] Wherein, the above steps S4-3~S4-8 can be performed multiple times as needed, so that the first RDL composite layer can include N layers of the metal connection layer prepared and electrically connected based on the metal connection layer of the lower layer, N≥2, such as 2 layers, 3 layers, 4 layers, etc., and so that the second RDL composite layer can include M layers of the metal connection layer prepared and electrically connected based on the metal connection layer of the lower layer, M≥2, such as 2 layers, 3 layers, 4 layers, etc., and the specific number of repetitions can be selected as needed, and in the embodiment, only the formation of a first RDL composite layer with 2 layers of metal connection layers and a second RDL composite layer with 1 layer is taken as an example, but not limited thereto.

[0103] As an example, the line width of the metal connection layer in the first RDL composite layer is ≥1μm, such as 1μm, 2μm, 5μm, etc., and the line spacing of the metal connection layer in the first RDL composite layer is ≥1μm, such as 1μm, 2μm, 5μm, etc.; the line width of the metal connection layer in the second RDL composite layer is ≥1μm, such as 1μm, 2μm, 5μm, etc., and the line spacing of the metal connection layer in the second RDL composite layer is ≥1μm, such as 1μm, 2μm, 5μm, etc.

[0104] Next, referring to Figure 19 , step S5 is performed to form a solder mask layer 700 on the surface of the second RDL composite layer, and step S6 is performed to form a groove 701 in the solder mask layer 700, which exposes the metal connection layer.

[0105] Next, referring to Figure 20 , step S7 is performed to form a tin ball 800 in the groove 701, and a second chip 202 and a packaging layer 110 are formed on the first RDL composite layer, one end of the tin ball 900 is electrically connected to the second metal connection layer, and the other end is exposed on the solder mask layer 700; the second chip 202 is located on the first RDL composite layer, and the second chip 202 is electrically connected to the first metal connection layer; the packaging layer 110 is located on the first RDL composite layer, covering the first RDL composite layer and encapsulating the second chip 202.

[0106] Specifically, the solder resist layer 700 can be made by the process of sticking a film→exposure→development→post-curing, and the groove 701 is made at the corresponding position to expose the second metal connection layer, and then the solder ball 800 is implanted at the groove 701. And the metal bump 900 corresponding to the second metal connection layer 602 is electroplated on the first RDL composite layer to connect the second chip 202. The metal bump 900 can be, but is not limited to, copper, copper alloy, iron, iron alloy, tin, tin-silver alloy, nickel, nickel alloy, tungsten and the like. The second chip 202 can include multiple, such as 2, 3, 5, etc., and preferably the active surface of the second chip 202 and the upper surface of the metal bump 900 are in the same plane to facilitate electrical connection. The specific number of the second chip 202 is not limited here, and after the completion of the manufacturing, the second chip 202 can be packaged using packaging resin and the like, and finally a stacked packaging structure based on an organic carrier board and RDL is formed.

[0107] As an example, the packaging structure can include a fan-out packaging structure or a fan-in packaging structure.

[0108] Specifically, in the embodiment, the packaging structure is preferably a fan-out packaging structure.

[0109] Referring to Figures 3-20 The embodiment also provides a stacked packaging structure based on an organic carrier board and RDL, which includes:

[0110] An organic carrier board 100, which includes a first surface and an opposite second surface, and includes an organic core layer 101 and a metal layer 102 located on opposite surfaces of the organic core layer 101 and electrically connected to each other, and has a through slot in the organic carrier board 100;

[0111] A first chip 201, which is placed in the through slot, and the pads of the first chip 201 and the first surface of the organic carrier board 100 are located on the same side;

[0112] A first RDL composite layer, which is located on the first surface of the organic carrier board 100, and includes a first insulating medium layer and a first metal connection layer, and the first metal connection layer is electrically connected to the pads of the first chip 201 and the metal layer of the organic carrier board 100;

[0113] a second RDL composite layer on the second surface of the organic carrier 100, the second RDL composite layer comprising a second insulating medium layer and a second metal connection layer, the second insulating medium layer filling the through slot and covering the first chip 201 and the second surface of the organic carrier 100, the second metal connection layer being electrically connected with the metal layer of the organic carrier 100;

[0114] a second chip 202 on the first RDL composite layer, the second chip 202 being electrically connected with the first metal connection layer;

[0115] a packaging layer 110 on the first RDL composite layer, covering the first RDL composite layer and encapsulating the second chip 202;

[0116] a solder resist layer 700 on the second RDL composite layer, covering the second RDL composite layer and having a groove 701 in the solder resist layer 700 exposing the second metal connection layer;

[0117] a tin ball 800 in the groove 701, one end of the tin ball 800 being electrically connected with the second metal connection layer and the other end of the tin ball 800 being exposed from the solder resist layer 700.

[0118] As an example, the packaging structure comprises a plurality of the first chips 201, and the pads corresponding to the first chips 201 are located in the same plane; the packaging structure comprises a plurality of the second chips 202.

[0119] As an example, the second chip 202 is electrically connected with the first metal connection layer through a metal bump 900 formed by electroplating.

[0120] As an example, the first RDL composite layer comprises the first metal connection layer stacked and electrically connected; the second RDL composite layer comprises the second metal connection layer stacked and electrically connected.

[0121] As an example, the line width of the first metal connection layer is ≥1 μm, and the line spacing of the first metal connection layer is ≥1 μm; the line width of the second metal connection layer is ≥1 μm, and the line spacing of the second metal connection layer is ≥1 μm.

[0122] As an example, the first insulating medium layer comprises a photosensitive medium layer or a non-photosensitive medium layer; the second insulating medium layer comprises a photosensitive medium layer or a non-photosensitive medium layer.

[0123] As an example, the packaging structure includes a fan-out packaging structure or a fan-in packaging structure, and the embodiment is preferably a fan-out packaging structure to increase the number and distribution of I / O contacts.

[0124] The specific material, preparation, structure, etc. of the packaging structure can be referred to the above preparation of the packaging structure, and will not be repeated here, but the preparation of the packaging structure is not limited to the above preparation method.

[0125] In summary, the organic carrier board and RDL-based stacked packaging structure and preparation method of the present application combines the organic carrier board with the first RDL composite layer and the second RDL composite layer, accommodates the first chip in the organic carrier board and electrically connects it with the first RDL composite layer, and the second chip is electrically connected with the first RDL composite layer, and the first RDL composite layer combines the organic carrier board and the second RDL composite layer to be electrically connected to be electrically led out through the tin ball.

[0126] The present application is suitable for large-area manufacturing, which can improve productivity and reduce cost; the setting of the RDL composite layer can replace the setting of a part of the internal circuit of the chip, and the stacked structure provides flexibility for chip design, which can be flexibly mixed and connected to meet the needs, reducing the complexity and cost of design; the first RDL composite layer is directly electrically connected with the pad of the first chip, and the second chip is electrically connected with the first RDL composite layer through the metal bump, so as to reduce the stress and improve the packaging reliability; the combination of the RDL composite layer can reduce the packaging thickness, shorten the conduction distance between chips, realize the densification and refinement of the circuit, and meet the demand of thin and small packaging; the fan-out packaging structure can make the size of the packaged chip larger, and also make the I / O contact pitch more flexible; thus, the organic carrier board and RDL-based stacked packaging structure and preparation method of the present application can reduce cost, reduce thermal resistance, improve reliability, shorten the interconnection path, realize the densification, refinement and flexibility of packaging, make the signal transmission faster, improve the application range, and meet the needs of future such as cloud infrastructure, 5G, autonomous driving and artificial intelligence.

[0127] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. An organic carrier board and RDL based stacked package structure, characterized by, The packaging structure comprises: an organic carrier plate comprising a first surface and an opposite second surface, the organic carrier plate comprising an organic core layer and metal layers located on opposite sides of the organic core layer and electrically connected to each other, the organic carrier plate having a through slot therein; a first chip located in the through slot, and the pads of the first chip being located on the same side as the first surface of the organic carrier plate, the pads of the first chip being located in the same plane as the metal layer located on the first surface of the organic carrier plate; a first RDL composite layer located on the first surface of the organic carrier plate, the first RDL composite layer comprising a first insulating medium layer and a first metal connection layer, and the first metal connection layer being electrically connected to the pads of the first chip and the metal layer of the organic carrier plate, the line width of the first metal connection layer being ≥1μm, and the line spacing of the first metal connection layer being ≥1μm; a second RDL composite layer located on the second surface of the organic carrier plate, the second RDL composite layer comprising a second insulating medium layer and a second metal connection layer, the second insulating medium layer filling the through slot and covering the first chip and the second surface of the organic carrier plate, the second insulating medium layer being a heat dissipation material, the second metal connection layer being electrically connected to the metal layer of the organic carrier plate, the line width of the second metal connection layer being ≥1μm, and the line spacing of the second metal connection layer being ≥1μm; a second chip located on the first RDL composite layer, and the second chip being electrically connected to the first metal connection layer; a packaging layer located on the first RDL composite layer, covering the first RDL composite layer and encapsulating the second chip; a solder resist layer located on the second RDL composite layer, covering the second RDL composite layer and having a groove in the solder resist layer exposing the second metal connection layer; a tin ball located in the groove, and one end of the tin ball being electrically connected to the second metal connection layer and the other end of the tin ball being exposed from the solder resist layer.

2. The package structure of claim 1, wherein: The packaging structure comprises a plurality of the first chips, and the pads corresponding to the first chips are located in the same plane; and the packaging structure comprises a plurality of the second chips.

3. The package structure of claim 1, wherein: The second chip is electrically connected to the metal bump of the first metal connection layer formed by electroplating.

4. The package structure of claim 1, wherein: The first RDL composite layer comprises the first metal connection layer stacked and electrically connected; and the second RDL composite layer comprises the second metal connection layer stacked and electrically connected.

5. The package structure of claim 1, wherein: The first insulating medium layer comprises a photosensitive medium layer or a non-photosensitive medium layer; and the second insulating medium layer comprises a photosensitive medium layer or a non-photosensitive medium layer.

6. The package structure of claim 1, wherein: The packaging structure comprises a fan-out packaging structure or a fan-in packaging structure.

7. A method for preparing a stacked packaging structure based on an organic carrier and RDL, characterized in that: The method comprises the following steps: providing an organic carrier plate comprising a first surface and an opposite second surface, the organic carrier plate comprising an organic core layer and metal layers located on opposite sides of the organic core layer and electrically connected to each other, the organic carrier plate having a through slot therein; providing a support substrate, the support substrate being attached to the first surface of the organic carrier substrate; providing a first chip, the first chip being disposed in the through-hole, and the pads of the first chip being oriented toward the support substrate, the pads of the first chip being coplanar with the metal layer on the first surface of the organic carrier substrate; removing the support substrate, forming a first RDL composite layer on the first surface of the organic carrier substrate, the first RDL composite layer including a first insulating medium layer and a first metal connection layer, the first metal connection layer being electrically connected to the pads of the first chip and the metal layer of the organic carrier substrate; and forming a second RDL composite layer on the second surface of the organic carrier substrate, the second RDL composite layer including a second insulating medium layer and a second metal connection layer, the second insulating medium layer filling the through-hole and covering the first chip and the second surface of the organic carrier substrate, the second insulating medium layer being a heat dissipation material, the second metal connection layer being electrically connected to the metal layer of the organic carrier substrate, the first metal connection layer having a line width ≥ 1 μm and a line spacing ≥ 1 μm, the second metal connection layer having a line width ≥ 1 μm and a line spacing ≥ 1 μm; forming a solder resist layer on the surface of the second RDL composite layer; forming a recess in the solder resist layer, the recess exposing the second metal connection layer; forming a solder ball in the recess, and forming a second chip and a packaging layer on the first RDL composite layer, one end of the solder ball being electrically connected to the second metal connection layer and the other end being exposed on the solder resist layer, the second chip being disposed on the first RDL composite layer and being electrically connected to the first metal connection layer, and the packaging layer being disposed on the first RDL composite layer and covering the first RDL composite layer and the second chip.

8. The method of claim 7, wherein: The second chip and the first metal connection layer are electrically connected by a metal bump, and the method for forming the metal bump includes electroplating.

9. The method of claim 7, wherein: The first insulating medium layer includes a photosensitive medium layer or a non-photosensitive medium layer, and the second insulating medium layer includes a photosensitive medium layer or a non-photosensitive medium layer; when the medium layer is a non-photosensitive medium layer, the patterning method includes laser, and when the medium layer is a photosensitive medium layer, the patterning method includes dry etching or wet etching.

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