Electronic module and its manufacturing method and electronic packaging part

Abstract

An electronic module and its manufacturing method and electronic packaging device, including a first metal layer, an insulating layer, and a second metal layer formed in sequence on the side and non-active surface of an electronic component to serve as a capacitor structure, wherein the capacitor structure exposes the active surface of the electronic component, so that the distance between the capacitor structure and the electronic component is minimized by directly forming the capacitor structure on the electronic component, thereby achieving the best effect of suppressing impedance.

Description

Technical Field

[0001] The present invention relates to a semiconductor chip, in particular to an electronic module with a capacitor structure and a manufacturing method and an electronic packaging component. Background Art

[0002] With the rapid development of terminal products for high-speed computing applications (such as autonomous driving, supercomputers or mobile devices), the internal electronic components of these products have also encountered technical bottlenecks and challenges. For example, a semiconductor chip is placed on a substrate. When the loop current of the metal trace of the substrate is connected to the semiconductor chip, high-frequency power supply impedance is generated, thereby generating noise. Therefore, the semiconductor chip is prone to generate erroneous signals at critical positions due to interference, thereby generating erroneous actions.

[0003] Therefore, the industry has set up decoupling capacitors (Decap) at different locations around the substrate to suppress the occurrence of high-frequency power supply impedance.

[0004] Figure 1A A cross-sectional schematic diagram of an existing electronic device 1. Figure 1A As shown, the electronic device 1 includes a semiconductor package 1a, which has a silicon interposer (TSI) 13 disposed between a package substrate 11 and a semiconductor chip 10. The silicon interposer 13 has a conductive through-silicon via (TSV) 130 and a redistribution layer (RDL) 131 formed on the conductive through-silicon via 130, so that the conductive through-silicon via 130 on its interposer side 13b is electrically connected to the pad 110 of the package substrate 11 with a larger spacing through a plurality of conductive elements 16, and the conductive elements 16 are coated with an underfill 15, and the electrode pad 100 of the semiconductor chip 10 with a smaller spacing is electrically connected to the redistribution layer 131 on the die side 13a of the silicon interposer 13 through a plurality of solder bumps 101, and the solder bumps 101 are coated with an underfill 14. Finally, a packaging resin 12 is formed on the packaging substrate 11 so that the packaging resin 12 covers the semiconductor chip 10 and the silicon interposer 13 .

[0005] The electronic device 1 further includes a circuit board 1 b , and a plurality of solder balls 17 are formed on the lower side of the package substrate 11 of the semiconductor package 1 a to be combined with the circuit board 1 b .

[0006] In the conventional electronic device 1, if the impedance value generated when no decoupling capacitor structure is configured is defined as 1x, then when at least one decoupling capacitor element 18a is placed at different positions in the electronic device 1, the closer to the semiconductor chip 10, the better the impedance suppression effect is, as shown in the following Table 1:

[0007]

[0008] Table 1.

[0009] Therefore, based on the above principle, the industry has integrated the decoupling capacitor (Decap) structure into the silicon interposer 13. Figure 1B As shown, when the silicon interposer 13 is making the conductive silicon through-hole 130, a plurality of conductive openings 132 which are arranged at intervals and do not penetrate the silicon interposer 13 are also made, so that the conductive openings 132 can be used as decoupling capacitors 18b, so that the decoupling capacitors 18b are electrically connected to the semiconductor chip 10 through the line redistribution structure 131, so that the decoupling capacitors 18b can be very close to the semiconductor chip 10 to achieve the effect of suppressing impedance (the impedance value is 0.058x as shown in Table 1).

[0010] However, in the silicon interposer 13, the conductive openings 132 need to be manufactured in conjunction with the conductive silicon through-vias 130, and thus processes such as filling the holes with dielectric materials and electroplating metal materials need to be performed. This will result in problems such as lengthy process time, increased manufacturing costs, greatly increased manufacturing difficulty, and reduced manufacturing yields, and thus does not meet the need to reduce the cost of the electronic device 1.

[0011] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the invention

[0012] In view of the above-mentioned defects of the prior art, the present invention provides an electronic module and a manufacturing method thereof and an electronic package, which can achieve the best effect of suppressing impedance.

[0013] The electronic module of the present invention comprises: an electronic component having an active surface and an inactive surface opposite to each other and side surfaces adjacent to the active surface and the inactive surface, and the active surface has a plurality of electrode pads; and a capacitor structure formed on the electronic component and exposing the active surface, wherein the capacitor structure comprises a first metal layer disposed on the electronic component and electrically connected to the plurality of electrode pads, an insulating layer disposed on the first metal layer, and a second metal layer disposed on the insulating layer and electrically coupled to the first metal layer, and the first metal layer does not contact the second metal layer.

[0014] The present invention also provides a method for manufacturing an electronic module, comprising: arranging an electronic component on a carrier, wherein the electronic component has an active surface and an inactive surface relative to each other and side surfaces adjacent to the active surface and the inactive surface, and the active surface has a plurality of electrode pads so that the electronic component is coupled to the carrier via the active surface; sequentially forming a first metal layer, an insulating layer and a second metal layer on the electronic component, and the first metal layer does not contact the second metal layer, so that the first metal layer, the insulating layer and the second metal layer serve as a capacitor structure; and removing the carrier.

[0015] In the aforementioned electronic module and its manufacturing method, the capacitor structure is formed on the inactive surface and / or the side surface of the electronic element.

[0016] In the aforementioned electronic module and its manufacturing method, the capacitor structure is a decoupling capacitor type.

[0017] In the aforementioned electronic module and its manufacturing method, at least one wire electrically connected to the electrode pad is disposed inside the electronic component so that the first metal layer is electrically connected to the wire. For example, the wire is exposed on the side surface and / or the inactive surface of the electronic component.

[0018] In the aforementioned electronic module and its manufacturing method, the electronic element has a single set of power transmission structures, so that the capacitor structure is electrically connected to the power transmission structure.

[0019] In the aforementioned electronic module and its manufacturing method, the electronic component has multiple groups of power transmission structures, so that the capacitor structure is electrically connected to the multiple groups of power transmission structures. For example, the first metal layer includes multiple electrical connection parts that are spaced apart from each other (separated and not connected), so that the multiple electrical connection parts are electrically connected to different groups of the power transmission structures. Further, the inactive surface is formed with a separation area between each of the electrical connection parts, so that the first metal layer does not cover the separation area, so that the insulating layer is formed on the separation area and contacts the inactive surface.

[0020] The present invention further provides an electronic package, comprising: a supporting structure having a circuit layer; and the aforementioned electronic module, which is arranged on the supporting structure, and the capacitor structure is electrically connected to the circuit layer.

[0021] The aforementioned electronic package also includes a wiring structure electrically connected to the electronic component. For example, the wiring structure has a first surface and a second surface opposite to each other, so that the electronic module is arranged on the first surface, and at least one second electronic component is arranged on the second surface. Alternatively, the circuit layer of the supporting structure and the wiring structure are electrically connected to each other via a plurality of conductive pillars.

[0022] In the aforementioned electronic package, a plurality of conductive pillars electrically connected to the circuit layer are formed on the supporting structure, and for example, a coating layer covering the plurality of conductive pillars, the electronic components and the capacitor structure is also included.

[0023] The aforementioned electronic package also includes a coating layer that coats the electronic element and the capacitor structure.

[0024] As can be seen from the above, the electronic module and its manufacturing method and the electronic package of the present invention mainly form the capacitor structure directly on the electronic component so that the capacitor structure is adjacent to the electronic component. Therefore, compared with the prior art, the electronic module of the present invention can not only minimize the distance between the decoupling capacitor (i.e., the capacitor structure) and the semiconductor chip (i.e., the electronic component), thereby achieving the best effect of suppressing impedance, but also meet the demand of reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A It is a cross-sectional schematic diagram of a conventional electronic device.

[0026] Figure 1B for Figure 1A A cross-sectional schematic diagram of another embodiment of a silicon interposer.

[0027] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing an electronic package of the present invention.

[0028] FIG. 3A to FIG. 3F It is a cross-sectional schematic diagram of a method for manufacturing an electronic module of the present invention.

[0029] Figure 3E-1 to Figure 3F-1 for FIG. 3E to FIG. 3F A cross-sectional schematic diagram of another embodiment of the present invention.

[0030] Figure 3E-2 for Figure 3E-1 A partial top view schematic diagram of .

[0031] Description of Reference Numerals

[0032] 1: Electronic devices

[0033] 1b, 2b: Circuit board

[0034] 1a: Semiconductor package

[0035] 10: Semiconductor Chips

[0036] 100,210,300,300b,300c: Electrode pads

[0037] 101:Solder Bumps

[0038] 11:Packaging substrate

[0039] 110: Solder pad

[0040] 12: Encapsulation colloid

[0041] 13: Silicon interposer

[0042] 13a: Chip side

[0043] 13b: Intermediary side

[0044] 130: Conductive silicon via

[0045] 131: Line redistribution structure

[0046] 132: Conductive opening

[0047] 14,15: Primer

[0048] 16,29: Conductive elements

[0049] 17: Solder ball

[0050] 18a: Decoupling capacitor element

[0051] 18b: Decoupling capacitor

[0052] 2: Electronic packaging

[0053] 20: Bearing structure

[0054] 20a: First side

[0055] 20b: Second side

[0056] 200: first dielectric layer

[0057] 201: First circuit layer

[0058] 21: First Electronic Components

[0059] 21a, 30a: Action surface

[0060] 21b, 30b: non-active surface

[0061] 21c,30c: Side

[0062] 210a, 300a: Contact

[0063] 211,301,301b,301c: Wire

[0064] 212: Conductor

[0065] 22,32: Capacitor structure

[0066] 220,32b: Insulation layer

[0067] 221,32a: First metal layer

[0068] 222,32c: Second metal layer

[0069] 23: Conductive column

[0070] 24: Second electronic component

[0071] 25: Coating layer

[0072] 26: Wiring structure

[0073] 26a: First surface

[0074] 26b: Second surface

[0075] 260: Second dielectric layer

[0076] 261: Second circuit layer

[0077] 27: Conductive bump

[0078] 28: Encapsulation layer

[0079] 3,3a: Electronic module

[0080] 30,31: Electronic components

[0081] 321, 322: Electrical connection part

[0082] 4: Wafer

[0083] 8,9: Bearing parts

[0084] 90:Plate body

[0085] 91: Binding layer

[0086] A: Separation area

[0087] L, S: cutting path. DETAILED DESCRIPTION

[0088] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0089] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0090] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 with a capacitor structure 22 according to the present invention.

[0091] like Figure 2A As shown, a supporting structure 20 is disposed on a supporting member 9, and the supporting structure 20 has a first side 20a and a second side 20b opposite to each other, and at least one first electronic component 21 and a plurality of conductive columns 23 (such as made of copper metal material or solder material) are disposed on the first side 20a of the supporting structure 20.

[0092] In the present embodiment, the supporting structure 20 is, for example, a package substrate having a core layer and a circuit structure, a package substrate having a coreless circuit structure, a silicon interposer (TSI) with conductive through-silicon via (TSV), or other board types, which includes at least one first dielectric layer 200 and at least one first circuit layer 201 combined with the first dielectric layer 200, such as at least one fan-out type redistribution layer (RDL). For example, the material forming the first circuit layer 201 is copper, and the material forming the first dielectric layer 200 is a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), or prepreg (PP). It should be understood that the supporting structure 20 can also be other substrates for supporting chips, such as a lead frame, a wafer, or other boards with metal routing, etc., and is not limited to the above.

[0093] In addition, the second side 20a of the supporting structure 20 is disposed on the supporting member 9 via a plurality of conductive elements 29. For example, the supporting member 9 includes a plate 90 such as a semiconductor material, a dielectric material, a ceramic material, a glass or a metal material, but is not limited thereto, and the size of the supporting member 9 can be selected as a wafer form substrate or a general full-panel substrate according to the requirements, and a bonding layer 91 such as a release film or a glue material can be formed on the plate 90 by coating or laminating, so that the supporting structure 20 is pressed on the bonding layer 91, and the conductive elements 29 are embedded in the bonding layer 91.

[0094] In addition, the first electronic component 21 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. In this embodiment, in this embodiment, the first electronic component 21 is a semiconductor chip, which has an active surface 21a and an inactive surface 21b opposite to each other and a side surface 21c adjacent to the active surface 21a and the inactive surface 21b. The first electronic component 21 is disposed on the first side 20a of the supporting structure 20 with its inactive surface 21b, and the active surface 21a has a plurality of electrode pads 210 (which can be located as shown in FIG. Figure 2A The middle of the active surface 21a shown in FIG. 1 ) and a plurality of contact points 210a (which may be located as shown in FIG. Figure 2A ), wherein the first electronic component 21 is internally provided with at least one wire 211 electrically connected to the electrode pad 210 and a plurality of integrated circuits (not shown) electrically connected to the contact 210a, and the wire 211 is exposed at the side 21c of the first electronic component 21. For example, a conductor 212 in the shape of a column, needle or other bump may be formed on the electrode pad 210 and the contact 210a as required, and an insulating protective film (not shown) is formed on the active surface 21a so that the conductor 212 is exposed at the insulating protective film.

[0095] In addition, a capacitor structure 22 electrically connected to the first electronic element 21 is formed on the inactive surface 21b and the side surface 21c of the first electronic element 21, such as a decoupling capacitor (Decap), which includes a first metal layer 221 disposed on the first electronic element 21 (inactive surface and side surface) and electrically connected to the conductive line 211, an insulating layer 220 disposed on the first metal layer 221, and a second metal layer 222 disposed on the insulating layer 220 and electrically coupled to the first metal layer 221, so that the first electronic element 21 is disposed on the first side 20a of the supporting structure 20 via the capacitor structure 22, and the second metal layer 222 is electrically connected to the first circuit layer 201 to serve as the grounding terminal of the capacitor structure 22. For example, the material forming the first metal layer 221 and the second metal layer 222 is copper, and the material forming the insulating layer 220 is a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), prepreg (PP), etc.

[0096] like Figure 2B As shown, a coating layer 25 is formed on the first side 20a of the supporting structure 20, so that the coating layer 25 covers the first electronic element 21, the capacitor structure 22 and the conductive pillars 23. Then, a wiring structure 26 is formed on the coating layer 25, so that the wiring structure 26 electrically connects the conductive pillars 23 and the first electronic element 21.

[0097] In this embodiment, the material forming the coating layer 25 is an insulating material such as polyimide (PI), dry film, epoxy resin or molding compound, but is not limited to the above. For example, the coating layer 25 can be formed on the first side 20a of the supporting structure 20 by lamination or molding.

[0098] In addition, a flattening process may be performed as required to make the upper surface of the cladding layer 25 flush with the end surface of the conductive pillar 23 and the top surface of the conductor 212, so that the end surface of the conductive pillar 23 and the top surface of the conductor 212 are exposed from the cladding layer 25. For example, the flattening process may be performed by grinding to remove part of the material of the conductive pillar 23, part of the material of the conductor 212, and part of the material of the cladding layer 25.

[0099] In addition, the wiring structure 26 has a first surface 26 a and a second surface 26 b opposite to each other, so that the wiring structure 26 is combined with the cladding layer 25 through its first surface 26 a, and the first electronic element 21 and the conductive pillar 23 are disposed on the first surface 26 a.

[0100] In addition, the wiring structure 26 has at least one second dielectric layer 260 and a second wiring layer 261 (such as RDL) disposed on the second dielectric layer 260, so that the second wiring layer 261 of the wiring structure 26 electrically connects the conductive pillars 23 and the conductor 212 on the first electronic element 21. For example, the material forming the second wiring layer 261 is copper, and the material forming the second dielectric layer 260 is a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), or prepreg (PP).

[0101] like Figure 2C As shown, at least one second electronic component 24 is disposed on the second surface 26 b of the wiring structure 26 , and then a packaging layer 28 is used to cover the second electronic component 24 .

[0102] In this embodiment, the second electronic component 24 is an active component, a passive component or a combination of the two, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the second electronic component 24 is electrically connected to the second wiring layer 261 of the wiring structure 26 through a plurality of conductive bumps 27 such as solder bumps, copper bumps or other conductive bumps in a flip chip manner; however, there are many ways to connect the second electronic component 24 to the wiring structure 26, such as wire bonding packaging, and is not limited to the above.

[0103] In addition, the packaging layer 28 can simultaneously cover the second electronic component 24 and the conductive bumps 27. Alternatively, a primer (not shown) can be first formed between the second electronic component 24 and the second surface 26b of the wiring structure 26 to cover the conductive bumps 27, and then the packaging layer 28 can be formed to cover the primer and the second electronic component 24.

[0104] In addition, the packaging layer 28 is an insulating material, such as polyimide (PI), dry film, packaging colloid such as epoxy, or molding compound, which can be formed on the wiring structure 26 by lamination or molding. It should be understood that the material forming the packaging layer 28 can be the same as or different from the material of the covering layer 25.

[0105] In addition, the packaging layer 28 can cover the back side of the second electronic element 24 (not shown) or expose the back side of the second electronic element 24 (such as Figure 2C shown).

[0106] like Figure 2D As shown, the carrier 9 and the bonding layer 91 thereon are removed to expose the plurality of conductive elements 29 .

[0107] like Figure 2EAs shown, along Figure 2D The cutting path S shown is used for performing a singulation process to obtain a plurality of electronic packages 2 , so that the electronic packages 2 can be placed on a circuit board 2 b via the conductive elements 29 .

[0108] Therefore, the electronic package 2 of the present invention mainly adopts the Metal-insulator-metal diode (MIM diode) technology to form the capacitor structure 22 on the first electronic component 21, so that the capacitor structure 22 is adjacent to the first electronic component 21, so that the decoupling capacitor (Decap) is closest to the semiconductor chip. Therefore, compared with the prior art, according to the principle of the aforementioned Table 1, the electronic package 2 of the present invention embeds the capacitor structure 22 and the first electronic component 21 in the same place in the coating layer 25, so that the distance between the two is minimized, thereby achieving the best effect of suppressing impedance (impedance value is less than 0.058x, about 0.01x~0.04x), and further eliminating the noise generated by impedance.

[0109] FIG. 3A to FIG. 3F It is a cross-sectional schematic diagram of a manufacturing method of an electronic module 3 related to a first electronic component 21 having a capacitor structure 22 of the present invention.

[0110] like FIG. 3A to FIG. 3B As shown, a wafer 4 is singulated to obtain a plurality of electronic components 30. Then, the plurality of electronic components 30 are arranged on a full-format carrier 8 at intervals.

[0111] In this embodiment, the electronic component 30 is similar to the structure of the first electronic component 21, and has an active surface 30a and an inactive surface 30b opposite to each other. The active surface 30a has a plurality of electrode pads 300 and a plurality of contacts 300a. A plurality of wires 301 electrically connected to the electrode pads 300 are disposed inside the electronic component 30, and the active surface 30a is combined with the carrier 8. It should be understood that the electrode pads 300 and the contacts 300a may be formed as required. Figure 2A The conductor 212 is shown and is covered with an insulating protective film (not shown) so that the electronic component 30 is combined with the carrier 8 through the insulating protective film.

[0112] In addition, after the wafer 4 is singulated, the conductive wire 301 will be exposed on the side surface 30 c of the electronic component 30 . It should be understood that the conductive wire 301 may also be exposed on the inactive surface 30 b of the electronic component 30 .

[0113] like FIG. 3C to FIG. 3EAs shown, a first metal layer 32a, an insulating layer 32b and a second metal layer 32c are sequentially formed on the inactive surface 30b and the side surface 30c of the electronic component 30, and the first metal layer 32a does not contact the second metal layer 32c, so that the first metal layer 32a, the insulating layer 32b and the second metal layer 32c serve as a capacitor structure 32, such as a decoupling capacitor (Decap), so that the capacitor structure 32 covers the electronic component 30.

[0114] In this embodiment, the first metal layer 32a is coated on all or part of the inactive surface 30b and / or all or part of the side surface 30c of the electronic component 30 by electroplating, deposition or other methods, and the insulating layer 32b is coated on the entire surface of the first metal layer 32a, and the second metal layer 32c is coated on the entire surface of the first metal layer 32a by electroplating, deposition or other methods.

[0115] In addition, the first metal layer 32a contacts the wire 301 to electrically connect the electrode pad 300 via the wire 301, and the first metal layer 32a is not electrically connected to the contacts 300a. For example, the capacitor structure 32 corresponds to a single set of power transmission structures (i.e., the electrode pads 300) of the electronic component 30, so the first metal layer 32a is only a single electrical connection portion, and the second metal layer 32c serves as a ground port of the capacitor structure 32.

[0116] Or, if Figure 3E-1 As shown, the capacitor structure 32 may also correspond to multiple power transmission structures of the electronic component 31. For example, the electronic component 31 has two power transmission structures, and the first metal layer 32a includes multiple electrical connection parts 321, 322 that are separated from each other and not connected. Figure 3E-2 As shown, the plurality of electrical connection parts 321, 322 are respectively electrically connected to different groups of power transmission structures (i.e., different wires 301b, 301c or different electrode pads 300b, 300c), and the second metal layer 32c serves as a ground port of the capacitor structure 32. Specifically, the inactive surface 30b is formed with a separation area A between the electrical connection parts 321, 322, so that the first metal layer 32a does not cover the separation area A, and the insulating layer 32b is formed on the separation area A and contacts the inactive surface 30b.

[0117] like Figure 3F As shown, continued Figure 3E The process is as follows Figure 3E The cutting path L shown is used for singulation process, and then the carrier 8 is removed to obtain a plurality of electronic modules 3 , and the capacitor structure 32 is not formed on the active surface 30 a of the electronic components 30 , 31 .

[0118] In this embodiment, the electronic module 3 is applied to Figure 2E In the electronic package 2 shown, the electronic component 30 has only one set of power transmission structures (ie, the electrode pads 300 ), so the electronic component 30 can provide the power required by one second electronic component 24 , while other second electronic components 24 need to be connected to other power sources.

[0119] In addition, if the continuation Figure 3E-1 The process can be obtained as Figure 3F-1 The electronic module 3a shown in FIG. Figure 2E In the electronic package 2 shown, the electronic component 31 has two sets of power transmission structures (ie, the electrode pads 300 b and 300 c ), so the electronic component 30 can provide power required by the two second electronic components 24 .

[0120] It should be understood that based on the number of power transmission structures of the electronic components 30 , 31 , the number of the electrical connection portions 321 , 322 of the first metal layer 32 a can be designed as required and is not limited to the above.

[0121] Therefore, the electronic module 3, 3a of the present invention mainly adopts the Metal-insulator-metal diode (MIM diode) technology to form the capacitor structure 32 on the electronic component 30, 31 to simplify the process. Therefore, compared with the silicon plate drilling operation of the prior art, the electronic module 3, 3a of the present invention is simple to manufacture, has a short process time, a high production yield and a low manufacturing cost, and can meet the demand for reducing the cost of the electronic package 2 and its subsequent product applications.

[0122] The present invention provides an electronic module 3 , 3 a including: an electronic component 30 , 31 and a capacitor structure 32 .

[0123] The electronic components 30 , 31 have an active surface 30 a and an inactive surface 30 b opposite to each other and a side surface 30 c adjacent to the active surface 30 a and the inactive surface 30 b , and the active surface 30 a has a plurality of electrode pads 300 , 300 b , 300 c .

[0124] The capacitor structure 32 is formed on the electronic components 30, 31 and exposes the active surface 30a, wherein the capacitor structure 32 includes a first metal layer 32a disposed on the electronic components 30, 31 and electrically connected to the multiple electrode pads 300, 300b, 300c, an insulating layer 32b disposed on the first metal layer 32a, and a second metal layer 32c disposed on the insulating layer 32b and electrically coupled to the first metal layer 32a, and the first metal layer 32a does not contact the second metal layer 32c.

[0125] In one embodiment, the capacitor structure 32 is formed on the inactive surface 30 a and / or the side surface 30 c of the electronic element 30 , 31 .

[0126] In one embodiment, the capacitor structure 32 is a decoupling capacitor.

[0127] In one embodiment, at least one conductive wire 301, 301b, 301c electrically connected to the electrode pad 300, 300b, 300c is disposed inside the electronic component 30, 31, so that the first metal layer 32a is electrically connected to the conductive wire 301, 301b, 301c. For example, the conductive wire 301, 301b, 301c is exposed on the side surface 30c and / or the inactive surface 30b of the electronic component 30, 31.

[0128] In one embodiment, the electronic component 30 has a single set of power transmission structures (ie, connected electrode pads 300 and conductive wires 301 ), so that the capacitor structure 32 is electrically connected to the power transmission structure.

[0129] In one embodiment, the electronic component 31 has multiple groups of power transmission structures (i.e., connected electrode pads 300b and wires 301b, and connected electrode pads 300c and wires 301c), so that the capacitor structure 32 is electrically connected to the multiple groups of power transmission structures. For example, the first metal layer 32a includes multiple electrically connected portions 321, 322 that are separated from each other and not connected, so that the multiple electrically connected portions 321, 322 are electrically connected to different groups of the power transmission structures. Further, the inactive surface 30b is formed with a separation area A between each of the electrical connection portions 321, 322, so that the first metal layer 32a does not cover the separation area A, so that the insulating layer 32b is formed on the separation area A and contacts the inactive surface 30b.

[0130] In one embodiment, the electronic module 3, 3a can be applied to an electronic package 2, and the electronic package 2 sets the electronic module 3, 3a on a supporting structure 20 having a first circuit layer 201, and the electronic module 3, 3a includes the electronic component 30, 31 (or the first electronic component 21) and the capacitor structure 22, 32, and the capacitor structure 22, 32 is electrically connected to the first circuit layer 201.

[0131] The electrode pads 300 , 210 of the electronic components 30 , 31 (or the first electronic component 21 ) of the electronic modules 3 , 3 a are electrically connected to a wiring structure 26 .

[0132] In one embodiment, the wiring structure 26 has a first surface 26a and a second surface 26b opposite to each other, so that the electronic module 3, 3a is disposed on the first surface 26a, and at least one second electronic element 24 is disposed on the second surface 26b. Alternatively, the first circuit layer 201 of the supporting structure 20 and the wiring structure 26 are electrically connected to each other via a plurality of conductive pillars 23.

[0133] In one embodiment, a plurality of conductive pillars 23 electrically connected to the first circuit layer 201 are formed on the supporting structure 20 .

[0134] In one embodiment, the electronic package 2 further includes a covering layer 25 covering the plurality of conductive pillars 23 , the electronic components 30 , 31 (or the first electronic component 21 ), and the capacitor structures 22 , 32 .

[0135] In summary, the electronic module and its manufacturing method and the electronic package of the present invention are mainly due to the direct formation of a multi-layer composite capacitor structure on the electronic component so that the capacitor structure is adjacent to the electronic component. Therefore, the electronic module of the present invention can not only minimize the distance between the decoupling capacitor and the semiconductor chip, thereby achieving the best effect of suppressing impedance, but also meet the demand of reducing manufacturing costs.

[0136] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic module, characterized in that: include: An electronic component having an opposite active surface and an inactive surface and side surfaces adjacent to the active surface and the inactive surface, wherein the active surface has a plurality of electrode pads; as well as A capacitor structure is formed on the inactive surface and / or the side surface of the electronic component and the active surface is exposed, wherein the capacitor structure includes a first metal layer arranged on the inactive surface and / or the side surface of the electronic component and electrically connected to the multiple electrode pads, an insulating layer arranged on the first metal layer, and a second metal layer arranged on the insulating layer and electrically coupled to the first metal layer, and the first metal layer does not contact the second metal layer.

2. The electronic module according to claim 1, characterized in that The capacitor structure is a decoupling capacitor type.

3. The electronic module according to claim 1, characterized in that: At least one conductive wire electrically connected to the electrode pad is disposed inside the electronic component so that the first metal layer is electrically connected to the conductive wire.

4. The electronic module according to claim 3, characterized in that: The lead wire is exposed on the side surface and / or the inactive surface of the electronic component.

5. The electronic module according to claim 1, characterized in that: The electronic component has a single set of power transmission structures, and the capacitor structure is electrically connected to the power transmission structure.

6. The electronic module according to claim 1, characterized in that: The electronic component has a plurality of power transmission structures, and the capacitor structure is electrically connected to the plurality of power transmission structures.

7. The electronic module according to claim 6, characterized in that: The first metal layer includes a plurality of electrical connection portions spaced apart from each other, so that the plurality of electrical connection portions are respectively electrically connected to different groups of the power transmission structures.

8. The electronic module according to claim 7, characterized in that: The inactive surface forms a separation area between each of the electrical connection parts so that the first metal layer does not cover the separation area, and the insulating layer is formed on the separation area and contacts the inactive surface.

9. An electronic package, characterized in that: include: A bearing structure having a circuit layer; as well as The electronic module as claimed in any one of claims 1 to 8 is arranged on the supporting structure, and the capacitor structure is electrically connected to the circuit layer.

10. The electronic package according to claim 9, wherein: The electronic package also includes a wiring structure electrically connected to the electronic element.

11. The electronic package according to claim 10, wherein: The wiring structure has a first surface and a second surface opposite to each other, so that the electronic module is arranged on the first surface, and at least one second electronic element is arranged on the second surface.

12. The electronic package according to claim 10, wherein: The circuit layer of the supporting structure and the wiring structure are electrically connected to each other via a plurality of conductive pillars.

13. The electronic package according to claim 9, wherein: A plurality of conductive posts electrically connected to the circuit layer are formed on the supporting structure.

14. The electronic package according to claim 13, wherein: The electronic package also includes a coating layer that covers the plurality of conductive pillars, the electronic element and the capacitor structure.

15. The electronic package according to claim 9, wherein: The electronic package also includes a coating layer that covers the electronic element and the capacitor structure.

16. A method for manufacturing an electronic module, characterized in that: include: An electronic component is arranged on a carrier, wherein the electronic component has an active surface and an inactive surface opposite to each other and side surfaces adjacent to the active surface and the inactive surface, and the active surface has a plurality of electrode pads so that the electronic component is bonded to the carrier via the active surface; A first metal layer, an insulating layer and a second metal layer are sequentially formed on the inactive surface and / or the side surface of the electronic component, and the first metal layer does not contact the second metal layer, so that the first metal layer, the insulating layer and the second metal layer serve as a capacitor structure; and Remove the carrier.

17. The method for manufacturing an electronic module according to claim 16, wherein: The capacitor structure is not formed on the active surface of the electronic component.

18. The method for manufacturing an electronic module according to claim 16, wherein: At least one conductive wire electrically connected to the electrode pad is disposed inside the electronic component, so that the conductive wire is exposed on the side surface and / or the inactive surface of the electronic component.

19. The method for manufacturing an electronic module according to claim 16, wherein: The capacitor structure is a decoupling capacitor type.

20. The method for manufacturing an electronic module according to claim 16, wherein: At least one conductive wire electrically connected to the electrode pad is disposed inside the electronic component so that the first metal layer is electrically connected to the conductive wire.

21. The method for manufacturing an electronic module according to claim 16, wherein: The electronic component has a single set of power transmission structures, and the capacitor structure is electrically connected to the power transmission structure.

22. The method for manufacturing an electronic module according to claim 16, wherein: The electronic component has a plurality of power transmission structures, and the capacitor structure is electrically connected to the plurality of power transmission structures.

23. The method for manufacturing an electronic module according to claim 22, wherein: The first metal layer includes a plurality of electrical connection portions spaced apart from each other, so that the plurality of electrical connection portions are respectively electrically connected to different groups of the power transmission structures.

24. The method for manufacturing an electronic module according to claim 23, wherein: The inactive surface forms a separation area between each of the electrical connection parts so that the first metal layer does not cover the separation area, and the insulating layer is formed on the separation area and contacts the inactive surface.

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