Memory device and method of manufacturing the same, system

Abstract

A memory device and a method of manufacturing the same are provided. The memory device includes a stack layer including a plurality of gate layers and a plurality of dielectric layers alternately stacked, a plurality of contact structures each of which passes through the stack layer and contacts a gate layer of a respective predetermined depth, wherein each gate layer is in contact with at least two contact structures, a plurality of insulating layers surrounding sidewalls of the plurality of contact structures to electrically isolate the plurality of structures from the gate layers penetrated by the plurality of contact structures, and one or more gate trenches extending through the stack layer.

Description

Technical Field

[0001] This invention relates primarily to a method for manufacturing semiconductor devices, and more particularly to a memory device, a method for manufacturing the same, and a system including the memory device. Background Technology

[0002] To overcome the limitations of two-dimensional memory devices, the industry has developed and mass-produced memory devices with three-dimensional (3D) structures, which increase integration density by arranging memory cells three-dimensionally on a substrate. Memory devices such as 3D NAND flash memory include a core region and a stair step (SS) region. The core region forms multiple memory strings, each containing multiple memory cells. The stair step region is used to bring out contact structures from word lines at each layer. These contact structures connect to a controller, allowing the memory cells to perform programming, reading, and erasing operations.

[0003] The formation process of the step region requires etching a large area of ​​stacked structure, followed by filling and planarization. This method is costly, has a long production cycle, and suffers from the challenge of planarization. These problems limit the development of memory devices towards more layers and larger capacities. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a memory device and a method thereof for directly forming the contact structure without step forming.

[0005] To address the aforementioned technical problems, the present invention provides a memory device comprising: a stacked layer including a plurality of alternately stacked gate layers and a plurality of dielectric layers; a plurality of contact structures, each of the plurality of contact structures passing through the stacked layer and contacting a gate layer at a predetermined depth, wherein each gate layer contacts at least two contact structures; a plurality of insulating layers surrounding the sidewalls of the plurality of contact structures to electrically isolate the plurality of structures from the gate layers penetrated by the plurality of contact structures; and one or more gate spacers extending through the stacked layer.

[0006] In one embodiment of this application, a semiconductor layer is further included, and the stacked layer is located on the semiconductor layer.

[0007] In one embodiment of this application, the at least two contact structures on each gate layer are arranged along the extension direction of the gate spacer.

[0008] In one embodiment of this application, the at least two contact structures on each gate layer are offset in the extension direction of the gate trench.

[0009] In one embodiment of this application, the plurality of contact structures have an enlarged top.

[0010] In one embodiment of this application, the memory device includes a core region and a word line connection region, the core region having a memory array, and the plurality of contact structures located in the word line connection region.

[0011] In one embodiment of this application, a plurality of virtual channel structures are also included, located in the word line connection area and passing through the stacked layer.

[0012] In one embodiment of this application, the upper surface of the stacked layer is flat.

[0013] In one embodiment of this application, the contact structure and the gate layer are integrally formed.

[0014] To address the aforementioned technical problems, this application also proposes a method for manufacturing a memory device, comprising the following steps: forming a stacked layer comprising alternating stacked sacrificial layers and multiple dielectric layers, and having a core region and a word line connection region; forming multiple contact holes of different depths in the word line connection region of the stacked layer, wherein the multiple contact holes reach the sacrificial layer at their respective depths, wherein each sacrificial layer has at least two contact holes reaching it; forming an insulating layer on the sidewalls and bottom of the multiple contact holes; filling the insulating layer of the multiple contact holes with sacrificial material to form a sacrificial structure; replacing the multiple sacrificial layers in the stacked layer with gate layers; removing the sacrificial structures in the multiple contact holes to expose the gate layers; and forming contact structures in the multiple contact holes.

[0015] In one embodiment of this application, the method further includes forming a first dielectric layer covering the stacked layer. The step of forming a plurality of contact holes of different depths in the word line connection region of the stacked layer includes: forming a hard mask layer covering the first dielectric layer, and covering the hard mask layer with a photoresist layer; patterning the hard mask layer through the photoresist layer to form a plurality of openings penetrating the first dielectric layer and reaching the top of the stacked layer in a sacrificial layer or dielectric layer; forming the plurality of contact holes of different depths using the plurality of openings by cyclically performing a trimming-etching process; and removing the photoresist layer and the hard mask layer.

[0016] In one embodiment of this application, the step of forming a plurality of contact holes of different depths in the word line connection area of ​​the stacked layer includes: forming a hard mask layer covering the stacked layer, and covering the hard mask layer with a photoresist layer; forming the plurality of contact holes of different depths by repeatedly performing a trimming-etching process; and removing the photoresist layer and the hard mask layer to enlarge the bottom of the plurality of contact holes along the extension direction of the stacked layer.

[0017] In one embodiment of this application, the step of cyclically performing the trimming-etching process includes trimming the photoresist layer in the direction of the word line connection area toward the core area to expose a predetermined number of openings and etching the exposed openings, wherein each time the exposed openings are etched, the etched openings are deepened by an etching depth to reach the next insulating layer.

[0018] In one embodiment of this application, prior to the cyclical execution of the trimming-etching process, a plurality of stepped partitions with different depths of contact holes are formed in the word line connection area, arranged parallel to the core area.

[0019] In one embodiment of this application, after the trimming-etching process is performed cyclically, a cutting process is also performed to form multiple step partitions. The contact holes in each step partition are located at different depths of the stacked layer, and the depth of the contact holes in each step partition gradually increases or decreases in the direction away from the core area.

[0020] In one embodiment of this application, after filling the inner side of the insulating layer of the plurality of contact holes with sacrificial structures, a second capping layer covering the stacked layer is further formed; after replacing the plurality of sacrificial layers in the stacked layer with gate layers, the second capping layer is further patterned to form an opening exposing the sacrificial structures in the plurality of contact holes, the opening being used to remove the sacrificial structures and the insulating layer.

[0021] In one embodiment of this application, the critical dimension of the opening is larger than the overall critical dimension of the insulating layer and the sacrificial pillar along the extension direction of the stacked layers.

[0022] In one embodiment of this application, before forming a plurality of contact holes of different depths in the stacked layer, a plurality of virtual channel structures penetrating the stacked layer are further formed in the core region of the stacked layer.

[0023] In one embodiment of this application, after a sacrificial structure is filled inside the insulating layer of the plurality of contact holes, a plurality of virtual channel structures penetrating the stacked layer are formed in the core region of the stacked layer.

[0024] To address the aforementioned technical problems, this application also proposes a method for manufacturing a memory device, comprising the following steps: forming a stacked layer comprising alternating stacked sacrificial layers and multiple dielectric layers, and having a core region and a word line connection region; forming multiple contact holes of different depths in the word line connection region of the stacked layer, wherein the multiple contact holes reach the sacrificial layers at their respective depths, wherein each sacrificial layer has at least two contact holes reaching it; forming an insulating layer on the sidewalls and bottom of the multiple contact holes; covering the stacked layer with a hard mask layer; patterning the hard mask layer and using the patterned hard mask layer to form gate line slots in the stacked layer; removing the hard mask layer; removing the multiple sacrificial layers to form multiple gaps between the multiple dielectric layers; and filling the multiple contact holes and the multiple gaps with conductive material to form contact structures and gate layers, respectively.

[0025] In one embodiment of this application, after forming a plurality of contact holes of different depths in the word line connection area of ​​the stacked layer, the method further includes: expanding the bottom of the plurality of contact holes along the extension direction of the stacked layer.

[0026] In one embodiment of this application, the method further includes forming a first dielectric layer covering the stacked layer. The step of forming a plurality of contact holes of different depths in the word line interconnect region of the stacked layer includes: forming a hard mask layer covering the first dielectric layer, and covering the hard mask layer with a photoresist layer; patterning the hard mask layer through the photoresist layer to form a plurality of openings penetrating the first dielectric layer and reaching the top of the stacked layer in a sacrificial layer or dielectric layer; forming the plurality of contact holes of different depths using the plurality of openings by cyclically performing a trimming-etching process; and removing the photoresist layer and the hard mask layer.

[0027] In one embodiment of this application, the step of forming a plurality of contact holes of different depths in the word line connection area of ​​the stacked layer includes: forming a hard mask layer covering the stacked layer and covering the hard mask layer with a photoresist layer; forming the plurality of contact holes of different depths by repeatedly performing a trimming-etching process; and removing the photoresist layer and the hard mask layer.

[0028] In one embodiment of this application, the step of cyclically performing the trimming-etching process includes trimming the photoresist layer in the direction of the word line connection area toward the core area to expose a predetermined number of openings and etching the exposed openings, wherein each time the exposed openings are etched, the etched openings are deepened by an etching depth to reach the next insulating layer.

[0029] In one embodiment of this application, prior to the cyclical execution of the trimming-etching process, a plurality of stepped partitions with different depths of contact holes are formed in the word line connection area, arranged parallel to the core area.

[0030] In one embodiment of this application, after the trimming-etching process is performed cyclically, a cutting process is also performed to form multiple step partitions. The contact holes in each step partition are located at different depths of the stacked layer, and the depth of the contact holes in each step partition gradually increases or decreases in the direction away from the core area.

[0031] In one embodiment of this application, before forming a plurality of contact holes of different depths in the stacked layer, a plurality of virtual channel structures penetrating the stacked layer are further formed in the word line connection area of ​​the stacked layer.

[0032] To address the aforementioned technical problems, this application also proposes a system comprising a memory device as described above, configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.

[0033] In one embodiment of this application, a host coupled to the memory controller is also included.

[0034] Compared with existing technologies, the manufacturing method of the memory device of the present invention directly forms multiple contact structures in a stepped form on the stacked layers, eliminating the need for the original step forming method. This manufacturing method offers high process flexibility, saves process steps, reduces costs, and facilitates further increases in the number of layers in the memory device. Furthermore, the contact structure of the word line connection area in the present invention is locally flexible, with each gate layer contacting at least two contact structures, significantly increasing the contact area. Attached Figure Description

[0035] The accompanying drawings are included to provide a further understanding of this application; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of this application. In the drawings:

[0036] FIGS. 1A-1C This is a schematic diagram of a semiconductor structure with a stepped region;

[0037] FIG. 1D This is a schematic diagram of another semiconductor structure with a stepped region;

[0038] FIG. 2 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of this application;

[0039] FIGS. 3A-3GThis is a cross-sectional schematic diagram of an exemplary process in a method for manufacturing a memory device according to an embodiment of this application;

[0040] FIG. 4 yes FIG. 3D Top view;

[0041] FIG. 5 This is an exemplary flowchart of forming multiple contact holes of different depths according to an embodiment of this application;

[0042] FIGS. 6A-6G This is a cross-sectional schematic diagram of an exemplary process in forming a plurality of contact holes in a manufacturing method according to an embodiment of this application;

[0043] FIGS. 7A-7C This is a partial top view of a manufacturing method according to an embodiment of this application in which multiple contact holes are formed;

[0044] FIGS. 8A-8B These are cross-sectional and top views of a manufacturing method for removing the sacrificial structure according to an embodiment of this application;

[0045] FIG. 9 This is an exemplary flowchart of forming multiple contact holes of different depths according to another embodiment of this application;

[0046] FIGS. 10A-10C This is a cross-sectional schematic diagram of an exemplary process in forming a plurality of contact holes in a manufacturing method according to another embodiment of this application;

[0047] FIGS. 11A-11C This is a cross-sectional schematic diagram of an exemplary process in a method for manufacturing a memory device according to an embodiment of this application;

[0048] FIGS. 12A-12D This is a cross-sectional schematic diagram of an exemplary process in a method for manufacturing a memory device according to an embodiment of this application;

[0049] FIGS. 13A-13G This is a cross-sectional schematic diagram of an exemplary process in forming a plurality of contact holes in a manufacturing method according to an embodiment of this application;

[0050] FIGS. 14A-14C These are cross-sectional views of memory devices according to various embodiments of this application;

[0051] FIGS. 15A-15G This is a schematic diagram showing the layout of the core area and word line connection area of ​​the memory device in various embodiments of this application;

[0052] FIG. 16 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of this application;

[0053] FIGS. 17A-17GThis is a cross-sectional schematic diagram of an exemplary process in a method for manufacturing a memory device according to an embodiment of this application;

[0054] FIGS. 18A-18C yes FIG. 16 An exemplary layout diagram of the contact structure and virtual channel structure of the embodiment shown;

[0055] FIG. 19A and 19B Cross-sectional and top views of memory devices for comparison;

[0056] FIG. 20 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of this application;

[0057] FIGS. 21A-21G This is a cross-sectional schematic diagram of an exemplary process in a method for manufacturing a memory device according to an embodiment of this application;

[0058] FIG. 22 This is a top view of the formation of grid grooves in a manufacturing method according to an embodiment of this application;

[0059] FIG. 23 This is a block diagram of a system having a memory device according to an embodiment of this application;

[0060] FIG. 24A This is a block diagram of a memory card including a memory device according to an embodiment of this application;

[0061] FIG. 24B This is a block diagram of an SSD including a memory device according to an embodiment of this application. Detailed Implementation

[0062] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0063] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0064] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0065] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0066] For ease of description, spatial relative terms such as “above,” “over,” “on the upper surface,” “above,” etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as “above” or “above” other devices or structures would subsequently be positioned as “below” or “under” other devices or structures. Thus, the exemplary term “above” can include both orientations of “above” and “below”. The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0067] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. Additionally, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used but also through the meaning implied by each term.

[0068] It should be understood that when a component is referred to as "on another component," "connected to another component," "coupled to another component," or "in contact with another component," it can be directly on, connected to, coupled to, or in contact with that other component, or there may be an intervening component. In contrast, when a component is referred to as "directly on another component," "directly connected to," "directly coupled to," or "directly in contact with" another component, there is no intervening component. Similarly, when a first component is referred to as "electrically contacting" or "electrically coupled to" a second component, there is an electrical path between the first and second components that allows current to flow. This electrical path may include capacitors, coupled inductors, and / or other components that allow current to flow, even if there is no direct contact between the conductive components.

[0069] As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0070] As used herein, "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0071] As used in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes thereon. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0072] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0073] FIGS. 1A-1C This is a schematic diagram of a semiconductor structure with a stepped region. FIG. 1D This is a schematic diagram of another semiconductor structure with a stepped region.

[0074] refer to FIG. 1A As shown, a substrate 11 and a stacked layer 12 formed on the substrate 11 are illustrated. The stacked layer 12 is formed by alternating dielectric and conductive layers. A step structure 13 is formed on one side of the stacked layer 12, which constitutes the step region SS of the semiconductor structure. To form the step region SS, a trimming-etching operation is typically performed on the stacked layer 12 to gradually remove the stacked material above the step structure 13. This process is time-consuming and costly.

[0075] refer to FIG. 1B As shown, in order to form contacts connecting each word line in the step region SS, the space above the step structure 13 needs to be filled first. For example, an oxide layer 14 is formed using high-density plasma (HDP) + tetraethyl orthosilicate (TEOS) deposition. Then, the top of the stacked layer 12 is planarized, for example using a CMP (chemical mechanical planarization) process. FIG. 1C As shown, the upper surface of the oxide layer 14 is smoothed.

[0076] However, in actual manufacturing processes, on the one hand, as the number of layers in 3D NAND increases, the depressions formed by the stepped areas (SS) become deeper, making them difficult to fill completely; on the other hand, the planarization process for the filling material is quite challenging, making it difficult to grind it to an ideal level, resulting in issues such as... FIG. 1C The uneven upper surface is shown. Furthermore, in some special stepped structures, for example... FIG. 1D The semiconductor structure shown has multiple step regions of different depths. This step-forming method, which removes large areas of stacked layers, also brings severe stress effects, makes the process steps more complex, and increases costs.

[0077] FIG. 2 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of this application. Figures 3A-3G are schematic cross-sectional views of an exemplary process in a method for manufacturing a memory device according to an embodiment of this application. (Reference) FIG. 2 , FIGS. 3A-3G As shown, the manufacturing method of this embodiment includes the following steps:

[0078] In step 201, a stacked layer is formed, which includes multiple sacrificial layers and multiple dielectric layers stacked alternately, and has a core region and a word line connection region.

[0079] In some embodiments, the stacked layer has a core region and a plurality of word line connection regions, which are distributed on the side of the core region or within the core region.

[0080] In some embodiments, at least two sides of the word line connection area are adjacent to the core area.

[0081] In some embodiments, stacked layers are formed as shown in the figure. FIG. 3A The semiconductor layer 301 shown is a substrate. In some embodiments, the semiconductor layer 301 comprises amorphous silicon. This specification uses a substrate as an example and does not limit the specific implementation of the semiconductor layer 301.

[0082] like FIG. 3AAs shown, the substrate can be any one or a combination of silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon-on-insulator (SOI), or germanium-on-insulator (GOI). In some embodiments, the substrate can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. The substrate can also be a stacked structure, such as Si / SiGe. The substrate can also include other epitaxial structures, such as silicon-on-germanium (SGOI). In some embodiments, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafers. FIG. 3A The substrate shown may have undergone some necessary processing, such as forming a common active region and undergoing necessary cleaning.

[0083] FIGS. 3A-3G This is a cross-sectional view along a first direction X of the semiconductor structure used to fabricate a memory device. The first direction X represents the direction in which the gate trenches or word lines extend in the three-dimensional memory; in this specification, the first direction X is also referred to as the X-direction. Reference FIG. 3A As shown, in step 201, a stacked layer 310 is formed on the substrate 301. The stacked layer 310 consists of alternately stacked sacrificial layers 311 and dielectric layers 312.

[0084] Stack layer 310 has a core region and word line connection regions. The core region (not shown) is used to arrange the memory array. FIG. 3A The image shows the word line connection area.

[0085] The sacrificial layer 311 and the dielectric layer 312 can be selected from materials including at least one insulating medium, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and combinations thereof. The sacrificial layer 311 and the dielectric layer 312 have different etching selectivity; for example, they can be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polycrystalline or amorphous silicon, or a combination of silicon oxide or silicon nitride and amorphous carbon. The deposition methods for the sacrificial layer 311 and the dielectric layer 312 can include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, and various other methods.

[0086] In some embodiments, the substrate material is, for example, silicon. The sacrificial layer 311 and the dielectric layer 312 are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, silicon nitride and silicon oxide can be alternately deposited on the substrate sequentially using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods to form a stacked layer 310.

[0087] In one embodiment, a first dielectric layer 313 is further formed to cover the stacked layer 310. Since this first dielectric layer 313 is on top at this step, it may also be referred to as a first capping layer 313. The first dielectric layer 313 may be made of the same material as the dielectric layer 312, such as silicon oxide.

[0088] In one embodiment, a plurality of virtual channel structures 320 extending through the stack layer are formed in the word line connection area of ​​the stack layer 310. The virtual channel structures 320 are used to support the word line connection area. In some embodiments, the virtual channel structures 320 and the storage channel structures in the core area are formed in the same process. In other embodiments, the virtual channel structures 320 and the storage channel structures in the core area are formed in different processes.

[0089] Although an exemplary configuration of the initial semiconductor structure has been described herein, it will be understood that one or more features may be omitted, substituted, or added to this semiconductor structure. For example, various well regions may be formed in the substrate as needed.

[0090] In step 202, multiple contact holes of different depths are formed in the word line connection area of ​​the stacked layer, and these contact holes reach the sacrificial layer at their respective depths. This application does not limit the specific location of the sacrificial layer at each depth reached by each contact hole; each contact hole can reach a sacrificial layer at different depths, or multiple contact holes can reach the sacrificial layer at the same depth.

[0091] For example, such as FIG. 3B As shown, each of the multiple contact holes 314 reaches a sacrificial layer of a predetermined depth. The rightmost contact hole reaches the second sacrificial layer from top to bottom of the stacked layer 310; from right to left (in the -X direction), the contact hole depth gradually increases, with the second contact hole from the left reaching the bottommost sacrificial layer of the stacked layer. Furthermore, the leftmost contact hole reaches the substrate 301. In other words, the predetermined depth of the multiple contact holes 314 decreases sequentially at equal intervals along the first direction X.

[0092] Combination FIG. 4 The top view shown, FIG. 3B It is along FIG. 4 A cross-sectional view of line AA' in the diagram. FIG. 4Multiple contact holes 314 are shown in the figure. Multiple contact holes 314 are distributed along the first direction X and along the second direction Y (also known as the Y direction) perpendicular to the first direction X. Only some of them are shown in the figure.

[0093] This application does not limit the specific location distribution of the word line connection area forming the contact hole in the memory device. In some embodiments, such as FIG. 3B As shown, the core area is located to the right of the word line connecting area along the first direction X, or to the left of the word line connecting area along the opposite direction X (-X). The word line connecting area and the core area can have various positional relationships, which will be described in detail later.

[0094] Contact hole 314 can be formed by a trimming-etching process, which will be described in detail later.

[0095] In step 203, an insulating layer is formed on the sidewalls and bottom of the plurality of contact holes.

[0096] like FIG. 3C As shown, an insulating layer 315 is formed on the sidewalls and bottom of each contact hole 314. The insulating layer 315 includes an insulating layer 315a located on the sidewall of the contact hole 314 and an insulating layer 315b located on the bottom of the contact hole 314. This application does not limit the method of forming the insulating layer 315; for example, atomic layer deposition can be used. It is understood that, due to... FIG. 3C This is a cross-sectional view, and the sidewall of the contact hole 314 should be the inner wall of the contact hole 314. In some embodiments, the deposition thickness of the insulating layer 315a on the sidewall is equal to the deposition thickness of the insulating layer 315b at the bottom.

[0097] In some embodiments, step S203 employs a single process step to simultaneously form an insulating layer on the sidewall and bottom of the contact hole, wherein the insulating layer at the bottom of the contact hole can block etching during the wet etching of the sacrificial layer 311.

[0098] In step 204, a sacrificial structure is formed by filling the inner side of the insulating layer of the multiple contact holes with sacrificial material.

[0099] Continue to refer to FIG. 3C As shown, sacrificial material is further filled inside the insulating layer 315 in the contact hole 314 to form a sacrificial structure 316. For example, the sacrificial material is in contact with the insulating layer 315 and can fill the gaps inside the insulating layer.

[0100] In some embodiments, the insulating layer 315 is made of an oxide such as silicon oxide, and the sacrificial material includes carbon.

[0101] In step 205, multiple sacrificial layers in the stacked layers are replaced with gate layers.

[0102] Reference FIG. 3D sectional view and FIG. 4 A top view shows a gate line slot 318 formed along the first direction X, penetrating the stacked layer 310. This gate line slot 318 extends to the substrate 301 in a direction perpendicular to the substrate 301. The gate line slot 318 has an elongated shape and is also referred to as a slit. Wet etching through the gate line slot 318 completely removes the sacrificial layer 311 in the stacked layer 310. Conductive material is then filled into the voids formed after the removal of the sacrificial layer 311 using semiconductor processes to form a gate layer 311a. This results in a structure in the stacked layer 310 comprising alternating stacked gate layers 311a and dielectric layers 312. For example, in subsequent processes, the gate line slot 318 may be filled with an insulating layer and conductive material to bring out the source on the substrate 301. In other embodiments, the source on the substrate 301 may also be brought out from the back side of the substrate 301 without passing through the gate line slot 318.

[0103] According to the manufacturing method of this application, when etching to form contact holes, the bottom of each contact hole may be flush with its corresponding sacrificial layer, or it may extend into the sacrificial layer. The insulating layer 315b formed at the bottom of the contact hole can block etching during the wet etching of the sacrificial layer 311. Therefore, after forming the gate layer 311a, the bottom insulating layer 315b of some contact holes is flush with the top surface of the corresponding gate layer 311a, and the bottom insulating layer 316 of some contact holes is located below the top surface of the corresponding gate layer 311a.

[0104] like FIG. 3D As shown, in some embodiments, a second capping layer 317 is also covered on the first dielectric layer 313 before the gate layer replacement described above, in order to protect the insulating layer 315 and the sacrificial structure 316 in the virtual channel structure 320 and the contact hole 314.

[0105] In step 206, the sacrificial structure in the multiple contact holes and the insulating layer at the bottom of the contact holes are removed to expose the gate layer.

[0106] refer to FIG. 3E As shown, the sacrificial structure 316 in multiple contact holes 314 is removed. (Reference) FIG. 3F As shown, the insulating layer 315b at the bottom of the multiple contact holes 314 is removed. Therefore, in FIG. 3F In this case, only the insulating layer 315a of the sidewalls remains in the contact hole 314. This insulating layer 315a insulates the contact structure to be formed from the surrounding gate layer. In some embodiments, the insulating layer 315b at the bottom of the contact hole 314 is removed using dry etching.

[0107] refer to FIG. 3E and 3FAs shown, after removing the sacrificial structure 316, a plurality of second cap layer openings 317a are formed in the second cap layer 317. These second cap layer openings 317a are located on top of each contact hole and correspond one-to-one with the plurality of contact holes. An insulating layer 315a is formed on the sidewall of the contact hole, such that the critical dimension of the contact hole is smaller than the critical dimension of the second cap layer opening 317a. In embodiments where the contact hole is a circular hole, the second cap layer opening 317a is also a circular hole, and the critical dimension refers to the diameter of the circular hole.

[0108] In step 207, a contact structure is formed in the multiple contact holes.

[0109] refer to FIG. 3G As shown, multiple contact structures 319 are formed by filling multiple contact holes 314 with conductive material. (As illustrated...) FIG. 3G As shown, the bottom of each contact structure 319 contacts the gate layer 311a reached by each contact hole. The sidewalls of each contact structure 319 are electrically isolated from other gate layers traversed by the corresponding gate layer 315a. In some embodiments, the conductive material includes tungsten.

[0110] refer to FIG. 3G As shown, after step 207, FIG. 3F The second cap layer opening 317a shown is simultaneously filled with conductive material, thereby forming a contact structure plug 319a located on top of the contact structure 319. The critical dimension of the contact structure plug 319a is larger than the critical dimension of the contact structure 319.

[0111] In the manufacturing method of this application, a chemical mechanical polishing (CMP) process can be performed at some steps to give the film a smooth surface. For example, after forming... FIG. 3A After stacking layer 310, grind down its top layer; FIG. 3C In the steps shown, after filling with sacrificial structure 316, the top layer is ground smooth; FIG. 3D and 4 The diagram shows the process of replacing the sacrificial layer with another sacrificial layer, and filling the gate slots 318 with conductive material, followed by grinding the top layer flat; FIG. 3G After forming the contact structure 319 and the contact structure plug 319a, the top layer is ground flat. The grinding steps in the manufacturing method of this application are not exhaustively described here; they can be added or removed as needed.

[0112] In some embodiments, the bottom of the contact hole is flush with or below the top surface of the gate layer 311a, so the contact surface of each contact structure 319 with the gate layer 311a it contacts is located at or below the top surface of the gate layer it contacts.

[0113] According to some embodiments of this application, multiple contact structures reaching their respective depths of the gate layer are formed on the stacked layers, eliminating the need for the original step-forming method. This provides high process flexibility, saves process steps, reduces costs, and facilitates further increases in the number of layers in memory devices. Memory devices manufactured using this method exhibit uniform film layer distribution between the step region and the core memory region, resolving various stress problems caused by film layer variations. Furthermore, it improves the effective utilization of wafer area, enhances product performance, and promotes the development of memory devices with more layers and larger capacities.

[0114] Furthermore, after forming the insulating layer 315 on the sidewalls and bottom of the contact hole in step 203, the insulating layer 315b at the bottom of the contact hole 314 is retained until the sacrificial layer 311 is replaced with the gate layer 311a, and then removed in step 207. This is because the inventors of this application discovered that the conventional practice of immediately removing the insulating layer 315b at the bottom of the contact hole after forming the insulating layer on the sidewalls and bottom of the contact hole 314 causes the sacrificial structure 316 to directly contact the sacrificial layer 311. This makes the sacrificial structure 316 and the contact hole 314 susceptible to corrosion during wet etching of the sacrificial layer 311, resulting in defects. Retaining the insulating layer 315b at the bottom of the contact hole 314 protects the sacrificial structure 316 and the contact hole 314 during wet etching, thus avoiding the aforementioned defects.

[0115] FIG. 5 This is an exemplary flowchart of forming multiple contact holes of different depths according to an embodiment of this application. FIGS. 6A-6G This is a cross-sectional schematic diagram of an exemplary process in forming a plurality of contact holes in a manufacturing method according to an embodiment of this application. (Reference) FIG. 5 , FIGS. 6A-6G As shown, the manufacturing method of this embodiment includes the following steps:

[0116] In step 501, a hard mask layer covering the first dielectric layer is formed, and a photoresist layer is coated on the hard mask layer.

[0117] like FIG. 6A As shown, a hard mask layer 330 covers the first dielectric layer 313 above the stacked layer 310. In some embodiments, the hard mask layer 330 is aluminum oxide.

[0118] like FIG. 6B As shown, in order to pattern the hard mask layer 330, a photoresist layer 340 is covered on the hard mask layer 330.

[0119] In step 502, the hard mask layer is patterned with a photoresist layer to form multiple openings in the sacrificial layer that penetrate the first dielectric layer and reach the top of the stacked layers.

[0120] Continue as FIG. 6B As shown, the photoresist layer 340 has a plurality of openings 341. FIG. 7A It corresponds to FIG. 6B Top view, FIG. 6B It is along FIG. 7A A cross-sectional view along line AA'. FIG. 7A In the diagram, openings 341 are represented by squares without fill patterns, with rows in the X direction and columns in the Y direction. Multiple openings 341 have multiple rows along line AA', as shown below. FIG. 7A The diagram shows three rows, with line AA' passing through one of them; there are also multiple columns along a direction perpendicular to line AA' (Y direction), each column comprising three openings 341. FIG. 7A The diagram also shows a top view of multiple virtual channel structures 320, indicated by shaded squares. In this embodiment, multiple openings 341 are staggered from the multiple virtual channel structures 320.

[0121] It should be noted that, although FIG. 7A The opening is shown to be square, but it is understood that the opening may also be rectangular, circular, linear or other shapes, and this application is not limited thereto.

[0122] refer to FIG. 6C As shown, the hard mask layer 330 is patterned according to the photoresist layer 340, forming a plurality of openings 331 on the hard mask layer 330. It can be understood that the openings 331 and 341 are located in the same position. In some embodiments, the plurality of openings 331 are evenly spaced along a first direction X. The openings 331 rest on the sacrificial layer 311 at the top of the stacked layer 310.

[0123] The process after step S502 includes removing the photoresist layer 340. This application does not limit the method for removing the photoresist layer 340.

[0124] In step 503, multiple contact holes of different depths are formed by repeatedly performing the trimming-etching process and utilizing multiple openings.

[0125] The steps of cyclically performing a trimming-etching process typically include trimming the photoresist layer in the direction of the word line connection area toward the core area to expose a predetermined number of openings, and etching the exposed openings, wherein each etching of the exposed openings deepens the etched openings toward the substrate by one etching depth to reach the next insulating layer.

[0126] refer to FIG. 6D As shown, a photoresist layer 350 is first formed on the hard mask layer 330. The photoresist layer 350 exposes a row of first openings 331a located at the leftmost end. This step can be performed directly on the hard mask layer 330. FIG. 6DThe photoresist layer 350 shown can also be made by first completely covering the hard mask layer 330 with a photoresist layer, and then trimming the photoresist layer to expose the first opening 331a. This application does not limit this.

[0127] FIG. 7B yes FIG. 6D Top view, FIG. 6D It is along FIG. 7B The cross-sectional view of line AA' shows the first direction X, which is parallel to line AA'. (See reference.) FIG. 7B As shown, a first photoresist layer 350 is trimmed in the first direction X, exposing a row of first openings 331a. In this embodiment, the predetermined number is three, and these three first openings 331a are located in the same row. However... FIG. 6D and 7B It is not used to limit the quantity ordered.

[0128] In some embodiments, the plurality of first openings 331a may not be in the same column, but may be distributed arbitrarily.

[0129] refer to FIG. 6E As shown, the stacked layer 310 corresponding to the first exposed opening 331a is etched, deepening the exposed opening 331a towards the substrate 301 by an etching depth. In this embodiment, the etching depth is a thickness, namely the thickness of a pair of sacrificial layers 311 and dielectric layer 312. In other embodiments, the etching depth can be an integer multiple of the thickness of a pair of sacrificial layers 311 and dielectric layer 312. FIG. 6E As shown, the first opening 331a passes through the first pair of sacrificial layers 311 and dielectric layer 312 at the top of the stacked layers 320 to reach the sacrificial layer 312.

[0130] refer to FIG. 6F As shown, the photoresist layer 350 is further trimmed along the X direction, further exposing multiple openings 331b adjacent to the multiple openings 331a. Combined with... FIG. 6F The corresponding top view FIG. 7C The multiple openings 331b also include multiple openings located in the same column.

[0131] refer to FIG. 6G As shown, after etching the exposed openings 331a and 331b, opening 331a is etched to a greater thickness toward the substrate 301, passing through the second pair of sacrificial layers 311 and dielectric layer 312 at the top of the stacked layer 310 to reach the sacrificial layer 312 below it; opening 351b is etched to a greater thickness toward the substrate 301, passing through the pair of sacrificial layers 311 and dielectric layer 312 to reach the sacrificial layer 312 below it.

[0132] Understandable, FIG. 6GFollowing the steps shown, the process continues cyclically, trimming the photoresist layer 350 in the first direction X, exposing a predetermined number of openings, and etching the stacked layers corresponding to the exposed openings. When the cycle reaches a certain number of steps, the leftmost opening 331a first penetrates the stacked layer 310 and reaches the semiconductor layer 301; the rightmost opening etches the first pair of sacrificial layers 311 and dielectric layers 312 at the top of the stacked layer 320. At this point, the cycle ends, and this cyclic step is called the trim-etch step.

[0133] In step 504, the photoresist layer 350 and the hard mask layer 330 are removed.

[0134] After step 504, the result is as follows: FIG. 3B The structure shown. (Reference) FIG. 3B As shown, after the trimming-etching process is completed, the openings in the stacked layer become multiple contact holes 314. Each of these multiple contact holes 314 reaches a sacrificial layer at a predetermined depth.

[0135] In one embodiment, it is possible to FIG. 3D The sacrificial structure and insulation layer are removed from the structure through the following process. FIG. 8B yes FIG. 8A The corresponding top view. FIG. 8A It is along FIG. 8B A cross-sectional view of line AA' in the diagram. (See also...) FIG. 8A and 8B As shown, a photoresist layer 360 is formed on the second cap layer 317, and the photoresist layer 360 and the second cap layer 317 are patterned to form openings 361 exposing the sacrificial structures in the plurality of contact holes. Next, the sacrificial structure 316 and the bottom portion of the insulating layer 315 are removed through each opening 361. Here, along the extension direction of the stacked layer 310, the critical dimension d (width direction in the figure) of the opening 361 is larger than the overall critical dimension of the insulating layer and the sacrificial pillar. This design not only facilitates the removal of the sacrificial structure 316, but also allows the subsequently formed contact structure 319 to have... FIG. 3G The enlarged top 319a shown allows for the formation of a contact structure plug 319a with a larger critical dimension in the second cap layer 318 in subsequent steps by filling it with conductive material, as shown. FIG. 3G As shown, this facilitates the connection between the contact structure 319 and external components, and improves the conductivity of the contact structure 319.

[0136] FIG. 9 This is an exemplary flowchart of forming multiple contact holes of different depths according to another embodiment of this application. FIGS. 10A-10C This is a cross-sectional schematic diagram of an exemplary process in forming a plurality of contact holes in a manufacturing method according to another embodiment of this application. (Reference) FIG. 9 , FIG. 10AFirst, in step 901, a hard mask layer 330 is formed over the stacked layer 310, and a photoresist layer 350 is applied over the hard mask layer 330. Next, in step 902, a trimming-etching process is performed cyclically to form multiple contact holes of different depths using multiple openings. FIG. 10B This shows that the etched hard mask layer 330 forms an opening 332a. FIG. 10C This illustrates etching down to a depth using opening 332a (including a pair of sacrificial layers and a dielectric layer). By repeatedly trimming the photoresist layer 350 and etching the opening, the following can be obtained: FIG. 3B Multiple contact holes of different depths are shown. Finally, as in step 903, the photoresist layer and hard mask layer are removed.

[0137] In one embodiment of this application, in FIG. 2 Following step 202, the method further includes widening the bottom of the multiple contact holes along the extension direction of the stacked layers. (See reference...) FIG. 11A As shown, after bottom enlargement, each contact hole 314 has an enlarged portion 314a at its bottom. These enlarged portions 314a enter each sacrificial layer 311. A similar process is then performed. FIGS. 3C to 3E After the process, an insulating layer is formed on the sidewall and bottom of the contact hole 314, and a sacrificial structure is continued to be filled. After the sacrificial layer is replaced with the gate layer, the sacrificial structure and the insulating layer at the bottom of the contact hole 314 are removed, and a bottom enlargement is performed again to remove at least a portion of the insulating layer on the sidewall of the enlarged portion 314a, such as... FIG. 11B As shown. Reference FIG. 11C After filling with conductive material, a contact structure 319 is formed. This bottom expansion step helps to improve the bonding force between the contact structure 319 and the gate layer 311a, making the memory device more stable.

[0138] exist FIGS. 3A-3G In the example shown, the virtual channel structure 320 is formed before the contact hole 314 is formed. In another embodiment of this application, the virtual channel structure 320 can be formed after the contact hole 314 is formed. Specifically, this can be achieved by... FIG. 3B to FIG. 3C The process of forming the contact hole 314 and its internal insulating layer 315 and sacrificial structure 316 includes... FIGS. 6A-FIG. 6G The process involves a cycle of trimming and etching. After the aforementioned process, the desired result is... FIG. 12A The structure is shown. Next, a third cap layer 318 is placed over the second cap layer 317 to protect the virtual channel structure 320, as shown. FIG. 12B As shown. Next, the sacrificial layer 311 is replaced with the gate layer 311a, resulting in the following: FIG. 12C The structure shown. Finally, it undergoes the process as follows: FIGS. 3E-3G The process described forms contact structure 319. FIG. 12DThe memory device after the formation of contact structure 319 and contact structure plug 319a is shown. FIG. 3G Compared to the memory devices shown, FIG. 3G In this configuration, the top of the contact structure 319 is almost flush with the top of the virtual channel structure 320. FIG. 12D In the memory device of the illustrated embodiment, the top of the contact structure 319 is slightly lower than the top of the virtual channel structure 320. This difference in position between the top of the contact structure 319 and the top of the virtual channel structure 320 is due to the different order of process steps, and both are within the scope of protection claimed in this application.

[0139] It is understandable that the aforementioned FIGS. 8A to 11C The various examples or variations shown also apply to FIGS. 12A-12D Another embodiment is shown.

[0140] In various embodiments of this application, the stack layer 310 may be formed in one step or may be composed of multiple stacks formed separately. In these embodiments, the virtual channel structure 320 may be formed in one step or immediately after the formation of each stack structure.

[0141] For example, in FIG. 5 process and FIGS. 6A-6G During the process, the contact hole depth changes as a result of the cyclical trimming-etching process along the first direction X. The contact hole 314 gradually becomes shallower from left to right along the first direction X. Meanwhile, in the second direction Y (refer to...), which is perpendicular to the first direction X... FIG. 7A A row of contact holes arranged on the surface (as shown) have the same depth.

[0142] In another embodiment of this application, multiple stepped zones with different contact hole depths can be formed by first performing a trimming-etching process cyclically in the second direction Y, and then performing a trimming-etching process cyclically in the first direction X, thereby obtaining contact holes with depth variations in both the first direction X and the second direction Y. (See reference...) FIG. 13A As shown, first, multiple openings 333 of the same depth reaching the stacked layer 310 are formed, and then a photoresist layer 370 is applied. Next, as... FIG. 13B As shown, the photoresist layer 370 is trimmed to expose one row of openings 333a on each side in the Y direction. Next, as... FIG. 13CAs shown, the stacked layer 310 corresponding to the exposed opening 333a is etched, deepening the exposed opening 333a towards the substrate 301 by an etching depth. In this embodiment, the etching depth is a thickness, namely the thickness of a pair of sacrificial layers 311 and dielectric layer 312. In other embodiments, the etching depth can be an integer multiple of the thickness of a pair of sacrificial layers 311 and dielectric layer 312. Next, as... FIG. 13D Trim the photoresist layer 370 to expose the four rows of openings 333a and 333b on both sides of the Y direction. Then, as follows... FIG. 13E As shown, the stacked layer 310 corresponding to the exposed openings 333a and 333b is etched, deepening the exposed openings 333a and 333b towards the substrate 301 by an etching depth. Then, as... FIG. 13F As shown, the photoresist layer 370 is trimmed to expose six rows of openings 333a, 333b, and 333c on both sides of the Y direction. Then, as... FIG. 13G As shown, the stacked layer 310 corresponding to the exposed openings 333a, 333b, and 333c is etched, deepening the exposed openings 333a, 333b, and 333c towards the substrate 301 by an etching depth. Ultimately, four contact holes of different depths are formed.

[0143] exist FIG. 13G When performing a trimming-etching process in the first direction X in the semiconductor structure shown, the etching depth for each step is 4 times the thickness of the sacrificial layer 311 and the dielectric layer 312.

[0144] The above example shows a 4-partition formation along the second direction Y. It can be understood that examples with 2-partition, 3-partition, 6-partition, etc. are also within the scope of this application.

[0145] In another embodiment of this application, after performing a trimming-etching process cyclically in the first direction X, a cutting (CHOP) process can also be performed to form multiple step partitions. For more information on step partitioning, please refer to... FIG. 1D As shown, but not in accordance with FIG. 1D The contact holes in each step zone are located at different depths of the stacked layers, and within each step zone, the depth of the contact holes gradually increases or decreases in the first direction X.

[0146] FIGS. 14A-14C Schematic diagrams of three different memory devices are shown. All three memory devices utilize a stacked layer 110 formed as described above, including multiple contact structures 119 that are in contact with gate layers of their respective depths. The contact structures 119 and contact structure plugs 119a are similar to the contact structures 319 and contact structure plugs 319a described above, and can be referred to the preceding description.

[0147] To formFIGS. 14A-14C The memory device shown can be constructed by first forming a stacked layer 110 with multiple contact structures 119 according to the method described above, wherein the semiconductor layer 103 can be the substrate described above. Then, the stacked layer 110 is inverted, and its structure is as follows... FIGS. 14A-14C The lower surface shown is connected to another semiconductor layer 101. An electrical connection is established with the semiconductor layer 101 through a contact structure plug 119a formed in a cap layer on top of the original stacked layer 110.

[0148] In some embodiments, semiconductor layer 101 includes logic devices in back-to-end (BEOL) processes. In some embodiments, semiconductor layer 101 includes CMOS devices.

[0149] refer to FIG. 14A As shown, according to one embodiment of this application, a memory device 100a has a core region A and a word line connection region B, and includes a substrate 101, a dielectric layer 102, and a stacked layer 110 stacked sequentially. The stacked layer 110 includes a plurality of gate layers 111 and a plurality of dielectric layers 112 stacked alternately. The core region A has a channel structure 130 extending through the stacked layer 110, serving as a memory array. The channel structure 130 may include a channel layer and, for example, a barrier layer, a charge trapping layer, or a tunneling layer. This is merely an example and is not intended to limit the scope of the application. The channel structure 130 located in the core region A is connected to a semiconductor layer 103 above the stacked layer 110 via a conductive portion 131. The word line connection region B has a plurality of virtual channel structures 120 extending through the stacked layer 110, and a plurality of contact structures 119 formed in the stacked layer according to the method described above. Each of the plurality of contact structures 119 extends through several layers in the stacked layer and contacts a gate layer 111 at a predetermined depth, respectively. Multiple insulating layers 115 surround the sidewalls of multiple contact structures 119 to electrically isolate the multiple contact structures 119 from the surrounding gate layer. For example, one or more gate spacers (not shown) extend through the stacked layer 110 to divide the stacked layer 110 into multiple memory blocks.

[0150] In this embodiment, since it is not necessary to etch the stacked layer 110 into a stepped structure, the upper surface of the stacked layer 110 is flat, or a relatively flat upper surface obtained after chemical mechanical polishing.

[0151] refer to FIG. 14B As shown, memory device 100b according to another embodiment of this application and FIG. 14A The difference lies in that, instead of forming conductive portions connected to the semiconductor layer 103, a channel structure 130 extends into the semiconductor layer 103. The semiconductor layer 103 includes a semiconductor sublayer 104. In some embodiments, this semiconductor sublayer 104 is used to form a doped well region. For example...FIG. 14B As shown, the channel structure 130 is a portion of structure 130a located in the semiconductor sublayer 104. Its side barrier layer, charge trapping layer, tunneling layer, etc., are stripped away, exposing the channel layer 132, which is in electrical contact with the semiconductor sublayer 104. The multiple virtual channel structures 120 located in the word line connection region B also have a similar structure. The portion of virtual channel structure 120 120 located in the semiconductor sublayer 104 has an exposed central structure 122, which is in contact with the surrounding semiconductor sublayer 104.

[0152] refer to FIG. 14C As shown, the memory device 100c according to another embodiment of this application differs from that in FIG. 14A in that it does not form a conductive portion connected to the semiconductor layer 103. Instead, it extends from the channel structure 130 into the semiconductor layer 103. The barrier layer, charge trapping layer, tunneling layer, etc., on the side of the channel structure 130 are stripped, exposing a portion of the structure 132a of the channel layer 132 in the semiconductor layer 103, which is in electrical contact with the semiconductor layer 103. The plurality of virtual channel structures 120 located in the word line connection region B also have a similar structure. A portion of the central structure 122a of the virtual channel structure 120 in the semiconductor sublayer 103 is exposed, and this portion of the central structure 122a is in contact with the surrounding semiconductor sublayer 104.

[0153] In some embodiments, FIGS. 14A-14C The semiconductor layer 103 is a polycrystalline silicon layer. In some embodiments, FIG. 14B and 14C A dielectric layer 105 is also formed on the semiconductor layer 103. After forming a stacked layer 110 with multiple contact structures 119 as described above, the stacked layer 110 is inverted, and after processing the upper surface, a polysilicon layer is redeposited on it, thereby forming a structure as described above. FIG. 14C The semiconductor layer 103 is shown. The inventors of this application have discovered that, since it is not necessary to form a step structure on the stacked layers, the layout of the word line connection area can be flexibly varied. FIGS. 14A-14C In various embodiments, the core area A and the word line connection area B can have different layouts.

[0154] FIGS. 15A-15G This is a schematic diagram showing the layout of the core area and word line connection area of ​​the memory device in various embodiments of this application, with reference to... FIGS. 15A-15B As shown, the X and Y directions are perpendicular to each other. In a three-dimensional memory, the X direction is parallel to the word line extension direction, and the Y direction is parallel to the bit line extension direction.

[0155] In some embodiments, the word line connection region extends in a direction parallel to the gate slot.

[0156] In some embodiments, the word line connection area extends in a direction perpendicular to the gate slot.

[0157] like FIG. 15A and 15B As shown, in one embodiment, there are two word line connection areas B, located on two opposite sides of the core area A. For example, FIG. 15A Two word line connection areas B are shown, which are arranged on both sides of the core area A along the X direction, and each word line connection area B extends along the Y direction; FIG. 15B Two word line connection areas B are shown, which are arranged along the Y direction on both sides of the core area A, and each word line connection area B extends along the X direction.

[0158] refer to FIGS. 15C-15E As shown, the word line connection area B can be a single entity, with at least two sides adjacent to the core area A. For example, two opposite sides of the word line connection area B are adjacent to the core area, such as... FIG. 15C As shown in 15D, or the four opposite sides of the word line connecting area B are adjacent to the core area, such as FIG. 15E As shown. The word line connection area B can extend along the X direction or the Y direction.

[0159] In some embodiments, the two ends of the word line connection area extend to the edge of the core area.

[0160] In some embodiments, at least one end of the word line connection area is located within the core area.

[0161] Furthermore, the word line connection region B can extend to the edge of the core region A. Advantageously, since only contact structures and virtual channel structures are arranged in the word line connection region B, without cutting off the individual gate layers, the gate layers on the core region A remain integrated. In this case, the memory device does not require additional bridging structures to connect the separated gate layers, thus simplifying this localized structure. FIG. 15E In the example, both ends of the word line connector B are located within the core area A. For example, the word line connector B is located in the center of the core area A.

[0162] In some embodiments, the memory device has a core region A and a plurality of word line connection regions B. For example... FIG. 15F As shown, these word line connection areas B are scattered along the sides of the core area A. Furthermore, multiple word line connection areas B are distributed on each of the opposite sides of the core area A, for example, four on each side. FIG. 15GAs shown, these word line connection areas B are dispersed within the core area A. Furthermore, the multiple word line connection areas B are distributed in multiple columns within the core area, for example, two columns with four elements in each column. It should be noted that the dispersed arrangement listed here is merely an example; other arrangements are possible without affecting the implementation of this application.

[0163] According to the manufacturing method of this application, the positional distribution of the core area A and the word line connection area B can be flexibly arranged according to product needs, reducing unnecessary leads or shortening lead lengths, thereby improving memory performance.

[0164] The inventors of this application have also discovered that, since it is not necessary to form a stepped structure on the stacked layers, the layout of the contact structure in the word line connection area can be flexibly varied. Therefore, according to one embodiment of this application, another method for manufacturing a memory device is proposed.

[0165] FIG. 16 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of this application. Figures 17A-17G are schematic cross-sectional views of an exemplary process in a method for manufacturing a memory device according to an embodiment of this application. Referring now to... FIG. 16 and FIGS. 17A-17G The manufacturing method of this embodiment is described in the figure.

[0166] In step 1601, a stacked layer is formed on the substrate. The stacked layer includes multiple sacrificial layers and multiple dielectric layers stacked alternately, and has a core region and a word line interconnect region. This step is related to... FIG. 2 The steps shown in step 201 are similar.

[0167] In some embodiments, at least two sides of the word line connection area are adjacent to the core area.

[0168] In some embodiments, multiple word line connection areas are distributed on the sides of the core area or within the core area.

[0169] The inventors of this application discovered during the trimming-etching process that each trimming-etching step requires strict control of the etching depth, especially when the number of cycles is high and deep-hole etching is involved, demanding high levels of process control. Poor control may lead to the risk of underetching (where etching penetrates a sacrificial layer, causing an entire memory cell to become uncircuited). Therefore, increasing the process window of the etching process is a pressing issue. FIG. 16In the manufacturing method of the illustrated embodiment, in step 1602, at least two contact holes are brought to the same sacrificial layer, thereby increasing the number of contact structures connected to the word lines of the same layer. This reduces the risk of contact structure underetching and increases the contact hole etching process window without adding additional process steps. Simultaneously, since multiple contact structures are connected in parallel on the same word line, the connection resistance of the contact structures can also be reduced.

[0170] like FIG. 17A As shown, the virtual channel structure is not shown in the cross-sectional view because the virtual channel structure and the contact hole to be formed are not aligned in the X direction. FIGS. 17A-17G This is used to illustrate the manufacturing method shown in Figure 16 and is not intended to limit whether the memory device includes a virtual channel structure or other structures such as a channel structure.

[0171] In step 1602, a plurality of contact holes of different depths are formed in the word line connection area of ​​the stacked layer, and the plurality of contact holes reach the sacrificial layer at their respective depths, wherein each sacrificial layer has at least two contact holes reaching it.

[0172] like FIG. 17B As shown, this embodiment is similar to FIG. 2 Step 202 and shown FIG. 3B The difference in the structure shown is that each sacrificial layer 311 has at least two contact holes. For example, FIG. 17B The two leftmost contact holes 302a both reach the semiconductor layer 301, and the two contact holes 302b adjacent to them both reach the first sacrificial layer 311 above the semiconductor layer 301. Here, "reaching" means that the bottom of the contact hole remains on the surface or inside the sacrificial layer 311, but does not penetrate it. FIG. 17B The structure shown can be achieved by... FIG. 5 or FIG. 9 In the process shown, the trimming-etching process changes each trimming step from one opening in the X direction to two openings in the X direction. FIG. 18A An exemplary trimming step is shown.

[0173] In step 1603, an insulating layer is formed on the sidewalls of the plurality of contact holes.

[0174] like FIG. 17C As shown, an insulating layer 315a is formed on the sidewall of each contact hole 314, while no insulating layer is formed at the bottom of the contact hole or is removed immediately after formation.

[0175] In step 1604, sacrificial material is filled inside the insulating layer of the plurality of contact holes to form a sacrificial structure.

[0176] like FIG. 17DAs shown, a sacrificial structure 316 is formed, with its bottom contacting each sacrificial layer 311.

[0177] exist FIG. 17D In the illustrated embodiment, there is no insulating layer at the bottom of the contact hole, and the sacrificial structure 316 directly contacts each sacrificial layer 311. In other embodiments, the manufacturing method shown in FIG6 can refer to the manufacturing method shown in FIG2, where the insulating layer at the bottom of the contact hole is retained first, and after filling the sacrificial structure 316, an insulating layer exists at the bottom of the sacrificial structure 316, such as... FIG. 3D As shown. In subsequent steps, the sacrificial structure 316 and the bottom insulating layer are removed, and conductive material is filled to form a contact structure, so that the contact structure is electrically connected to its corresponding gate layer.

[0178] In step 1605, multiple sacrificial layers in the stacked layers are replaced with gate layers.

[0179] like FIG. 17E As shown, the sacrificial layer 311 is replaced with the gate layer 311a. This step is similar to... FIG. 2 The steps shown in step 205 are similar.

[0180] In step 1606, the sacrificial structure in the contact hole is removed to expose the gate layer.

[0181] like FIG. 17F As shown, the sacrificial structure 316 of the contact hole 314 is removed to expose the gate layer 311a.

[0182] In step 1607, a contact structure is formed in the plurality of contact holes.

[0183] like FIG. 17G As shown, a contact structure 319 is formed in the contact hole 314. This step is related to... FIG. 2 Step 207 is similar. After this step, each gate layer 311a contacts two contact structures 319. Furthermore, a contact structure plug 319a is formed on top of each contact structure 319.

[0184] In another embodiment, an insulating layer may be formed or retained at the bottom of the contact hole 314 in step 1603, and in step 1606, after removing the sacrificial structure 316, the insulating layer at the bottom of the contact hole 314 is further removed. The process is now the same as... FIG. 2 The process shown is similar, the difference being the depth arrangement of the contact structure.

[0185] Understandable, FIG. 16 The process shown can also be combined with FIGS. 8A-8B The steps shown form the top opening 361, thereby forming a contact structure plug 319a with a larger critical dimension; combined with the processes shown in 11A-11C, an enlarged portion at the bottom of the contact structure is formed; combined withFIGS. 12A-12C The process shown forms a structure where the top of the contact structure 319 is lower than the top of the virtual channel structure 320; combined with FIGS. 13A-13G The process shown forms a memory structure with multiple partitions; or other variations or optimizations described above, which will not be elaborated here.

[0186] FIGS. 18A-18C yes FIG. 16 The illustrated embodiment shows an exemplary layout diagram of the contact structure and virtual channel structure. First, refer to... FIG. 18A As shown, the two contact structures 319b and two contact structures 319c are formed by filling contact holes created through a single trimming-etching process, and can be considered a group of contact structures that reach the same gate layer. Taking the two contact structures 319b as an example, the two contact structures 319b on each gate layer are arranged along the X direction. If the X direction is called a row, then the two contact structures 319b are located in the same row. It can be understood that the other two contact structures 319c are also located in the same row. A virtual channel structure 320 is arranged around the contact structures 319. FIGS. 18A-18C For illustrative purposes only, this is not intended to limit the actual arrangement of the contact structure 319, or the positional relationship between the virtual channel structure 320 and the contact structure 319.

[0187] refer to FIG. 18B As shown, the two contact structures 319b on each gate layer are staggered in the X direction, that is, located in different rows.

[0188] refer to FIG. 18C As shown, a set of contact structures reaching the same gate layer includes three contact structures 319b and three contact structures 319c. Each contact structure is staggered in the X direction and is not located in the same row. Some contact structures are aligned in the Y direction, that is, located in the same column.

[0189] In some embodiments, the diameter of the contact structure is about 200 nm. Using the layout of this embodiment, each gate layer will be in contact with more than two contact structures with a diameter of about 200 nm, which significantly increases the contact area.

[0190] FIG. 19A and 19B Cross-sectional and top views of memory devices for comparison. FIG. 17G and FIG. 19A , FIGS. 18A-18C and FIG. 19B ,like FIG. 19A and 19BDuring the formation of the conventional stepped contact structure, due to limitations in the step trimming and contact structure process window, only one contact structure 1901 and one virtual channel structure 1902 can be placed on the first trimming step. The contact structure 1901 cannot be placed where the virtual channel structure 1902 is located; otherwise, the contact structure 1901 would contact both steps, causing gate word line leakage. However, in the word line connection area of ​​this embodiment, there are no steps. Therefore, within the same trimming window, multiple contact structures can be designed to fall on the same word line. During back-end wiring, contact structures on the same word line can be connected in parallel. This design can increase the contact structure etching window and reduce resistance.

[0191] The memory device formed in this embodiment and FIGS. 14A-14C The difference in the illustrated memory device is that each gate layer 112 is in contact with at least two contact structures 119. Other structures can be found in [reference needed]. FIG. 14A - 14C, which will not be described in detail here.

[0192] FIG. 20 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of this application. Figures 21A-21G are schematic cross-sectional views of an exemplary process of a method for manufacturing a memory device according to an embodiment of this application. Referring now to... FIG. 20 and FIGS. 21A-21D The manufacturing method of this embodiment is described in the figure.

[0193] In step 2001, a stacked layer 310 is formed on the substrate. The stacked layer 310 includes a plurality of alternately stacked sacrificial layers 311 and a plurality of dielectric layers 312, and has a core region and a word line connection region, as shown in FIG21A. This step is related to... FIG. 16 The steps shown in step 1601 are similar, and the relevant explanatory content can be used to explain this step 2001.

[0194] In step 2002, a plurality of contact holes 314 of different depths are formed in the word line connection area of ​​the stacked layer 310. The plurality of contact holes 314 reach the sacrificial layer 311 at their respective depths, wherein each sacrificial layer is reached by at least two contact holes 314, such as... FIG. 21B As shown. This step is related to... FIG. 16 The steps shown in step 1602 are similar, and the relevant explanatory content can be used to explain this step 2002.

[0195] In step 2003, an insulating layer 315a is formed on the sidewalls of the plurality of contact holes 314, such as FIG. 21C As shown. This step is related to... FIG. 16 The steps shown in step 2003 are similar, and the relevant explanatory content can be used to explain step 2003.

[0196] In step 2004, a hard mask layer 380 is overlaid on the stacked layer 310, such as... FIG. 21D As shown. A hard mask layer 380 is overlaid on the stacked layer 310 to protect each contact hole 314.

[0197] In step 2005, the hard mask layer 380 is patterned, and the patterned hard mask layer 380 is used to form gate slots 318 in the stacked layer.

[0198] In step 2006, the hard mask layer 380 is removed.

[0199] like FIG. 22 As shown, a patterned hard mask layer 380 is used to form gate spacing slots 318 in the stacked layers. Then, the hard mask layer is removed to obtain... FIG. 21E The structure shown.

[0200] In step 2007, multiple sacrificial layers are removed to form multiple gaps between multiple dielectric layers.

[0201] like FIG. 21F As shown, wet etching is performed through the gate line slots 318 to remove the sacrificial layer 311, thereby forming multiple gaps 311s between the dielectric layers 312.

[0202] In step 2008, conductive material is filled into multiple contact holes and multiple gaps to form contact structures and gate layers, respectively.

[0203] like FIG. 21G As shown, a gate layer 311a is formed by filling the gap 311s with conductive material, and a contact structure 319 is formed by filling the contact hole 314 with conductive material. After this step, each gate layer 311a contacts two contact structures 319. In this embodiment, filling the contact hole and the gap together can save process steps such as filling the contact hole with sacrificial material, etching the cap layer, and filling the contact hole.

[0204] Understandable, FIG. 20 The process shown can also be combined with FIGS. 8A-8B The steps shown are the process flow shown in 11A-11C. FIGS. 12A-12C The process shown is as follows: FIGS. 13A-13G The process shown, or other variations or optimizations described above, will not be elaborated upon here.

[0205] In the above process, before forming multiple contact holes of different depths in the stacked layer 310, multiple channel structures penetrating the stacked layer are also formed in the core area of ​​the stacked layer.

[0206] The advantage of this embodiment is that the contact structure 319 and the gate layer 311a are integrally formed, which eliminates the need for features such as... FIG. 16The process shown includes steps such as filling the sacrificial structure and opening the cap layer before removing the sacrificial structure.

[0207] In the context of this application, the memory device may be 3D flash memory, such as 3D NAND flash memory.

[0208] FIG. 23 This is a block diagram of a system having a memory device according to an embodiment of this application. (Reference) FIG. 23 As shown, the system 2300 includes a memory system 2302. The memory system 2302 has one or more memory devices 2304 and a memory controller 2306. The memory device 2304 is any of the memory devices described above and is configured to store data. The memory controller 2306 is coupled to the memory device 2304 and is configured to control the memory device 2304.

[0209] refer to FIG. 23 As shown, in some embodiments, the system 2300 also includes a host 2308 coupled to the memory controller 2306.

[0210] System 2300 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (having storage therein). Host 2308 may be a processor of the electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 2308 may be configured to send or receive data to and from memory device 2304.

[0211] The memory device 2304 may be any memory device disclosed herein. In some embodiments, each memory device 2304 includes an array of memory cells and peripheral circuitry of the array of memory cells, the array of memory cells and the peripheral circuitry being stacked on top of each other in different planes.

[0212] According to some embodiments, memory controller 2306 is coupled to memory device 2304 and host 2308 and is configured to control memory device 2304. Memory controller 2306 can manage data stored in memory device 2304 and communicate with host 2308. In some embodiments, memory controller 2306 is designed to operate in a low duty cycle environment, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 2306 is designed to operate in a high duty cycle environment, such as SSDs or embedded multi-media cards (eMMCs) used as data storage devices in mobile devices such as smartphones, tablets, laptops, etc. Memory controller 2306 can be configured to control the operation of memory device 2304, such as read, erase, and program operations. In some embodiments, the memory controller 2306 is configured to control an array of memory cells via first and second peripheral circuitry. The memory controller 2306 may also be configured to manage various functions relating to data stored in or to be stored in the memory device 2304, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 2306 is further configured to process error correction codes (ECCs) relating to data read from or written to the memory device 2304. The memory controller 2306 may also perform any other appropriate functions, such as formatting the memory device 2304. The memory controller 2306 may communicate with external devices (e.g., host 2308) according to a specific communication protocol.For example, the memory controller 2306 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0213] The memory controller 2306 and one or more memory devices 2304 can be integrated into various types of memory devices, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 2302 can be implemented and packaged into different types of end electronic products. FIG. 24A In one example shown, the memory controller 2306 and a single memory device 2304 can be integrated into the memory card 2402. The memory card 2402 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 2402 may further include a connection between the memory card 2402 and a host (e.g., FIG. 23 The memory card connector 2404 is coupled to the host 2308. In such a... FIG. 24B In another example shown, the memory controller 2306 and multiple memory devices 2304 can be integrated into the SSD 2406. The SSD 2406 may further include interfaces between the SSD 2406 and a host (e.g., ...). FIG. 23 The SSD connector 2408 is coupled to the host 2308. In some embodiments, the storage capacity and / or operating speed of the SSD 2406 is higher than that of the memory card 2402.

[0214] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0215] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0216] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0217] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0218] Although this application has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, any changes or modifications to the above embodiments within the essential spirit of this application will fall within the scope of the claims of this application.

Claims

1. A memory device, comprising: A stacked layer, comprising multiple gate layers and multiple dielectric layers stacked alternately; Multiple contact structures, each of which passes through the stacked layer and contacts a gate layer at a predetermined depth, wherein each gate layer contacts at least two contact structures; Multiple insulating layers surround the sidewalls of the multiple contact structures to electrically isolate the multiple contact structures from the gate layer penetrated by the multiple contact structures; as well as One or more gate spacers extend through the stacked layer.

2. The memory device as claimed in claim 1, characterized in that, It also includes a semiconductor layer, and the stacked layer is located on the semiconductor layer.

3. The memory device as claimed in claim 1, characterized in that, The at least two contact structures on each gate layer are arranged along the extension direction of the gate spacer.

4. The memory device as claimed in claim 1, characterized in that, The at least two contact structures on each gate layer are offset in the direction of extension of the gate slot.

5. The memory device as claimed in claim 1, characterized in that, The plurality of contact structures have enlarged tops.

6. The memory device as claimed in claim 1, characterized in that, The memory device includes a core region and a word line connection region, the core region having a memory array, and the plurality of contact structures located in the word line connection region.

7. The memory device as claimed in claim 6, characterized in that, It also includes multiple virtual channel structures located in the word line connection area and passing through the stack layer.

8. The memory device as claimed in claim 1, characterized in that, The upper surface of the stacked layer is flat.

9. The memory device as claimed in claim 1, characterized in that, The contact structure and the gate layer are integrally formed.

10. A method for manufacturing a memory device, comprising the following steps: A stacked layer is formed, the stacked layer comprising multiple sacrificial layers and multiple dielectric layers stacked alternately, and having a core region and a word line connection region; Multiple contact holes of different depths are formed in the word line connection area of ​​the stacked layer, and the multiple contact holes reach the sacrificial layer at their respective depths, wherein each sacrificial layer is reached by at least two contact holes; An insulating layer is formed on the sidewalls and bottom of the plurality of contact holes; Sacrificial material is filled inside the insulating layer of the plurality of contact holes to form a sacrificial structure; Replace the plurality of sacrificial layers in the stacked layers with gate layers; Remove the sacrificial structures in the plurality of contact holes to expose the gate layer; as well as A contact structure is formed in the plurality of contact holes.

11. The method as described in claim 10, characterized in that, The step of forming a first dielectric layer covering the stacked layer, wherein forming a plurality of contact holes of different depths in the word line connection region of the stacked layer includes: A hard mask layer is formed covering the first dielectric layer, and a photoresist layer is coated on the hard mask layer; The hard mask layer is patterned by the photoresist layer to form multiple openings in the sacrificial layer or dielectric layer that penetrate the first dielectric layer and reach the top of the stacked layer; By cyclically performing a trimming-etching process, multiple contact holes of varying depths are formed using the multiple openings; and Remove the photoresist layer and hard mask layer.

12. The method as described in claim 10, characterized in that, The step of forming multiple contact holes of different depths in the word line connection area of ​​the stacked layer includes: A hard mask layer is formed to cover the stacked layers, and a photoresist layer is coated on the hard mask layer; By cyclically performing a trimming-etching process, multiple contact holes of varying depths are formed using the multiple openings; and Remove the photoresist layer and hard mask layer, and enlarge the bottom of the plurality of contact holes along the extension direction of the stacked layers.

13. The method as described in claim 11 or 12, characterized in that, The steps of cyclically performing the trimming-etching process include trimming the photoresist layer in the direction of the word line connection area toward the core area to expose a predetermined number of openings and etching the exposed openings, wherein each time the exposed openings are etched, the etched openings are deepened by an etching depth to reach the next insulating layer.

14. The method as described in claim 13, characterized in that, Before performing the trimming-etching process, the process also includes forming multiple stepped partitions of different depths of contact holes arranged parallel to the core area in the word line connection area.

15. The method as described in claim 11 or 12, characterized in that, After the trimming-etching process is repeated, a cutting process is also performed to form multiple step partitions. The contact holes in each step partition are located at different depths of the stacked layers, and the depth of the contact holes in each step partition gradually increases or decreases in the direction away from the core area.

16. The method as described in claim 10, characterized in that, After filling the insulating layer inside the plurality of contact holes with a sacrificial structure, a second capping layer is also formed to cover the stacked layers; After replacing the plurality of sacrificial layers in the stacked layers with gate layers, the process further includes patterning the second cap layer to form openings that expose the sacrificial structures in the plurality of contact holes, the openings being used to remove the sacrificial structures and the insulating layers.

17. The method as described in claim 16, characterized in that, Along the extension direction of the stacked layers, the critical dimension of the opening is larger than the overall critical dimension of the insulating layer and the sacrificial pillar.

18. The method as described in claim 10, characterized in that, Before forming multiple contact holes of different depths in the stacked layer, multiple virtual channel structures that penetrate the stacked layer are also formed in the core area of ​​the stacked layer.

19. The method as described in claim 10, characterized in that, After filling the inner side of the insulating layer of the plurality of contact holes with sacrificial structures, a plurality of virtual channel structures penetrating the stacked layer are formed in the core region of the stacked layer.

20. A method for manufacturing a memory device, comprising the following steps: A stacked layer is formed, the stacked layer comprising multiple sacrificial layers and multiple dielectric layers stacked alternately, and having a core region and a word line connection region; Multiple contact holes of different depths are formed in the word line connection area of ​​the stacked layer, and the multiple contact holes reach the sacrificial layer at their respective depths, wherein each sacrificial layer is reached by at least two contact holes; An insulating layer is formed on the sidewalls and bottom of the plurality of contact holes; Cover the stacked layers with a hard mask layer; The hard mask layer is patterned, and the patterned hard mask layer is used to form gate slots in the stacked layers; Remove the hard mask layer; Remove the plurality of sacrificial layers to form a plurality of gaps between the plurality of dielectric layers; Conductive material is filled into the plurality of contact holes and the plurality of gaps to form contact structures and gate layers, respectively.

21. The method as described in claim 20, characterized in that, After forming multiple contact holes of different depths in the word line connection area of ​​the stacked layer, the method further includes: The bottom of the plurality of contact holes is enlarged along the extension direction of the stacked layer.

22. The method as described in claim 20, characterized in that, The step of forming a first dielectric layer covering the stacked layers, wherein forming a plurality of contact holes of different depths in the word line interconnect region of the stacked layers includes: A hard mask layer is formed covering the first dielectric layer, and a photoresist layer is coated on the hard mask layer; The hard mask layer is patterned by the photoresist layer to form multiple openings in the sacrificial layer or dielectric layer that penetrate the first dielectric layer and reach the top of the stacked layer; By cyclically performing a trimming-etching process, multiple contact holes of varying depths are formed using the multiple openings; and Remove the photoresist layer and hard mask layer.

23. The method as described in claim 20, characterized in that, The step of forming multiple contact holes of different depths in the word line connection area of ​​the stacked layer includes: A hard mask layer is formed to cover the stacked layers, and a photoresist layer is coated on the hard mask layer; By cyclically performing a trimming-etching process, multiple contact holes of varying depths are formed using the multiple openings; and Remove the photoresist layer and hard mask layer.

24. The method as described in claim 22 or 23, characterized in that, The steps of cyclically performing the trimming-etching process include trimming the photoresist layer in the direction of the word line connection area toward the core area to expose a predetermined number of openings and etching the exposed openings, wherein each time the exposed openings are etched, the etched openings are deepened by an etching depth to reach the next insulating layer.

25. The method as described in claim 24, characterized in that, Before performing the trimming-etching process, the process also includes forming multiple stepped partitions of different depths of contact holes arranged parallel to the core area in the word line connection area.

26. The method as described in claim 22 or 23, characterized in that, After the trimming-etching process is repeated, a cutting process is also performed to form multiple step partitions. The contact holes in each step partition are located at different depths of the stacked layers, and the depth of the contact holes in each step partition gradually increases or decreases in the direction away from the core area.

27. The method as described in claim 20, characterized in that, Before forming multiple contact holes of different depths in the stacked layer, multiple virtual channel structures that penetrate the stacked layer are also formed in the word line connection area of ​​the stacked layer.

28. A system, characterized in that, Includes a memory device as described in any one of claims 1-9, configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.

29. The system as described in claim 28, characterized in that, It also includes a host coupled to the memory controller.

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