Circuit arrangement with reduced dependency on layout environment

Abstract

This application relates to a circuit arrangement having reduced dependency on a layout environment. An integrated circuit includes an intermediate active area structure between a first set of active area structures and a second set of active area structures. The integrated circuit also includes a main circuit, a first set of circuits, and a second set of circuits. The main circuit includes at least one boundary gate conductor intersecting the intermediate active area structure. The first set of circuits includes a first set of isolation structures separating the first set of active area structures into a first portion in the first set of circuits and a second portion in a first adjacent circuit. The second set of circuits includes a second set of isolation structures separating the second set of active area structures into a first portion in the second set of circuits and a second portion in a second adjacent circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and more specifically to a circuit arrangement with reduced dependency on layout environment. BACKGROUND

[0002] Recent trends in miniaturizing integrated circuits (ICs) have resulted in smaller devices that consume less power but provide functionality at higher speeds. The miniaturization process has also resulted in more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs of integrated circuits while ensuring that the standard cell layout designs and manufacturing specifications are met. SUMMARY

[0003] According to a first aspect of the present disclosure, there is provided an integrated circuit comprising: an intermediate active region structure between a first set of active region structures and a second set of active region structures, wherein the intermediate active region structure is aligned with the first set of active region structures and the second set of active region structures along a first direction; a main circuit comprising: a first boundary gate conductor intersecting the intermediate active region structure at a first end of the intermediate active region structure, a second boundary gate conductor intersecting the intermediate active region structure at a second end of the intermediate active region structure, and an adjacent gate conductor separated by a pitch distance equal to a contact poly pitch (“CPP”) between the first boundary gate conductor and the second boundary gate conductor; a first set of circuits comprising: a first set of boundary gate conductors intersecting the first set of active region structures at a first end of the first set of active region structures and separated by a pitch distance of one CPP from the first boundary gate conductor in the main circuit, and a first set of isolation structures separating the first set of active region structures into a first portion in the first set of circuits and a second portion in a first adjacent circuit, wherein a width of the first set of isolation structures along the first direction is less than half of the CPP; and a second set of circuits comprising: a second set of boundary gate conductors intersecting the second set of active region structures at a first end of the second set of active region structures and separated by a pitch distance of one CPP from the second boundary gate conductor in the main circuit, and a second set of isolation structures separating the second set of active region structures into a first portion in the second set of circuits and a second portion in a second adjacent circuit, wherein a width of the second set of isolation structures along the first direction is less than half of the CPP.

[0004] According to a second aspect of the disclosure, a method for forming a semiconductor structure is provided, comprising: fabricating an active region semiconductor structure on an insulator support; fabricating a gate conductor intersecting the active region semiconductor structure; fabricating a terminal conductor intersecting the active region semiconductor structure; dividing the active region semiconductor structure into a plurality of active region semiconductor structures including an intermediate active region structure between a first group of active region structures and a second group of active region structures such that a first boundary gate conductor is formed at a first end of the intermediate active region structure, a second boundary gate conductor is formed at a second end of the intermediate active region structure, a first group of boundary gate conductors is formed at first ends of the first group of active region structures, and a second group of boundary gate conductors is formed at first ends of the second group of active region structures; depositing an interlayer dielectric material covering the intermediate active region structure, the first group of active region structures, the second group of active region structures, and the gate conductor; forming a first trench to divide the first group of active region structures into a first portion and a second portion after removing a first gate conductor, and forming a second trench to divide the second group of active region structures into a first portion and a second portion after removing a second gate conductor; and forming a first group of isolation structures in the first trench, and forming a second group of isolation structures in the second trench.

[0005] According to a third aspect of the disclosure, an integrated circuit is provided, comprising: an intermediate first-type active region structure between a first group of first-type active region structures and a second group of first-type active region structures, wherein the intermediate first-type active region structure is aligned with the first group of first-type active region structures and the second group of first-type active region structures along a first direction; a main circuit comprising: a first boundary gate conductor intersecting the intermediate first-type active region structure at a first end of the intermediate first-type active region structure, and an adjacent gate conductor separated by a pitch distance equal to a contact poly pitch (“CPP”); a first group circuit comprising: a first group boundary gate conductor intersecting the first group of first-type active region structures at a first end of the first group of first-type active region structures, and separated from the first boundary gate conductor in the main circuit by a pitch distance of one CPP, and a first group isolation structure separating the first group of first-type active region structures into a first portion in the first group circuit and a second portion in a first adjacent circuit, wherein a width of the first group isolation structure along the first direction is less than half of the CPP; and a second group circuit comprising: a second group isolation structure separating the second group of first-type active region structures into a first portion in the second group circuit and a second portion in a second adjacent circuit, wherein a width of the second group isolation structure along the first direction is less than half of the CPP. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can be best understood with reference to the following specific description in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions can be arbitrarily increased or decreased for the sake of discussion. The drawings are intended to be illustrative, and not limiting.

[0007] Figures 1A-1C is a schematic layout of an integrated circuit according to some embodiments.

[0008] Figures 1D-1E is a cross-sectional view of an integrated circuit in Figures 1A-1C according to some embodiments.

[0009] Figures 2A-2B and Figures 2A(a)-2B(a) is a cross-sectional view of a circuit cell of an integrated circuit at a boundary in Figures 1A-1C according to some embodiments.

[0010] Figures 3A-3D and Figures 3B(a)-3C(a) is a cross-sectional view of an integrated circuit in Figures 1A-1C at a selected cut plane according to some embodiments.

[0011] Figures 4A-4B is a schematic layout of an integrated circuit according to some embodiments.

[0012] Figures 4C-4D is a cross-sectional view of an integrated circuit in Figures 4A-4B according to some embodiments.

[0013] Figures 5A-5D and Figure 5B is a cross-sectional view of an integrated circuit in Figures 4A-4B at a selected cut plane according to some embodiments.

[0014] Figures 6A-6F is a schematic layout of an integrated circuit according to some embodiments.

[0015] Figures 6G-6H is a cross-sectional view of an integrated circuit in Figures 6A-6F according to some embodiments.

[0016] Figures 7A-7D and Figures 7A(a)-7D(a) is a cross-sectional view of an integrated circuit in Figures 6A-6F at a selected cut plane according to some embodiments.

[0017] Figures 8A-8C is a schematic layout of an integrated circuit according to some embodiments.

[0018] Figures 8D-8E is a cross-sectional view of an integrated circuit in Figures 8A-8C

[0019] Figures 9A-9D and Figures 9A(a)-9B(a) is a cross-sectional view of an integrated circuit in Figures 8A-8C

[0020] Figure 10A is a layout view of an integrated circuit having a main circuit between a first group of circuits and a second group of circuits, according to some embodiments.

[0021] Figures 10B-10C is a cross-sectional view of an integrated circuit in Figure 10A

[0022] Figure 11 is a layout view of an integrated circuit having a main circuit between a first group of circuits and a second group of circuits, according to some embodiments.

[0023] Figure 12A is a layout view of a combinational circuit cell and an adjacent cell adjacent to the combinational circuit cell, according to some embodiments.

[0024] Figures 12B-12C is a cross-sectional view of an integrated circuit in Figure 12A

[0025] Figure 13A is a layout view of a combinational circuit cell and an adjacent cell adjacent to the combinational circuit cell, according to some embodiments.

[0026] Figures 13B-13C is a cross-sectional view of an integrated circuit in Figure 13A

[0027] Figure 14 is a flowchart of a method of manufacturing an integrated circuit, according to some embodiments.

[0028] Figures 15A-15F is a cross-sectional view of an integrated circuit at various stages of manufacture, according to some embodiments.

[0029] Figure 16 is a block diagram of an electronic design automation (EDA) system, according to some embodiments.

[0030] Figure 17 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0031] ​​​​​The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described herein to simplify the present disclosure. These are, of course, merely examples and are in no way limiting to the scope of the present disclosure. Other components, values, operations, materials, arrangements, etc. are contemplated. For instance, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature, such that the first feature and the second feature can not be in direct contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0032] Moreover, spatially relative terms (e.g., "beneath," "below," "lower," "above," "upper," and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Such spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0033] In some embodiments, the combined circuit cell includes a main circuit between a first set of circuits and a second set of circuits. A first set of isolation structures separates a first set of active region structures into a first portion in the first set of circuits and a second portion in a first adjacent circuit. A second set of isolation structures separates a second set of active region structures into a first portion in the second set of circuits and a second portion in a second adjacent circuit. In some embodiments, each active region structure includes a channel region, a source region, and a drain region of a transistor. While the combined circuit cell in a layout design generated by an auto placement and routing (APR) program can still be affected by layout environment changes, the main circuit has reduced dependency on the layout environment. Because the first set of circuits and the second set of circuits separate the main circuit from adjacent circuits, the variation / uncertainty of the timing delay of the main circuit due to layout environment changes is reduced compared to some alternative implementations in which the main circuit is placed directly in the layout design by the APR program.

[0034] Figures 1A-1C is a schematic layout diagram of integrated circuits 100A, 100B, and 100C in accordance with some embodiments. Figures 1A-1CEach schematic layout diagram includes a layout pattern for specifying a first set of first-type active region structures 82L extending in the X direction, an intermediate first-type active region structure 82M extending in the X direction, and a second set of first-type active region structures 82R extending in the X direction. Figures 1A-1C Each schematic layout diagram also includes a layout pattern for specifying a first set of second-type active region structures 84L extending in the X direction, an intermediate second-type active region structure 84M extending in the X direction, and a second set of second-type active region structures 84R extending in the X direction.

[0035] in addition, Figures 1A-1C Each schematic layout diagram includes a layout pattern for specifying a first boundary gate conductor 51 extending in the Y direction, a second boundary gate conductor 59 extending in the Y direction, a first set of boundary gate conductors 41 extending in the Y direction, a second set of boundary gate conductors 61 extending in the Y direction, and various gate conductors (e.g., 142, 148, 152, 158, 162, 168) extending in the Y direction. Figures 1A-1C Each schematic layout diagram also includes a layout pattern for specifying a first set of isolation structures 49 extending in the Y direction and a second set of isolation structures 69 extending in the Y direction. Figures 1A-1C In the schematic layout diagram, the Y direction is perpendicular to the X direction. Layout patterns CPO1 and CPO9, extending in the X direction, specify the cuts to the gate conductors and boundary gate conductors. Although extending in the Y direction, each gate conductor and boundary gate conductor terminates before reaching the two horizontal boundaries of the circuit cell (extending in the X direction). Neither gate conductor nor boundary gate conductor extends into adjacent circuit cells.

[0036] like Figures 1A-1C As shown in the schematic layout diagram, the intermediate first-type active region structure 82M is located between the first group of first-type active region structures 82L and the second group of first-type active region structures 82R. The intermediate first-type active region structure 82M is aligned with the first group of first-type active region structures 82L and the second group of first-type active region structures 82R along the X-direction. The intermediate second-type active region structure 84M is located between the first group of second-type active region structures 84L and the second group of second-type active region structures 84R. The intermediate second-type active region structure 84M is aligned with the first group of second-type active region structures 84L and the second group of second-type active region structures 84R along the X-direction.

[0037] exist Figures 1A-1CIn some embodiments, each active region structure is a p-type active region structure or an n-type active region structure. A transistor fabricated with a p-type active region structure is a PMOS, and a transistor fabricated with an n-type active region structure is an NMOS. In some embodiments, the active region structure is a fin structure, and the transistor fabricated with the active region structure is a FinFET. In some embodiments, the active region structure is a nanosheet structure, and the transistor fabricated with the active region structure is a nanosheet transistor. In some embodiments, the active region structure is a nanowire structure, and the transistor fabricated with the active region structure is a nanowire transistor.

[0038] In some embodiments, each of the intermediate first-type active region structures 82M, the first set of first-type active region structures 82L, and the second set of first-type active region structures 82R is a p-type active region structure, and each of the intermediate second-type active region structures 84M, the first set of second-type active region structures 84L, and the second set of second-type active region structures 84R is an n-type active region structure. In some alternative embodiments, each of the intermediate first-type active region structures 82M, the first set of first-type active region structures 82L, and the second set of first-type active region structures 82R is an n-type active region structure, and each of the intermediate second-type active region structures 84M, the first set of second-type active region structures 84L, and the second set of second-type active region structures 84R is a p-type active region structure.

[0039] In some embodiments, the first set of first-type active region structures 82L and the second set of first-type active region structures 82R are each a set of p-type active region structures, and the first set of second-type active region structures 84L and the second set of second-type active region structures 84R are each a set of n-type active region structures. Figures 1A-1C In some embodiments, the first set of first-type active region structures 82L and the second set of first-type active region structures 82R are each a set of n-type active region structures, and the first set of second-type active region structures 84L and the second set of second-type active region structures 84R are each a set of p-type active region structures. Figure 1A In some embodiments, the first set of first-type active region structures 82L and the second set of first-type active region structures 82R are each a set of n-type active region structures, and the first set of second-type active region structures 84L and the second set of second-type active region structures 84R are each a set of p-type active region structures.

[0040] In some embodiments, the first set of first-type active region structures 82L and the second set of first-type active region structures 82R are each a set of n-type active region structures, and the first set of second-type active region structures 84L and the second set of second-type active region structures 84R are each a set of p-type active region structures. Figure 1B In some embodiments, the first set of first-type active region structures 82L and the second set of first-type active region structures 82R are each a set of n-type active region structures, and the first set of second-type active region structures 84L and the second set of second-type active region structures 84R are each a set of p-type active region structures.

[0041] In Figure 1C , the layout pattern CPO4 specifies that the first boundary gate conductor 51 is cut into a first segment 51U and a second segment 51L. The first segment 51U and the second segment 51L of the first boundary gate conductor 51 each intersect a respective middle active area structure at a first end of the middle active area structure 82M and 84M, respectively. The second boundary gate conductor 59 intersects a respective middle active area structure at a second end of each middle active area structure 82M and 84M.

[0042] In Figures 1A-1C , the main circuit 50 further includes gate conductors (e.g., 152,..., and 158) that extend in the Y direction between the first boundary gate conductor 51 and the second boundary gate conductor 59. One or more gate conductors in the main circuit 50 intersect a middle active area structure 82M and / or 84M at a channel region of a transistor in the main circuit 50. In Figures 1A-1C , one or more gate conductors (indicated by the ellipsis “...”) between the gate conductors 152 and 158 are not explicitly depicted with a gate conductor pattern. The main circuit 50 further includes terminal conductors that are not explicitly depicted with a terminal conductor pattern in Figures 1A-1C . The terminal conductors in the main circuit 50 intersect a middle active area structure 82M and / or 84M at a channel region of a transistor in the main circuit 50. The terminal region is a source region or a drain region. Other elements in the main circuit 50 that are not explicitly shown in Figures 1A-1C include various via connections and various wiring conductors in one or more metal layers.

[0043] In Figures 1A-1C , at least one pair of adjacent gate conductors in the main circuit 50 has a pitch distance that is equal to a contacted poly pitch (“CPP”). The pitch distance between the first boundary gate conductor 51 and the gate conductor 152 is one CPP, and the pitch distance between the second boundary gate conductor 59 and the gate conductor 158 is one CPP.

[0044] In Figures 1A-1CIn particular embodiments, the first set of circuitry 40 includes a first set of boundary gate conductors 41 and a first set of isolation structures 49. The first set of boundary gate conductors 41 intersects the respective first set of active region structures at the first end of each first set of active region structures 82L and 84L. The first set of boundary gate conductors 41 in the first set of circuitry 40 is separated from the first boundary gate conductor 51 in the main circuitry 50 by a pitch distance of one CPP. Thus, the vertical boundary (extending in the Y direction) of the first set of circuitry 40 and the main circuitry 50 is separated by a pitch distance of one CPP. In some embodiments, the implementation of the first set of boundary gate conductors 41 and the first boundary gate conductor 51 at the end of the respective active region structures is referred to as a Poly On Diffusion Edge (“PODE”) implementation.

[0045] In Figures 1A-1C In particular embodiments, the first set of isolation structures 49 separates each first set of active region structures 82L and 84L into a first portion in the first set of circuitry 40 and a second portion in the first adjacent circuitry. The width “W*” of the first set of isolation structures 49 along the X direction is less than one half of a CPP. In some embodiments, the width “W*” of the first set of isolation structures 49 is less than one fourth of a CPP. In some embodiments, the implementation of separating an active region structure (e.g., 82L or 84L) into two portions with an isolation structure (e.g., 49) is referred to as a Continuous Poly On Oxide Definition (“CPODE”) implementation, and the isolation structure (e.g., 49) is referred to as a CPODE isolation structure.

[0046] In Figures 1A-1CIn some embodiments, the first set of circuitry 40 further includes gate conductors (e.g., 142,..., and 148) between the first set of isolation structures 49 and the first set of boundary gate conductors 41. One or more gate conductors (indicated by the symbol “..”) between gate conductors 142 and 148 are not explicitly depicted with the gate conductor pattern. In some embodiments, one or more gate conductors (e.g., 142,..., 148) intersect the first set of active area structures 82L and / or 84L at channel regions of transistors in the first set of circuitry 40 and form gate terminals of the transistors. In some embodiments, one or more gate conductors (e.g., 142,..., 148) intersect the first set of active area structures 82L and / or 84L but do not serve as gate terminals of transistors in the first set of circuitry 40. In some embodiments, the first set of circuitry 40 further includes terminal conductors that are not explicitly depicted with the terminal conductor pattern. In some embodiments, terminal conductors in the first set of circuitry 40 intersect the first set of active area structures 82L and / or 84L at channel regions of transistors in the first set of circuitry 40 and form source / drain terminals of the transistors. In some embodiments, terminal conductors in the first set of circuitry 40 intersect the first set of active area structures 82L and / or 84L but do not serve as source / drain terminals of transistors in the first set of circuitry 40. In some embodiments, the first set of circuitry 40 further includes additional elements that are not explicitly shown in Figures 1A-1C Examples of additional elements include via connections and routing wires in one or more metal layers.

[0047] In Figures 1A-1C In some embodiments, the second set of circuitry 60 includes a second set of boundary gate conductors 61 and a second set of isolation structures 69. The second set of boundary gate conductors 61 intersects the respective first set of active area structures at the first end of each second set of active area structures 82R and 84R. The second set of boundary gate conductors 61 in the second set of circuitry 60 is separated from the second boundary gate conductor 59 in the main circuitry 50 by a pitch distance of one CPP. Thus, the vertical boundary (extending in the Y direction) of the second set of circuitry 60 and the main circuitry 50 is separated by a pitch distance of one CPP. In some embodiments, the implementation of the second set of boundary gate conductors 61 and the second boundary gate conductor 59 at the end of the respective active area structures is referred to as a PODE implementation.

[0048] In Figures 1A-1CIn some embodiments, the second set of isolation structures 69 separate each of the second set of active region structures 82R and 84R into a first portion in the second set of circuits 60 and a second portion in a second adjacent circuit. The width "W*" of the second set of isolation structures 69 along the X-direction is less than half of CPP. In some embodiments, the width "W*" of the second set of isolation structures 69 is less than a quarter of CPP. In some embodiments, the implementation of separating an active region structure (e.g., 82R or 84R) into two portions with an isolation structure (e.g., 69) is referred to as a CPODE implementation, and the isolation structure (e.g., 69) is referred to as a CPODE isolation structure.

[0049] In Figures 1A-1C In some embodiments, one or more gate conductors (indicated by the ellipsis ".. ") between the gate conductors 162 and 168 are not explicitly depicted with the gate conductor pattern. In some embodiments, one or more gate conductors (e.g., 162,..., 168) intersect the second set of active region structures 82R and / or 84R at channel regions of transistors in the second set of circuits 60 and form gate terminals of the transistors. In some embodiments, one or more gate conductors (e.g., 162,..., 168) intersect the second set of active region structures 82R and / or 84R but do not serve as gate terminals of transistors in the second set of circuits 60. In some embodiments, the second set of circuits 60 further includes terminal conductors that are not explicitly depicted with the terminal conductor pattern. In some embodiments, terminal conductors in the second set of circuits 60 intersect the second set of active region structures 82R and / or 84R at channel regions of transistors in the second set of circuits 60 and form source / drain terminals of the transistors. In some embodiments, terminal conductors in the second set of circuits 60 intersect the second set of active region structures 82R and / or 84R but do not serve as source / drain terminals of transistors in the second set of circuits 60. In some embodiments, the second set of circuits 60 further includes additional elements not explicitly shown in Figures 1A-1C In some embodiments, the additional elements include via connections and routing wires in one or more metal layers.

[0050] In Figures 10A-10C In some embodiments, examples of the main circuit 50 include a clock circuit, a logic gate circuit, or any functional circuit where improvement in variation / uncertainty in timing delay is needed when placing the circuit of interest in the layout design through the APR program. Examples of the first set of circuits 40 and the second set of circuits 60 also include other logic gate circuits, e.g., an inverter gate, a NAND gate, or a NOR gate. One example of the first set of circuits 40 and the second set of circuits 60 is an inverter, as shown in Figure 11 andFigure 1D The meaning of the first set of circuits 40 is broadly construed to include any circuit structure having at least one gate conductor between the first set of isolation structures 49 and the first set of border gate conductors 41. Similarly, the meaning of the second set of circuits 60 is broadly construed to include any circuit structure having at least one gate conductor between the second set of isolation structures 69 and the second set of border gate conductors 61. The circuit structure of the first set of circuits 40 or the circuit structure of the second set of circuits 60 typically forms a functional logic circuit. However, in some embodiments, the circuit structure of the first set of circuits 40 or the circuit structure of the second set of circuits 60 does not form a functional logic circuit. In some embodiments, at least one gate conductor in the first set of circuits 40 or the second set of circuits 60 is a gate terminal of a transistor. In some embodiments, at least one gate conductor in the first set of circuits 40 or the second set of circuits 60 is a dummy gate conductor.

[0051] Figures 1A-1C is a schematic diagram of a cross-sectional view in a cut plane P-P’ designated by the layout map as in Figure 1E is a schematic diagram of a cross-sectional view in a cut plane Q-Q’ designated by the layout map as in Figures 1A-1C is a schematic diagram of a cross-sectional view in a cut plane P-P’ designated by the layout map as in Figure 1D is a schematic diagram of a cross-sectional view in a cut plane Q-Q’ designated by the layout map as in

[0052] In Figure 1D , the first border gate conductor 51 of the main circuit 50 intersects the middle first-type active region structure 82M at a first end of the middle first-type active region structure 82M, and the second border gate conductor 59 of the main circuit 50 intersects the middle first-type active region structure 82M at a second end of the middle first-type active region structure 82M.

[0053] In Figure 1D , the first set of border gate conductors 41 of the first set of circuits 40 intersects the first set of first-type active region structures 82L at a first end of the first set of first-type active region structures 82L. The first set of isolation structures 49 of the first set of circuits 40 separates the first set of first-type active region structures 82L into a first portion 82L1 and a second portion 82L2. The first portion 82L1 of the first set of first-type active region structures 82L is in the first set of circuits 40. The second portion 82L2 of the first set of first-type active region structures 82L is in a first adjacent circuit that shares a common vertical border with the first set of circuits 40 at the first set of isolation structures 49. In some embodiments, a width “W*” of the first set of isolation structures 49 along the X-direction is less than half of CPP. In some embodiments, the width “W*” of the first set of isolation structures 49 is less than a quarter of CPP. In some embodiments, the first set of isolation structures 49 is a CPODE isolation structure.

[0054] exist Figure 1E In this configuration, the second set of boundary gate conductors 61 of the second set of circuits 60 intersects with the second set of first-type active region structures 82R at the first end of the second set of first-type active region structures 82R. The second set of isolation structures 69 of the second set of circuits 60 divides the second set of first-type active region structures 82R into a first portion 82R1 and a second portion 82R2. The first portion 82R1 of the second set of first-type active region structures 82R is in the second set of circuits 60. The second portion 82R2 of the second set of first-type active region structures 82R is in a second adjacent circuit (which shares a common vertical boundary with the second set of circuits 60 at the second set of isolation structures 69). In some embodiments, the width “W*” of the second set of isolation structures 69 along the X direction is less than half of the CPP. In some embodiments, the width “W*” of the second set of isolation structures 69 is less than one-quarter of the CPP. In some embodiments, the second set of isolation structures 69 is a CPODE isolation structure.

[0055] exist Figure 1E In the main circuit 50, the first boundary gate conductor 51 intersects with the intermediate second type active region structure 84M at the first end, and the second boundary gate conductor 59 of the main circuit 50 intersects with the intermediate second type active region structure 84M at the second end.

[0056] exist Figure 1E In the circuit, the first set of boundary gate conductors 41 of the first set of circuits 40 intersects with the first set of second-type active region structures 84L at the first end of the first set of second-type active region structures 84L. The first set of isolation structures 49 of the first set of circuits 40 divides the first set of second-type active region structures 84L into a first part 84L1 and a second part 84L2. The first part 84L1 of the first set of second-type active region structures 84L is in the first set of circuits 40. The second part 84L2 of the first set of second-type active region structures 84L is in a first adjacent circuit (which shares a common vertical boundary with the first set of circuits 40 at the first set of isolation structures 49).

[0057] exist Figure 1DIn the second group circuit 60, the second group boundary gate conductor 61 of the second group circuit 60 intersects the second group second-type active region structure 84R at a first end of the second group second-type active region structure 84R. The second group isolation structure 69 of the second group circuit 60 separates the second group second-type active region structure 84R into a first portion 84R1 and a second portion 84R2. The first portion 84R1 of the second group second-type active region structure 84R is in the second group circuit 60. The second portion 84R2 of the second group second-type active region structure 84R is in a second adjacent circuit that shares a common vertical boundary with the second group circuit 60 at the second group isolation structure 69.

[0058] In Figure 1E and Figure 1D , the first group boundary gate conductor 41 in the first group circuit 40 is separated from the first boundary gate conductor 51 in the main circuit 50 by a pitch distance of one CPP. The second group boundary gate conductor 61 in the second group circuit 60 is also separated from the second boundary gate conductor 59 in the main circuit 50 by a pitch distance of one CPP. The gate conductors (e.g., 152,..., and 158) in the main circuit 50 are between the first boundary gate conductor 51 and the second boundary gate conductor 59. In Figure 1E some embodiments of the Figure 1E , each gate conductor 152 and 158 intersects the middle first-type active region structure 82M at a channel region of a first-type transistor. In Figure 1D some embodiments of the Figure 1D , each gate conductor 152 and 158 intersects the middle second-type active region structure 84M at a channel region of a second-type transistor.

[0059] In Figure 1E and Figure 1D , the gate conductors 142 and 148 in the first group circuit 40 are between the first group boundary gate conductor 41 and the first group isolation structure 49. The gate conductors 162 and 168 in the second group circuit 60 are between the second group boundary gate conductor 61 and the second group isolation structure 69. In Figure 1E , the gate conductors 142 and 148 in the first group circuit 40 intersect the first group first-type active region structure 82L, while the gate conductors 162 and 168 in the second group circuit 60 intersect the second group first-type active region structure 82R. In Figure 1D , the gate conductors 142 and 148 in the first group circuit 40 intersect the first group second-type active region structure 84L, while the gate conductors 162 and 168 in the second group circuit 60 intersect the second group second-type active region structure 84R.

[0060] In Figure 1E and Figures 1A-1CIn some embodiments, the first set of isolation structures 49 extend into the insulator support 20 to separate the first set of first-type active region structures 82L into a first portion 82L1 and a second portion 82L2, and to separate the first set of second-type active region structures 84L into a first portion 84L1 and a second portion 84L2. The first set of isolation structures 49 also have a height "H" that is greater than a thickness "t" of the first set of active region structures 82L and 84L. In some embodiments, the second set of isolation structures 69 extend into the insulator support 20 to separate the second set of first-type active region structures 82R into a first portion 82R1 and a second portion 82R2, and to separate the second set of second-type active region structures 84R into a first portion 84R1 and a second portion 84R2. The second set of isolation structures 69 also have a height "H" that is greater than a thickness "t" of the second set of active region structures 82R and 84R.

[0061] In Figures 2A-2B , when the main circuit 50 is combined with the first set of circuits 40 and the second set of circuits 60 to form a combined circuit unit, the combined circuit unit has a first vertical boundary (extending in the Y direction) at the first set of isolation structures 49 and a second vertical boundary (extending in the Y direction) at the second set of isolation structures 69.

[0062] Figures 2A(a)-2B(a) and Figures 1A-1C are cross-sectional views at the cut-planes L-L', R-R' through the isolation structures at the boundaries of the combined circuit unit as specified by the layout map in Figures 2A-2B . The cross-sectional views of the integrated circuits 100A-100C in the cut-planes as specified by the lines L-L' and R-R' are respectively shown in Figure 2A . In Figure 2B , the first set of isolation structures 49 separates the first set of first-type active region structures 82L into a first portion 82L1 and a second portion 82L2, and the first set of isolation structures 49 also separates the first set of second-type active region structures 84L into a first portion 84L1 and a second portion 84L2. In Figure 2A , the second set of isolation structures 69 separates the second set of first-type active region structures 82R into a first portion 82R1 and a second portion 82R2, and the second set of isolation structures 69 also separates the second set of second-type active region structures 84R into a first portion 84R1 and a second portion 84R2.

[0063] In some alternative embodiments, Figure 2A the first set of isolation structures 49 in Figure 2BThe two first set isolation structures 49U and 49L in (a). The first set isolation structure 49U separates the first set of first type active area structures 82L into a first portion 82L1 and a second portion 82L2. The first set isolation structure 49L separates the first set of second type active area structures 84L into a first portion 84L1 and a second portion 84L2. In some alternative embodiments, Figure 2B The second set isolation structure 69 in (a) is replaced with Figures 3A-3D The two second set isolation structures 69U and 69L in (a). The second set isolation structure 69U separates the second set of first type active area structures 82R into a first portion 82R1 and a second portion 82R2. The second set isolation structure 69L separates the second set of second type active area structures 84R into a first portion 84R1 and a second portion 84R2.

[0064] Figures 3B(a)-3C(a) And Figures 1A-1C are cross-sectional views at selected cut planes as specified by the layout diagrams in Figure 3A .

[0065] Cross-sectional views of the integrated circuit 100A in cut planes as specified by lines A-A’, B-B’, C-C’, and D-D’ are respectively depicted in Figure 3B , Figure 3C , Figure 3D and Figure 3A . In Figure 3B , the first set boundary gate conductor 41 intersects both the first set of first type active area structures 82L and the first set of second type active area structures 84L. In Figure 3C , the first boundary gate conductor 51 of the main circuit 50 intersects both the middle first type active area structures 82M and the middle second type active area structures 84M. In Figure 3D , the second boundary gate conductor 59 of the main circuit 50 intersects both the middle first type active area structures 82M and the middle second type active area structures 84M. In Figure 3A , the second set boundary gate conductor 61 intersects both the second set of first type active area structures 82R and the second set of second type active area structures 84R.

[0066] Cross-sectional views of the integrated circuit 100B in cut planes as specified by lines A-A’, B-B’, C-C’, and D-D’ are respectively depicted in Figure 3B , Figure 3C (a), Figure 3D (a), and Figure 3A . In Figure 3BIn this configuration, the first group of boundary gate conductors 41 intersects with both the first group of first-type active region structures 82L and the second group of second-type active region structures 84L. Figure 3C In (a), the first segment 51U of the first boundary gate conductor 51 intersects with the intermediate first type active region structure 82M, and the second segment 51L of the first boundary gate conductor 51 intersects with the intermediate second type active region structure 84M. Figure 3D In (a), the first segment 59U of the second boundary gate conductor 59 intersects with the intermediate first type active region structure 82M, and the second segment 59L of the second boundary gate conductor 59 intersects with the intermediate second type active region structure 84M. Figure 3A In the middle, the second group of boundary gate conductors 61 intersects with the second group of first type active region structure 82R and the second group of second type active region structure 84R.

[0067] The cross-sectional views of integrated circuit 100C in the cutting planes specified by lines A-A', B-B', C-C', and D-D' are correspondingly in Figure 3B , Figure 3C (a) Figure 3D and Figure 3A Depicted in [the text]. Figure 3B In this configuration, the first group of boundary gate conductors 41 intersects with both the first group of first-type active region structures 82L and the first group of second-type active region structures 84L. Figure 3C In (a), the first segment 51U of the first boundary gate conductor 51 intersects with the intermediate first type active region structure 82M, and the second segment 51L of the first boundary gate conductor 51 intersects with the intermediate second type active region structure 84M. Figure 3D In the main circuit 50, the second boundary gate conductor 59 intersects with both the intermediate first-type active region structure 82M and the intermediate second-type active region structure 84M. Figures 1A-1C In the middle, the second group of boundary gate conductors 61 intersects with the second group of first type active region structure 82R and the second group of second type active region structure 84R.

[0068] exist Figures 4A-4B In the layout diagram, the first end of each intermediate active region structure (82M or 84M) is separated from the corresponding first group of active region structures by a gap, and the second end of each intermediate active region structure (82M or 84M) is separated from the corresponding second group of active region structures along the X direction. In some alternative embodiments, for example in Figures 4A-4B In the integrated circuits 400A-400B, one end of each intermediate active region structure is connected to the corresponding second group of active region structures along the X direction.

[0069] Figure 4Ais a schematic layout diagram of an integrated circuit 400A-400B according to some embodiments. Figure 1A is a modification of the layout diagram of the integrated circuit 100A in Figure 4B is a modification of the layout diagram of the integrated circuit 100A in Figure 1C is a schematic layout diagram of an integrated circuit 400B according to some embodiments. Figure 1A is a modification of the layout diagram of the integrated circuit 100C in Figure 1C or Figure 4A is replaced with a layout pattern of a dummy gate conductor 59D and a boundary isolation structure 59C in Figure 4B or Figures 4A-4B . The modification further includes adding a layout pattern CPO6 that separates the layout pattern of the dummy gate conductor 59D and the layout pattern of the boundary isolation structure 59C. The modification further includes joining the layout pattern of each intermediate active area structure (82M or 84M) with the layout pattern of the corresponding second set of active area structures (82R or 84R). In Figures 1A-1C , the layout pattern of the second set of boundary gate conductors 61 in Figure 4C is also removed.

[0070] Figures 4A-4B is a schematic cross-sectional view of the integrated circuit 400A-400B according to some embodiments in a cutting plane P-P’ as specified by the layout diagram in Figure 4C . Figures 4A-4B is a schematic cross-sectional view of the integrated circuit 400A-400B according to some embodiments in a cutting plane Q-Q’ as specified by the layout diagram in Figure 4C .

[0071] Figure 1D is a modification of the cross-sectional view in Figure 4C . Figure 1D and Figure 4C . The difference between the integrated circuits 400A-400B and 100A-100C is the connectivity between the intermediate first-type active area structures 82M and the second set of first-type active area structures 82R. In the integrated circuits 400A-400B, as shown in Figure 1D , the intermediate first-type active area structures 82M are joined with the second set of first-type active area structures 82R under the dummy gate conductors 59D and form a single first-type active area structure. In comparison, in the integrated circuits 100A-100C, as shown in Figure 1D , the intermediate first-type active area structures 82M are separated from the second set of first-type active area structures 82R by the gap between the second boundary gate conductors 59 and the second set of boundary gate conductors 61. In some embodiments, Figure 4Dthe gap between the middle first-type active-area structure 82M and the second set of first-type active-area structures 82R is greater than half of the CPP.

[0072] Figure 1E the cross-sectional view in (a) is a modification of the cross-sectional view in Figure 4D (a). Figure 1E and Figure 4D The difference between (a) and (b) is the connectivity between the middle second-type active-area structure 84M and the second set of second-type active-area structures 84R. In the integrated circuit 400A-400B, as shown in (a), while the boundary isolation structure 59C (e.g., a CPODE isolation structure) physically links the middle second-type active-area structure 84M with the second set of second-type active-area structures 84R, the boundary isolation structure 59C also forms an electrical isolation between the middle second-type active-area structure 84M and the second set of second-type active-area structures 84R. In comparison, in the integrated circuit 100A-100C, as shown in (b), the middle second-type active-area structure 84M is separated from the second set of second-type active-area structures 84R by a gap between the second boundary gate conductor 59 and the second set of boundary gate conductors 61. Figure 1E Figures 5A-5D

[0073] Figure 5B and Figures 4A-4B (a) is a cross-sectional view of an integrated circuit according to some embodiments at a selected cut plane as designated in the layout diagram in Figure 5A (a).

[0074] The cross-sectional view of the integrated circuit 400A-400B in a cut plane as designated by line A-A’ is depicted in Figure 5A (a). In Figure 5B (a), the first set of boundary gate conductors 41 intersects both the first set of first-type active-area structures 82L and the first set of second-type active-area structures 84L.

[0075] The cross-sectional view of the integrated circuit 400A in a cut plane as designated by line B-B’ is depicted in Figure 5B (a). The cross-sectional view of the integrated circuit 400B in a cut plane as designated by line B-B’ is depicted in Figure 5B (a). In Figure 5B (a), the first boundary gate conductor 51 of the main circuit 50 intersects both the middle first-type active-area structure 82M and the middle second-type active-area structure 84M. In Figure 5C (a), a first segment 51U of the first boundary gate conductor 51 intersects the middle first-type active-area structure 82M, while a second segment 51L of the first boundary gate conductor 51 intersects the middle second-type active-area structure 84M. ​​

[0076] A cross-sectional view of integrated circuits 400A-400B in a cut plane as designated by line C-C’ is depicted in Figure 5C In Figure 5C the boundary isolation structure 59C (e.g., a CPODE isolation structure) physically links the intermediate second-type active area structure 84M with the second set of second-type active area structures 84R and simultaneously provides electrical isolation between the intermediate second-type active area structure 84M and the second set of second-type active area structures 84R. In addition, in Figure 5D the dummy gate conductor 59D intersects the intermediate first-type active area structure 82M.

[0077] A cross-sectional view of integrated circuits 400A-400B in a cut plane as designated by line D-D’ is depicted in Figure 5D In Figures 1A-1C the gate conductor 161 intersects both the second set of first-type active area structures 82R and the second set of second-type active area structures 84R.

[0078] In the layout of Figures 6A-6F each intermediate active area structure (82M or 84M) is separated from the respective first set of active area structures by a gap and each intermediate active area structure (82M or 84M) is separated from the respective second set of active area structures along the X-direction. In some alternative embodiments, for example in integrated circuits 600A-600F of Figures 6A-6F the intermediate first-type active area structure 82M is linked with both the first set of first-type active area structures 82L and the second set of first-type active area structures 82R.

[0079] Figure 6A is a schematic layout of integrated circuits 600A-600F according to some embodiments. Figure 1A The layout of integrated circuit 600A in Figure 1A is a modification of the layout of integrated circuit 100A in Figure 6A Similar to integrated circuit 100A in Figure 6A integrated circuit 600A in comprises main circuit 50, first set of circuits 40, and second set of circuits 60.

[0080] Figure 6AIn the main circuit 50, the first boundary gate conductor 51 intersects the respective intermediate active region structure at a first end of each intermediate active region structure 82M and 84M. The second boundary gate conductor 59 intersects the respective intermediate active region structure at a second end of each intermediate active region structure 82M and 84M. The main circuit 50 further includes gate conductors (e.g., 152,..., and 158) that extend in the Y direction between the first boundary gate conductor 51 and the second boundary gate conductor 59. One or more of the gate conductors in the main circuit 50 intersect the intermediate active region structure 82M and / or 84M at a channel region of a transistor in the main circuit 50. The gate conductors in the main circuit 50 that intersect the intermediate active region structure 82M and / or 84M are spaced apart from the first boundary gate conductor 51 and the second boundary gate conductor 59 by a distance of one CPP. Figure 6A Elements not explicitly shown in the main circuit 50 include gate conductors between gate conductors 152 and 158 (indicated by the symbol “...”), terminal conductors for source terminals or drain terminals of transistors, various via connections in one or more metal layers, and various routing wires.

[0081] In the first circuit 20, the first boundary gate conductor 21 intersects the respective first active region structure 22L at a first end of the first active region structure 22L. The second boundary gate conductor 29 intersects the respective first active region structure 22L at a second end of the first active region structure 22L. The first circuit 20 further includes gate conductors (e.g., 24, 26, 28, and 30) that extend in the Y direction between the first boundary gate conductor 21 and the second boundary gate conductor 29. One or more of the gate conductors in the first circuit 20 intersect the first active region structure 22L at a channel region of a transistor in the first circuit 20. The gate conductors in the first circuit 20 that intersect the first active region structure 22L are spaced apart from the first boundary gate conductor 21 and the second boundary gate conductor 29 by a distance of one CPP. Figure 6A In the first circuit 20, the first boundary gate conductor 21 intersects the respective first active region structure 22L at a first end of the first active region structure 22L. The second boundary gate conductor 29 intersects the respective first active region structure 22L at a second end of the first active region structure 22L. The first circuit 20 further includes gate conductors (e.g., 24, 26, 28, and 30) that extend in the Y direction between the first boundary gate conductor 21 and the second boundary gate conductor 29. One or more of the gate conductors in the first circuit 20 intersect the first active region structure 22L at a channel region of a transistor in the first circuit 20. The gate conductors in the first circuit 20 that intersect the first active region structure 22L are spaced apart from the first boundary gate conductor 21 and the second boundary gate conductor 29 by a distance of one CPP. Figure 6A Elements not explicitly shown in the first circuit 20 include gate conductors between gate conductors 24 and 30 (indicated by the symbol “..”), terminal conductors for source terminals or drain terminals of transistors, various via connections in one or more metal layers, and various routing wires.

[0082] In the first circuit 20, the first boundary gate conductor 21 intersects the respective first active region structure 22L at a first end of the first active region structure 22L. The second boundary gate conductor 29 intersects the respective first active region structure 22L at a second end of the first active region structure 22L. The first circuit 20 further includes gate conductors (e.g., 24, 26, 28, and 30) that extend in the Y direction between the first boundary gate conductor 21 and the second boundary gate conductor 29. One or more of the gate conductors in the first circuit 20 intersect the first active region structure 22L at a channel region of a transistor in the first circuit 20. The gate conductors in the first circuit 20 that intersect the first active region structure 22L are spaced apart from the first boundary gate conductor 21 and the second boundary gate conductor 29 by a distance of one CPP. Figure 6AIn the second set circuit 60, the second set of boundary gate conductors 61 intersects the respective first set of active region structures at the first end of each second set active region structure 82R and 84R. The second set of boundary gate conductors 61 in the second set circuit 60 is separated from the second boundary gate conductor 59 in the main circuit 50 by a pitch distance of one CPP. The second set of isolation structures 69 separates each second set active region structure 82R and 84R into a first portion in the second set circuit 60 and a second portion in a second adjacent circuit. The second set of boundary gate conductors 61 in the second set circuit 60 is separated from the second set of boundary gate conductors 61 in the second adjacent circuit by a pitch distance of one CPP. The second set of isolation structures 69 in the second set circuit 60 is separated from the second set of isolation structures 69 in the second adjacent circuit by a pitch distance of one CPP. Figure 6B Elements not explicitly shown in include gate conductors between gate conductors 162 and 168 (represented by the symbol ".. "), terminal conductors for source terminals or drain terminals of transistors, various via connections in one or more metal layers, and various wiring conductors.

[0083] Figure 6A The integrated circuit 600B in is a modification of the integrated circuit 600A in Figure 6B The integrated circuit 600A in is a modification of the integrated circuit 600B in Figure 6A In the second set circuit 60, the second set of boundary gate conductors 61 intersects the respective first set of active region structures at the first end of each second set active region structure 82R and 84R. The second set of boundary gate conductors 61 in the second set circuit 60 is separated from the second boundary gate conductor 59 in the main circuit 50 by a pitch distance of one CPP. The second set of isolation structures 69 separates each second set active region structure 82R and 84R into a first portion in the second set circuit 60 and a second portion in a second adjacent circuit. The second set of boundary gate conductors 61 in the second set circuit 60 is separated from the second set of boundary gate conductors 61 in the second adjacent circuit by a pitch distance of one CPP. The second set of isolation structures 69 in the second set circuit 60 is separated from the second set of isolation structures 69 in the second adjacent circuit by a pitch distance of one CPP. Figure 6A The second boundary gate conductor 59 in is divided into a first segment 59U and a second segment 59L, and Figure 6C The second set of boundary gate conductors 61 in is divided into a first segment 61U and a second segment 61L.

[0084] Figure 6B The integrated circuit 600C in is a modification of the integrated circuit 600B in Figure 6C The integrated circuit 600B in is a modification of the integrated circuit 600A in Figure 6B In the second set circuit 60, the second set of boundary gate conductors 61 intersects the respective first set of active region structures at the first end of each second set active region structure 82R and 84R. The second set of boundary gate conductors 61 in the second set circuit 60 is separated from the second boundary gate conductor 59 in the main circuit 50 by a pitch distance of one CPP. The second set of isolation structures 69 separates each second set active region structure 82R and 84R into a first portion in the second set circuit 60 and a second portion in a second adjacent circuit. The second set of boundary gate conductors 61 in the second set circuit 60 is separated from the second set of boundary gate conductors 61 in the second adjacent circuit by a pitch distance of one CPP. The second set of isolation structures 69 in the second set circuit 60 is separated from the second set of isolation structures 69 in the second adjacent circuit by a pitch distance of one CPP. Figure 6B The first boundary gate conductor 51 in is divided into a first segment 51U and a second segment 51L, and Figure 6D The first set of boundary gate conductors 41 in is divided into a first segment 41U and a second segment 41L.

[0085] Figure 6A The integrated circuit 600D in is a modification of the integrated circuit 600A in Figure 6D The integrated circuit 600A in is a modification of the integrated circuit 600B in Figure 6A In the second set circuit 60, the second set of boundary gate conductors 61 intersects the respective first set of active region structures at the first end of each second set active region structure 82R and 84R. The second set of boundary gate conductors 61 in the second set circuit 60 is separated from the second boundary gate conductor 59 in the main circuit 50 by a pitch distance of one CPP. The second set of isolation structures 69 separates each second set active region structure 82R and 84R into a first portion in the second set circuit 60 and a second portion in a second adjacent circuit. The second set of boundary gate conductors 61 in the second set circuit 60 is separated from the second set of boundary gate conductors 61 in the second adjacent circuit by a pitch distance of one CPP. The second set of isolation structures 69 in the second set circuit 60 is separated from the second set of isolation structures 69 in the second adjacent circuit by a pitch distance of one CPP. Figure 6D The first boundary gate conductor 51 in is divided into a first segment 51U and a second segment 51L, and Figure 6A The second boundary gate conductor 59 in is divided into a first segment 59U and a second segment 59L. Figure 6E The second boundary gate conductor 59 in is divided into a first segment 59U and a second segment 59L.

[0086] Figure 6A The integrated circuit 600E in is a modification of the integrated circuit 600D in Figure 6EModifications to the 600A integrated circuit in [the system]. In [the context of the modification]. Figure 6A In, as specified in layout pattern CPO6, Figure 6F The second boundary gate conductor 59 is divided into a first segment 59U and a second segment 59L.

[0087] Figure 6B The integrated circuit 600F in it is Figure 6F Modification of the 600B integrated circuit in [the system]. Figure 6B In, as specified in layout pattern CPO4, Figure 6G The first boundary gate conductor 51 is divided into a first segment 51U and a second segment 51L.

[0088] Figures 6A-6F The integrated circuits 600A-600F according to some embodiments are as follows: Figure 6H A schematic diagram of the cross-sectional view in the cutting plane P-P' specified in the layout diagram. Figures 6A-6F The integrated circuits 600A-600F according to some embodiments are as follows: ​ A schematic diagram of the cross-sectional view in the cutting plane Q-Q' specified in the layout diagram.

[0089] FIG. 6G The cross-sectional view in the middle is FIG. 1D Modification of the cross-sectional view in the document. FIG. 6G and FIG. 1D The difference lies in the connectivity between the intermediate first-type active region structure 82M and the first group of first-type active region structures 82L, as well as the connectivity between the intermediate first-type active region structure 82M and the second group of first-type active region structures 82R. In integrated circuits 600A-600F, such as... FIG. 6G As shown, the intermediate first type active region structure 82M is connected to both the first group of first type active region structures 82L and the second group of first type active region structures 82R. Conversely, in integrated circuits 100A-100C, as... FIG. 1D As shown, one end of the intermediate first type active region structure 82M is separated from the first group of first type active region structures 82L, and the other end of the intermediate first type active region structure 82M is separated from the second group of first type active region structures 82R.

[0090] FIG. 6H The cross-sectional view in FIG. 1E The cross-sectional views are the same. FIG. 6H and FIG. 1E Of the two, one end of the intermediate second type active region structure 84M is separated from the first group of second type active region structures 84L, and the other end of the intermediate second type active region structure 84M is separated from the second group of second type active region structures 84R.

[0091] FIG. 7A-FIG. 7D and FIG. 7A(a)-FIG. 7D(a) are cross-sectional views of the integrated circuit according to some embodiments at selected cut-planes as specified by the layout diagrams in FIG. 6A-FIG. 6F .

[0092] Cross-sectional views of the integrated circuits 600A-600B and 600D-600F in cut-planes as specified by line A-A’ are depicted in FIG. 7A . Cross-sectional views of the integrated circuit 600C in cut-planes as specified by line A-A’ are depicted in FIG. 7A (a). In FIG. 7A , the first set of boundary gate conductors 41 intersects both the first set of first-type active region structures 82L and the first set of second-type active region structures 84L. In FIG. 7A (a), a first segment 41U of the first set of boundary gate conductors 41 intersects the first set of first-type active region structures 82L, while a second segment 41L of the first set of boundary gate conductors 41 intersects the first set of second-type active region structures 84L.

[0093] Cross-sectional views of the integrated circuits 600A-600B and 600E in cut-planes as specified by line B-B’ are depicted in FIG. 7B . Cross-sectional views of the integrated circuits 600C-600D and 600F in cut-planes as specified by line B-B’ are depicted in FIG. 7B (a). In FIG. 7B , the first boundary gate conductor 51 of the main circuit 50 intersects both the middle first-type active region structure 82M and the middle second-type active region structure 84M. In FIG. 7B (a), a first segment 51U of the first boundary gate conductor 51 intersects the middle first-type active region structure 82M, while a second segment 51L of the first boundary gate conductor 51 intersects the middle second-type active region structure 84M.

[0094] Cross-sectional views of the integrated circuit 600A in cut-planes as specified by line C-C’ are depicted in FIG. 7C . Cross-sectional views of the integrated circuits 600B-600F in cut-planes as specified by line C-C’ are depicted in FIG. 7C (a). In FIG. 7C , the second boundary gate conductor 59 of the main circuit 50 intersects both the middle first-type active region structure 82M and the middle second-type active region structure 84M. In FIG. 7CIn (a), the first segment 59U of the second boundary gate conductor 59 intersects the middle first-type active region structure 82M, and the second segment 59L of the second boundary gate conductor 59 intersects the middle second-type active region structure 84M.

[0095] Cross-sectional views of the integrated circuits 600A, 600D, and 600E in a cut plane as specified by the line D-D’ are depicted in FIG. 7D Cross-sectional views of the integrated circuits 600B-600C and 600F in a cut plane as specified by the line D-D’ are depicted in FIG. 7D (a). In FIG. 7D (a), the first segment 61U of the second set of boundary gate conductors 61 intersects the second set of first-type active region structures 82R, and the second segment 61L of the second set of boundary gate conductors 61 intersects the second set of second-type active region structures 84R. FIG. 7D

[0096] In the layout of FIG. 6A-FIG. 6F (a), the first end of the middle second-type active region structure 84M is separated (has a gap along the X-direction) from the first set of second-type active region structures 84L, and the second end of the middle second-type active region structure 84M is separated (has a gap along the X-direction) from the second set of second-type active region structures 84R. In some alternative embodiments, for example in the integrated circuits 800A-800C of FIG. 8A-FIG. 8C (a), the boundary isolation structure 59C physically connects the middle second-type active region structure 84M with the second set of second-type active region structures 84R, and at the same time provides electrical isolation between the middle second-type active region structure 84M and the second set of second-type active region structures 84R. Additionally, in FIG. 8A-FIG. 8C (a), the dummy gate conductor 59D intersects the middle first-type active region structure 82M.

[0097] FIG. 8A-FIG. 8C is a schematic layout of the integrated circuits 800A-800C according to some embodiments. FIG. 8A The layout of the integrated circuit 800A in FIG. 6E is a modification of the layout of the integrated circuit 600E in FIG. 8A The difference between FIG. 6E is the connectivity between the middle second-type active region structure 84M and the second set of second-type active region structures 84R. In the integrated circuit 800A, as FIG. 8A ​As shown, the intermediate second-type active region structure 84M is connected to the second group of second-type active region structures 84R through a boundary isolation structure 59C. For comparison, in integrated circuit 600E, as... FIG. 6E As shown, the middle second type active region structure 84M and the second group of second type active region structures 84R are separated by a gap extending in the X direction.

[0098] FIG. 8B The 800B integrated circuit in it is FIG. 8A Modifications to the 800A integrated circuit. In FIG. 8B In, as specified in layout pattern CPO4, FIG. 8A The first boundary gate conductor 51 is divided into a first segment 51U and a second segment 51L.

[0099] FIG. 8C The 800C integrated circuit in it is FIG. 8A Modifications to the 800A integrated circuit. In FIG. 8C In, as specified in layout pattern CPO4, FIG. 8A The first boundary gate conductor 51 is divided into a first segment 51U and a second segment 51L, and FIG. 8A The first set of boundary gate conductors 41 is divided into a first segment 41U and a second segment 41L.

[0100] FIG. 8D The integrated circuits 800A-800C according to some embodiments are as follows: FIG. 8A-FIG. 8C A schematic diagram of the cross-sectional view in the cutting plane P-P' specified in the layout diagram. FIG. 8E The integrated circuits 800A-800C according to some embodiments are as follows: FIG. 8A-FIG. 8C A schematic diagram of the cross-sectional view in the cutting plane Q-Q' specified in the layout diagram.

[0101] FIG. 8D The cross-sectional view in the middle is similar to FIG. 6G A cross-sectional view in [the context]. FIG. 8D and FIG. 6G Of the two, the intermediate first-type active region structure 82M is connected to both the first group of first-type active region structures 82L and the second group of first-type active region structures 82R. However, FIG. 8D Replacement of dummy gate conductor 59D and gate conductor 161 FIG. 6G The second boundary gate conductor 59 and the second set of boundary gate conductors 61.

[0102] FIG. 8E The cross-sectional view in FIG. 4D The cross-sectional views are the same. FIG. 8E and FIG. 4DIn both, the boundary isolation structure 59C physically connects the intermediate second-type active region structure 84M with the second set of second-type active region structures 84R while also electrically isolating the intermediate second-type active region structure 84M from the second set of second-type active region structures 84R. In FIG. 8E and FIG. 4D In both, the intermediate second-type active region structure 84M is separated from the first set of second-type active region structures 84L by a gap extending in the X-direction.

[0103] FIG. 9A-FIG. 9D and FIG. 9A(a)-FIG. 9B(a) is a cross-sectional view of an integrated circuit according to some embodiments at a selected cut plane as specified by the layout map in FIG. 8A-FIG. 8C .

[0104] A cross-sectional view of the integrated circuit 800A-800B in a cut plane as specified by the line A-A’ is depicted in FIG. 9A . A cross-sectional view of the integrated circuit 800C in a cut plane as specified by the line A-A’ is depicted in FIG. 9A (a). FIG. 9A In (a), the first set of boundary gate conductors 41 intersects both the first set of first-type active region structures 82L and the first set of second-type active region structures 84L. In FIG. 9A (a), a first segment 41U of the first set of boundary gate conductors 41 intersects the first set of first-type active region structures 82L while a second segment 41L of the first set of boundary gate conductors 41 intersects the first set of second-type active region structures 84L.

[0105] A cross-sectional view of the integrated circuit 800A in a cut plane as specified by the line B-B’ is depicted in FIG. 9B . A cross-sectional view of the integrated circuit 800B-800C in a cut plane as specified by the line B-B’ is depicted in FIG. 9B (a). FIG. 9B In (a), the first boundary gate conductor 51 of the main circuit 50 intersects both the intermediate first-type active region structure 82M and the intermediate second-type active region structure 84M. In FIG. 9B (a), a first segment 51U of the first boundary gate conductor 51 intersects the intermediate first-type active region structure 82M while a second segment 51L of the first boundary gate conductor 51 intersects the intermediate second-type active region structure 84M.

[0106] A cross-sectional view of the integrated circuit 800A-800C in a cut plane as specified by the line C-C’ is depicted in FIG. 9C . In FIG. 9CIn the middle, the boundary isolation structure 59C physically connects the intermediate second-type active region structure 84M to the second group of second-type active region structures 84R, and simultaneously provides electrical isolation between the intermediate second-type active region structure 84M and the second group of second-type active region structures 84R. Additionally, in FIG. 9C In the middle, the dummy gate conductor 59D intersects with the intermediate first type active region structure 82M.

[0107] A cross-sectional view of integrated circuit 800A-800C in the cutting plane specified by line D-D'. FIG. 9D Depicted in [the text]. FIG. 9D In the middle, the gate conductor 161 intersects with both the second group of first type active region structure 82R and the second group of second type active region structure 84R.

[0108] FIG. 10A This is a layout diagram of an integrated circuit 1000 having a main circuit 50 between a first group of circuits 40 and a second group of circuits 60, according to some embodiments. FIG. 10A In this embodiment, the first group of circuits 40 is implemented as an inverter 1040. In the example embodiment, the first group of first-type active region structures 82L is a p-type active region structure, and the first group of second-type active region structures 84L is an n-type active region structure. In the example embodiment, gate conductors 142 and 148 intersect with the first group of first-type active region structures 82L at the channel regions of the first PMOS transistor and the second PMOS transistor, and gate conductors 142 and 148 also intersect with the first group of second-type active region structures 84L at the channel regions of the first NMOS transistor and the second NMOS transistor. In the example embodiment, gate conductor 142 electrically connects the gate terminals of the first PMOS transistor and the first NMOS transistor, and gate conductor 148 electrically connects the gate terminals of the second PMOS transistor and the second NMOS transistor.

[0109] In an example embodiment, the terminal conductor MD1 intersects the first set of first-type active area structures 82L at source regions of the first and second PMOS transistors, and the terminal conductor MD3 intersects the first set of second-type active area structures 84L at source regions of the first and second NMOS transistors. The terminal conductor MD1 is configured to receive a first supply voltage VDD, and the terminal conductor MD3 is configured to receive a second supply voltage VSS. The terminal conductor MD2 intersects the first set of first-type active area structures 82L and the first set of second-type active area structures 84L, respectively, at drain regions of the first PMOS transistor and the first NMOS transistor. The terminal conductor MD4 intersects the first set of first-type active area structures 82L and the first set of second-type active area structures 84L, respectively, at drain regions of the second PMOS transistor and the second NMOS transistor. The terminal conductor MD2 conductively connects a drain terminal of the first PMOS transistor with a drain terminal of the first NMOS transistor, and the terminal conductor MD4 conductively connects a drain terminal of the second PMOS transistor with a drain terminal of the second NMOS transistor.

[0110] In an example embodiment, the horizontal conductor HC1 is conductively connected to each of the gate conductors 142 and 148 via a respective gate via connection VG. The horizontal conductor HC1 is configured as an input terminal of the inverter 1040 for receiving an input logic signal. The horizontal conductor HC2 is conductively connected to each of the terminal conductors MD2 and MD4 via a respective terminal via connection VD. The horizontal conductor HC2 is configured as an output terminal of the inverter 1040 for generating an output logic signal.

[0111] FIG. 10B-FIG. 10C is a cross-sectional view of the integrated circuit 1000 as specified by the layout map in FIG. 10A . The cross-sectional view of the integrated circuit 1000 in a cut plane as specified by the line P-P’ is depicted in FIG. 10B . The cross-sectional view of the inverter 1040 in a cut plane as specified by the line Q-Q’ is depicted in FIG. 10C .

[0112] In FIG. 10BIn the example shown in FIG. 1, the gate conductors 142 and 148 intersect the first set of first-type active region structures 82L at the channel regions of the first and second PMOS transistors, respectively. Each of the gate conductors 142 and 148 is conductively connected to a horizontal conductor HC1 in the first metal layer via a respective gate via connection VG. The terminal conductor MD1 intersects the first set of first-type active region structures 82L at the source regions of the first and second PMOS transistors. The terminal conductors MD2 and MD4 intersect the first set of first-type active region structures 82L at the drain regions of the first and second PMOS transistors, respectively.

[0113] In the example shown in FIG. 1, the gate conductors 142 and 148 intersect the first set of first-type active region structures 82L at the channel regions of the first and second PMOS transistors, respectively. Each of the gate conductors 142 and 148 is conductively connected to a horizontal conductor HC1 in the first metal layer via a respective gate via connection VG. The terminal conductor MD1 intersects the first set of first-type active region structures 82L at the source regions of the first and second PMOS transistors. The terminal conductors MD2 and MD4 intersect the first set of first-type active region structures 82L at the drain regions of the first and second PMOS transistors, respectively. FIG. 10C In the example shown in FIG. 1, the gate conductors 142 and 148 intersect the first set of first-type active region structures 82L at the channel regions of the first and second PMOS transistors, respectively. Each of the gate conductors 142 and 148 is conductively connected to a horizontal conductor HC1 in the first metal layer via a respective gate via connection VG. The terminal conductor MD1 intersects the first set of first-type active region structures 82L at the source regions of the first and second PMOS transistors. The terminal conductors MD2 and MD4 intersect the first set of first-type active region structures 82L at the drain regions of the first and second PMOS transistors, respectively.

[0114] FIG. 10A In the example shown in FIG. 1, the gate conductors 142 and 148 intersect the first set of first-type active region structures 82L at the channel regions of the first and second PMOS transistors, respectively. Each of the gate conductors 142 and 148 is conductively connected to a horizontal conductor HC1 in the first metal layer via a respective gate via connection VG. The terminal conductor MD1 intersects the first set of first-type active region structures 82L at the source regions of the first and second PMOS transistors. The terminal conductors MD2 and MD4 intersect the first set of first-type active region structures 82L at the drain regions of the first and second PMOS transistors, respectively.

[0115] In the example shown in FIG. 1, the gate conductors 142 and 148 intersect the first set of first-type active region structures 82L at the channel regions of the first and second PMOS transistors, respectively. Each of the gate conductors 142 and 148 is conductively connected to a horizontal conductor HC1 in the first metal layer via a respective gate via connection VG. The terminal conductor MD1 intersects the first set of first-type active region structures 82L at the source regions of the first and second PMOS transistors. The terminal conductors MD2 and MD4 intersect the first set of first-type active region structures 82L at the drain regions of the first and second PMOS transistors, respectively. FIG. 10A FIG. 10A In the example shown in FIG. 1, the gate conductors 142 and 148 intersect the first set of first-type active region structures 82L at the channel regions of the first and second PMOS transistors, respectively. Each of the gate conductors 142 and 148 is conductively connected to a horizontal conductor HC1 in the first metal layer via a respective gate via connection VG. The terminal conductor MD1 intersects the first set of first-type active region structures 82L at the source regions of the first and second PMOS transistors. The terminal conductors MD2 and MD4 intersect the first set of first-type active region structures 82L at the drain regions of the first and second PMOS transistors, respectively. FIG. 11 FIG. 11 In the example shown in FIG. 1, the gate conductors 142 and 148 intersect the first set of first-type active region structures 82L at the channel regions of the first and second PMOS transistors, respectively. Each of the gate conductors 142 and 148 is conductively connected to a horizontal conductor HC1 in the first metal layer via a respective gate via connection VG. The terminal conductor MD1 intersects the first set of first-type active region structures 82L at the source regions of the first and second PMOS transistors. The terminal conductors MD2 and MD4 intersect the first set of first-type active region structures 82L at the drain regions of the first and second PMOS transistors, respectively.

[0116] ​​​FIG. 11 is a layout diagram of an integrated circuit 1100 having a main circuit 50 between a first group of circuits 40 and a second group of circuits 60 according to some embodiments. In FIG. 11 , the first group of circuits 40 and the second group of circuits 60 are respectively implemented as inverters 1140 and 1160. In the first group of circuits 40, the gate conductor 148 intersects the first group of first-type active area structures 82L and the first group of second-type active area structures 84L at the channel regions of the first-type transistors and the channel regions of the second-type transistors, respectively. The terminal conductor MD4 intersects the first group of first-type active area structures 82L and the first group of second-type active area structures 84L at the drain regions of the first-type transistors and the drain regions of the second-type transistors, respectively. The terminal conductor MD1 intersects the first group of first-type active area structures 82L at the source regions of the first-type transistors, and the terminal conductor MD3 intersects the first group of second-type active area structures 84L at the source regions of the second-type transistors. The horizontal conductor HC1 is electrically connected to the gate conductor 148 via a gate via connection VG. The horizontal conductor HC2 is electrically connected to the terminal conductor MD4 via a terminal via connection VD. The horizontal conductor HC1 is configured as an input terminal of the inverter 1140 for receiving an input logic signal. The horizontal conductor HC2 is configured as an output terminal of the inverter 1140 for generating an output logic signal. The layout design of the inverter 1160 is similar to that of the inverter 1140 in the first group of circuits 40. Therefore, the layout design of the inverter 1160 in the second group of circuits 60 will not be described in more detail in this disclosure.

[0117] In FIG. 1A-FIG. 1C , FIG. 4A-FIG. 4B , FIG. 6A-FIG. 6F , FIG. 8A-FIG. 8C , FIG. 10A and FIG. 11 In each of the integrated circuits shown, the main circuit 50 is between the first group of circuits 40 and the second group of circuits 60. When the main circuit 50 is combined with the first group of circuits 40 and the second group of circuits 60 to form a combined circuit cell, the combined circuit cell has a first vertical boundary (extending in the Y direction) at the first group of isolation structures 49 and a second vertical boundary (extending in the Y direction) at the second group of isolation structures 69. When the combined circuit cell is used in a layout design generated by an automatic place and route (APR) program, the main circuit 50 has improved timing performance, e.g., reduced variation / uncertainty in time delay, compared to some alternative implementations in which the main circuit 50 is used directly in the layout design by the automatic place and route (APR) program.

[0118] When the master circuit 50 is placed directly in the layout design by an automatic placement and routing (APR) program and is placed directly in the layout dependent environment by the APR program, the timing delay in the master circuit 50 depends on the neighboring cells that occupy the same row as the master circuit 50 in the layout map. In contrast, when the master circuit 50 is placed between the first set of circuits 40 and the second set of circuits 60 to form the combined circuit cell, only the combined circuit cell is placed directly in the layout dependent environment by the APR program. The master circuit 50 in the combined circuit cell is in a controlled layout environment, and the first set of circuits 40 and the second set of circuits 60 are held as the abutted circuits of the master circuit 50. When the master circuit 50 is in the controlled layout environment, the variation / uncertainty of the timing delay of the master circuit 50 is reduced.

[0119] FIG. 12A and FIG. 13A is a layout map of a combined circuit cell 1200 and neighboring cells that abut the combined circuit cell according to some embodiments. FIG. 12B-FIG. 12C is a cross-sectional view in the cutting planes P-P’ and Q-Q’ designated in FIG. 12A is a cross-sectional view in the cutting planes P-P’ and Q-Q’ designated in FIG. 13B-FIG. 13C is a cross-sectional view in the cutting planes P-P’ and Q-Q’ designated in FIG. 13A is a cross-sectional view in the cutting planes P-P’ and Q-Q’ designated in

[0120] In FIG. 12A and FIG. 13A , the combined circuit cell 1200 includes the master circuit 50 between the first set of circuits 40 and the second set of circuits 60. The first boundary gate conductor 51 of the master circuit 50 is separated from the first set of boundary gate conductors 41 of the first set of circuits 40 by a pitch distance of one CPP (as also shown in FIG. 12B-FIG. 12C and FIG. 13B-FIG. 13C ). The second boundary gate conductor 59 of the master circuit 50 is separated from the second set of boundary gate conductors 61 of the second set of circuits 60 by a pitch distance of one CPP (as also shown in FIG. 12B-FIG. 12C and FIG. 13B-FIG. 13C ).

[0121] In FIG. 12A , the combined circuit cell 1200 abuts neighboring circuits 1210 and 1220. In FIG. 13A , the combined circuit cell 1200 abuts neighboring circuits 1310 and 1320. In FIG. 12A and FIG. 13AIn FIG. 12A , the first set of isolation structures 49 (e.g., CPODE isolation structures) separate the first set of first-type active-area structures 82L into a first portion 82L1 and a second portion 82L2, and separate the first set of second-type active-area structures 84L into a first portion 84L1 and a second portion 84L2. The first portion 82L1 and the first portion 84L1 are in the first set of circuits 40. The second portion 82L2 and the second portion 84L2 are in an adjacent circuit 1210 (in FIG. 13A ) or in an adjacent circuit 1310 (in FIG. 12A ). FIG. 13A Similarly, in FIG. 12A and FIG. 13A , the second set of isolation structures 69 (e.g., CPODE isolation structures) separate the second set of first-type active-area structures 82R into a first portion 82R1 and a second portion 82R2, and separate the second set of second-type active-area structures 84R into a first portion 84R1 and a second portion 84R2. The first portion 82R1 and the first portion 84R1 are in the second set of circuits 60. The second portion 82R2 and the second portion 84R2 are in an adjacent circuit 1220 (in ) or in an adjacent circuit 1320 (in

[0122] ). FIG. 12A-FIG. 12C In FIG. 12A , the adjacent circuit 1210 includes gate conductors PO1 and PO2. In FIG. 12B and FIG. 12A , the gate conductors PO1 and PO2 intersect the second portion 82L2 of the first set of first-type active-area structures 82L. In FIG. 12C and FIG. 12A-FIG. 12C , the gate conductors PO1 and PO2 intersect the second portion 84L2 of the first set of second-type active-area structures 84L. In , the adjacent circuit 1210 also includes terminal conductors (e.g., MDs) that intersect the second portion 82L2 of the first set of first-type active-area structures 82L and / or the second portion 84L2 of the first set of second-type active-area structures 84L.

[0123] FIG. 13A-FIG. 13C In FIG. 13B , the adjacent circuit 1310 includes a gate conductor PO2. The gate conductor PO2 intersects the second portion 82L2 of the first set of first-type active-area structures 82L (in FIG. 13C ), and intersects the second portion 84L2 of the first set of second-type active-area structures 84L (in FIG. 13A-FIG. 13CIn the adjacent circuit 1310, terminal conductors (e.g., MD) intersect with the second portion 82L2 of the first group of first type active region structures 82L and / or the second portion 84L2 of the first group of second type active region structures 84L.

[0124] exist FIG. 12A-FIG. 12C In this context, the distance from the first isolation structure 49 to the nearest gate conductor (which is gate conductor PO1) in the adjacent circuit 1210 is one CPP. FIG. 13A-FIG. 13C In this implementation, the spacing from the first isolation structure 49 to the nearest gate conductor (which is gate conductor PO2) in the adjacent circuit 1310 is two CPPs. In some other implementations, depending on the layout environment generated by the APR program, the spacing from the first isolation structure 49 to the nearest gate conductor in the adjacent circuit can be greater than two CPPs (e.g., equal to five CPPs). The spacing from the first isolation structure 49 to the nearest gate conductor changes when the layout of the adjacent circuits 1210 or 1310 changes. However, because the first circuit 40 is between the main circuit 50 and the adjacent circuits (e.g., 1210 or 1310), the variation / uncertainty of the time delay of the main circuit 50 (due to changes in the layout of the adjacent circuits 1210 or 1310) is reduced compared to alternative implementations where the main circuit 50 is directly adjacent to the adjacent circuits 1210 or 1310. Similarly, because the second set of circuits 60 is located between the main circuit 50 and the adjacent circuits (e.g., 1220 or 1320), it also reduces the variation / uncertainty of the time delay of the main circuit 50 (due to the layout change of the adjacent circuits 1220 or 1320).

[0125] Additionally, in some embodiments, when the first boundary gate conductor 51 of the main circuit 50 is separated from the first group boundary gate conductor 41 of the first group of circuits 40 by a CPP spacing distance, the speed performance of the main circuit 50 is improved compared to some alternative implementations where the main circuit 50 and the first group of circuits 40 share a common vertical boundary at the CPODE isolation structure. In some embodiments, such as in the PODE implementation, the speed performance of the main circuit 50 is optimized when the first boundary gate conductor 51 and the second boundary gate conductor 59 of the main circuit 50 are correspondingly separated from the first group boundary gate conductor 41 and the second group boundary gate conductor 61 by a CPP spacing distance.

[0126] FIG. 14 This is a flowchart of a method 1400 for manufacturing an integrated circuit according to some embodiments. It should be understood that... FIG. 14Additional operations are performed before, during, and / or after the depicted method 1400, and only some of the other processes are briefly described herein. Other orders of the other operations of the method 1400 fall within the scope of the present disclosure in some embodiments. The method 1400 includes exemplary operations, but the operations need not be performed in the order shown. Operations can be appropriately added, substituted, reordered, and / or eliminated, as appropriate, in light of the spirit and scope of the disclosed embodiments. FIG. 15A-FIG. 15F is a cross-sectional view of an integrated circuit at various stages of fabrication when the integrated circuit is manufactured using the method 1400 in FIG. 14 . FIG. 15A-FIG. 15F Each cross-sectional view in FIG. 10B is in the same cut plane as designated by the line P-P’ in the plan view of

[0127] In operation 1410 of the method 1400, an active region semiconductor structure is fabricated on an insulator support. In some embodiments, the insulator support is a substrate. In some embodiments, the insulator support includes one or more layers of insulating material deposited on a substrate. As a non-limiting example, in the embodiment shown in FIG. 15A , an active region semiconductor structure 82 is fabricated on the insulator support 20. Examples of the active region semiconductor structure 82 include fin structures, nanosheet structures, and nanowire structures.

[0128] In operation 1420 of the method 1400, a gate conductor is fabricated intersecting the active region semiconductor structure. In the example embodiment shown in FIG. 15B , the gate conductor intersecting the active region semiconductor structure 82 includes gate conductors 49D, 142, 148, 41, 51, 152, 158, 59, 61, 162, 168, and 69D.

[0129] In operation 1430 of the method 1400, a terminal conductor is fabricated intersecting the active region semiconductor structure. In the example embodiment shown in FIG. 15C , the terminal conductor intersecting the active region semiconductor structure 82 includes terminal conductors MD2, MD1, and MD4.

[0130] In operation 1440 of the method 1400, the active region semiconductor structure is divided into intermediate active region structures between a first set of active region structures and a second set of active region structures. In the example embodiment shown in FIG. 15DIn the example embodiment shown, the active region semiconductor structure 82 is divided into a middle active region structure 82M, a first set of active region structures 82L, and a second set of active region structures 82R. In some embodiments, portions of the active region semiconductor structure 82 between the first border gate conductor 51 and the first set of border gate conductors 41 are removed by an etching process to separate the middle active region structure 82M from the first set of active region structures 82L; and portions of the active region semiconductor structure 82 between the second border gate conductor 59 and the second set of border gate conductors 61 are removed by an etching process to separate the middle active region structure 82M from the second set of active region structures 82R. After the etching process, the first border gate conductor 51 is at a first end of the middle active region structure 82M, while the first set of border gate conductors 41 are at a first end of the first set of active region structures 82L; and the second border gate conductor 59 is at a second end of the middle active region structure 82M, while the second set of border gate conductors 61 are at a first end of the second set of active region structures 82R.

[0131] In operation 1450 of the method 1400, an interlayer dielectric material is deposited that covers the active region structures and the gate conductors. In FIG. 15D In the example embodiment shown, an interlayer dielectric material layer 1510 is deposited. The interlayer dielectric material layer 1510 covers the middle active region structure 82M, the first set of active region structures 82L, and the second set of active region structures 82R. The interlayer dielectric material layer 1510 also covers the various gate conductors and the various terminal conductors.

[0132] In operation 1460 of the method 1400, first trenches are formed after the first gate conductors are removed, and second trenches are formed after the second gate conductors are removed. In FIG. 15E In the example embodiment shown, the first gate conductors 49D in FIG. 15D are removed before the first trenches 1549 are formed, and the second gate conductors 69D in FIG. 15D are removed before the second trenches 1569 are formed. In FIG. 15E In the example embodiment shown, each of the first trenches 1549 and the second trenches 1569 extends into the insulator support 20.

[0133] In operation 1470 of the method 1400, a first set of isolation structures are formed in the first trenches, and a second set of isolation structures are formed in the second trenches. In FIG. 15F In the example embodiment shown, the first trenches 1549 are filled with insulating material to form the first set of isolation structures 49, and the second trenches 1569 are filled with insulating material to form the second set of isolation structures 69. In FIG. 15FIn some embodiments, the first set of isolation structures 49 separates the first set of active region structures 82L into a first portion 82L1 and a second portion 82L2, and the second set of isolation structures 69 separates the second set of active region structures 82R into a first portion 82R1 and a second portion 82R2.

[0134] In some embodiments, in operations following operation 1470, various via connections are fabricated through the interlayer dielectric material layer 1510, and various wiring conductors are fabricated on top of the interlayer dielectric material layer 1510. In the illustrated example embodiment, a via connection VG is fabricated for connecting the gate conductor 142 and 148 with the horizontal conductor HC1. FIG. 10B

[0135] FIG. 16 is a block diagram of an electronic design automation (EDA) system 1600 in accordance with some embodiments.

[0136] In some embodiments, the EDA system 1600 includes an APR system. The methods described herein for designing a layout map representing a wire routing arrangement, for example, in accordance with some embodiments, can be implemented using the EDA system 1600, in accordance with one or more embodiments.

[0137] In some embodiments, the EDA system 1600 is a general purpose computing device, including a hardware processor 1602 and a non-transitory computer-readable storage medium 1604. Among other things, the storage medium 1604 is encoded with (i.e., stores) computer program code 1606 (i.e., a set of executable instructions). The hardware processor 1602 executes the instructions 1606 to represent, at least in part, an EDA tool that implements part or all of the methods described herein (referred to processes and / or methods hereinafter), in accordance with one or more embodiments.

[0138] The processor 1602 is electrically coupled to the computer-readable storage medium 1604 via a bus 1608. The processor 1602 is also electrically coupled to an I / O interface 1610 via the bus 1608. A network interface 1612 is also electrically coupled to the processor 1602 via the bus 1608. The network interface 1612 is connected to a network 1614, enabling the processor 1602 and the computer-readable storage medium 1604 to connect to external elements via the network 1614. The processor 1602 is configured to execute the computer program code 1606 encoded in the computer-readable storage medium 1604, such that the system 1600 is operable to perform part or all of the mentioned processes and / or methods. In one or more embodiments, the processor 1602 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0139] ​In one or more embodiments, the computer-readable storage medium 1604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1604 includes a semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and / or an optical disc. In one or more embodiments using an optical disc, the computer-readable storage medium 1604 includes a compact disc - read only memory (CD-ROM), a compact disc - read / write (CD-R / W), and / or a digital video disc (DVD).

[0140] In one or more embodiments, the storage medium 1604 stores computer program code 1606 configured to cause the system 1600 (where such execution (at least partially) represents an EDA tool) to perform some or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1604 also stores information that facilitates some or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1604 stores a library 1607 of standard cells, including such standard cells disclosed herein. In one or more embodiments, the storage medium 1604 stores one or more layout maps 1609 corresponding to one or more layouts disclosed herein.

[0141] The EDA system 1600 includes an I / O interface 1610. The I / O interface 1610 is coupled to external circuits. In one or more embodiments, the I / O interface 1610 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touchscreen, and / or cursor direction keys for communicating information and commands to the processor 1602.

[0142] The EDA system 1600 also includes a network interface 1612 coupled to the processor 1602. The network interface 1612 allows the system 1600 to communicate with a network 1614 to which one or more other computer systems are connected. The network interface 1612 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE- 1364. In one or more embodiments, some or all of the processes and / or methods mentioned are implemented in two or more systems 1600.

[0143] The system 1600 is configured to receive information through the I / O interface 1610. The information received through the I / O interface 1610 includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters for processing by the processor 1602. The information is transferred to the processor 1602 via the bus 1608. The EDA system 1600 is configured to receive information related to a UI through the I / O interface 1610. The information is stored in the computer-readable medium 1604 as a user interface (UI) 1642.

[0144] In some embodiments, part or all of the processes and / or methods referred to are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods referred to are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods referred to are implemented as a plug-in of a software application. In some embodiments, at least one of the processes and / or methods referred to is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods referred to are implemented as a software application used by the EDA system 1600. In some embodiments, a tool such as the CANDENCE® DESIGN SYSTEMS, INC. or other suitable place and route tool is used to generate a layout including standard cells.

[0145] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, one or more of external / removable and / or internal / built-in storage devices or memory units, such as an optical disc like a DVD, a magnetic disc like a hard disk, a semiconductor memory like one or more of ROM, RAM, a memory card, and the like.

[0146] FIG. 17 is a block diagram of an integrated circuit (IC) manufacturing system 1700 and associated IC manufacturing flow in accordance with some embodiments. In some embodiments, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is manufactured using the manufacturing system 1700 based on a layout.

[0147] In FIG. 17In overview, the IC manufacturing system 1700 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 1760, such as a design house 1720, a mask house 1730, and an IC manufacturer / fabricator ("fab") 1750. The entities in the system 1700 are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is various different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1720, the mask house 1730, and the IC fab 1750 are owned by a single large company. In some embodiments, two or more of the design house 1720, the mask house 1730, and the IC fab 1750 coexist in a common facility and use common resources.

[0148] The design house (or design team) 1720 generates an IC design layout 1722. The IC design layout 1722 includes various geometric patterns designed for the IC device 1760. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various components of the IC device 1760 to be manufactured. The various layers are combined to form various IC functions. For example, a portion of the IC design layout 1722 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain, interconnect metal lines or vias, and openings for pads. The design house 1720 implements appropriate design processes to form the IC design layout 1722. The design processes include one or more of logic design, physical design, or place and route operations. The IC design layout 1722 is represented in one or more data files having geometric pattern information. For example, the IC design layout 1722 can be expressed in a GDSII file format or a DFII file format.

[0149] The mask room 1730 includes data preparation 1732 and mask manufacturing 1744. The mask room 1730 uses the IC design layout 1722 to manufacture one or more masks 1745 for use in fabricating the various layers of the IC device 1760 according to the IC design layout 1722. The mask room 1730 performs mask data preparation 1732 in which the IC design layout 1722 is converted to a representative data file ("RDF"). The mask data preparation 1732 provides the RDF for mask manufacturing 1744. The mask manufacturing 1744 includes a mask writer. The mask writer converts the RDF to an image on a substrate, such as a mask (reticle) 1745 or a semiconductor wafer 1753. The IC design layout 1722 is processed by the mask data preparation 1732 to conform to the particular characteristics of the mask writer and / or the requirements of the IC fab 1750. In FIG. 17 In some embodiments, the mask data preparation 1732 and the mask manufacturing 1744 can be collectively referred to as mask data preparation.

[0150] In some embodiments, the mask data preparation 1732 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image errors, such as those that can result from diffraction, interference, other processing effects, etc. The OPC adjusts the IC design layout 1722. In some embodiments, the mask data preparation 1732 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used that treat the OPC as an inverse imaging problem.

[0151] In some embodiments, the mask data preparation 1732 includes a mask rule checker (MRC) that checks the IC design layout 1722 that has already been processed in the OPC using a set of mask creation rules that include certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in the semiconductor fabrication process, etc. In some embodiments, the MRC modifies the IC design layout 1722 to compensate for limitations during the mask manufacturing 1744 that can undo a portion of the modifications performed by the OPC to satisfy the mask creation rules.

[0152] In some embodiments, mask data preparation 1732 includes lithography process check (LPC), which simulates the processing to be implemented by IC fab 1750 to manufacture IC device 1760. LPC simulates the processing based on IC design layout 1722 to create a simulated manufactured device, such as IC device 1760. The processing parameters in the LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as, for example, projection contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and / or combinations thereof. In some embodiments, after a simulated manufactured device is created by the LPC, if the simulated device is not close enough in shape to satisfy design rules, then OPC and / or MRC are repeated to further refine IC design layout 1722.

[0153] It should be appreciated that the above description of mask data preparation 1732 has been simplified for the sake of clarity. In some embodiments, data preparation 1732 includes additional features, such as logic operations (LOP), to modify IC design layout 1722 according to manufacturing rules. Additionally, the processing applied to IC design layout 1722 during data preparation 1732 can be performed in a variety of different orders.

[0154] After mask data preparation 1732 and during mask manufacturing 1744, a mask 1745 or a mask set 1745 is manufactured based on the modified IC design layout 1722. In some embodiments, mask manufacturing 1744 includes performing one or more photolithography exposures based on the IC design layout 1722. In some embodiments, a mechanism using an electron beam (e-beam) or multiple electron beams is used to form a pattern on a mask (photomask or reticle) 1745 based on the modified IC design layout 1722. The mask 1745 can be formed using various techniques. In some embodiments, the mask 1745 is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation (e.g., an ultraviolet (UV) beam) used to expose a layer of image- sensitive material (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 1745 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1745 is formed using phase shift technology. In a phase shift mask (PSM) version of the mask 1745, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or a

[0155] IC fab 1750 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, the IC Fab 1750 is a semiconductor foundry. For example, there can be one manufacturing plant for front-end-of-line (FEOL) manufacturing of multiple IC products, while a second manufacturing plant can provide back-end-of-line (BEOL) manufacturing for interconnects and packaging of the IC products, and a third manufacturing plant can provide other services for the foundry business.

[0156] IC fab 1750 includes manufacturing tool 1752 configured to perform various manufacturing operations on semiconductor wafer 1753 to manufacture IC device 1760 according to one or more masks (e.g., mask 1745). In various embodiments, manufacturing tool 1752 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more manufacturing processes discussed herein.

[0157] IC fab 1750 uses one or more masks 1745 manufactured by mask chamber 1730 to fabricate IC device 1760. Therefore, IC fab 1750 uses IC design layout 1722 at least indirectly to fabricate IC device 1760. In some embodiments, IC fab 1750 uses one or more masks 1745 to fabricate semiconductor wafer 1753 to form IC device 1760. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1722. Semiconductor wafer 1753 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1753 also includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0158] Regarding integrated circuit (IC) manufacturing systems (e.g., FIG. 17 Details of the system (1700) and the associated IC manufacturing process can be found in the following documents: for example, U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, which are incorporated herein by reference in their entirety.

[0159] One aspect of the disclosure relates to an integrated circuit. The integrated circuit includes an intermediate active region structure between a first set of active region structures and a second set of active region structures. The intermediate active region structure is aligned with the first set of active region structures and the second set of active region structures along a first direction. The integrated circuit also includes a main circuit, a first set of circuits, and a second set of circuits. The main circuit includes a first boundary gate conductor, a second boundary gate conductor, and an adjacent gate conductor separated by a pitch distance equal to a contact poly pitch (“CPP”) between the first boundary gate conductor and the second boundary gate conductor. The first boundary gate conductor intersects the intermediate active region structure at a first end of the intermediate active region structure. The second boundary gate conductor intersects the intermediate active region structure at a second end of the intermediate active region structure. The first set of circuits includes a first set of boundary gate conductors that intersect the first set of active region structures at first ends of the first set of active region structures, and a first set of isolation structures that separate the first set of active region structures into a first portion in the first set of circuits and a second portion in a first adjacent circuit. The first set of boundary gate conductors are separated by a pitch distance of one CPP from the first boundary gate conductor in the main circuit. A width of the first set of isolation structures along the first direction is less than half of the CPP. The second set of circuits includes a second set of boundary gate conductors that intersect the second set of active region structures at first ends of the second set of active region structures, and a second set of isolation structures that separate the second set of active region structures into a first portion in the second set of circuits and a second portion in a second adjacent circuit. The second set of boundary gate conductors are separated by a pitch distance of one CPP from the second boundary gate conductor in the main circuit. A width of the second set of isolation structures along the first direction is less than half of the CPP.

[0160] Another aspect of the present disclosure relates to a method. The method includes fabricating an active region semiconductor structure on an insulator support, fabricating a gate conductor intersecting the active region semiconductor structure, and fabricating a terminal conductor intersecting the active region semiconductor structure. The method further includes dividing the active region semiconductor structure into a plurality of active region semiconductor structures including an intermediate active region structure between a first group of active region structures and a second group of active region structures. By dividing the active region semiconductor structure, the method includes forming a first boundary gate conductor at a first end of the intermediate active region structure, forming a second boundary gate conductor at a second end of the intermediate active region structure, forming a first group of boundary gate conductors at a first end of the first group of active region structures, and forming a second group of boundary gate conductors at a first end of the second group of active region structures. The method further includes depositing an interlayer dielectric material covering the intermediate active region structure, the first group of active region structures, the second group of active region structures, and the gate conductor. The method further includes forming a first trench to divide the first group of active region structures into a first portion and a second portion after removing the first gate conductor, and forming a second trench to divide the second group of active region structures into a first portion and a second portion after removing the second gate conductor. The method further includes forming a first group of isolation structures in the first trench, and forming a second group of isolation structures in the second trench.

[0161] Another aspect of the present disclosure still relates to an integrated circuit. The integrated circuit includes an intermediate first type active region structure between a first group of first type active region structures and a second group of first type active region structures. The intermediate first type active region structure is aligned with the first group of first type active region structures and the second group of first type active region structures along a first direction. The integrated circuit further includes a main circuit, a first group of circuits, and a second group of circuits. The main circuit includes a first boundary gate conductor intersecting the intermediate first type active region structure at a first end of the intermediate first type active region structure, and an adjacent gate conductor separated by a pitch distance equal to a contact poly pitch (“CPP”). The first group of circuits includes a first group of boundary gate conductors intersecting the first group of first type active region structures at a first end of the first group of first type active region structures, and a first group of isolation structures dividing the first group of first type active region structures into a first portion in the first group of circuits and a second portion in a first adjacent circuit. The first group of boundary gate conductors is separated from the first boundary gate conductor in the main circuit by a pitch distance of one CPP. The first group of isolation structures has a width along the first direction that is less than half of the CPP. The second group of circuits includes a second group of isolation structures dividing the second group of first type active region structures into a first portion in the second group of circuits and a second portion in a second adjacent circuit. The second group of isolation structures has a width along the first direction that is less than half of the CPP.

[0162] Those of ordinary skill in the art will readily understand that the one or more embodiments disclosed implement one or more of the advantages set forth above. Various changes, substitutions, equivalents, and various other embodiments thereof disclosed herein can be ascertained by one of ordinary skill in the art after reading the foregoing description. Thus, the protection afforded to the application is not limited to the specific embodiments disclosed, but rather is to be accorded the full scope consistent with the claims and their equivalents.

[0163] Example

[0164] Example 1. An integrated circuit comprising: an intermediate active area structure between a first set of active area structures and a second set of active area structures, wherein the intermediate active area structure is aligned with the first set of active area structures and the second set of active area structures along a first direction; a main circuit comprising: a first boundary gate conductor intersecting the intermediate active area structure at a first end of the intermediate active area structure, a second boundary gate conductor intersecting the intermediate active area structure at a second end of the intermediate active area structure, and an adjacent gate conductor separated by a pitch distance equal to a contact poly pitch ("CPP") between the first boundary gate conductor and the second boundary gate conductor; a first set of circuits comprising: a first set of boundary gate conductors intersecting the first set of active area structures at a first end of the first set of active area structures and separated by a pitch distance of one CPP from the first boundary gate conductor in the main circuit, and a first set of isolation structures separating the first set of active area structures into a first portion in the first set of circuits and a second portion in a first adjacent circuit, wherein a width of the first set of isolation structures along the first direction is less than half of the CPP; and a second set of circuits comprising: a second set of boundary gate conductors intersecting the second set of active area structures at a first end of the second set of active area structures and separated by a pitch distance of one CPP from the second boundary gate conductor in the main circuit, and a second set of isolation structures separating the second set of active area structures into a first portion in the second set of circuits and a second portion in a second adjacent circuit, wherein a width of the second set of isolation structures along the first direction is less than half of the CPP.

[0165] Example 2. The integrated circuit of example 1, wherein: a pitch distance between the first set of boundary gate conductors and the first set of isolation structures is equal to or greater than two CPPs; and a pitch distance between the second set of boundary gate conductors and the second set of isolation structures is equal to or greater than two CPPs.

[0166] Example 3. The integrated circuit of Example 2, wherein each of the first and second sets of circuitry comprises: one or more gate conductors intersecting the first or second set of active area structures.

[0167] Example 4. The integrated circuit of Example 2, wherein each of the first and second sets of circuitry comprises: one or more dummy gate conductors intersecting the first or second set of active area structures.

[0168] Example 5. The integrated circuit of Example 2, wherein each of the first and second sets of circuitry comprises: one or more terminal conductors intersecting the first or second set of active area structures.

[0169] Example 6. The integrated circuit of Example 1, wherein: the first adjacent circuit has a first gate conductor intersecting a second portion of the first set of active area structures at a first channel region of a first transistor, and wherein the first gate conductor is separated from the first set of isolation structures by a pitch distance of one CPP; and the second adjacent circuit has a second gate conductor intersecting a second portion of the second set of active area structures at a second channel region of a second transistor, and wherein the second gate conductor is separated from the second set of isolation structures by a pitch distance of one CPP.

[0170] Example 7. The integrated circuit of Example 6, wherein: the first adjacent circuit further comprises a first terminal conductor intersecting the second portion of the first set of active area structures at a first terminal region between the first set of isolation structures and the first channel region; and the second adjacent circuit further comprises a second terminal conductor intersecting the second portion of the second set of active area structures at a second terminal region between the second set of isolation structures and the second channel region.

[0171] Example 8. A method for forming a semiconductor structure, comprising: fabricating an active region semiconductor structure on an insulator support; fabricating gate conductors intersecting the active region semiconductor structure; fabricating terminal conductors intersecting the active region semiconductor structure; dividing the active region semiconductor structure into a plurality of active region semiconductor structures, the plurality of active region semiconductor structures including an intermediate active region structure between a first group of active region structures and a second group of active region structures, such that a first boundary gate conductor is formed at a first end of the intermediate active region structure, a second boundary gate conductor is formed at a second end of the intermediate active region structure, a first group of boundary gate conductors is formed at first ends of the first group of active region structures, and a second group of boundary gate conductors is formed at first ends of the second group of active region structures; depositing an interlayer dielectric material covering the intermediate active region structure, the first group of active region structures, the second group of active region structures, and the gate conductors; forming a first trench to divide the first group of active region structures into a first portion and a second portion after removing a first gate conductor, and forming a second trench to divide the second group of active region structures into a first portion and a second portion after removing a second gate conductor; and forming a first group of isolation structures in the first trench, and forming a second group of isolation structures in the second trench.

[0172] Example 9. The method of example 8, wherein adjacent gate conductors are separated by a pitch distance equal to a contact poly pitch (“CPP”), and wherein dividing the active region semiconductor structure comprises: forming the first boundary gate conductor and the first group of boundary gate conductors separated by one CPP; and forming the second boundary gate conductor and the second group of boundary gate conductors separated by one CPP.

[0173] Example 10. The method of example 8, wherein forming the first trench and forming the second trench comprises: forming the first trench to extend into the insulator support; and forming the second trench to extend into the insulator support.

[0174] Example 11. An integrated circuit comprising: an intermediate first-type active region structure between a first set of first-type active region structures and a second set of first-type active region structures, wherein the intermediate first-type active region structure is aligned with the first set of first-type active region structures and the second set of first-type active region structures along a first direction; a main circuit comprising: a first boundary gate conductor intersecting the intermediate first-type active region structure at a first end of the intermediate first-type active region structure, and an adjacent gate conductor separated by a pitch distance equal to a contact poly pitch ("CPP"); a first set of circuits comprising: a first set of boundary gate conductors intersecting the first set of first-type active region structures at a first end of the first set of first-type active region structures and separated by a pitch distance of one CPP from the first boundary gate conductor in the main circuit, and a first set of isolation structures separating the first set of first-type active region structures into a first portion in the first set of circuits and a second portion in a first adjacent circuit, wherein a width of the first set of isolation structures along the first direction is less than half of the CPP; and a second set of circuits comprising: a second set of isolation structures separating the second set of first-type active region structures into a first portion in the second set of circuits and a second portion in a second adjacent circuit, wherein a width of the second set of isolation structures along the first direction is less than half of the CPP.

[0175] Example 12. The integrated circuit of example 11, wherein: the main circuit further comprises a second boundary gate conductor intersecting the intermediate first-type active region structure at a second end of the intermediate first-type active region structure; and the second set of circuits further comprises a second set of boundary gate conductors intersecting the second set of first-type active region structures at a first end of the second set of first-type active region structures and separated by a pitch distance of one CPP from the second boundary gate conductor in the main circuit.

[0176] Example 13. The integrated circuit of example 11, wherein: the main circuit further comprises a boundary isolation structure terminating the intermediate first-type active region structure at a second end of the intermediate first-type active region structure; and the second set of first-type active region structures in the second set of circuits is joined to the intermediate first-type active region structure in the main circuit by the boundary isolation structure.

[0177] Example 14. The integrated circuit of Example 11, further comprising: an intermediate second-type active region structure between the first set of second-type active region structures and the second set of second-type active region structures, wherein the intermediate second-type active region structure is aligned with the first set of second-type active region structures and the second set of second-type active region structures along the first direction; and wherein the main circuit comprises first-type transistors having first-type channel regions in the intermediate first-type active region structure and second-type transistors having second-type channel regions in the intermediate second-type active region structure.

[0178] Example 15. The integrated circuit of Example 14, wherein the intermediate second-type active region structure is separated from at least one of the first set of second-type active region structures or the second set of second-type active region structures by a distance that is more than half of the CPP in the first direction.

[0179] Example 16. The integrated circuit of Example 14, wherein the intermediate second-type active region structure is joined with at least one of the first set of second-type active region structures or the second set of second-type active region structures to form a continuous second-type active region structure.

[0180] Example 17. The integrated circuit of Example 16, the main circuit further comprising a dummy gate conductor intersecting the continuous second-type active region structure at a boundary of the main circuit.

[0181] Example 18. The integrated circuit of Example 17, wherein: the main circuit further comprises a boundary isolation structure terminating with the intermediate first-type active region structure at a second end of the intermediate first-type active region structure, the boundary isolation structure joining the intermediate first-type active region structure in the main circuit with the second set of first-type active region structures; and the dummy gate conductor at the boundary of the main circuit is aligned with the boundary isolation structure along a second direction that is perpendicular to the first direction.

[0182] Example 19. The integrated circuit of Example 14, wherein the first boundary gate conductor further intersects the intermediate second-type active region structure at a first end of the intermediate second-type active region structure.

[0183] Example 20. The integrated circuit of Example 14, wherein the first boundary gate conductor includes a first gate conductor segment that intersects the middle first-type active area structure at a first end of the middle first-type active area structure, and wherein the first boundary gate conductor further includes a second gate conductor segment that is separated from the first gate conductor segment, and wherein the second gate conductor segment intersects the middle second-type active area structure at a first end of the middle second-type active area structure.

Claims

1. An integrated circuit comprising: an intermediate active region structure between a first set of active region structures and a second set of active region structures, wherein the intermediate active region structure is aligned with the first set of active region structures and the second set of active region structures along a first direction; a main circuit comprising: a first boundary gate conductor intersecting the intermediate active region structure at a first end of the intermediate active region structure, a second boundary gate conductor intersecting the intermediate active region structure at a second end of the intermediate active region structure, and an adjacent gate conductor separated by a pitch distance equal to a contact poly pitch (CPP) between the first boundary gate conductor and the second boundary gate conductor; a first set of circuits comprising: a first set of boundary gate conductors intersecting the first set of active region structures at a first end of the first set of active region structures and separated by a pitch distance of one CPP from the first boundary gate conductor in the main circuit, and a first set of isolation structures separating the first set of active region structures into a first portion in the first set of circuits and a second portion in a first adjacent circuit, wherein a width of the first set of isolation structures along the first direction is less than half of the CPP; and a second set of circuits comprising: a second set of boundary gate conductors intersecting the second set of active region structures at a first end of the second set of active region structures and separated by a pitch distance of one CPP from the second boundary gate conductor in the main circuit, and a second set of isolation structures separating the second set of active region structures into a first portion in the second set of circuits and a second portion in a second adjacent circuit, wherein a width of the second set of isolation structures along the first direction is less than half of the CPP.

2. The integrated circuit of claim 1, wherein: a pitch distance between the first set of boundary gate conductors and the first set of isolation structures is equal to or greater than two CPPs; and a pitch distance between the second set of boundary gate conductors and the second set of isolation structures is equal to or greater than two CPPs.

3. The integrated circuit of claim 2, wherein, each of the first set of circuits and the second set of circuits comprises: one or more gate conductors intersecting the first set of active region structures or the second set of active region structures.

4. The integrated circuit of claim 2, wherein, each of the first set of circuits and the second set of circuits comprises: one or more dummy gate conductors intersecting the first set of active region structures or the second set of active region structures.

5. The integrated circuit of claim 2, wherein, each of the first set of circuits and the second set of circuits comprises: one or more terminal conductors intersecting the first set of active region structures or the second set of active region structures.

6. The integrated circuit of claim 1, wherein: the first adjacent circuit has a first gate conductor intersecting the second portion of the first set of active region structures at a first channel region of a first transistor, and wherein the first gate conductor is separated by a pitch distance of one CPP from the first set of isolation structures; and the second adjacent circuit has a second gate conductor intersecting the second portion of the second set of active region structures at a second channel region of a second transistor, and wherein the second gate conductor is separated by a pitch distance of one CPP from the second set of isolation structures. The second adjacent circuit has a second gate conductor intersecting a second portion of the second set of active area structures at a second channel region of a second transistor, and wherein the second gate conductor is separated from the second set of isolation structures by a pitch distance equal to a contact poly pitch (CPP).

7. The integrated circuit of claim 6, wherein: The first adjacent circuit further includes a first terminal conductor intersecting a second portion of the first set of active area structures at a first terminal region between the first set of isolation structures and the first channel region; and The second adjacent circuit further includes a second terminal conductor intersecting a second portion of the second set of active area structures at a second terminal region between the second set of isolation structures and the second channel region.

8. A method for forming a semiconductor structure, comprising: fabricating an active area semiconductor structure on an insulator support; fabricating a gate conductor intersecting the active area semiconductor structure; fabricating a terminal conductor intersecting the active area semiconductor structure; dividing the active area semiconductor structure into a plurality of active area semiconductor structures including an intermediate active area structure between a first set of active area structures and a second set of active area structures such that a first boundary gate conductor is formed at a first end of the intermediate active area structure, a second boundary gate conductor is formed at a second end of the intermediate active area structure, a first set of boundary gate conductors is formed at a first end of the first set of active area structures, and a second set of boundary gate conductors is formed at a first end of the second set of active area structures; depositing an interlayer dielectric material covering the intermediate active area structure, the first set of active area structures, the second set of active area structures, and the gate conductor; forming a first trench to divide the first set of active area structures into a first portion and a second portion after removing a first gate conductor, and forming a second trench to divide the second set of active area structures into a first portion and a second portion after removing a second gate conductor; and forming a first set of isolation structures in the first trench and a second set of isolation structures in the second trench, wherein adjacent gate conductors are separated by a pitch distance equal to a contact poly pitch (CPP), and wherein dividing the active area semiconductor structure includes forming the first boundary gate conductor and the first set of boundary gate conductors separated by one CPP, and forming the second boundary gate conductor and the second set of boundary gate conductors separated by one CPP; and wherein a width of the first set of isolation structures along a first direction is less than half of the CPP, and wherein a width of the second set of isolation structures along the first direction is less than half of the CPP.

9. The method of claim 8, wherein, forming the first trench and forming the second trench includes: forming the first trench to extend into the insulator support; and forming the second trench to extend into the insulator support.

10. An integrated circuit, comprising: an intermediate first-type active region structure between the first set of first-type active region structures and the second set of first-type active region structures, wherein the intermediate first-type active region structure is aligned with the first set of first-type active region structures and the second set of first-type active region structures along a first direction; a main circuit comprising: a first boundary gate conductor intersecting the intermediate first-type active region structure at a first end of the intermediate first-type active region structure, and adjacent gate conductors separated by a pitch distance equal to a contact poly pitch (CPP); a first set of circuits comprising: a first set of boundary gate conductors intersecting the first set of first-type active region structures at a first end of the first set of first-type active region structures and separated from the first boundary gate conductor in the main circuit by a pitch distance of the CPP, and a first set of isolation structures separating the first set of first-type active region structures into a first portion in the first set of circuits and a second portion in a first adjacent circuit, wherein a width of the first set of isolation structures along the first direction is less than half of the CPP; and a second set of circuits comprising: a second set of isolation structures separating the second set of first-type active region structures into a first portion in the second set of circuits and a second portion in a second adjacent circuit, wherein a width of the second set of isolation structures along the first direction is less than half of the CPP.

11. The integrated circuit of claim 10, wherein: the main circuit further comprises a second boundary gate conductor intersecting the intermediate first-type active region structure at a second end of the intermediate first-type active region structure; and the second set of circuits further comprises a second set of boundary gate conductors intersecting the second set of first-type active region structures at a first end of the second set of first-type active region structures and separated from the second boundary gate conductor in the main circuit by a pitch distance of the CPP.

12. The integrated circuit of claim 10, wherein: the main circuit further comprises a boundary isolation structure terminating the intermediate first-type active region structure at a second end of the intermediate first-type active region structure; and the second set of first-type active region structures in the second set of circuits is joined to the intermediate first-type active region structure in the main circuit by the boundary isolation structure.

13. The integrated circuit of claim 10, further comprising: an intermediate second-type active region structure between a first set of second-type active region structures and a second set of second-type active region structures, wherein the intermediate second-type active region structure is aligned with the first set of second-type active region structures and the second set of second-type active region structures along the first direction; and the first set of second-type active region structures and the second set of second-type active region structures are separated by a pitch distance equal to a contact poly pitch (CPP). wherein the main circuit includes a first type transistor having a first type channel region in the intermediate first type active area structure and a second type transistor having a second type channel region in the intermediate second type active area structure.

14. The integrated circuit of claim 13, wherein, The intermediate second type active area structure is separated from at least one of the first set of second type active area structures or the second set of second type active area structures by a distance that is more than half of the CPP in the first direction.

15. The integrated circuit of claim 13, wherein, The intermediate second type active area structure is joined with at least one of the first set of second type active area structures or the second set of second type active area structures to form a continuous second type active area structure.

16. The integrated circuit of claim 15, the main circuit further comprising a dummy gate conductor intersecting the continuous second type active area structure at a boundary of the main circuit.

17. The integrated circuit of claim 16, wherein: the main circuit further comprises a boundary isolation structure terminating with the intermediate first type active area structure at a second end of the intermediate first type active area structure, the boundary isolation structure joining the intermediate first type active area structure in the main circuit with the second set of first type active area structures; and the dummy gate conductor at a boundary of the main circuit is aligned with the boundary isolation structure along a second direction that is perpendicular to the first direction.

18. The integrated circuit of claim 13, wherein, The first boundary gate conductor further intersects the intermediate second type active area structure at a first end of the intermediate second type active area structure.

19. The integrated circuit of claim 13, wherein, The first boundary gate conductor includes a first gate conductor segment intersecting the intermediate first type active area structure at a first end of the intermediate first type active area structure, and wherein the first boundary gate conductor further includes a second gate conductor segment separated from the first gate conductor segment, and wherein the second gate conductor segment intersects the intermediate second type active area structure at a first end of the intermediate second type active area structure.

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