Manufacturing method for reducing leakage between gates of NAND flash memory

Abstract

The present invention discloses a manufacturing method for reducing leakage between word lines of a NAND flash memory, including: Step 1, providing a semiconductor substrate on which a gate structure has been fabricated. Step 2, loading the wafer into a first type of FOUP to complete: Step 21, depositing a nickel-platinum alloy. Step 22, performing a first silicidation annealing process. Step 23, removing the remaining nickel-platinum alloy. Step 3, loading the wafer into a second type of FOUP to complete: using the PECVD process to grow a second dielectric layer to seal the first trench and form an air gap. Step 4, loading the wafer into a first type of FOUP to complete: Step 41, performing a second silicidation annealing process. Step 42, performing a first wet cleaning process for replacing the FOUP. Step 5, loading the wafer into a second type of FOUP and completing: performing a third annealing on the second dielectric layer. The present invention can prevent the word lines formed by the polysilicon control gate connections of the memory cells from tilting, thereby reducing the leakage between the word lines.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and particularly to a manufacturing method for reducing leakage between gates of a NAND flash memory. Background Art

[0002] Some chip bins of NAND flash memories fail due to leakage between gates, and there is a special map distribution in the test result map, such as the test results in the up and down directions of the Y-axis are worse. Since the aspect ratio of the word line (WL) is as high as 12:1, the gate etch (GT ET) and subsequent processes are very likely to cause the WL to tilt, thereby causing leakage between WLs. Through research, it is found that it is strongly related to the process between the second nickel silicide annealing process and the replacement of the pre-cleaning in the front opening unified pod (FOUP). It is suspected that when the temperature is relatively high, it is easier to cause the WL to tilt or the WL space to decrease when entering the wet bench for cleaning.

[0003] As Figure 1 shown, it is a flowchart of a conventional manufacturing method for reducing leakage between word lines of a NAND flash memory; Figure 1 Only the steps between the formation of nickel silicide and the formation of the air gap after the formation of the gate structure are given. For the device structure in the conventional manufacturing method for reducing leakage between word lines of a NAND flash memory, please also refer to Figure 1 shown. The conventional manufacturing method for reducing leakage between word lines of a NAND flash memory includes the following steps:

[0004] First, as Figure 1 shown, a semiconductor substrate 101 on which the gate structure has been fabricated is provided. The semiconductor substrate 101 is a wafer; a plurality of memory cells are formed in the storage area of the flash memory. The gate structure of each memory cell is a first gate structure 201, and the first gate structure 201 includes a floating gate dielectric layer 102, a polysilicon floating gate 103, a control dielectric layer 104, and a polysilicon control gate 105 formed in sequence on the surface of the semiconductor substrate 101; the polysilicon control gates 105 of the memory cells in the same row are connected together and serve as word lines.

[0005] A first trench is formed between the first gate structures 201, and a first dielectric layer 106 is formed on the inner surface of the first trench.

[0006] Generally, the semiconductor substrate 101 includes a silicon substrate.

[0007] The first dielectric layer 106 is an oxide layer.

[0008] The first dielectric layer 106 is formed by thermally oxidizing the semiconductor substrate 101, the polysilicon floating gate 103, and the polysilicon control gate 105 exposed on the inner surface of the first trench.

[0009] The aspect ratio of the first trench is greater than or equal to 12:1.

[0010] A selection transistor is also formed in the storage area, and the storage cells in the same column are all connected in series with the selection transistor. Figure 1 In, the second gate structure 202 of the selection transistor is also formed by stacking the floating gate dielectric layer 102, the polysilicon floating gate 103, the control dielectric layer 104, and the polysilicon control gate 105, but a part or all of the control dielectric layer 104 is removed, so that the polysilicon floating gate 103 and the polysilicon control gate 105 are in contact.

[0011] An outer peripheral area is further included outside the storage area, and peripheral transistors are formed in the outer peripheral area. Figure 1 In, the third gate structure 203 of the peripheral transistor is also formed by stacking the floating gate dielectric layer 102, the polysilicon floating gate 103, the control dielectric layer 104, and the polysilicon control gate 105, but a part or all of the control dielectric layer 104 is removed, so that the polysilicon floating gate 103 and the polysilicon control gate 105 are in contact.

[0012] Sidewalls are further formed on the side of the outside of the second gate structure 202 and the side of the third gate structure 203. The sidewalls include a stacked structure of a nitride layer 204, an oxide layer 205, and a nitride layer 206. A dielectric layer including a dielectric layer 207 and a dielectric layer 208 is further filled in the interval area between the outer side surface of the second gate structure 202 and the adjacent third gate structure 203 or between the third gate structures 203.

[0013] Then, the following steps are performed:

[0014] Step S101: Deposit a nickel-platinum (NiPt) alloy (not shown). Figure 1 The subsequent formed second nickel silicide 107 is directly shown in. Figure 1 In, NiPt dep in the box of step S101 indicates the deposition of the nickel-platinum alloy, and dep represents the deposition process.

[0015] Step 102: Perform a first silicidation annealing process for generating the first nickel silicide. The first silicidation annealing process causes the nickel-platinum alloy to react with the silicon of the polysilicon control gate 105 to form the first nickel silicide with the chemical formula Ni2PtSi. Figure 1In this process, 1st ANN shown in the box of step S102 represents the first silicidation annealing process, where ANN is the abbreviation of annealing.

[0016] Generally, the first silicidation annealing process adopts rapid thermal annealing (RTA).

[0017] The temperature of the first silicidation annealing process is 200°C to 350°C.

[0018] Step 103: Remove the remaining nickel-platinum alloy that is not reacted on the surface of the first nickel silicide and outside the first nickel silicide. Generally, wet etching is used to remove the remaining nickel-platinum alloy. Figure 1 In the box of step S103, wet clean post RTA1 shown represents the wet etching process for removing the remaining nickel-platinum alloy, where RTA1 represents the first silicidation annealing process.

[0019] Step 104: Perform a second silicidation annealing process. The second silicidation annealing process converts the first nickel silicide into a second nickel silicide 107107 with the molecular formula NiPtSi; the temperature of the second silicidation annealing process is higher than that of the first silicidation annealing process.

[0020] Generally, the second silicidation annealing process adopts rapid thermal annealing.

[0021] The temperature of the second silicidation annealing process is 400°C to 450°C.

[0022] Figure 1 In this process, 2nd ANN shown in the box of step S104 represents the second silicidation annealing process.

[0023] Step S105: Perform a first wet cleaning process, and the first wet cleaning process is for cleaning to replace the FOUP.

[0024] The etching solution of the first wet cleaning process is likely to enter the inside of the first trench. After the second silicidation annealing process, the etching solution of the second wet process is likely to etch the inner surface of the first trench, resulting in the first gate structure 201 being inclined (leaning), or reducing the spacing (space) between the first gate structures 201 and generating water vapor residues, etc. All these are likely to cause leakage between the word lines.

[0025] Figure 1 In this process, Wet clean for FOUP change shown in the box of step S105 represents the first wet cleaning process, that is, the cleaning for replacing the FOUP.

[0026] Figure 1 In this case, the boxes of steps S101 to S105 are filled with dots, indicating that steps S101 to S105 all use the first type of FOUP to carry the wafer. That is to say, after the wafer completes the corresponding process steps, it needs to be placed in the first type of FOUP, and then the first type of FOUP is carried to the machine equipment corresponding to the next process step and the next process is performed. In each of steps S101 to S105, the same FOUP can be used, or different FOUPs can be used respectively, but it is necessary to ensure that the types of all FOUPs are the same, that is, all are of the first type.

[0027] Step S106: Grow undoped silicon dioxide (USG) 108 by PECVD process. In the storage area, the undoped silicon dioxide 108 is formed on the surface of the first nickel silicide, and the undoped silicon dioxide 108 also seals the first trench and thus forms an air gap in the first trench.

[0028] Figure 1 In this case, PE-SiH4dep shown in the box of step S106 represents growing undoped silicon dioxide by PECVD process. PE represents PECVD, SiH4 represents that the silicon source gas is SiH4, and dep represents deposition. PE-SiH4 represents undoped silicon dioxide formed by using SiH4 as the silicon source and PECVD process.

[0029] Step S107: Perform the third annealing on the undoped silicon dioxide 108.

[0030] Figure 1 In this case, PE-SiH4ANN shown in the box of step S107 represents the third annealing, that is, the annealing of the undoped silicon dioxide 108.

[0031] Figure 1 In this case, the boxes of steps S106 to S107 are filled with slashes, indicating that steps S106 to S107 use the second type of FOUP to carry the wafer. In each of steps S106 to S107, the same FOUP can be used, or different FOUPs can be used respectively, but it is necessary to ensure that the types of all FOUPs are the same, that is, all are of the second type.

[0032] The first type of FOUP and the second type of FOUP are different to prevent contamination. For example, it is easy to cause contamination to the chip or the machine equipment for manufacturing the chip during the process between metal and dielectric. Summary of the Invention

[0033] The technical problem to be solved by the present invention is to provide a manufacturing method for reducing leakage between word lines of a NAND flash memory, which can prevent the word lines formed by the connection of the polysilicon control gates of the storage units in the storage area from tilting, thereby reducing the leakage between the word lines.

[0034] To solve the above technical problem, the manufacturing method for reducing leakage between word lines of a NAND flash memory provided by the present invention includes the following steps:

[0035] Step 1: Provide a semiconductor substrate on which a gate structure has been fabricated, and the semiconductor substrate is a wafer; a plurality of storage units are formed in the storage area of the flash memory, and the gate structure of each storage unit is a first gate structure. The first gate structure includes a floating gate dielectric layer, a polysilicon floating gate, a control dielectric layer, and a polysilicon control gate formed in sequence on the surface of the semiconductor substrate; the polysilicon control gates of the storage units in the same row are connected together and serve as word lines.

[0036] A first trench is formed between each of the first gate structures, and a first dielectric layer is formed on the inner surface of the first trench.

[0037] Step 2: Load the wafer into a first type of FOUP, and transport the wafer through the first type of FOUP to complete the following steps:

[0038] Step 21: Deposit a nickel-platinum alloy. In the storage area, the nickel-platinum alloy covers the top surface of the polysilicon control gate and the surface of the first dielectric layer in the first trench.

[0039] Step 22: Perform a first silicidation annealing process for generating the first nickel silicide. The first silicidation annealing process causes the nickel-platinum alloy and the silicon of the polysilicon control gate to react to form the first nickel silicide with the chemical formula Ni2PtSi.

[0040] Step 23: Remove the remaining nickel-platinum alloy that has not reacted on the surface of the first nickel silicide and outside the first nickel silicide.

[0041] Step 3: Load the wafer into a second type of FOUP, and transport the wafer through the second type of FOUP to complete the following steps:

[0042] Use the PECVD process to grow a second dielectric layer. In the storage area, the second dielectric layer is formed on the surface of the first nickel silicide, and the second dielectric layer also seals the first trench and thus forms an air gap in the first trench.

[0043] Step 4. Load the wafer into the first type of FOUP, and transport the wafer through the first type of FOUP to complete the following steps:

[0044] Step 41. Perform a second silicidation annealing process, which converts the first nickel metal silicide into a second nickel metal silicide with the chemical formula NiPtSi; the temperature of the second silicidation annealing process is higher than that of the first silicidation annealing process.

[0045] Step 42. Perform a first wet cleaning process, which is a cleaning process for replacing the FOUP. The structure of the first trench seal prevents the etching solution of the first wet cleaning process from entering the inside of the first trench, and thus prevents the etching solution of the second wet process from etching the inner surface of the first trench and causing the first gate structure to tilt, thereby reducing the leakage between the word lines.

[0046] Step 5. Load the wafer into the second type of FOUP, and transport the wafer through the second type of FOUP to complete the following steps:

[0047] Perform a third annealing on the second dielectric layer.

[0048] A further improvement is that the semiconductor substrate includes a silicon substrate.

[0049] A further improvement is that the first dielectric layer is an oxide layer.

[0050] A further improvement is that the first dielectric layer is formed by thermally oxidizing the semiconductor substrate, the polysilicon floating gate, and the polysilicon control gate exposed on the inner surface of the first trench.

[0051] A further improvement is that in step 1, the aspect ratio of the first trench is greater than or equal to 12:1.

[0052] A further improvement is that in step 21, the nickel-platinum alloy is formed by a sputtering process.

[0053] A further improvement is that in step 21, after forming the nickel-platinum alloy, there is also a step of forming a protective layer on the surface of the nickel-platinum alloy, which prevents the nickel-platinum alloy from being oxidized; in step 23, the protective layer needs to be removed first and then the nickel-platinum alloy.

[0054] A further improvement is that the material of the protective layer includes TiN.

[0055] A further improvement is that the protective layer is formed by a sputtering process.

[0056] A further improvement is that the first silicidation annealing process described in step 22 uses rapid thermal annealing.

[0057] A further improvement is that the temperature of the first silicidation annealing process is 200°C to 350°C.

[0058] A further improvement is that in step three, the second dielectric layer is undoped silicon dioxide.

[0059] A further improvement is that the second silicidation annealing process described in step 41 uses rapid thermal annealing.

[0060] A further improvement is that the temperature of the second silicidation annealing process is 400°C to 450°C.

[0061] A further improvement is that in step one, a selection transistor is also formed in the storage area, and the storage units in the same column are all connected in series with the selection transistor.

[0062] After the gate structure of the NAND flash memory is formed in the present invention, during the process of self-aligning and forming nickel silicide on the top of the polysilicon control gate of the storage unit in the storage area, after the first silicidation annealing process with a lower temperature is completed, instead of directly performing the second silicidation annealing process with a higher temperature, a second dielectric layer is formed by PECVD growth. The second dielectric layer closes the first trench between the first gate structures of the storage units and forms an air gap inside. Then, the second silicidation annealing process for forming nickel silicide is carried out, and then the first wet cleaning process for replacing the FOUP is carried out to prevent the etching solution of the first wet cleaning process from entering the inside of the first trench. Since the etching solution of the first wet cleaning process is likely to etch the inner surface that has undergone the second silicidation annealing process at a higher temperature, the present invention can prevent this etching from occurring, so it can prevent the first gate structure from tilting. Therefore, the present invention can prevent the word lines formed by connecting the polysilicon control gates of the storage units in the storage area from tilting, thereby reducing the leakage between the word lines.

[0063] In addition, the present invention can be realized only by making corresponding adjustments to the process sequence, so the present invention will not increase additional process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:

[0065] Figure 1 is a flowchart of a manufacturing method of an existing NAND flash memory;

[0066] Figure 2 is a flowchart of a manufacturing method of the present invention's embodiment for reducing the leakage between the word lines of a NAND flash memory;

[0067] Figure 3 It is a schematic diagram of a device structure in a manufacturing method for reducing leakage between word lines of a NAND flash memory according to an embodiment of the present invention. Specific embodiments

[0068] As Figure 2 shown, it is a flowchart of a manufacturing method for reducing leakage between word lines of a NAND flash memory according to an embodiment of the present invention; as Figure 3 shown, it is a schematic diagram of a device structure in a manufacturing method for reducing leakage between word lines of a NAND flash memory according to an embodiment of the present invention; the manufacturing method for reducing leakage between word lines of a NAND flash memory according to an embodiment of the present invention includes the following steps:

[0069] Step 1: As Figure 3 shown, provide a semiconductor substrate 101 on which a gate structure has been fabricated, and the semiconductor substrate 101 is a wafer; a plurality of memory cells are formed in the storage area of the flash memory, and the gate structure of each memory cell is a first gate structure 201, and the first gate structure 201 includes a floating gate dielectric layer 102, a polysilicon floating gate 103, a control dielectric layer 104, and a polysilicon control gate 105 formed in sequence on the surface of the semiconductor substrate 101; the polysilicon control gates 105 of the memory cells in the same row are connected together and serve as word lines.

[0070] A first trench is formed between the first gate structures 201, and a first dielectric layer 106 is formed on the inner surface of the first trench.

[0071] In an embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.

[0072] The first dielectric layer 106 is an oxide layer.

[0073] The first dielectric layer 106 is formed by thermally oxidizing the semiconductor substrate 101, the polysilicon floating gate 103, and the polysilicon control gate 105 exposed on the inner surface of the first trench.

[0074] The aspect ratio of the first trench is greater than or equal to 12:1.

[0075] A selection transistor is also formed in the storage area, and the memory cells in the same column are all connected in series with the selection transistor. Figure 3 In, the second gate structure 202 of the selection transistor is also formed by stacking a floating gate dielectric layer 102, a polysilicon floating gate 103, a control dielectric layer 104, and a polysilicon control gate 105, but part or all of the control dielectric layer 104 is removed, so that the polysilicon floating gate 103 and the polysilicon control gate 105 are in contact.

[0076] Outside the storage area, there is also a peripheral area, and peripheral transistors are formed in the peripheral area. Figure 3 In Figure 3 , the third gate structure 203 of the peripheral transistor is also formed by stacking a floating gate dielectric layer 102, a polysilicon floating gate 103, a control dielectric layer 104, and a polysilicon control gate 105. However, part or all of the control dielectric layer 104 is removed, so that the polysilicon floating gate 103 and the polysilicon control gate 105 are in contact.

[0077] Sidewalls are also formed on the side of the outside of the second gate structure 202 and the side of the third gate structure 203. The sidewalls include a stacked structure of a nitride layer 204, an oxide layer 205, and a nitride layer 206. A dielectric layer, including a dielectric layer 207 and a dielectric layer 208, is also filled in the interval area between the outer side surface of the second gate structure 202 and the adjacent third gate structure 203 or between the third gate structures 203.

[0078] Step Two: Load the wafer into the first type of FOUP, and carry the wafer through the first type of FOUP to complete the following steps:

[0079] Step 21: Deposit a nickel-platinum alloy (not shown). Figure 3 The subsequent formed second nickel silicide 107 is directly shown in Figure 3 . In the storage area, the nickel-platinum alloy covers the top surface of the polysilicon control gate 105 and the surface of the first dielectric layer 106 in the first trench. Step 21 corresponds to Figure 2 Step S201 in Figure 2 . In the box of step S201, NiPt dep deposits a nickel-platinum alloy, and dep represents the deposition process.

[0080] In the embodiment of the present invention, the nickel-platinum alloy is formed by a sputtering process.

[0081] After forming the nickel-platinum alloy, there is also a step of forming a protective layer (not shown) on the surface of the nickel-platinum alloy, and the protective layer prevents the nickel-platinum alloy from being oxidized.

[0082] The material of the protective layer includes TiN.

[0083] The protective layer is formed by a sputtering process.

[0084] In the subsequent step 23, the protective layer needs to be removed first and then the nickel-platinum alloy is removed.

[0085] Step 22: Perform a first silicidation annealing process for generating the first nickel silicide. The first silicidation annealing process causes the nickel-platinum alloy and the silicon of the polysilicon control gate 105 to react to form the first nickel silicide with the molecular formula Ni2PtSi. Step 22 corresponds to Figure 2In step S202, the 1st ANN shown in the box of step S202 represents the first silicidation annealing process.

[0086] In an embodiment of the present invention, the first silicidation annealing process in step 22 uses rapid thermal annealing.

[0087] The temperature of the first silicidation annealing process is 200°C to 350°C.

[0088] Step 23: Remove the remaining nickel-platinum alloy that is not reacted on the surface of the first nickel silicide and outside the first nickel silicide. In an embodiment of the present invention, the remaining nickel-platinum alloy is usually removed by wet etching. Step 23 corresponds to Figure 2 step S203 in, and the wet clean post RTA1 shown in the box of step S203 represents the wet etching process for removing the remaining nickel-platinum alloy, where RTA1 represents the first silicidation annealing process.

[0089] Figure 2 In, dot filling is used in the boxes of steps S201 to S203, indicating that the first type of FOUP is used to transport the wafer in steps S201 to S203. That is, after the wafer completes the corresponding process steps, it needs to be placed in the first type of FOUP, and then the first type of FOUP is transported to the machine equipment corresponding to the next process step and the next process is carried out. In each of steps S201 to S203, the same FOUP can be used, or different FOUPs can be used respectively, but it is necessary to ensure that the types of all FOUPs are the same, that is, all are of the first type.

[0090] Step three: Load the wafer into the second type of FOUP, and transport the wafer through the second type of FOUP to complete the following steps:

[0091] Use the PECVD process to grow the second dielectric layer 108. In the storage area, the second dielectric layer 108 is formed on the surface of the first nickel silicide, and the second dielectric layer 108 also seals the first trench and thus forms an air gap in the first trench.

[0092] In an embodiment of the present invention, the second dielectric layer 108 is undoped silica (USG).

[0093] Step three corresponds to Figure 2In step S204, PE-SiH4dep shown in the box of step S204 indicates that the second dielectric layer 108 is grown by PECVD process. PE represents PECVD, SiH4 represents that the silicon source gas is SiH4, dep represents deposition, and PE-SiH4 represents that the silicon dioxide formed by using SiH4 as the silicon source and PECVD process is the second dielectric layer 108.

[0094] Figure 2 In, the box of step S204 is filled with slashes, indicating that step S204 uses the second type of FOUP to carry the wafer.

[0095] Step Four: Load the wafer into the first type of FOUP, and carry the wafer through the first type of FOUP to complete the following steps:

[0096] Step 41: Perform a second silicidation annealing process, which converts the first nickel silicide into a second nickel silicide 107 with the molecular formula NiPtSi; the temperature of the second silicidation annealing process is higher than that of the first silicidation annealing process.

[0097] In the embodiment of the present invention, the second silicidation annealing process adopts rapid thermal annealing.

[0098] The temperature of the second silicidation annealing process is 400°C to 450°C.

[0099] Step 41 corresponds to Figure 2 step S205 in, and 2nd ANN shown in the box of step S205 represents the second silicidation annealing process.

[0100] Step 42: Perform a first wet cleaning process, which is a cleaning for replacing the FOUP. The structure of the first trench seal prevents the etching solution of the first wet cleaning process from entering the inside of the first trench, and thus prevents the etching solution of the second wet process from etching the inner surface of the first trench and causing the first gate structure 201 to tilt, thereby reducing the leakage between the word lines. Step 42 corresponds to Figure 2 step S206 in, and Wet clean for FOUP change shown in the box of step S206 represents the first wet cleaning process, that is, the cleaning for replacing the FOUP.

[0101] Figure 2In the figure, the boxes of steps S205 to S206 are filled with dots, indicating that steps S205 to S206 all use the first type of FOUP to carry the wafer. In each of steps S201 to S203 and S205 to S206, the same FOUP can be used, or different FOUPs can be used respectively, but it is only necessary to ensure that the types of all FOUPs are the same, that is, all are of the first type.

[0102] Step Five: Load the wafer into the second type of FOUP, and carry the wafer through the second type of FOUP to complete the following steps: perform a third annealing on the second dielectric layer 108.

[0103] Step Five corresponds to Figure 2 step S207 in the figure. The PE-SiH4ANN shown in the box of step S207 represents the third annealing, that is, the annealing of the second dielectric layer.

[0104] Figure 2 In the figure, the boxes of step S207 are filled with slashes, indicating that step S207 uses the second type of FOUP to carry the wafer. In each of steps S204 and S207, the same FOUP can be used, or different FOUPs can be used respectively, but it is only necessary to ensure that the types of all FOUPs are the same, that is, all are of the second type.

[0105] After that, the subsequent processes are continued, including the metal interconnection process. Since there are no technical problems related to the tilt of the first gate structure 201 in the subsequent processes, no detailed description is given in the specification of the present invention.

[0106] and Figure 1 relatively restrained, in the embodiment of the present invention Figure 2 In the corresponding process, the PECVD process is moved forward to before wet clean for FOUP change to form an Air gap in advance. The surface is protected by the second dielectric layer formed by PECVD, so that the clean after 2nd ANN will not penetrate into the trench, thus preventing problems such as high aspect ratio WL leaning, space reduction, and water vapor residue caused by clean, thereby reducing WL leakage and improving the yield.

[0107] After the gate structure of the NAND flash memory is formed in the embodiment of the present invention, during the process of self-aligning and forming nickel silicide on the top of the polysilicon control gate 105 of the memory cells in the storage area, after the first silicidation annealing process with a relatively low temperature is completed, instead of directly performing the second silicidation annealing process with a relatively high temperature, a second dielectric layer 108 is formed by PECVD growth. The second dielectric layer 108 is used to close the first trench between the first gate structures 201 of the memory cells and form an air gap inside. Then, the second silicidation annealing process for forming nickel silicide is performed. After that, the first wet cleaning process for replacing the FOUP is performed to prevent the etching solution of the first wet cleaning process from entering the inside of the first trench. Since the etching solution of the first wet cleaning process is likely to etch the inner surface that has undergone the second silicidation annealing process at a relatively high temperature, the present invention can prevent such etching from occurring, thereby preventing the first gate structure 201 from tilting. Therefore, the embodiment of the present invention can prevent the word lines formed by connecting the polysilicon control gates 105 of the memory cells in the storage area from tilting, thereby reducing the leakage between the word lines.

[0108] In addition, the embodiment of the present invention can be realized only by making corresponding adjustments to the process sequence, so the embodiment of the present invention will not increase additional process costs.

[0109] The present invention has been described in detail through specific embodiments above, but these do not constitute limitations to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A manufacturing method for reducing leakage between word lines of a NAND flash memory, characterized in that, Including the following steps: Step 1: Provide a semiconductor substrate on which a gate structure has been fabricated, the semiconductor substrate being a wafer; a plurality of memory cells are formed in the memory area of the flash memory, and the gate structure of each memory cell is a first gate structure, the first gate structure including a floating gate dielectric layer, a polysilicon floating gate, a control dielectric layer, and a polysilicon control gate formed in sequence on the surface of the semiconductor substrate; the polysilicon control gates of the memory cells in the same row are connected together and serve as word lines; A first trench is formed between the first gate structures, and a first dielectric layer is formed on the inner surface of the first trench; Step 2: Load the wafer into a first type of FOUP, and carry the wafer through the first type of FOUP to complete the following steps: Step 21: Deposit a nickel-platinum alloy, in the memory area, the nickel-platinum alloy covers the top surface of the polysilicon control gate and the surface of the first dielectric layer in the first trench; Step 22: Perform a first silicidation annealing process to generate a first nickel silicide, the first silicidation annealing process causing the nickel-platinum alloy and the silicon of the polysilicon control gate to react to form the first nickel silicide with the chemical formula Ni2PtSi; Step 23: Remove the unreacted remaining nickel-platinum alloy on the surface of the first nickel silicide and outside the first nickel silicide; Step 3: Load the wafer into a second type of FOUP, and carry the wafer through the second type of FOUP to complete the following steps: Grow a second dielectric layer by PECVD process, in the memory area, the second dielectric layer is formed on the surface of the first nickel silicide, and the second dielectric layer also seals the first trench and thus forms an air gap in the first trench; Step 4: Load the wafer into the first type of FOUP, and carry the wafer through the first type of FOUP to complete the following steps: Step 41: Perform a second silicidation annealing process, the second silicidation annealing process converts the first nickel silicide into a second nickel silicide with the chemical formula NiPtSi; the temperature of the second silicidation annealing process is higher than that of the first silicidation annealing process; Step 42: Perform a first wet cleaning process, the first wet cleaning process is a cleaning for replacing the FOUP, and the sealed structure of the first trench prevents the etching solution of the first wet cleaning process from entering the interior of the first trench, and thus prevents the etching solution of the first wet cleaning process from etching the inner surface of the first trench and causing the first gate structure to tilt, thereby reducing the leakage between the word lines; Step 5: Load the wafer into a second type of FOUP, and carry the wafer through the second type of FOUP to complete the following steps: Perform a third annealing on the second dielectric layer.

2. The manufacturing method for reducing leakage between word lines of a NAND flash memory as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

3. The manufacturing method for reducing leakage between word lines of a NAND flash memory according to claim 2, wherein: The first dielectric layer is an oxide layer.

4. The manufacturing method for reducing leakage between word lines of a NAND flash memory according to claim 3, characterized in that: The first dielectric layer is formed by thermally oxidizing the semiconductor substrate, the polysilicon floating gate, and the polysilicon control gate exposed on the inner surface of the first trench.

5. The manufacturing method for reducing leakage between word lines of a NAND flash memory as described in claim 1, wherein: In step one, the aspect ratio of the first trench is greater than or equal to 12:

1.

6. The manufacturing method for reducing leakage between word lines of a NAND flash memory as claimed in claim 1, wherein: In step 21, the nickel-platinum alloy is formed by a sputtering process.

7. The manufacturing method for reducing leakage between word lines of a NAND flash memory according to claim 5, characterized in that: In step 21, after forming the nickel-platinum alloy, there is also a step of forming a protective layer on the surface of the nickel-platinum alloy, and the protective layer prevents the nickel-platinum alloy from being oxidized; in step 23, the protective layer needs to be removed first and then the nickel-platinum alloy is removed.

8. The manufacturing method for reducing leakage between word lines of a NAND flash memory according to claim 7, characterized in that: The material of the protective layer includes TiN.

9. The manufacturing method for reducing leakage between word lines of a NAND flash memory as claimed in claim 8, wherein: The protective layer is formed by a sputtering process.

10. The manufacturing method for reducing leakage between word lines of a NAND flash memory as described in claim 1, characterized in that: The first silicidation annealing process in step 22 uses rapid thermal annealing.

11. The manufacturing method for reducing leakage between word lines of a NAND flash memory as described in claim 10, characterized in that: The temperature of the first silicidation annealing process is 200°C to 350°C.

12. The manufacturing method for reducing leakage between word lines of a NAND flash memory as claimed in claim 1, characterized in that: In step three, the second dielectric layer is undoped silicon dioxide.

13. The manufacturing method for reducing leakage between word lines of a NAND flash memory as described in claim 1, wherein: The second silicidation annealing process in step 41 uses rapid thermal annealing.

14. The manufacturing method for reducing leakage between word lines of a NAND flash memory according to claim 13, characterized in that: The temperature of the second silicidation annealing process is 400°C to 450°C.

15. The manufacturing method for reducing leakage between word lines of a NAND flash memory as claimed in claim 1, wherein: In step one, a selection transistor is also formed in the storage area, and the storage cells in the same column are all connected in series with the selection transistor.

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