Heterojunction bipolar transistor and method of making the same

Abstract

The application discloses a heterojunction bipolar transistor, comprising: a substrate; a channel layer formed on the substrate, the channel layer being formed with a downwardly recessed mesa; a barrier layer formed on a region of the channel layer without the mesa, the barrier layer being adapted to generate a two-dimensional electron gas layer by polarization in the channel layer; a p-type base region formed on a partial region of the barrier layer; an n-type emitter region formed on a partial region of the p-type base region; and a drain formed on the mesa of the channel layer, the drain being adapted to form an ohmic contact with the two-dimensional electron gas layer; wherein the p-type base region and the n-type emitter region form a heterojunction structure, the heterojunction structure being adapted to input a current to the channel layer through the barrier layer, and the two-dimensional electron gas layer being adapted to transmit the current to the drain. The application also discloses a manufacturing method of the heterojunction bipolar transistor.

Description

TECHNICAL FIELD

[0001] At least one embodiment of the present application relates to a semiconductor device, and more particularly, to a heterojunction bipolar transistor and a manufacturing method thereof. BACKGROUND

[0002] At present, the third generation semiconductor materials such as SiC and GaN are increasingly applied to power electronic devices due to their superior material properties compared to Si. GaN-based materials have wide application prospects in high-temperature, high-frequency and high-power fields due to their large band gap, high breakdown field, high carrier saturation velocity and strong polarization effect.

[0003] GaN high electron mobility transistor (HEMT) is a type of transistor based on the two-dimensional electron gas layer (2DEG) generated by polarization of GaN material, which is the core device of GaN-based power electronic devices and radio frequency, microwave amplifiers. Currently, many GaN manufacturers have launched power switches with voltage levels of 200V, 650V, 1200V and other voltage levels based on HEMT devices, and many HEMT radio frequency, microwave products have been released and put into use. However, HEMT devices have the problem of being difficult to realize common-off operation. SUMMARY

[0004] Therefore, the present application provides a heterojunction bipolar transistor (HBT) based on HEMT epitaxial structure, which forms a heterojunction bipolar transistor by etching or selective regrowth of the emitter, thereby solving the problem of HEMT devices being difficult to realize common-off operation.

[0005] The present application provides a heterojunction bipolar transistor, which comprises: a substrate; a channel layer formed on the substrate, the channel layer having a downwardly recessed mesa formed thereon; a barrier layer formed on a region of the channel layer where no mesa is formed, the barrier layer being adapted to generate a two-dimensional electron gas layer by polarization in the channel layer; a p-type base region formed on a part of the barrier layer; an n-type emitter region formed on a part of the p-type base region; a drain formed on the mesa of the channel layer, the drain being adapted to form an ohmic contact with the two-dimensional electron gas layer; an emitter electrode formed on the n-type emitter region; a collector formed on the drain; and a base formed on the p-type base region; wherein the p-type base region and the n-type emitter region form a heterojunction structure, the heterojunction structure being adapted to input current to the channel layer through the barrier layer, and the two-dimensional electron gas layer being adapted to transmit the current to the drain.

[0006] The present application also provides a manufacturing method of a heterojunction bipolar transistor, which is adapted to manufacture the heterojunction bipolar transistor as described above, and comprises:

[0007] Forming a channel layer, a barrier layer, a p-type base region and an n-type emitter region on a substrate in sequence; etching the n-type emitter region and the p-type base region to form a base mesa; etching the n-type emitter region to form an emitter mesa; forming a first dielectric mask layer on the barrier layer, the p-type base region and the n-type emitter region; etching the first dielectric mask layer, the barrier layer and the channel layer to form a mesa; forming a drain electrode on the mesa; and forming an emitter electrode on the n-type emitter region, a collector electrode on the drain electrode and a base electrode on the p-type base region.

[0008] The application further provides a manufacturing method of the heterojunction bipolar transistor, which is suitable for manufacturing the heterojunction bipolar transistor as described above, and comprises the following steps:

[0009] Forming a channel layer, a barrier layer and a p-type base region on a substrate in sequence; etching the p-type base region to form a base mesa; forming a second dielectric mask layer on the barrier layer and the p-type base region; etching the second dielectric mask layer, the barrier layer and the channel layer to form a mesa; forming a drain electrode on the mesa; forming a third dielectric mask layer on the p-type base region, the barrier layer and the drain electrode; etching the third dielectric mask layer to form an emitter regrowth window; wherein the emitter regrowth window is located on the p-type base region; forming an n-type emitter region on the emitter regrowth window; and forming an emitter electrode on the n-type emitter region, a collector electrode on the drain electrode and a base electrode on the p-type base region.

[0010] According to the heterojunction bipolar transistor provided by the above-mentioned embodiment of the application, the heterojunction structure formed by the p-type base region and the n-type emitter region can inject high-density current into the channel layer, the high mobility and high-density 2DEG generated by the polarization effect can better transmit the high-density current injected by the heterojunction structure and finally collect in the drain electrode, thereby reducing the on-resistance of the device.

[0011] According to the heterojunction bipolar transistor provided by the above-mentioned embodiment of the application, the heterojunction bipolar transistor is constructed based on a p-GaN gate HEMT structure, that is, the heterojunction bipolar transistor is formed on the p-GaN gate HEMT structure by etching or selectively regrowing an emitter, the heterojunction bipolar transistor has the advantages of high electron injection efficiency and current gain of the HBT device and the advantages of high mobility 2DEG of the HEMT device, and can realize normal-off operation without completely depleting the 2DEG of the p-GaN gate. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 FIG. 1 is a cross-sectional schematic view of a heterojunction bipolar transistor according to an embodiment of the application;

[0013] Figure 2 FIG. 2 is a flowchart of a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the application;

[0014] Figures 3(a)-3(j) A cross-sectional view of a fabrication process of a heterojunction bipolar transistor according to another embodiment of the present application;

[0015] Figure 4 A flow chart of a fabrication method of a heterojunction bipolar transistor according to another embodiment of the present application; and

[0016] Figures 5(a)-5(m) A cross-sectional view of a fabrication process of a heterojunction bipolar transistor according to another embodiment of the present application.

[0017] REFERENCE NUMERALS

[0018] 1 - substrate;

[0019] 2 - channel layer;

[0020] 21 - mesa;

[0021] 3 - barrier layer;

[0022] 4 - p-type base region;

[0023] 41 - base region mesa;

[0024] 5 - n-type emitter region;

[0025] 51 - emitter region mesa;

[0026] 6 - first dielectric mask layer;

[0027] 7 - drain;

[0028] 81 - emitter electrode;

[0029] 82 - collector;

[0030] 83 - base electrode;

[0031] 9 - second dielectric mask layer;

[0032] 10 - third dielectric mask layer;

[0033] 01 - first photoresist layer;

[0034] 011 - first region of the first photoresist layer;

[0035] 02 - second photoresist layer;

[0036] 021 - second region of the second photoresist layer;

[0037] 03 - third photoresist layer;

[0038] 031 - third region of the third photoresist layer;

[0039] 04 - fourth photoresist layer;

[0040] 041 - fourth region of the fourth photoresist layer;

[0041] 05 - fifth photoresist layer;

[0042] 051 - fifth region of the fifth photoresist layer;

[0043] 06 - sixth photoresist layer;

[0044] 061 - sixth region of the sixth photoresist layer. DETAILED DESCRIPTION

[0045] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the present application with specific examples and with reference to the drawings. However, the present application can be implemented in different forms, and should not be interpreted as limited to the examples presented here. On the contrary, these examples are provided to make the application thorough and complete, and to fully convey the scope of the present application to those skilled in the art. In the drawings, the sizes and relative sizes of the layers and regions can be exaggerated for clarity, and the same reference signs represent the same elements throughout.

[0046] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present application. The terms "comprise", "include", and the like as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0047] Therefore, the present application proposes a heterojunction bipolar transistor (HBT). The HBT device proposed by the present application is based on a p-GaN gate HEMT structure, which has the advantages of high mobility 2DEG of HEMT devices, and can also solve the problem of difficulty in realizing normally-off operation of HEMT devices.

[0048] In the related art, the main coupling method of HBT devices and HEMT devices is lateral coupling, that is, the epitaxial layers of HBT devices and HEMT devices are formed on the same substrate, and finally electrically isolated to form laterally arranged HBT devices and HEMT devices.

[0049] The HBT device provided by the application is longitudinally coupled with HBT epitaxial structure and HEMT epitaxial structure, which not only retains the characteristics and advantages of the two types of devices, but also improves the integration degree. The HBT device provided by the application is longitudinally coupled with HBT epitaxial structure and HEMT epitaxial structure, that is, the HBT device is formed on the p-GaN gate HEMT structure by etching or selective epitaxial growth of the emitter. The HBT device is turned on and off by the current-controlled transistor, which can solve the problem that the HEMT device is difficult to realize the normally-off operation. In addition, the HBT device provided by the application has a heterojunction structure formed by the p-type base region and the n-type emitter region. The heterojunction structure has current gain and high electron injection efficiency, so that the HBT device has higher current handling capability.

[0050] Figure 1 A cross-sectional view of a heterojunction bipolar transistor according to an embodiment of the application.

[0051] According to an exemplary embodiment of the application, the application provides a heterojunction bipolar transistor, as shown in Figure 1 , comprising:

[0052] a substrate 1; a channel layer 2 formed on the substrate 1, the channel layer 2 having a downwardly recessed mesa 21 formed thereon; a barrier layer 3 formed on a region of the channel layer 2 not having the mesa 21 formed thereon, the barrier layer 3 being adapted to polarize to generate a two-dimensional electron gas layer within the channel layer 2; a p-type base region 4 formed on a portion of the barrier layer 3; an n-type emitter region 5 formed on a portion of the p-type base region 4; a drain 7 formed on the mesa 21 of the channel layer 2, the drain 7 being adapted to form an ohmic contact with the two-dimensional electron gas layer; wherein the p-type base region 4 and the n-type emitter region 5 form a heterojunction structure, the heterojunction structure being adapted to input current to the channel layer 2 through the barrier layer 3, and the two-dimensional electron gas layer being adapted to transmit the current to the drain 7.

[0053] According to an embodiment of the application, the barrier layer 3 polarizes to generate and conduct a two-dimensional electron gas layer (2DEG) within the channel layer 2 by polarization effect, and the current generated by the heterojunction structure formed by the p-type base region 4 and the n-type emitter region 5 and injected through the p-type base region 4 can be collected in the drain 7 through the high-density 2DEG within the channel layer 2.

[0054] It should be noted that, Figure 1 the dashed line in the channel layer 2 represents a two-dimensional electron gas layer (2DEG).

[0055] According to an embodiment of the application, an emitter electrode 81 is formed on the n-type emitter region 5, a collector electrode 82 is formed on the drain 7, and a base electrode 83 is formed on the p-type base region 4.

[0056] According to an embodiment of the present application, the material of the heterojunction bipolar transistor includes an AlGaN / GaN material system, a GaN / InGaN material system, and an AlGaAs / GaAs material system.

[0057] According to an embodiment of the present application, the heterojunction bipolar transistor is of the AlGaN / GaN material system; the channel layer 2 includes unintentionally doped GaN or unintentionally doped AlGaN; the thickness of the channel layer 2 ranges from 500 nm to 6 μm, for example, can be 500 nm, 1 μm, 2 μm, 4 μm, or 6 μm; the p-type base region 4 includes GaN; the thickness of the p-type base region 4 ranges from 50 nm to 500 nm, for example, can be 50 nm, 100 nm, 200 nm, 300 nm, or 500 nm; and the n-type emitter region 5 includes AlGaN.

[0058] According to an embodiment of the present application, the heterojunction bipolar transistor is of the GaN / InGaN material system; the channel layer 2 includes unintentionally doped GaN or unintentionally doped AlGaN; the thickness of the channel layer 2 ranges from 500 nm to 6 μm, for example, can be 500 nm, 1 μm, 2 μm, 4 μm, or 6 μm; the p-type base region 4 includes In x Ga 1-x N, 0≤x≤0.45; the thickness of the p-type base region 4 ranges from 50 nm to 500 nm, for example, can be 50 nm, 100 nm, 200 nm, 300 nm, or 500 nm; and the n-type emitter region 5 includes AlGaN or GaN.

[0059] According to an embodiment of the present application, the heterojunction bipolar transistor is of the AlGaAs / GaAs material system; the channel layer 2 includes unintentionally doped GaAs; the thickness of the channel layer 2 ranges from 500 nm to 6 μm, for example, can be 500 nm, 1 μm, 2 μm, 4 μm, or 6 μm; the p-type base region 4 includes GaAs; the thickness of the p-type base region 4 ranges from 50 nm to 500 nm, for example, can be 50 nm, 100 nm, 200 nm, 300 nm, or 500 nm; and the n-type emitter region 5 includes AlGaAs.

[0060] According to an embodiment of the present application, the material of the drain 7 includes GaN or an alloy of GaN and a Ⅲ-Ⅴ group material.

[0061] Figure 2 A flow chart of a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present application. Figures 3(a)-3(j) A cross-sectional schematic diagram of a manufacturing process of a heterojunction bipolar transistor according to an embodiment of the present application.

[0062] According to an exemplary embodiment of the present application, the present application provides a manufacturing method of a heterojunction bipolar transistor, which refers toFigure 2 As shown, the steps S01-S07 are included.

[0063] In step S01, a channel layer 2, a barrier layer 3, a p-type base region 4 and an n-type emitter region 5 are sequentially formed on a substrate 1.

[0064] It should be noted that the embodiments of the present application are described by taking the AlGaN / GaN material system as an example.

[0065] According to the embodiments of the present application, referring to Fig. 3(a), the channel layer 2, the barrier layer 3, the p-type base region 4 and the n-type emitter region 5 are formed on the substrate 1 by using a metal organic compound chemical vapor deposition method or a molecular beam epitaxy method.

[0066] According to the embodiments of the present application, the substrate 1 includes one of the following: a Si substrate, a sapphire substrate, a SiC substrate and a GaN self-supporting substrate.

[0067] According to the embodiments of the present application, the channel layer 2 includes non-doped GaN or non-doped AlGaN; the thickness of the channel layer 2 is 500 nm-6 μm. The barrier layer 3 is non-doped AlGaN. The p-type base region 4 includes GaN; the thickness of the p-type base region 4 ranges from 50 nm to 500 nm. The doping concentration of the p-type base region 4 is 2×1018 cm-3-3×1018 cm-3. The n-type emitter region 5 includes AlGaN. 17 cm -3 -3×10 19 cm -3 The doping concentration can be a single value or a gradually changing concentration. The n-type emitter region 5 includes AlGaN.

[0068] In step S02, the n-type emitter region 5 and the p-type base region 4 are etched to form a base region mesa 41.

[0069] According to the embodiments of the present application, referring to Fig. 3(b), a first photoresist layer 01 is coated on the n-type emitter region 5, a first region 011 of the first photoresist layer 01 is exposed and developed to remove the photoresist of the first region 011 of the first photoresist layer 01. As shown in Fig. 3(c), taking the first photoresist layer 01 as a mask, the n-type emitter region 5 and the p-type base region 4 corresponding to the first region 011 of the first photoresist layer 01 are removed to form the base region mesa 41. After the base region mesa 41 is formed, the first photoresist layer 01 is removed.

[0070] According to the embodiments of the present application, the method of exposing and developing the first region 011 of the first photoresist layer 01 includes electron beam exposure, contact photolithography or step photolithography.

[0071] According to an embodiment of the present application, the size of the first region 011 of the first photoresist layer 01 is 10 nm-1 μm, which can be set according to the device performance and the size requirement of the base region mesa 41.

[0072] It should be noted that the first photoresist layer 01 is a positive photoresist, and the part irradiated by light in the positive photoresist can be dissolved in a photoresist developer, while the part not irradiated by light cannot be dissolved or is very slow to dissolve.

[0073] In step S03, the n-type emitter region 5 is etched to form the emitter region mesa 51.

[0074] According to an embodiment of the present application, referring to FIG. 3(d), the second photoresist layer 02 is formed on the n-type emitter region 5, and the second region 021 of the second photoresist layer 02 is exposed and developed to remove the photoresist of the second region 021 of the second photoresist layer 02. As shown in FIG. 3(e), the n-type emitter region 5 corresponding to the second region 021 of the second photoresist layer 02 is removed to form the emitter region mesa 51, with the second photoresist layer 02 as a mask. After the emitter region mesa 51 is formed, the second photoresist layer 02 is removed.

[0075] According to an embodiment of the present application, the size of the second region 021 of the second photoresist layer 02 is 10 nm-1 μm, which can be set according to the device performance and the size requirement of the emitter region mesa 51.

[0076] In step S04, the first dielectric mask layer 6 is formed on the barrier layer 3, the p-type base region 4, and the n-type emitter region 5.

[0077] According to an embodiment of the present application, referring to FIG. 3(f), the thickness of the first dielectric mask layer 6 is 50 nm-500 nm, for example, the thickness can be 50 nm, 100 nm, 200 nm, 300 nm, or 500 nm.

[0078] According to an embodiment of the present application, the first dielectric mask layer 6 includes at least one of an inorganic dielectric mask layer and a metal dielectric mask layer, the inorganic dielectric mask layer includes at least one of SiO2 and SiN x , and the metal dielectric mask layer includes at least one of W and Cr.

[0079] According to an embodiment of the present application, the first dielectric mask layer 6 is formed by at least one of vapor deposition, evaporation, atomic layer deposition, and sputtering, for example, SiO2 can be deposited as the first dielectric mask layer 6 by plasma chemical vapor deposition.

[0080] In step S05, the first dielectric mask layer 6, the barrier layer 3, and the channel layer 2 are etched to form the mesa 21.

[0081] According to the embodiment of the present application, referring to Fig. 3(g), a third photoresist layer 03 is coated on the first dielectric mask layer 6, and a third region 031 of the third photoresist layer 03 is exposed and developed to remove the photoresist of the third region 031 of the third photoresist layer 03. As shown in Fig. 3(h), the first dielectric mask layer 6, the barrier layer 3 and the channel layer 2 corresponding to the third region 031 of the third photoresist layer 03 are removed to form a mesa 21 which is recessed downward. After the mesa 21 is formed, the third photoresist layer 03 is removed.

[0082] According to the embodiment of the present application, the size of the third region 031 of the third photoresist layer 03 can be set according to the device performance and the size requirement of the mesa 21.

[0083] According to the embodiment of the present application, the method of etching the first dielectric mask layer 6, the barrier layer 3 and the channel layer 2 includes dry plasma etching, wet etching or reactive plasma etching.

[0084] In step S06, a drain 7 is formed on the mesa 21.

[0085] According to the embodiment of the present application, referring to Fig. 3(i), the drain 7 is formed on the mesa 21, and the method of forming the drain 7 includes metal organic compound chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HVPE).

[0086] According to the embodiment of the present application, the material of the drain 7 includes GaN or an alloy of GaN and Ⅲ-Ⅴ group material; for example, the material of the drain 7 can be an alloy of GaN and InN or an alloy of GaN and AlN. The drain 7 is doped with a donor impurity, and the donor impurity includes but is not limited to Si or Ge.

[0087] According to the embodiment of the present application, the distance between the p-type base region 4 and the drain 7 can be adjusted; by adjusting the distance between the p-type base region 4 and the drain 7, high breakdown voltage can be achieved.

[0088] In step S07, an emitter electrode 81 is formed on the n-type emitter region 5, a collector electrode 82 is formed on the drain 7, and a base electrode 83 is formed on the p-type base region 4.

[0089] According to the embodiment of the present application, referring to Fig. 3(j), the emitter electrode 81 is formed on the n-type emitter region 5, the collector electrode 82 is formed on the drain 7, and the base electrode 83 is formed on the p-type base region 4.

[0090] According to the embodiment of the present application, the emitter electrode 81, the collector electrode 82 and the base electrode 83 are a multi-layer metal system, and the multi-layer metal system includes but is not limited to a stack of Ti, Ni, Al and Au.

[0091] According to an embodiment of the present application, the p-type base region 4 and the n-type emitter region 5 form a heterojunction structure, which enables the p-type base region 4 and the n-type emitter region 5 to have current gain and higher electron injection efficiency.

[0092] According to an embodiment of the present application, the heterojunction bipolar transistor provided by the above embodiment is made based on the epitaxial layer structure of a p-GaN gate HEMT device; compared with the traditional heterojunction bipolar transistor, the high-doped collector region (n + -GaN) for conducting current is replaced by 2DEG with higher electron concentration and mobility.

[0093] According to an embodiment of the present application, the heterojunction structure formed by the p-type base region 4 and the n-type emitter region 5 can inject high-density current into the channel layer 2, and the high-mobility and high-density 2DEG generated by the polarization effect can better transmit the high-density current injected by the heterojunction structure and finally be collected at the drain, thereby reducing the on-resistance of the device.

[0094] According to an embodiment of the present application, the heterojunction bipolar transistor provided by the above embodiment does not need to completely deplete 2DEG by the p-GaN gate to realize the normally-off operation. Specifically, the traditional HEMT device is realized by a common-source common-gate (Cascode GaN HEMT) or a p-GaN gate cap layer to realize the enhancement-mode HEMT, while the p-GaN layer in the HBT device provided by the above embodiment can realize the normally-off device without completely depleting 2DEG, because the electrons of the traditional HEMT device enter the drain from the source via the channel layer, and the gate controls the turn-on and turn-off of the current by the field effect; the electrons of the HBT device provided by the above embodiment are provided by the emitter region, and the turn-on and turn-off of the current are controlled by the current of the base region; by replacing the field control with the current control, the HBT device provided by the above embodiment has higher current processing capacity and higher transconductance.

[0095] According to an embodiment of the present application, the heterojunction bipolar transistor provided by the above embodiment combines the structural advantages of HBT and HEMT devices, and simplifies the integration difficulty of related devices.

[0096] Figure 4 A flowchart of a manufacturing method of a heterojunction bipolar transistor according to another embodiment of the present application. Figures 5(a)-5(m) A cross-sectional schematic diagram of a manufacturing process of a heterojunction bipolar transistor according to another embodiment of the present application.

[0097] According to an exemplary embodiment provided by the present application, the present application provides a manufacturing method of a heterojunction bipolar transistor, which, as shown in Figure 4 Fig. 1, includes steps S01-S09.

[0098] In step S01, a channel layer 2, a barrier layer 3, and a p-type base region 4 are sequentially formed on a substrate 1.

[0099] In step S02, the p-type base region 4 is etched to form a base region mesa 41.

[0100] According to an embodiment of the present application, referring to Figures 5(a)-5(c) As shown in the figure, a fourth photoresist layer 04 is formed on the p-type base region 4, and a fourth region 041 of the fourth photoresist layer 04 is exposed and developed to remove the photoresist of the fourth region 041 of the fourth photoresist layer 04. The p-type base region 4 corresponding to the fourth region 041 of the fourth photoresist layer 04 is removed to form the base region mesa 41. After the base region mesa 41 is formed, the fourth photoresist layer 04 is removed.

[0101] In step S03, a second dielectric mask layer 9 is formed on the barrier layer 3 and the p-type base region 4.

[0102] In step S04, the second dielectric mask layer 9, the barrier layer 3, and the channel layer 2 are etched to form a mesa 21.

[0103] According to an embodiment of the present application, referring to Figures 5(d)-5(f) As shown in the figure, a fifth photoresist layer 05 is coated on the second dielectric mask layer 9, and a fifth region 051 of the fifth photoresist layer 05 is exposed and developed to remove the photoresist of the fifth region 051 of the fifth photoresist layer 05. The second dielectric mask layer 9, the barrier layer 3, and the channel layer 2 corresponding to the fifth region 051 of the fifth photoresist layer 05 are removed to form a downwardly recessed mesa 21. After the mesa 21 is formed, the fifth photoresist layer 05 is removed.

[0104] In step S05, a drain 7 is formed on the mesa 21.

[0105] In step S06, a third dielectric mask layer 10 is formed on the p-type base region 4, the barrier layer 3, and the drain 7.

[0106] According to an embodiment of the present application, referring to Figures 5(g)-5(h) As shown in the figure, the drain 7 is formed on the mesa 21. The third dielectric mask layer 10 is formed on the p-type base region 4, the barrier layer 3, and the drain 7.

[0107] In step S07, the third dielectric mask layer 10 is etched to form an emission region regrowth window, and the emission region regrowth window is located on the p-type base region 4.

[0108] According to an embodiment of the present application, referring to Figures 5(i)-5(j)As shown, a sixth photoresist layer 06 is coated on the third dielectric mask layer 10. The sixth region 061 of the sixth photoresist layer 06 is exposed and developed to remove the photoresist from the sixth region 061. Using the sixth photoresist layer 06 as a mask, the third dielectric mask layer 10 corresponding to the sixth region 061 of the sixth photoresist layer 06 is removed to form an emitter region regrowth window. After forming the emitter region regrowth window, the sixth photoresist layer 06 is removed.

[0109] In step S08, an n-type emitter region 5 is formed on the emitter regrowth window.

[0110] According to an embodiment of the present invention, referring to FIG5(k), the method for forming an n-type emitter region 5 on the emitter regeneration window includes metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0111] In step S09, an emitter electrode 81 is formed on the n-type emitter region 5, a collector electrode 82 is formed on the drain electrode 7, and a base electrode 83 is formed on the p-type GaN base region 4.

[0112] According to an embodiment of the present invention, referring to FIG5(m), the third dielectric mask layer 10 is removed, an emitter electrode 81 is formed on the n-type emitter region 5, a collector electrode 82 is formed on the drain electrode 7, and a base electrode 83 is formed on the p-type base region 4.

[0113] According to an embodiment of the present invention, reference Figure 2 The fabrication method shown first forms an epitaxial wafer with a complete HBT device epitaxial structure, including a p-type base region 4 and an n-type emitter region 5. Then, an etching method is used to form the base region mesas and emitter region mesas, followed by etching to obtain the emitter region, thus simplifying the emitter region fabrication process. (Reference) Figure 4 The fabrication method shown effectively avoids damage to the p-type base region 4 caused by the etching process by selectively growing the n-type emitter region 5, so as to better achieve ohmic contact between the p-type base region 4 and the base electrode 83.

[0114] According to the heterojunction bipolar transistor provided by the above embodiments of the present invention, the heterojunction structure formed by the p-type base region and the n-type emitter region can inject high-density current into the channel layer. The high mobility and high density of the 2DEG generated by the polarization effect can better transmit the high-density current injected into the heterojunction structure and finally collect it at the drain, thereby reducing the on-resistance of the device.

[0115] According to the heterojunction bipolar transistor provided by the above-mentioned embodiment of the present application, the heterojunction bipolar transistor is based on a p-GaN gate HEMT structure, and is formed on the p-GaN gate HEMT structure by etching or selective epitaxial growth of an emitter, so that the heterojunction bipolar transistor has the advantages of both HBT and HEMT, i.e., high electron injection efficiency and current gain of HBT and high mobility of 2DEG of HEMT, and the heterojunction bipolar transistor is controlled by a base region current to turn on and turn off the current, and can realize normal-off operation without complete depletion of 2DEG of the p-GaN gate.

[0116] According to the manufacturing method of the heterojunction bipolar transistor provided by the above-mentioned embodiment of the present application, the HBT epitaxial structure and the HEMT epitaxial structure are coupled longitudinally, so that the characteristics and advantages of the two types of devices are retained, the integration degree is improved, and the integration difficulty of related devices is simplified.

[0117] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., are used to modify the corresponding elements, and do not mean that the elements have any ordinal number, or represent the order of one element and another element, or the order of the manufacturing method. The ordinal numbers are used only to distinguish one element with a certain name from another element with the same name.

[0118] The above-mentioned specific embodiments further illustrate the purpose, technical solutions and advantages of the present application. It should be understood that the above-mentioned embodiments are only specific embodiments of the present application, and are not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A heterojunction bipolar transistor, characterized by, The application relates to a heterojunction bipolar transistor, comprising: a substrate (1); a channel layer (2) formed on the substrate (1), wherein a downwardly recessed mesa (21) is formed on the channel layer (2); a barrier layer (3) formed on a region of the channel layer (2) not formed with the mesa (21), wherein the barrier layer (3) is suitable for polarizing a two-dimensional electron gas layer in the channel layer (2); a p-type base region (4) formed on a partial region of the barrier layer (3); an n-type emitter region (5) formed on a partial region of the p-type base region (4); a drain (7) formed on the mesa (21) of the channel layer (2), wherein the drain (7) is suitable for forming an ohmic contact with the two-dimensional electron gas layer; wherein the p-type base region (4) and the n-type emitter region (5) form a heterojunction structure, the heterojunction structure is suitable for inputting a current to the channel layer (2) through the barrier layer (3), and the two-dimensional electron gas layer is suitable for transmitting the current to the drain (7).

2. The heterojunction bipolar transistor of claim 1, wherein An emitter electrode (81) is formed on the n-type emitter region (5), a collector (82) is formed on the drain (7), and a base electrode (83) is formed on the p-type base region (4).

3. The heterojunction bipolar transistor of claim 1, wherein The heterojunction bipolar transistor is an AlGaN / GaN material system; The channel layer (2) comprises unintentionally doped GaN or unintentionally doped AlGaN; The thickness of the channel layer (2) ranges from 500 nm to 6 mu m; The p-type base region (4) comprises GaN; The thickness of the p-type base region (4) ranges from 50 nm to 500 nm; The n-type emitter region (5) comprises AlGaN.

4. The heterojunction bipolar transistor of claim 1, wherein The heterojunction bipolar transistor is a GaN / InGaN material system; The channel layer (2) comprises unintentionally doped GaN or unintentionally doped AlGaN; The thickness of the channel layer (2) ranges from 500 nm to 6 mu m; The p-type base region (4) comprises In x Ga 1-x N, 0≤x≤0.45; The thickness of the p-type base region (4) ranges from 50 nm to 500 nm; The n-type emitter region (5) comprises AlGaN or GaN.

5. The heterojunction bipolar transistor of claim 1, wherein The heterojunction bipolar transistor is an AlGaAs / GaAs material system; The channel layer (2) comprises unintentionally doped GaAs; The thickness of the channel layer (2) ranges from 500 nm to 6 mu m; The p-type base region (4) comprises GaAs; The thickness of the p-type base region (4) ranges from 50 nm to 500 nm; The n-type emitter region (5) comprises AlGaAs.

6. A method of manufacturing a heterojunction bipolar transistor, which is suitable for manufacturing the heterojunction bipolar transistor according to any one of claims 1 to 5, characterized by, The application further relates to a manufacturing method of the heterojunction bipolar transistor, comprising the following steps: forming a channel layer (2), a barrier layer (3), a p-type base region (4) and an n-type emitter region (5) on a substrate (1) in sequence; etching the n-type emitter region (5) and the p-type base region (4) to form a base region mesa (41); etching the n-type emitter region (5) to form an emitter region mesa (51); forming a first dielectric mask layer (6) on the barrier layer (3), the p-type base region (4) and the n-type emitter region (5); etching the first dielectric mask layer (6), the barrier layer (3) and the channel layer (2) to form a mesa (21); Forming a drain (7) on the mesa (21); and Forming an emitter electrode (81) on the n-type emitter region (5), forming a collector (82) on the drain (7), and forming a base electrode (83) on the p-type base region (4).

7. The method of manufacturing according to claim 6, wherein, The method for forming the first dielectric mask layer (6) on the barrier layer (3), the p-type base region (4), and the n-type emitter region (5) comprises one of the following: vapor deposition, evaporation, atomic layer deposition, sputtering; The method for etching the first dielectric mask layer (6), the barrier layer (3), and the channel layer (2) comprises dry plasma etching, wet etching, or reactive plasma etching.

8. The method of manufacturing according to claim 6, wherein, The method for forming the drain (7) on the mesa (21) comprises one of the following: metal organic chemical vapor deposition, molecular beam epitaxy, and pulsed laser deposition.

9. The method of claim 6, wherein, The first dielectric mask layer (6) comprises at least one of the following: an inorganic dielectric mask layer and a metal dielectric mask layer; The material of the inorganic medium mask layer comprises at least one of SiO2, SiN x ; The material of the metal dielectric mask layer comprises at least one of the following: W and Cr.

10. A method of fabricating a heterojunction bipolar transistor, suitable for fabricating a heterojunction bipolar transistor according to any one of claims 1 to 5, characterized in that Comprise: Forming a channel layer (2), a barrier layer (3), and a p-type base region (4) on a substrate (1) in sequence; Etching the p-type base region (4) to form a base region mesa (41); Forming a second dielectric mask layer (9) on the barrier layer (3) and the p-type base region (4); Etching the second dielectric mask layer (9), the barrier layer (3), and the channel layer (2) to form a mesa (21); Forming a drain (7) on the mesa (21); Forming a third dielectric mask layer (10) on the p-type base region (4), the barrier layer (3), and the drain (7); Etching the third dielectric mask layer (10) to form an emitter region regrowth window; wherein the emitter region regrowth window is located on the p-type base region (4); Forming an n-type emitter region (5) on the emitter region regrowth window; and Forming an emitter electrode (81) on the n-type emitter region (5), forming a collector (82) on the drain (7), and forming a base electrode (83) on the p-type base region (4).

11. The method of manufacturing according to claim 10, wherein, The method for forming the drain (7) on the mesa (21) comprises one of the following: metal organic chemical vapor deposition, molecular beam epitaxy, and pulsed laser deposition.

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