A driving method of SiC MOSFET

Abstract

The present invention discloses a driving method of SiC MOSFET, belonging to the field of power electronics technology. The driving method comprises: inputting a signal into a modulation and demodulation circuit to realize electrical isolation of the circuit and generate a control signal; inputting a control signal into a logic control circuit to logically combine the control signal with the fault signal output by the short-circuit protection circuit to generate a driving signal; inputting the output signal of the logic control circuit and the drain output signal of the SiC MOSFET into the short-circuit protection circuit to output the fault signal to the logic control circuit; inputting a driving signal into a power amplifier circuit to output an enhanced driving signal; and inputting an enhanced driving signal into a Miller clamp circuit to suppress the crosstalk spikes generated by the opening and closing of the bridge arm circuit of the SiC MOSFET. The present invention can effectively suppress the crosstalk phenomenon, and can effectively protect the SiC MOSFET in the case of a sudden short circuit phenomenon.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a driving method of a SiC MOSFET. Background Art

[0002] In recent years, with the rapid development of the global new energy industry, power electronic devices have been widely used in electric vehicles, photovoltaic power generation, and aerospace, and other fields, which puts forward high reliability and high efficiency requirements for power electronic devices. The third-generation wide bandgap power devices such as silicon carbide SiC are developing rapidly, and they will surely attract widespread attention from researchers due to their excellent performance. From the current level of device development, SiC materials are more suitable for high-power power electronic devices, such as photovoltaic inverters and smart grids. Compared with traditional high-power Si IGBTs, SiC MOSFETs are more resistant to high voltages and have high switching speeds that Si IGBTs do not have. However, as the switching speed of SiC MOSFETs increases, the bridge circuit is more affected by parasitic parameters, and the crosstalk phenomenon becomes more serious, which restricts the superior performance of SiC MOSFETs. At the same time, there is also the problem of insufficient reliability. Summary of the invention

[0003] In view of the above problems, the present invention proposes a driving method for SiC MOSFET, which can effectively suppress the crosstalk phenomenon and effectively protect the SiC MOSFET in the event of a sudden short circuit.

[0004] In order to achieve the above object, the present invention proposes a driving method of SiC MOSFET, characterized in that: it comprises a SiC MOSFET driving circuit, the driving circuit comprises a modulation and demodulation circuit, a logic control circuit, a power amplifier circuit, a Miller clamp circuit, a short-circuit protection circuit, a first power supply, a second power supply and a third power supply;

[0005] The driving method comprises the following steps:

[0006] (1) Generating a control signal: The input signal PWM is input into the modulation and demodulation circuit to achieve electrical isolation of the circuit and generate a control signal;

[0007] (2) generating a driving signal: the control signal is input into the logic control circuit, and is logically combined with the fault signal output by the short-circuit protection circuit to generate a driving signal;

[0008] (3) Short-circuit protection: The output signal of the logic control circuit and the drain output signal of the SiC MOSFET are input into the short-circuit protection circuit, which detects the short-circuit fault and outputs a fault signal to the logic control circuit;

[0009] (4) Driving signal enhancement: the driving signal is input into the power amplifier circuit to enhance the driving capability of the driving signal and output an enhanced driving signal;

[0010] (5) Crosstalk suppression: The enhanced drive signal is input into the Miller clamp circuit to suppress the crosstalk spikes generated by the opening and closing of the bridge arm circuit of the SiC MOSFET, thereby controlling the opening and closing of the SiC MOSFET.

[0011] Further, the modulation and demodulation circuit includes: a first NOT gate, a second NOT gate, a third NOT gate, a first Schmitt trigger, a second Schmitt trigger, a first pulse transformer, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor and a third capacitor, wherein:

[0012] The input end of the first NOT gate is connected to the input signal input end and the first end of the second capacitor respectively, the output end of the first NOT gate is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the first end of the first resistor and the input end of the second NOT gate respectively, the second end of the second capacitor is connected to the first end of the second resistor and the input end of the third NOT gate respectively, the output ends of the second NOT gate and the third NOT gate are connected to the first and second ends of the first pulse transformer respectively, and the second ends of the first resistor and the second resistor are both connected to the reference ground of the input signal;

[0013] The positive electrode of the second power supply is connected to the first end of the third resistor, the second end of the third resistor is respectively connected to the third end of the first pulse transformer and the input end of the first Schmitt trigger, the first Schmitt trigger and the second Schmitt trigger are connected in series, the output end of the second Schmitt trigger is connected to the first input end of the logic control circuit, the fourth end of the first pulse transformer is respectively connected to the first end of the fourth resistor and the first end of the third capacitor, and the second end of the fourth resistor and the second end of the third capacitor are both connected to the positive electrode of the first power supply;

[0014] The modulation and demodulation circuit can electrically isolate the input signal, and capture the rising edge and falling edge of the input signal through the modulation circuit at the left end of the first pulse transformer, generate a positive pulse signal when the rising edge of the input signal is captured, and generate a negative pulse signal when the falling edge of the input signal is captured. After the output positive and negative pulse signals are isolated and transmitted by the first pulse transformer, the input signal is restored through the demodulation circuit on the right side of the first pulse transformer;

[0015] When there is no positive or negative pulse signal at the third or fourth end of the first pulse transformer, the magnitude relationship between the third resistor and the fourth resistor is set so that the input voltage of the first Schmitt trigger is between its positive and negative thresholds, and when the positive or negative pulse signal is generated at the first or second end of the first pulse transformer, the first Schmitt trigger outputs a low or high level signal, and reverse processing is performed by the second Schmitt trigger to restore the input signal and generate a control signal;

[0016] The differential pulse generating circuit composed of the first capacitor and the first resistor, the second capacitor and the second resistor, has a time constant that can determine the pulse width of the positive and negative pulse signals respectively.

[0017] Further, the logic control circuit includes: a first AND gate and a fourth NOT gate;

[0018] The first input end of the first AND gate is connected to the output end of the short-circuit protection circuit, the second input end is respectively connected to the output end of the modulation and demodulation circuit and the input end of the fourth NOT gate, the output end is connected to the input end of the power amplifier circuit, and the output end of the fourth NOT gate is connected to the second input end of the short-circuit protection circuit.

[0019] Furthermore, the power amplifier circuit includes: a fifth resistor, a sixth resistor, a first switch tube, a second switch tube, and a third switch tube;

[0020] The second end of the first switch tube is connected to the first output end of the logic control circuit, the first end thereof is respectively connected to the first end of the fifth resistor, the second end of the second switch tube and the second end of the third switch tube, the third end of the first switch tube is connected to the positive electrode of the first power supply, the second end of the fifth resistor is connected to the positive electrode of the third power supply, the first end of the third switch tube is connected to the positive electrode of the third power supply, the third end thereof is respectively connected to the first end of the sixth resistor and the first end of the second switch tube, the third end of the second switch tube is connected to the positive electrode of the first power supply, and the second end of the sixth resistor is connected to the gate of the SiC MOSFET;

[0021] The power amplifier circuit can realize level shifting and power amplification to improve the gate driving capability. When the circuit is working normally, when the driving signal is at a high level, the first switch tube and the third switch tube are turned on, thereby injecting current into the SiC MOSFET and providing a positive driving voltage; when the driving signal is at a low level, the second switch tube is turned on, thereby extracting current from the SiC MOSFET and providing a negative driving voltage.

[0022] Further, the Miller clamp circuit includes: a first comparator, a seventh resistor, an eighth resistor, a fourth capacitor and a fourth switch tube;

[0023] The first end of the eighth resistor is connected to the gate of the SiC MOSFET, the seventh resistor and the eighth resistor are connected in series, the second end of the seventh resistor is connected to the positive electrode of the first power supply, the fourth capacitor is connected in parallel with the seventh resistor, the negative input end of the first comparator is connected to the second end of the eighth resistor, the positive input end of the first comparator is connected to the reference ground of the power circuit, the output end of the first comparator is connected to the second end of the fourth switch tube, the first end of the fourth switch tube is connected to the gate of the SiC MOSFET, and the third end of the fourth switch tube is connected to the positive electrode of the first power supply;

[0024] The Miller clamp circuit turns on the fourth switch tube and clamps the gate voltage of the SiC MOSFET at the first power supply voltage when it is detected that the voltage at the negative input terminal of the first comparator is less than the reference zero potential of the power circuit, until a positive drive voltage signal arrives, turning off the fourth switch tube.

[0025] Further, the short-circuit protection circuit includes: a second comparator, a fifth switch tube, a fifth capacitor, a first diode, a second diode, a third diode, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor and a thirteenth resistor;

[0026] The first diode, the second diode, the tenth resistor and the ninth resistor are connected in series, the cathode of the first diode is connected to the drain of the SiC MOSFET, the second end of the ninth resistor is connected to the positive electrode of the third power supply, the second end of the fifth switch tube is connected to the second output end of the logic control circuit, the third end thereof and the second end of the fifth capacitor and the anode of the third diode are connected to the positive electrode of the first power supply, the first end thereof and the first end of the fifth capacitor, the cathode of the third diode, and the negative input end of the second comparator are connected to the midpoint of the ninth resistor and the tenth resistor, the eleventh resistor and the twelfth resistor are connected in series, the first end of the twelfth resistor is connected to the positive electrode of the third power supply, the second end of the eleventh resistor is connected to the positive electrode of the first power supply, the positive input end of the second comparator is connected to the midpoint of the eleventh resistor and the twelfth resistor, the output end thereof is respectively connected to the first end of the thirteenth resistor and the second input end of the logic drive circuit, and the second end of the thirteenth resistor is connected to the positive electrode of the second power supply;

[0027] The short-circuit protection circuit is used to detect a short-circuit fault and output a fault signal to turn off the drive signal. When the control signal is a low-level signal, the fifth switch is turned on, the input voltage clamp of the negative input terminal of the second comparator is located at the voltage of the first power supply, and the fifth capacitor is discharged. After passing through the logic control circuit, the drive signal is still a low-level signal; when the control signal is a high-level signal, the fifth switch is turned off, and the SiC MOSFET is turned on under normal working conditions. The third power supply, the ninth resistor, the tenth resistor, the first diode, the second diode and the SiC MOSFET form a closed loop. If a short circuit occurs, the voltage at the negative input terminal of the second comparator is greater than the reference voltage at its positive input terminal, and the fault signal is generated, so that the drive signal is turned off;

[0028] In the short-circuit protection circuit, when the control signal is a low-level signal, the first diode acts as a reverse blocking protection circuit due to the high voltage at the drain of the SiC MOSFET. In the case of a short circuit, the third diode prevents the reverse input terminal voltage of the second comparator from being too high, thereby playing a protective role.

[0029] Furthermore, the first diode is a silicon carbide diode or a fast recovery diode, the second diode and the third diode are Zener diodes, the first switch tube, the second switch tube, the fourth switch tube, and the fifth switch tube are all N-channel MOSFETs, and the third switch tube is a P-channel MOSFET.

[0030] Furthermore, the power supply voltage of all logic devices in the right circuit of the third and fourth ends of the first pulse transformer uses the first power supply voltage as a reference.

[0031] Furthermore, the voltage value of the first power supply is a negative voltage relative to the negative pole of the input power supply of the power circuit.

[0032] Furthermore, negative electrodes of the first power supply, the second power supply and the third power supply are connected to a reference ground of the power circuit.

[0033] Beneficial effects of the present invention:

[0034] The narrow pulse modulation adopted by the present invention can reduce the size of the transformer. The present invention also has Miller clamping protection, which is always clamped at the cut-off negative voltage before positive crosstalk and after negative crosstalk, and can also provide short-circuit protection function, thereby improving system reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1This is a structural block diagram of a driving method of a SiC MOSFET according to an embodiment of the present invention;

[0036] Figure 2 Schematic diagram of a driving circuit of a SiC MOSFET according to an embodiment of the present invention.

[0037] Wherein: 1. modulation and demodulation circuit, 2. logic control circuit, 3. power amplifier circuit, 4. Miller clamp circuit, 5. and short-circuit protection circuit; 01. first NOT gate, 02. second NOT gate, 03. third NOT gate, 04. first Schmitt trigger, 05. second Schmitt trigger, 06. first AND gate, 07. fourth NOT gate, 08. first comparator, 09. second comparator, R1. first resistor, R2. second resistor, R3. third resistor, R4. fourth resistor, R5. fifth resistor, R6. sixth resistor, R7. seventh resistor, R8. eighth resistor, R9. ninth resistor, R 10 , the tenth resistor, R 11 11th resistor, R 12 , the twelfth resistor, R 13 , the thirteenth resistor, C1, the first capacitor, C2, the second capacitor, C3, the third capacitor, C4, the fourth capacitor, C5, the fifth capacitor, S1, the first switch tube, S2, the second switch tube, S3, the third switch tube, S4, the fourth switch tube, S5, the fifth switch tube, D1, the first diode, D2, the second diode, D3, the third diode, U1, the first power supply, U2, the second power supply, U3, the third power supply. DETAILED DESCRIPTION

[0038] The present embodiment is described in detail below, and examples of the embodiment are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0039] A driving method of a SiC MOSFET according to the present embodiment is described below with reference to the accompanying drawings.

[0040] like Figure 1 As shown, a structural block diagram of the driving method is given.

[0041] The driving circuit is connected to the input signal input terminal and the power circuit respectively, and comprises: a modulation and demodulation circuit 1, a logic control circuit 2, a power amplifier circuit 3, a Miller clamp circuit 4 and a short circuit protection circuit 5.

[0042] An embodiment of the present invention provides a driving method for a SiC MOSFET, comprising the following steps:

[0043] S101, generating a control signal: inputting a PWM signal into the modulation and demodulation circuit to achieve electrical isolation of the circuit and generate a control signal;

[0044] Specifically, Figure 2 As shown, the modulation and demodulation circuit 1 includes: a first NOT gate 01, a second NOT gate 02, a third NOT gate 03, a first Schmitt trigger 04, a second Schmitt trigger 05, a first pulse transformer T1, a first power supply U1, a second power supply U2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2 and a third capacitor C3, wherein,

[0045] The input end of the first NOT gate 01 is respectively connected to the input signal input end and the first end of the second capacitor C2, and the output end thereof is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is respectively connected to the first end of the first resistor R1 and the input end of the second NOT gate 02, the second end of the second capacitor C2 is respectively connected to the first end of the second resistor R2 and the input end of the third NOT gate 03, the output ends of the second NOT gate 02 and the third NOT gate 03 are respectively connected to the first and second ends of the first pulse transformer T1, and the second ends of the first resistor R1 and the second resistor R2 are both connected to the reference ground GND1 of the input signal;

[0046] The positive electrode of the second power supply U2 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is respectively connected to the third end of the first pulse transformer T1 and the input end of the first Schmitt trigger 04, the first Schmitt trigger 04 and the second Schmitt trigger 05 are connected in series, the output end of the second Schmitt trigger 05 is connected to the first input end of the logic control circuit 2, the fourth end of the first pulse transformer T1 is respectively connected to the first end of the fourth resistor R4 and the first end of the third capacitor C3, the second end of the fourth resistor R4 and the second end of the third capacitor C3 are both connected to the positive electrode of the first power supply U1, and the negative electrodes of the first power supply U1 and the second power supply U2 are connected to the reference ground GND2 of the power circuit;

[0047] The modulation and demodulation circuit 1 can electrically isolate the input PWM signal, and capture the rising edge and falling edge of the input PWM signal through the modulation circuit at the left end of the first pulse transformer T1, generate a positive pulse signal when the rising edge of the input PWM signal is captured, and generate a negative pulse signal when the falling edge of the input PWM signal is captured. After the output positive and negative pulse signals are isolated and transmitted by the first pulse transformer T1, the input PWM signal is restored through the demodulation circuit on the right side of the first pulse transformer T1;

[0048] When there is no positive or negative pulse signal at the third and fourth terminals of the first pulse transformer T1, the size relationship between the third resistor R3 and the fourth resistor R4 is set so that the input terminal voltage of the first Schmitt trigger 04 is between its positive and negative thresholds. When positive or negative pulse signals are generated at the first and second terminals of the first pulse transformer T1, the first Schmitt trigger 04 outputs low or high level signals, which are reversely processed by the second Schmitt trigger 05 to restore the input PWM signal and generate a control signal.

[0049] The differential pulse generating circuit composed of the first capacitor C1 and the first resistor R1, the first capacitor C2 and the second resistor R2, has a time constant that can determine the pulse width of the positive and negative pulse signals respectively.

[0050] S102, generating a driving signal: the control signal is input into the logic control circuit, and is logically combined with the fault signal output by the short-circuit protection circuit to generate a driving signal;

[0051] Specifically, Figure 2 As shown, the logic control circuit 2 includes: a first AND gate 06 and a fourth NOT gate 07, wherein:

[0052] The first input end of the first AND gate 06 is connected to the output end of the short-circuit protection circuit 5, the second input end thereof is respectively connected to the output end of the modulation and demodulation circuit 1 and the input end of the fourth NOT gate 07, the output end thereof is connected to the input end of the power amplifier circuit 3, and the output end of the fourth NOT gate 07 is connected to the second input end of the short-circuit protection circuit 5;

[0053] The logic control circuit 2 can control the control signal U pulse With fault signal U fault Perform logical combination to generate drive signals.

[0054] S103, short circuit protection: the output signal of the logic control circuit and the drain output signal of the SiC MOSFET are input into the short circuit protection circuit, a short circuit fault is detected and a fault signal is output to the logic control circuit;

[0055] Specifically, Figure 2 As shown, the short circuit protection circuit 5 includes: a second comparator O9, a fifth switch tube S5, a fifth capacitor C5, a first diode D1, a second diode D2, a third diode D3, a ninth resistor R9, a tenth resistor R 10 11th resistor R 11 , the twelfth resistor R 12 、Thirteenth resistor R 13 , a first power supply U1, a second power supply U2 and a third power supply U3, wherein,

[0056] The first diode D1, the second diode D2, the ninth resistor R9 and the tenth resistor R 10 The cathode of the first diode D1 is connected to the drain of the SiC MOSFET, the second end of the ninth resistor R9 is connected to the positive electrode of the third power supply U3, the second end of the fifth switch tube S5 is connected to the second output end of the logic control circuit 2, the third end thereof is respectively connected to the second end of the fifth capacitor C5 and the anode of the third diode D3 to the positive electrode of the first power supply U1, and the first end thereof is respectively connected to the first end of the fifth capacitor C5, the cathode of the third diode D3, and the negative input end of the second comparator 09 to the ninth resistor R9 and the tenth resistor R 10 The midpoint of the eleventh resistor R 11 and the twelfth resistor R 12 The twelfth resistor R 12 The first end of the eleventh resistor R 11 The second end of is connected to the positive electrode of the first power supply U1, and the positive input end of the second comparator 09 is connected to the eleventh resistor R 11 and the twelfth resistor R 12 The midpoint of the output terminal is connected to the thirteenth resistor R 13 The first end of the thirteenth resistor R is connected to the second input end of the logic driving circuit 2. 13 The second end is connected to the positive electrode of the second power supply U2;

[0057] The short circuit protection circuit 5 is used to detect short circuit faults and output a fault signal U fault , to turn off the drive signal, when the control signal U pulse When the control signal U is low, the fifth switch tube S5 is turned on, the input voltage of the negative input terminal of the second comparator 09 is clamped at the voltage of the first power supply U1, and the fifth capacitor C5 is discharged, passing through the logic control circuit 2, so that the drive signal is still a low level signal; when the control signal U pulse When the signal is high, the fifth switch tube S5 is turned off, the SiC MOSFET is turned on in normal operation, and the third power supply U3, the ninth resistor R9, and the tenth resistor R 10 , the first diode D1, the second diode D2 and the SiC MOSFET form a closed loop. If a short circuit occurs, the voltage at the negative input terminal of the second comparator 09 is greater than the reference voltage U at its positive input terminal. ref , generating a fault signal U fault , so that the driving signal is turned off;

[0058] In the short-circuit protection circuit 5, the first diode D1 is pulseWhen it is a low level signal, since there is a high voltage at the drain of SiCMOSFET, it plays the role of a reverse blocking protection circuit. When the third diode D3 is short-circuited, it prevents the reverse input terminal voltage of the second comparator 09 from being too high, thereby playing a protective role.

[0059] like Figure 2 As shown, in one embodiment of the present invention, optionally, the first diode D1 is a silicon carbide diode or a fast recovery diode, the second diode D2 and the third diode D3 are Zener diodes, the first switch tube S1, the second switch tube S2, the fourth switch tube S4 and the fifth switch tube S5 are all N-channel MOSFETs, and the third switch tube S3 is a P-channel MOSFET.

[0060] S103, driving signal enhancement: the driving signal is input into the power amplifier circuit to enhance the driving capability of the driving signal and output an enhanced driving signal;

[0061] Specifically, Figure 2 As shown, the power amplifier circuit 3 includes: a fifth resistor R5, a sixth resistor R6, a first switch tube S1, a second switch tube S2, a third switch tube S3, a first power supply U1 and a third power supply U3, wherein:

[0062] The second end of the first switch tube S1 is connected to the first output end of the logic control circuit 2, and the first end thereof is respectively connected to the first end of the fifth resistor R5, the first switch tube S1 and the second end of the second switch tube S2, the third end of the first switch tube S1 is connected to the positive electrode of the first power supply U1, the second end of the fifth resistor R5 is connected to the positive electrode of the third power supply U3, the first end of the third switch tube S3 is connected to the positive electrode of the third power supply U3, the third end thereof is respectively connected to the first end of the sixth resistor R6 and the first end of the second switch tube S2, the third end of the second switch tube S2 is connected to the positive electrode of the first power supply U1, and the second end of the sixth resistor R6 is connected to the gate of the SiC MOSFET;

[0063] The power amplifier circuit 3 can realize level shifting and power amplification to improve the gate driving capability. When the circuit works normally, when the driving signal is at a high level, the first switch tube S1 and the third switch tube S3 are turned on, thereby injecting current into the SiC MOSFET and providing a positive driving voltage; when the driving signal is at a low level, the second switch tube S2 is turned on, thereby extracting current from the SiC MOSFET and providing a negative driving voltage.

[0064] S105, crosstalk suppression: the enhanced driving signal is input into the Miller clamp circuit to suppress the crosstalk spikes generated by the opening and closing of the bridge arm circuit of the SiC MOSFET, thereby controlling the opening and closing of the SiC MOSFET.

[0065] Specifically, Figure 2 As shown, the Miller clamp circuit 4 includes: a first comparator O8, a seventh resistor R7, an eighth resistor R8, a fourth capacitor C4, a fourth switch tube S4 and a first power supply U1, wherein:

[0066] The first end of the eighth resistor R8 is connected to the gate of the SiC MOSFET, the seventh resistor R7 and the eighth resistor R8 are connected in series, the second end of the seventh resistor R7 is connected to the positive electrode of the first power supply U1, the fourth capacitor C4 is connected in parallel with the seventh resistor R7, the negative input end of the first comparator O8 is connected to the second end of the eighth resistor R8, the positive input end thereof is connected to the reference ground GND2 of the power circuit, the output end thereof is connected to the second end of the fourth switch tube S4, the first end of the fourth switch tube S4 is connected to the gate of the SiC MOSFET, and the third end thereof is connected to the positive electrode of the first power supply U1;

[0067] Miller clamp circuit 4 can effectively suppress the crosstalk problem of the bridge arm circuit. When it is detected that the voltage at the negative input terminal of the first comparator 08 is less than the reference zero potential GND2 of the power circuit, the fourth switch tube S4 is turned on, and the gate voltage of the SiC MOSFET is clamped at the voltage of the first power supply U1 until the positive drive voltage signal arrives, so that the fourth switch tube S4 is turned off.

[0068] Optionally, the reference ground of all logic devices in the circuit on the right side of the first pulse transformer T1 uses the voltage of the first power supply U1 as a reference, and the voltage value of the first power supply U1 is a negative voltage relative to the negative electrode GND2 of the input power supply of the power circuit.

[0069] The driving circuit can also be applied to a volt-type driving circuit, and GND2 and a voltage using GND2 as a reference need to be replaced by a source voltage of a corresponding SiC MOSFET and a voltage using GND2 as a reference.

[0070] Combine the following Figure 2 The working principle of this embodiment is introduced.

[0071] When the input PWM signal is always a low-level signal, the input end of the third NOT gate 03 is a low-level signal, and its output is a high-level signal. The output of the first NOT gate 01 is a high-level signal, so the voltage across the first resistor R1 is zero, so the output of the second NOT gate 02 is also a high-level signal, and the voltage across the first transformer T1 is zero;

[0072] When the input PWM signal switches from a low-level signal to a high-level signal, the voltage signal at one end of the second resistor R2 is a high-level signal, so the output end of the third NOT gate 03 is a low-level signal, the output of the first NOT gate 01 changes to a low-level signal, and the voltage across the first resistor R1 remains zero, so the output of the second NOT gate 02 is also a high-level signal. Therefore, the voltage signal across the first transformer T1 is a high-level signal;

[0073] When the input PWM signal is always a high-level signal, the output of the second NOT gate 02 is always a high-level signal, and the voltage signal at one end of the second resistor R2 changes to a low-level signal, so the output end of the third NOT gate 03 is a high-level signal, and therefore, the voltage across the first transformer T1 is zero;

[0074] When the input PWM signal switches from a high-level signal to a low-level signal, the voltage signal at one end of the second resistor R2 remains a low-level signal, the output end of the third NOT gate 03 is a high-level signal, and the output signal of the first NOT gate 01 changes to a high-level signal, so the voltage signal at both ends of the first resistor R1 changes to a high-level signal, so the output of the second NOT gate 02 is a low-level signal, and the voltage signal at both ends of the first transformer T1 is a low-level signal;

[0075] Here, it is required that the time constant of the differential circuit composed of the first resistor R1 and the first capacitor C1, the second resistor R2 and the second capacitor C2 should be less than half of the input PWM signal cycle, thereby, the rising edge and falling edge signals of the input PWM signal can be captured on the left side of the first transformer T1;

[0076] When the left side of the first pulse transformer T1 does not generate a positive or negative pulse signal, the size relationship between the third resistor R3 and the fourth resistor R4 is set so that the input voltage of the first Schmitt trigger O4 is between its positive and negative thresholds. At this time, the secondary voltage U of the first pulse transformer T1 is s Satisfies the following formula (1):

[0077]

[0078] When positive and negative pulse signals are generated at both ends of the first pulse transformer T1, the first Schmitt trigger 04 outputs a low level or high level signal, wherein the transformation ratio of the first pulse transformer T1 is n:1, and the primary voltage U p The positive and negative threshold voltages of the first Schmitt trigger 04 are U - and U + The following formulas (2) and (3) are satisfied:

[0079]

[0080]

[0081] The second Schmitt trigger 05 performs signal inversion processing to restore the input PWM signal and generate a control signal U pulse , where when the secondary voltage U of the first pulse transformer T1 s Lower than U - When the first Schmitt trigger 04 outputs a high level signal, when the secondary voltage U s Higher than U + When , the first Schmitt trigger 04 outputs a low level signal.

[0082] When the control signal U pulse When the voltage is low, the output of the fourth NOT gate 07 is high, so that the fifth switch S5 is turned on, and the fifth capacitor C5 is discharged, so that the negative input voltage of the second comparator 09 is U1, which is less than the positive input voltage U ref , so the output fault signal U fault It is a high-level signal with a voltage amplitude of U2. After the first AND gate 06 performs a logic AND operation, the negative drive voltage is normally output, so that the second switch tube S2 is turned on. U1 is directly connected to the gate of SiCMOSFET, and the gate-source capacitor C gs Discharge is performed to turn off the SiC MOSFET. When it is detected that the voltage at the negative input terminal of the first comparator 08 is lower than GND2, the fourth switch tube S4 is turned on. Before the positive crosstalk and after the negative crosstalk, it is always clamped at U1 for the bridge arm circuit.

[0083] When the control signal U pulse When the signal is high level, the fifth switch tube S5 is turned off. At this time, the third power supply U3, the ninth resistor R9, and the tenth resistor R 10 The second diode D2 and the first diode D1 form a closed loop with the SiC MOSFET. The voltage at the negative input end of the second comparator 09 is the voltage of the tenth resistor R 10 , the sum of the voltage drops of the second diode D2 and the first diode D1 and the SiC MOSFET satisfies the following formula (4) under normal operation:

[0084] u R10 +u D2 +u D1 +u ds ≤U ref (4)

[0085] Then its voltage amplitude is U2, and after the first AND gate 06 performs a logic AND operation, the positive drive voltage is output normally; if short-circuit protection occurs, the voltage drop of the SiC MOSFET increases, and the voltage at the negative input terminal of the second comparator 09 is greater than its positive input terminal voltage U ref , is clamped and protected by the third diode D3, and satisfies the following formula (5) in the case of a short circuit:

[0086] u R10 +u D2 +u D1 +u ds =u D3 +U1≥U ref (5)

[0087] Among them, u R10 is the tenth resistor R 10 Voltage across the terminals, u D1 is the conduction voltage drop of the first diode D1, u D2 is the voltage across the second diode D2, u D3 is the voltage across the third diode D3, u ds is the drain-source on-state voltage drop of SiC MOSFET.

[0088] At this time, the second comparator 09 outputs a low level signal, which is logically ANDed by the first AND gate 06 to change the positive driving voltage into a negative driving voltage. The subsequent process is the same as the control signal U pulse When the first AND gate 06 outputs a positive driving voltage, the first switch tube S1 and the third switch tube S3 are turned on, and U3 is directly connected to the gate of the SiC MOSFET, which is connected to the gate-source capacitor C gs When the voltage at the negative input terminal of the first comparator 08 is detected to be higher than GND2, the fourth switch S4 is turned off, so that the SiC MOSFET is normally turned on.

[0089] In order to reduce the power supply in the driving circuit, the positive power supply voltage of the second comparator 09 is set to U3, the positive power supply voltages of the other logic devices are all U2, and the negative power supply voltages of all logic devices are all U1.

[0090] In summary, a driving method of a SiC MOSFET of the present invention adopts a narrow pulse modulation method to effectively reduce the size of the isolation transformer, has a Miller clamping function to effectively suppress the crosstalk phenomenon, and the circuit can effectively protect the SiC MOSFET in the event of a sudden short circuit, thereby improving the system reliability.

[0091] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0092] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A driving method for SiC MOSFET, characterized in that: A SiC MOSFET drive circuit is included, wherein the drive circuit includes a modulation and demodulation circuit, a logic control circuit, a power amplifier circuit, a Miller clamp circuit, a short-circuit protection circuit, a first power supply, a second power supply and a third power supply; the drive circuit is connected to the input signal input terminal and the power circuit respectively; The driving method comprises the following steps: (1) Generating a control signal: The input signal PWM is input into the modulation and demodulation circuit to achieve electrical isolation of the circuit and generate a control signal; (2) Generating a driving signal: the control signal is input into the logic control circuit, and is logically combined with the fault signal output by the short-circuit protection circuit to generate a driving signal; The logic control circuit comprises: a first AND gate and a fourth NOT gate; The first input end of the first AND gate is connected to the output end of the short-circuit protection circuit, the second input end thereof is respectively connected to the output end of the modulation and demodulation circuit and the input end of the fourth NOT gate, the output end thereof is connected to the input end of the power amplifier circuit, and the output end of the fourth NOT gate is connected to the second input end of the short-circuit protection circuit; (3) Short-circuit protection: The output signal of the logic control circuit and the drain output signal of the SiC MOSFET are input into the short-circuit protection circuit to detect the short-circuit fault and output a fault signal to the logic control circuit; (4) Driving signal enhancement: the driving signal is input into the power amplifier circuit to enhance the driving capability of the driving signal and output an enhanced driving signal; (5) Crosstalk suppression: The enhanced drive signal is input into the Miller clamp circuit to suppress the crosstalk spikes generated by the on / off switching of the bridge arm circuit of the SiC MOSFET, thereby controlling the on / off switching of the SiC MOSFET; The Miller clamp circuit comprises: a first comparator, a seventh resistor, an eighth resistor, a fourth capacitor and a fourth switch tube; The first end of the eighth resistor is connected to the gate of the SiC MOSFET, the seventh resistor and the eighth resistor are connected in series, the second end of the seventh resistor is connected to the positive electrode of the first power supply, the fourth capacitor is connected in parallel with the seventh resistor, the negative input end of the first comparator is connected to the second end of the eighth resistor, the positive input end of the first comparator is connected to the reference ground of the power circuit, the output end of the first comparator is connected to the second end of the fourth switch tube, the first end of the fourth switch tube is connected to the gate of the SiC MOSFET, and the third end of the fourth switch tube is connected to the positive electrode of the first power supply; The Miller clamp circuit turns on the fourth switch tube and clamps the gate voltage of the SiC MOSFET at the first power supply voltage when it is detected that the voltage at the negative input terminal of the first comparator is less than the reference zero potential of the power circuit, until a positive drive voltage signal arrives, turning off the fourth switch tube.

2. A driving method for SiC MOSFET according to claim 1, characterized in that: The modulation and demodulation circuit includes: a first NOT gate, a second NOT gate, a third NOT gate, a first Schmitt trigger, a second Schmitt trigger, a first pulse transformer, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor and a third capacitor, wherein: The input end of the first NOT gate is connected to the input signal input end and the first end of the second capacitor respectively, the output end of the first NOT gate is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the first end of the first resistor and the input end of the second NOT gate respectively, the second end of the second capacitor is connected to the first end of the second resistor and the input end of the third NOT gate respectively, the output ends of the second NOT gate and the third NOT gate are connected to the first and second ends of the first pulse transformer respectively, and the second ends of the first resistor and the second resistor are both connected to the reference ground of the input signal; The positive electrode of the second power supply is connected to the first end of the third resistor, the second end of the third resistor is respectively connected to the third end of the first pulse transformer and the input end of the first Schmitt trigger, the first Schmitt trigger and the second Schmitt trigger are connected in series, the output end of the second Schmitt trigger is connected to the first input end of the logic control circuit, the fourth end of the first pulse transformer is respectively connected to the first end of the fourth resistor and the first end of the third capacitor, and the second end of the fourth resistor and the second end of the third capacitor are both connected to the positive electrode of the first power supply; The first NOT gate, the second NOT gate and the third NOT gate are powered by independent power supplies; The modulation and demodulation circuit can electrically isolate the input signal, and capture the rising edge and falling edge of the input signal through the modulation circuit at the left end of the first pulse transformer, generate a positive pulse signal when the rising edge of the input signal is captured, and generate a negative pulse signal when the falling edge of the input signal is captured. After the output positive and negative pulse signals are isolated and transmitted by the first pulse transformer, the input signal is restored through the demodulation circuit on the right side of the first pulse transformer; When there is no positive or negative pulse signal at the third or fourth end of the first pulse transformer, the magnitude relationship between the third resistor and the fourth resistor is set so that the input voltage of the first Schmitt trigger is between its positive and negative thresholds, and when the positive or negative pulse signal is generated at the first or second end of the first pulse transformer, the first Schmitt trigger outputs a low or high level signal, and reverse processing is performed by the second Schmitt trigger to restore the input signal and generate a control signal; The differential pulse generating circuit composed of the first capacitor and the first resistor, the second capacitor and the second resistor, has a time constant that can determine the pulse width of the positive and negative pulse signals respectively.

3. A driving method for SiC MOSFET according to claim 2, characterized in that: The reference grounds of all logic devices in the circuit on the right side of the third and fourth ends of the first pulse transformer are all based on the first power supply voltage.

4. The driving method of SiC MOSFET according to claim 1, characterized in that: The power amplifier circuit comprises: a fifth resistor, a sixth resistor, a first switch tube, a second switch tube, and a third switch tube; The second end of the first switch tube is connected to the first output end of the logic control circuit, the first end thereof is respectively connected to the first end of the fifth resistor, the second end of the second switch tube and the second end of the third switch tube, the third end of the first switch tube is connected to the positive electrode of the first power supply, the second end of the fifth resistor is connected to the positive electrode of the third power supply, the first end of the third switch tube is connected to the positive electrode of the third power supply, the third end thereof is respectively connected to the first end of the sixth resistor and the first end of the second switch tube, the third end of the second switch tube is connected to the positive electrode of the first power supply, and the second end of the sixth resistor is connected to the gate of the SiC MOSFET; The power amplifier circuit can realize level shifting and power amplification to improve the gate driving capability; when the circuit works normally, when the driving signal is at a high level, the first switch tube and the third switch tube are turned on, thereby injecting current into the SiC MOSFET and providing a positive driving voltage; when the driving signal is at a low level, the second switch tube is turned on, thereby extracting current from the SiC MOSFET and providing a negative driving voltage; The first switch tube and the second switch tube are both N-channel MOSFETs, and the third switch tube is a P-channel MOSFET.

5. The driving method of SiC MOSFET according to claim 1, characterized in that: The short circuit protection circuit comprises: a second comparator, a fifth switch tube, a fifth capacitor, a first diode, a second diode, a third diode, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor and a thirteenth resistor; The first diode, the second diode, the tenth resistor and the ninth resistor are connected in series, the cathode of the first diode is connected to the drain of the SiC MOSFET, the anode of the first diode is connected to the anode of the second diode, the second end of the ninth resistor is connected to the positive electrode of the third power supply, the second end of the fifth switch tube is connected to the second output end of the logic control circuit, the third end thereof and the second end of the fifth capacitor and the anode of the third diode are connected to the positive electrode of the first power supply, the first end thereof and the first end of the fifth capacitor, the cathode of the third diode, and the negative input end of the second comparator are connected to the midpoint of the ninth resistor and the tenth resistor, the eleventh resistor and the twelfth resistor are connected in series, the first end of the twelfth resistor is connected to the positive electrode of the third power supply, the second end of the eleventh resistor is connected to the positive electrode of the first power supply, the positive input end of the second comparator is connected to the midpoint of the eleventh resistor and the twelfth resistor, the output end thereof is respectively connected to the first end of the thirteenth resistor and the second input end of the logic control circuit, and the second end of the thirteenth resistor is connected to the positive electrode of the second power supply; The short-circuit protection circuit is used to detect a short-circuit fault and output a fault signal to turn off the drive signal. When the control signal is a low-level signal, the fifth switch is turned on, the input voltage clamp of the negative input terminal of the second comparator is located at the voltage of the first power supply, and the fifth capacitor is discharged. After passing through the logic control circuit, the drive signal is still a low-level signal; when the control signal is a high-level signal, the fifth switch is turned off, and the SiCMOSFET is turned on under normal working conditions. The third power supply, the ninth resistor, the tenth resistor, the first diode, the second diode and the SiC MOSFET form a closed loop. If a short circuit occurs, the voltage at the negative input terminal of the second comparator is greater than the reference voltage at its positive input terminal, and the fault signal is generated, so that the drive signal is turned off; In the short-circuit protection circuit, when the control signal is a low-level signal, the first diode plays the role of a reverse blocking protection circuit due to the presence of a high voltage at the drain of the SiC MOSFET. In the case of a short circuit, the third diode prevents the reverse input terminal voltage of the second comparator from being too high, thereby playing a protective role. The first diode is a silicon carbide diode or a fast recovery diode, the second diode and the third diode are Zener diodes; and the fifth switch tube is an N-channel MOSFET.

6. The driving method of SiC MOSFET according to claim 1, characterized in that: The fourth switch tube is an N-channel MOSFET.

7. The driving method of SiC MOSFET according to claim 1, characterized in that: The voltage value of the first power supply is a negative voltage relative to the negative pole of the input power supply of the power circuit, and the voltage values ​​of the second power supply and the third power supply are positive voltages relative to the negative pole of the input power supply of the power circuit.

8. The driving method of SiC MOSFET according to claim 1, characterized in that: Negative electrodes of the first power supply, the second power supply and the third power supply are connected to a reference ground of a power circuit.

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