Control circuit, integrated circuit, multi-phase buck converter and operation method

Abstract

Embodiments of the present disclosure relate to control circuits, integrated circuits, multiphase buck converters, and operating methods. A control circuit for a multiphase buck converter includes a regulator circuit and a plurality of phase control circuits. The regulator circuit generates a regulation signal based on a feedback signal and a reference signal, and each phase control circuit receives a current sensing signal and generates a corresponding PWM signal based on the corresponding current sensing signal and the regulation signal. The control circuit includes a first selector circuit and a second selector circuit, which are configured to receive a selection signal and selectively connect each phase control circuit in a subset of the phase control circuits to a PWM signal for driving a corresponding stage of the multiphase buck converter and a current sensing signal provided by the corresponding stage of the multiphase buck converter. The selection control circuit generates a selection signal to connect the phase control circuit to different stages of the multiphase buck converter.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a multi-phase buck converter. Background Art

[0002] Power supply circuits such as AC / DC or DC / DC switching mode power supplies are well known in the art. There are many types of electronic converters, mainly divided into isolated and non-isolated converters. For example, non-isolated electronic converters are "buck", "boost", "buck-boost", "SEPIC" and "ZETA" type converters. In contrast, isolated converters are, for example, "flyback", "forward", "half-bridge" and "full-bridge" type converters. Such types of converters are well known to those skilled in the art, as demonstrated, for example, by application note AN513 / 0393 "Topologies for Switched Mode Power Supplies", L. Wuidart, 1999, STMicroelectronics. Summary of the invention

[0003] In view of the foregoing, various embodiments of the present disclosure are directed to improvements in multi-phase buck converters.

[0004] According to one or more embodiments, one or more technical advantages or benefits are achieved by a control circuit of a multiphase buck converter having the features as described herein. Embodiments also relate to corresponding integrated circuits, multiphase buck converters, and methods of operating a multiphase buck converter.

[0005] As previously mentioned, various embodiments of the present disclosure are directed to control circuits for multi-phase buck converters.

[0006] For example, as will be described in more detail below, such a multiphase buck converter may include first and second input terminals configured to receive an input voltage, and first and second output terminals configured to provide an output voltage. In this case, one or more capacitors may be connected between the first and second output terminals, and the feedback circuit generates a feedback signal indicating the output voltage. In addition, the multiphase buck converter includes a plurality of stages. Specifically, in various embodiments, each stage includes an inductor, wherein the first terminal of the inductor is connected to the first output terminal. In addition, a first electronic switch and a second electronic switch or a diode are connected between the first and second input terminals and are configured to selectively connect the second terminal of the inductor to the first input terminal or the second input terminal. In various embodiments, the driver circuit of the stage is configured to receive a corresponding PWM signal and generate a corresponding first drive signal for the first electronic switch, and optionally generate a corresponding second drive signal for the second electronic switch (if provided). In addition, the current sensor is configured to generate a corresponding current sensing signal indicating the current flowing through the corresponding inductor.

[0007] Thus, in various embodiments, the control circuit includes a feedback terminal configured to receive a feedback signal indicative of an output voltage generated by the multiphase buck converter. Similarly, the control circuit includes a plurality of current sensing terminals, wherein each current sensing terminal is configured to receive a respective current sensing signal indicative of a current flowing through an inductor of the respective stage from a respective stage of the multiphase buck converter. Finally, the control circuit includes a plurality of control terminals, wherein the number of control terminals corresponds to the number of current sensing terminals, wherein each control terminal is configured to provide a respective PWM signal to a driver circuit of a respective stage of the multiphase buck converter. Thus, in general, each PWM signal is associated with a respective stage and therefore with a respective current sensing signal.

[0008] In various embodiments, the driver circuit may also be integrated in the control circuit, that is, the control circuit may include a plurality of driver circuits, wherein the number of the driver circuits corresponds to the number of control terminals, and wherein each driver circuit is configured to receive a corresponding PWM signal and generate a corresponding first drive signal for a first electronic switch of a corresponding stage, and optionally generate a corresponding second drive signal for a second electronic switch of the corresponding stage (if provided).

[0009] Therefore, in various embodiments, the control circuit is configured to generate a PWM signal according to the feedback signal and the current sensing signal.

[0010] For example, in various embodiments, the control circuit includes a regulator circuit configured to generate a regulation signal by changing the regulation signal until the feedback signal corresponds to the reference signal. For example, the regulator circuit can be a (digital or analog) regulator including an integral component and optionally a proportional and / or differential component.

[0011] In this case, the control circuit further comprises a plurality of phase control circuits, wherein each phase control circuit is configured to receive a corresponding current sensing signal and generate a corresponding PWM signal by changing a duty cycle of the corresponding PWM signal according to the corresponding current sensing signal and a regulation signal generated by the regulator circuit. For example, the phase control circuit may comprise a comparator, the comparator being configured to signal the end of the conduction interval of the corresponding PWM signal when the instantaneous value of the corresponding current sensing signal reaches the regulation signal during the conduction interval, wherein the regulation signal represents a threshold value of the instantaneous current. Alternatively, the phase control circuit may comprise another regulator having an integral component and / or a proportional component, and the other regulator being configured to change the duty cycle of the corresponding PWM signal according to a difference between an average value of the corresponding current sensing signal during the conduction interval and the regulation signal, wherein the regulation signal represents a reference value of the average current.

[0012] Specifically, in various embodiments, the control circuit further includes a first selector circuit and a second selector circuit configured to receive a selection signal and, in response to the selection signal, selectively connect each phase control circuit in a subset of a given number of phase control circuits to one of the PWM signals via a corresponding second PWM signal, and selectively connect to a current sensing signal associated with the PWM signal connected to the phase control circuit, i.e., a current sensing signal associated with the PWM signal connected to the corresponding second PWM signal, via a corresponding second current sensing signal. For example, the first selector circuit may include a plurality of electronic switches for connecting each second current sensing signal to each current sensing signal, and the second selector circuit may include a plurality of electronic switches for connecting each second PWM signal to each PWM signal.

[0013] In various embodiments, the selection control circuit can thus be configured to generate a selection signal. Specifically, in a first switching mode, the selection control circuit can set the selection signal so as to connect a given number of phase control circuits to a first set of PWM signals and associated current sensing signals. Conversely, in a second switching mode, the selection control circuit can set the selection signal so as to connect a given number of phase control circuits to a second set of PWM signals and associated current sensing signals, wherein the second set is at least partially different from the first set.

[0014] For example, the number of phase control circuits in the subset may correspond to the number of activated phase control circuits. For example, for this purpose, the regulator circuit may be configured to determine the number of phase control circuits to be activated from the regulation signal and to activate a corresponding number of phase control circuits.

[0015] Typically, the number of phase control circuits may thus correspond to or may be smaller than the number of stages of the multi-phase buck converter (as indicated, for example, by the number of current sensing terminals).

[0016] In general, the selection control circuit may use different solutions to select a subset of stages to be connected to the phase control circuit.

[0017] For example, in various embodiments, the control circuit includes a communication interface, and the selection control circuit is configured to activate the first switching mode or the second switching mode according to a control signal received via the communication interface. In this case, the selection control circuit can be configured to select a level belonging to the first level subset (i.e., a corresponding first set of PWM signals and associated current sensing signals) and / or the second level subset (i.e., a corresponding second set of PWM signals and associated current sensing signals) according to the control signal received via the communication interface.

[0018] Additionally or alternatively, the selection control circuit can be configured to activate a first switching mode and monitor a corresponding first subset of current sensing signals of corresponding stages connected to the phase control circuit. Next, the selection control circuit can determine whether the monitored current sensing signal is greater than an upper threshold (e.g., indicating a short circuit condition) and / or less than a lower threshold (e.g., indicating an open load condition), and possibly activate a second switching mode in which a second set of stages (i.e., a corresponding set of current sensing signals and PWM signals) no longer includes the monitored stage / current sensing signal.

[0019] Additionally or alternatively, the selection control circuit may be configured to periodically activate the first switching mode and the second switching mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Embodiments of the present specification will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, in which:

[0021] Figure 1 is a schematic diagram illustrating an electronic converter according to some embodiments;

[0022] Figure 2 is a schematic diagram illustrating a buck converter according to a comparative example;

[0023] Figure 3 a to Figure 3 e is shown Figure 2 The waveform diagram of the buck converter waveform;

[0024] Figure 4 is a waveform diagram showing example waveforms when the buck converter operates in CCM;

[0025] Figure 5 is a waveform diagram showing example waveforms when the buck converter operates in DCM;

[0026] Figure 6 is a schematic diagram illustrating a control circuit for a single-stage buck converter according to one or more embodiments;

[0027] Figure 7 is a waveform diagram illustrating generation of a drive signal for an electronic switch of a buck converter according to a PWM signal according to one or more embodiments;

[0028] Figure 8 is a schematic diagram illustrating a driver circuit configured to generate a drive signal for an electronic switch of a buck converter according to a PWM signal according to one or more embodiments;

[0029] Fig. 9 is a schematic diagram illustrating a regulator circuit configured to generate a PWM signal based on a feedback signal of a buck converter according to one or more embodiments;

[0030] Fig.10 is a schematic diagram illustrating a multi-phase buck converter according to one or more embodiments;

[0031] Fig.11 is a diagram illustrating a device configured for Fig.10 A schematic diagram of a regulator circuit for generating a PWM signal from a multi-phase buck converter;

[0032] Fig.12 is a diagram illustrating an embodiment of the present invention according to one or more embodiments. Fig.11 A waveform diagram of the operation of the regulator circuit;

[0033] Fig.13 is a schematic diagram illustrating a regulator circuit including two switching circuits according to one or more embodiments;

[0034] Fig.14 and Fig.15 is a diagram illustrating an embodiment of the present invention according to one or more embodiments. Fig.13 A schematic diagram of further details of the switching circuit.

[0035] Fig.16 is a diagram illustrating an embodiment of the present invention according to one or more embodiments. Fig.13 A schematic diagram of a digital implementation of a regulator circuit; and

[0036] Fig.17 and Fig.18 is a diagram illustrating an embodiment of the present invention according to one or more embodiments. Fig.13 and Fig.16 A waveform diagram of the operation of the regulator circuit. DETAILED DESCRIPTION

[0037] In the following description, various specific details are illustrated for the purpose of enabling a deeper understanding of the embodiments. Embodiments may be provided without one or more specific details or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that various aspects of the embodiments are not obscured.

[0038] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear in various places in this specification do not necessarily refer to the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0039] The reference signs used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0040] Figure 1 2 is a schematic diagram of a DC / DC electronic converter 20. Specifically, the universal electronic converter 20 includes a circuit for receiving a DC voltage V in The two input terminals 200a and 200b are used to provide a DC voltage V out For example, the input voltage V in It can be provided by a DC voltage source 10 such as a battery, or it can be obtained from an AC voltage via a rectifier circuit such as a bridge rectifier and possibly a filtering circuit. out Can be used to power the load 30 .

[0041] Figure 2 FIG. 2 is a circuit diagram of an example of a buck converter 20. Specifically, the buck converter 20 includes a circuit for receiving a DC input voltage V in The two input terminals 200a and 200b and the regulated voltage V out The two output terminals 202a and 202b, where the output voltage is equal to or lower than the input voltage V in .

[0042] In the example considered, the buck converter 20 comprises two electronic switches Q1 and Q2 (and their current paths) connected in series (e.g. directly) between input terminals 200a and 200b, wherein an intermediate node between the electronic switches Q1 and Q2 represents a switching node Lx. Specifically, the electronic switch Q1 is a high-side switch connected (e.g. directly) between the (positive) terminal 200a and the switching node Lx, and the electronic switch Q2 is a low-side switch connected (e.g. directly) between the switching node Lx and the (negative) terminal 200b (typically representing ground GND). The (high-side) switch Q1 and the (low-side) switch Q2 thus represent a switch configured to connect the switching node Lx to the terminal 200a (voltage V in ) or half bridge of terminal 200b (ground GND).

[0043] In the example considered, an inductor L, such as an inductor, is connected (eg directly) between the switching node Lx and the (positive) output terminal 202a. In contrast, the (negative) output terminal 202b is connected (eg directly) to the (negative) input terminal 200b.

[0044] In the example considered, in order to stabilize the output voltage V out , the converter 20 typically includes a capacitor C connected (eg, directly) between the output terminals 202a and 202b. out .

[0045] In this context, Figure 3 Exemplary waveforms of signals of such an electronic converter are shown, where:

[0046] Figure 3 a shows the signal DRV for switching the electronic switch Q1 1 ;

[0047] Figure 3 b shows the signal DRV for switching the second electronic switch Q2 2 ;

[0048] Figure 3 c shows the current I flowing through the electronic switch Q1 Q1 ;

[0049] Figure 3 d shows the voltage V at the switching node Lx Lx (ie, the voltage at the second switch Q2); and

[0050] Figure 3 e shows the current I flowing through the inductor L L .

[0051] Specifically, when the electronic switch Q1 is at time t 1When the inductor L is closed (conduction state), the current I L (substantially) linearly increases. The electronic switch Q2 is turned off at the same time. On the contrary, when the electronic switch Q1 is in the interval T ON1 After the time t 2 (off state), the electronic switch Q2 is closed and the current I L Finally, the switch Q1 is switched to the OFF1 In the example considered, switch Q2 is therefore closed when switch Q1 is open, and vice versa. L Therefore, it can be used to out Charging, capacitor C out A voltage V is provided at terminals 202a and 202b. out .

[0052] In the example considered, the electronic converter 20 therefore comprises a control circuit 22 configured to drive the switching of the switches Q1 and Q2 so as to periodically repeat the interval T ON1 and T OFF1 For example, the buck converter 20 generally further includes a feedback circuit 24, such as a voltage divider, which is configured to generate a feedback signal FB indicating the output voltage V out (and preferably with the output voltage V out The control circuit 22 is configured to compare the feedback signal FB with a reference signal (eg, a reference voltage V ref ) to generate a driving signal DRV 1 and DRV 2 .

[0053] A large number of driving schemes are known for generating the driving signal DRV 1 and DRV 2 These solutions have in common that by adjusting the interval T ON1 and / or interval T OFF1 The duration of the regulation of the output voltage V out possibility.

[0054] For example, in various solutions, the control circuit 22 generates a pulse width modulation (PWM) signal DRV 1 , where the duty cycle T ON1 / (T ON1 +T OFF1 ) is variable. Usually, the switching period T SW =T ON1 +T OFF1 Can be constant or variable. For example, a typical control scheme includes a switching period T SW Constant, and interval TON1 The duration of is varied via a regulator circuit having at least one integrating component, such as a PI (proportional-integral) or PID (proportional-integral-derivative) regulator.

[0055] Typically, a buck converter can operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or transition mode (TM).

[0056] For example, Figure 4 As shown, when the control circuit 22 operates the converter in CCM mode, the current I flowing through the inductor L L In the switching period T SW At the end, it has a value different from zero. In this case, the control circuit 22 uses two switching phases T 1 and T 2 , where T SW =T 1 +T 2 ,in:

[0057] In phase T 1 (T 1 =T ON1 =T OFF2 ), switch Q1 is closed and switch / diode Q2 is open; and

[0058] In phase T2(T 2 =T OFF1 =T ON2 ), switch Q1 is open and switch / diode Q2 is closed.

[0059] On the contrary, Figure 5 As shown, in DCM, the control circuit 22 can use three switching phases T 1 、T 2 and T 3 , where T SW =T 1 +T 2 +T 3 ,in:

[0060] In phase T 1 (T 1 =T ON1 ), the switch Q1 is closed and the switch / diode Q2 is open;

[0061] In phase T 2 (T 2 =T ON2 ), switch Q1 is open and switch / diode Q2 is closed; and

[0062] In phase T 3 (T OFF1 =T2 +T 3 and T OFF2 =T 3 +T 1 ), switch Q1 is off and switch / diode Q2 is off.

[0063] Specifically, in DCM, when the current I L When it reaches zero, the electronic switch Q2 turns off (and remains off during interval T3).

[0064] In various solutions, a (usually fixed) dead time may also be introduced between the switching of the drive signal, e.g. 1 The falling edge of the signal DRV 2 and similarly (in CCM mode) between the rising edges of the drive signal DRV 2 The falling edge of the signal DRV 1 As long as these intervals have a duration of T ON and T OFF As these intervals are usually short in comparison, they will not be considered specifically below.

[0065] For higher currents, the buck converter can also be used in a multiphase configuration, i.e. a so-called multiphase buck converter. Specifically, in this case, multiple buck converters are used to supply the same output capacitor C out Charging, wherein each buck converter represents a phase of a multi-phase buck converter.

[0066] exist Figures 6 to 18 In, referenced Figures 1 to 5 Described parts, elements or components are denoted by the same reference numerals used previously in these figures; in order not to overburden this detailed description, the description of these previously described elements will not be repeated hereinafter.

[0067] As previously mentioned, various embodiments of the present disclosure relate to a control circuit for a multi-phase buck converter.

[0068] Figure 6 In this respect, an exemplary embodiment of a control circuit for a single-stage buck converter 20 a is shown.

[0069] As about Figure 2 As described, such a buck converter 20a includes a device for receiving a DC input voltage V in The two input terminals 200a and 200b and the regulated voltage V out The two output terminals 202a and 202b.

[0070] In the embodiment considered, the buck converter 20a includes two electronic switches Q1 and Q2 (and their current paths) connected in series (e.g., directly) between input terminals 200a and 200b, wherein the intermediate node between the electronic switches Q1 and Q2 represents the switching node Lx. Specifically, the electronic switch Q1 is a high-side switch connected (e.g., directly) between the (positive) terminal 200a and the switching node Lx, and the electronic switch Q2 is a low-side switch connected (e.g., directly) between the switching node Lx and the (negative) terminal 200b (generally representing ground GND). In various embodiments, the switches Q1 and / or Q2 are transistors, such as field effect transistors (FETs), such as metal oxide semiconductor field effect transistors (MOSFETs), for example n-channel FETs, such as NMOS. In various embodiments, the second electronic switch Q2 can be implemented using a diode D, wherein the anode is connected to the terminal 200b and the cathode is connected to the switching node Lx.

[0071] In the considered embodiment, an inductor L, such as an inductor, is connected (eg directly) between the switching node Lx and the (positive) output terminal 202a. In contrast, the (negative) output terminal 202b is connected (eg directly) to the (negative) input terminal 200b.

[0072] In the considered embodiment, the converter 20a typically comprises a capacitor Cout connected (eg directly) between the output terminals 202a and 202b.

[0073] Specifically, in Figure 6 In the embodiment, the buck converter 20a further comprises:

[0074] The feedback circuit 24 is configured to generate a feedback signal FB, the feedback signal FB indicating the output voltage V out (and preferably with the output voltage V out proportionately); and

[0075] The control circuit 22a is configured to ref , generates a drive signal DRV for the electronic switch Q1 1 and optionally generates a drive signal DRV for the electronic switch Q2 2 (When the electronic switch Q1 is not replaced by a diode), the reference signal V ref Indicates output voltage V out The requested value of (and preferably proportional to) .

[0076] Specifically, in Figure 6 In the embodiment, the control circuit 22a includes:

[0077] The PWM signal generator circuit 222 is configured to generate a PWM signal according to the feedback signal FB and the reference signal V ref generating a pulse width modulation (PWM) signal PWM; and

[0078] The driver circuit 220 is configured to generate a driving signal DRV for the electronic switch Q1 according to the PWM signal PWM. 1 and optionally a drive signal DRV for the electronic switch Q2 2 .

[0079] Usually, if Figure 7 As shown, the PWM signal PWM includes an on-period T in which the signal is set high. ON The switching period T SW =T ON +TOFF can be constant or variable.

[0080] Figure 8 One possible embodiment of driver circuit 220 is shown.

[0081] Specifically, in the case where the buck converter 20a includes the electronic switch Q1 and the diode D, the driver circuit 220 may include a circuit configured to generate the drive signal DRV according to the PWM signal PWM. 1 Specifically, in this case, the high-side driver circuit 2202 can receive a signal IN at the input. 1 , signal IN 1 Corresponding to the signal PWM, that is, the drive signal DRV 1 The logic level of corresponds to the logic level of the PWM signal PWM, but the signal level changes in order to correctly drive the high-side switch Q1 and also possible to achieve slew rate control.

[0082] In contrast, in the case where the buck converter 20a includes the electronic switch Q1 and the electronic switch Q2, the driver circuit 220 may include:

[0083] The high-side driver circuit 2202 is configured to 1 Generate drive signal DRV 1 ;

[0084] The low-side driver circuit 2204 is configured to 2 Generate drive signal DRV 2 ;as well as

[0085] The driver control circuit 2200 is configured to generate a signal IN for a high-side driver circuit 2202 and a low-side driver circuit 2204 according to a PWM signal PWM. 1 and IN2 .

[0086] Specifically, Figure 7 As shown, the driver control circuit 2220 can be configured to monitor the rising edge and the falling edge of the PWM signal PWM, and:

[0087] In response to detecting a rising edge, the signal IN 2 / DRV 2 (e.g., immediately) set to low and signal IN 1 / DRV 1 (immediately or preferably within the dead time DT 1 After that) is set to high; and

[0088] In response to detecting a falling edge, the signal IN1 / DRV 1 (e.g., immediately) is set to low and the signal IN 2 / DRV 2 (immediately or preferably within the dead time DT 2 After that) is set to high.

[0089] As mentioned above, this driving scheme can be used when the buck converter 20a is driven in CCM. In contrast, in DCM, the electronic switch Q2 (when used) should be turned off during the off period T OFF The driver circuit 220 is disconnected when the current flowing through the inductor L reaches zero. For example, for this purpose, the driver circuit 220 may also receive a so-called zero current signal ZC, which indicates the current I flowing through the inductor L. L Whether it reaches zero (at least in the interval T OFF Therefore, in this case, the driver control circuit 2220 can be configured to monitor the rising edge and the falling edge of the PWM signal PWM and the zero current signal ZC, and:

[0090] In response to detecting a rising edge, the signal IN 1 / DRV 1 (e.g. immediately) set to high; and

[0091] In response to detecting a falling edge, the signal IN 1 / DRV 1 (e.g. immediately) is set to low and the signal IN 2 / DRV 2 (immediately or preferably within the dead time DT 2 After that) is set to high; and

[0092] In response to detecting that the zero current signal ZC indicates that the current flowing through the inductor L is OFF period reaches zero, the signal IN 2 / DRV 2(e.g. immediately) set to low.

[0093] For example, Figure 6 As shown, the zero current signal ZC may be provided by a zero current detection circuit 224. For example, the zero current detection circuit 224 may be implemented using a comparator (so-called zero current comparator) that receives at its input a signal indicating that the zero current signal ZC is within the off period T. OFF The current I flowing through the inductor L during L Specifically, the zero current comparator can be configured to determine whether the monitored signal is below a given threshold (usually close to zero).

[0094] For example, Figure 6 As shown, the buck converter 20a may include a current sensor 26 directly connected in series with the inductor L, wherein the current sensor 26 provides a signal CS indicating a current I flowing through the inductor L. L (and preferably in proportion thereto).

[0095] Alternatively, during the off period T OFF The current I flowing through the inductor L during L The current sensor 26b may be monitored via a current sensor 26b connected directly in series with the electronic switch Q2, wherein the current sensor 26b provides a signal CSb indicative of (and preferably proportional to) the current flowing through the switch Q2 corresponding to the current flowing during the interval T OFF The current I flowing through the inductor L during L .

[0096] Therefore, the zero current comparator 224 may receive the signal CS or CSb.

[0097] To generate the PWM signal PWM, the PWM generator circuit 222 may use various solutions. Generally, these solutions have in common that, whether CCM or DCM is used, energy transfer can be adjusted by changing the duty cycle of the PWM signal DRV.

[0098] For example, in the first embodiment, the PWM generator circuit 222 is configured to directly change the duty cycle of the PWM signal PWM, for example:

[0099] When the feedback signal FB is less than the reference signal V ref When , increasing the duty cycle of the PWM signal PWM; and

[0100] When the feedback signal FB is greater than the reference signal V ref When , the duty cycle of the PWM signal PWM is reduced.

[0101] For example, for this purpose, the PWM generator circuit comprises a regulator having at least one integral component I, such as a PI or PID regulator, which is configured to be a function of the error, ie, the signal FB and V ref The difference between them changes the duty cycle of the PWM signal PWM. Generally, the PWM generator circuit can change the duty cycle of the signal PWM in the following ways:

[0102] Using a constant switching period T SW , and change the conduction period T ON ;

[0103] Using a constant on-time T ON , and change the switching period T SW ;or

[0104] Change the switching period T SW and conduction period T ON both.

[0105] In contrast, as will be described in more detail below, in a multi-phase buck converter, the PWM signal PWM is preferably generated based on the current flowing through the inductor L. This can, for example, balance the current flowing in the various stages.

[0106] Therefore, in the second solution, the PWM generator circuit 222 can be configured to monitor the indication during the conduction period T ON The current I flowing through the inductor L during L For example, this is Figure 6 , where the PWM generator circuit 222 receives the signal CS provided by the sensor 26.

[0107] Alternatively, during the conduction period T ON The current I flowing through the inductor L during L The current sensor 26a may be monitored via a current sensor 26a connected directly in series with the electronic switch Q1, wherein the current sensor 26a provides a signal CSa indicative of (preferably proportional to) the current flowing through the switch Q1 corresponding to the current flowing during the interval T ON The current I flowing through the inductor L during L .

[0108] Specifically, Fig. 9 As shown, in this case, the PWM generator circuit 222 may include:

[0109] A first regulator 2220 (inner loop) having at least one integral component I and / or a proportional component P, such as a PI or PID regulator, is configured to change the duty cycle of the PWM signal PWM according to a first error, the first error being specifically within the interval T ON The current I flowing through the inductor L duringL The difference between the average value of and the reference value REF; and

[0110] A second regulator 2222 (outer loop) having at least one integral component I, such as a PI or PID regulator, is configured to change the reference value REF according to the second error, which is specifically the feedback signal FB and the reference signal V ref The difference between.

[0111] Alternatively, the PWM generator circuit 222 may be configured to monitor the current indicating that the PWM generator circuit 222 is in the on-time period T ON The current I flowing through the inductor L during L For example, a current sensor 26 or a current sensor 26a can be used for this purpose.

[0112] Specifically, in this case, the PWM generator circuit 222 may include:

[0113] The comparator 2220 is configured to ON The current I flowing through the inductor L during L When the instantaneous value reaches the threshold TH, a signal is sent to notify the conduction interval T ON End; and

[0114] A regulator 2222 having at least one integral component I, such as a PI or PID regulator, is configured to be responsive to an error, specifically a feedback signal FB and a reference signal V ref The difference between them changes the threshold TH.

[0115] Therefore, in various embodiments, the regulation of the buck converter 20a may also be considered in the interval T ON and / or T OFF During the current I L The instantaneous and / or average values ​​of

[0116] For example, Figure 6 The current sensor shown in can be implemented using a shunt resistor, where the voltage across the shunt resistor is proportional to the current through the resistor. Alternatively, the DC resistance (DCR) of the inductor L (for sensor 26) or the resistance of the switch Q1 / Q2 (for example, the on-resistance R of the corresponding MOSFET) (for sensor 26a / 26b) can be used. DS,on (resistance between drain and source terminals in the on-state)). Other possible embodiments of a current sensor suitable for monitoring the instantaneous and / or average current in a buck converter are disclosed for example in Italian patent application 102020000028832, which is incorporated herein by reference.

[0117] Fig.10 shows n phases / stages 201 ,...,20 n Embodiment of a multi-phase buck converter.

[0118] Basically, each phase has Figure 6 The only difference in the structure shown is that all stages have the same capacitor C out (or multiple capacitors connected in parallel) are charged. Therefore, each stage 20 1 ,...,20 n The switch Q1 and the switch Q2 / diode D are connected to the switching node Lx via the corresponding inductor L. 1 ,...,L n connected to terminal 202a, wherein the switch Q1 and optionally the switch Q2 are driven by a corresponding driver circuit 220, which is configured to be driven according to a corresponding PWM modulation signal PWM 1 ,...,PWM n and optionally a zero current signal ZC to generate a drive signal DRV 1 and optionally the drive signal DRV 2 .

[0119] In the embodiment considered, the PWM generator circuit 222a can thus vary the power supplied to stage 20 1 ,...,20 n PWM modulation signal PWM 1 ,...,PWM n The duty cycle of the feedback circuit 24 is such that the signal FB provided by the feedback circuit 24 corresponds to the threshold value V ref In various embodiments, the PWM generator circuit 222 may also provide a PWM generator circuit 222 for each stage 20. 1 ,...,20 n The monitoring indicates that the current flowing through the corresponding inductor L 1 ,...,L n The current CS 1 ,...,CS n A signal, such as signal CS provided by sensor 26 or signal CSa provided by sensor 26a.

[0120] So basically, each level 20 1 ,...,20 n include:

[0121] An electronic switch Q1, and an electronic switch Q2 or a diode D;

[0122] Corresponding inductance L 1 , ..., L n ;

[0123] The current sensor provides an indication of the current flowing through the corresponding inductor L 1 ,...,L n The current I L The corresponding signal CS (instantaneous value or average value) (and preferably proportional thereto) 1 ,...,CS n ;

[0124] The driver circuit 220 is configured to generate a driving signal DRV for the electronic switch Q1 according to the PWM modulation signal. 1 and optionally a drive signal DRV for the electronic switch Q2 2 ;as well as

[0125] Optionally, in case the stage further comprises an electronic switch Q2 and can be operated in DCM, a corresponding zero current detection circuit 224 .

[0126] In contrast, the following circuit is common to multiphase buck converters:

[0127] (Multiple) output capacitors C out ;

[0128] Feedback circuit 24; and

[0129] The PWM generator circuit 222a is configured to generate a PWM signal according to the feedback signal FB and the reference signal V ref and by level 20 1 ,...,20 n The signal CS provided 1 ,...,CS n , generate PWM modulation signal PWM 1 ,...,PWM n .

[0130] For example, Fig.11 As shown, in various embodiments, the PWM generator circuit 222a may include:

[0131] For each level 20 1 ,...,20 n , the corresponding phase control circuit, such as:

[0132] Regulator 2220 having at least one integral component I and / or proportional component P 1 ,...,2220 n (Inner loop), such as a PI or PID regulator, which is configured to change the duty cycle of the PWM signal PWM according to the error, that is, the error in the corresponding conduction interval T ON1 ,...,T ONn During this period, the corresponding inductor L 1 ,...,Ln The current I L The difference between the average value of and a given reference value REF, or

[0133] Comparator 2220 1 ,...,2220 n , which is configured so that when the corresponding interval T ON1 , ..., T ONn During this period, the corresponding inductor L 1 ,...,L n The current I L When the instantaneous value of reaches a given threshold TH, a signal is sent to notify the corresponding conduction interval T ON1 ,...,T ONn End; and

[0134] A common regulator circuit 2222 having at least one integral component I, such as a PI or PID regulator, is configured to respectively ref The difference between them) changes the reference value REF or the threshold TH.

[0135] Therefore, in various embodiments, the PWM generator circuit 222a is configured to generate the PWM signal for use in stage 20. 1 ,...,20 n The common regulation signal REF or TH of the current (average or instantaneous value) flowing in the out , but the current of each stage can be controlled individually. For example, in this way the currents flowing in the various stages can be balanced to the same value.

[0136] like Fig.12 As shown, in various embodiments, the PWM generator circuit 222a, particularly the circuit 2220 1 ,...,2220 n , can be configured to generate a switching period T SW PWM signal PWM 1 ,...,PWM n , where the corresponding conduction period T ON1 ,...,T ONn Via the corresponding circuit 2220 1 ,...,2220 n In various embodiments, the PWM generator circuit 222a, in particular the circuit 2220 1 , ..., 2220 n , can be configured to generate a phase-shifted PWM signal PWM 1 , ..., PWM nFor example, in this way, each level 20 1 ,...,20 n The current peaks provided are also phase-shifted relative to one another.

[0137] In various embodiments, the circuit 2222 may also be configured to determine the number of stages k to be used, while the other nk stages are not switched. For example, the circuit 2222 may be configured to:

[0138] When the reference value REF or the threshold value TH is lower than the lower threshold value, the number k is decreased; and

[0139] When the reference value REF or the threshold value TH exceeds the upper threshold value, the number k is increased.

[0140] In general, the lower and upper thresholds may also be different for each value of k.

[0141] exist Fig.10 In the embodiment shown, the inductor L 1 ,...,L n and one or more capacitors C out is indicated as being at level 20 1 ,...,20 n The exterior, to emphasize level 20 1 ,...,20 n and possible PWM generator circuit 222, driver circuit 220 and optional electronic switches Q1 and Q2 may be implemented in one or more integrated circuits, while inductor L 1 ,...,L n and one or more capacitors C out It may be the case that one or more of these integrated circuits are externally connected to discrete components.

[0142] Typically, other control schemes can also be implemented in the PWM generator circuit to generate the PWM signal PWM 1 ,...,PWM n . For example, an alternative solution is described in the document "DocID030464Rev 1", "TN1246 Technical note: Digital multiphase constant-on-time regulator based on voltage controlled oscillator" STMicroelectronics, 2017. An improved multiphase buck converter that can have zero voltage switching is described in U.S. Patent Application No. US2019 / 0052165 A1, the contents of which are incorporated herein by reference.

[0143] Thus, a multiphase buck converter includes a plurality of phases, wherein each phase can provide a plurality of output capacitors C out Provides current pulses. In addition, by using PWM signal PWM 1 ,...,PWM n , the current pulses can be phase-shifted and the currents in the phases can be balanced. In general, as mentioned before, based on the load conditions, it may also be practical to use only a subset of the k phases.

[0144] Fig.13 An embodiment of an improved control circuit 22b for a multiphase buck converter with n phases / levels is shown. For example, such a control circuit 22b may be implemented in an integrated circuit.

[0145] Specifically, as mentioned above, the control circuit 22b includes:

[0146] Terminal, configured to receive a feedback signal FB, the feedback signal FB indicating the output voltage V generated by the multi-phase buck converter out (and preferably in proportion thereto),

[0147] n terminals, configured to receive a corresponding current sensing signal CS from each stage 1 ,...,CS n , a current sense signal is indicative of (and preferably proportional to) the current flowing through the inductor of the corresponding stage;

[0148] n terminals, configured to provide a PWM signal PWM to the driver circuit 220 of the corresponding stage 1 ,...,PWM n .

[0149] In various embodiments, the control circuit 22b may further include a circuit configured to receive a reference signal V ref The reference signal V ref Indicates (and is preferably proportional to) the requested value of the output voltage to be generated by the multi-phase buck converter.

[0150] In various embodiments, such as Fig.13 As shown, the integrated circuit of the control circuit 22b may also include a corresponding driver circuit 220 for each stage. 1 ,...,220 n Typically, as previously described, each driver circuit 220 1 ,...,220 n is configured to PWM according to the corresponding PWM signal 1 ,...,PWM n , generating a drive signal DRV for the electronic switch Q1 of the corresponding stage 1and optionally a drive signal DRV for the electronic switch Q2 of the corresponding stage 2 .

[0151] Therefore, in various embodiments, the integrated circuit of the control circuit 22b may include a circuit for feedback signal FB, signal CS 1 ,...,CS n , optionally reference signal V ref , or for PWM signal PWM 1 ,...,PWM n , or for driving signal DRV 1 and optional drive signal DRV 2 The pads of the corresponding tube die or the pins of the corresponding packaged integrated circuit.

[0152] In various embodiments, the electronic switch Q1 and the electronic switch Q2 / diode D may also be integrated in an integrated circuit. Therefore, in this case, the signal CS 1 ,...,CS n It may be generated internally, for example, by monitoring the voltage at the switching node Lx.

[0153] In the embodiment considered, the control circuit 22 b again comprises a regulator circuit 2222 configured to adjust the feedback signal FB to the reference signal V by varying the regulation value REG until the feedback signal FB corresponds to the reference signal V ref To generate the regulation value REG. As previously described, the regulator circuit 2222 may include at least an integral component (I) and optionally a proportional (P) and / or a differential (D) component.

[0154] Furthermore, in the embodiment considered, the control circuit 22b comprises n phase control circuits 2220 1 ,...,2220 n (one for each stage / phase), which is configured to be based on the corresponding current sense signal CS 1 ,...,CS n and the adjustment value REG changes the corresponding PWM signal PWM 1 ,...,PWM n The duty cycle is used to generate the corresponding PWM signal PWM 1 ,...,PWM n For example, the adjustment value REG may correspond to the current sensing signal CS 1 ,...,CS n The average value of the reference value REF or the current sensing signal CS 1 ,...,CS n Therefore, each control circuit 2220 1 ,...,2220 nThis can be achieved using corresponding comparators or additional regulators with P and / or I components.

[0155] Specifically, Fig.13 As shown, in fact, there are n phase control circuits 2220 1 ,...,2220 n Each of which receives a corresponding current sensing signal CS' 1 ,...,CS' n And generate the corresponding PWM signal PWM' 1 , ..., PWM' n In fact, in the embodiment considered, the control circuit 22b also comprises:

[0156] The first selector circuit 30′ is configured to generate a plurality of current sensing signals CS′ for each current sensing signal CS′ according to the selection signal SEL. 1 ,...,CS' n Select the corresponding current sensing signal CS 1 ,...,CS n ,as well as

[0157] The second selector circuit 32 is configured to generate a plurality of PWM signals PWM according to the selection signal SEL. 1 ,...,PWM n Select the corresponding PWM signal PWM' 1 ,...,PWM' n .

[0158] Therefore, in the embodiment considered, each pair of current sensing signals CS 1 ,...,CS n and PWM signal PWM 1 ,...,PWM n (associated with a given phase / level) can be routed to the corresponding control circuit 2220 via selector circuits 30 and 32 1 , ..., 2220 n .

[0159] In various embodiments, the control circuit 22 b therefore also includes a selection control circuit 34 configured to generate a selection signal SEL for the selector circuits 30 and 32 .

[0160] For example, the selector circuits 30 and 32 may be implemented using multiplexers or electronic switches. Typically, the control circuit 2220 is described below. 1 ,...,2220 n One or more of the control circuits 2220 may not be used. In this case, the selector circuits 30 and 32 may be configured to disconnect these unused control circuits 2220.1 ,...,2220 n .

[0161] For example, Fig.14 and Fig.15 Possible embodiments of selector circuits 30 and 32 are shown.

[0162] Specifically, in the embodiment considered, each current sensing signal CS' 1 ,...,CS' n is connected to all current sensing signals CS via corresponding electronic switches 1 ,...,CS n , such as electronic switches SC 11 , SC 12 and SC 13 For the current sensing signal CS' 1 Connect to the current sensing signal CS 1 , CS 2 , CS 3 , electronic switch SC 21 , SC 22 and SC 23 For the current sensing signal CS' 2 Connect to the current sensing signal CS 1 , CS 2 , CS 3 wait.

[0163] Similarly, in the embodiment considered, each PWM signal PWM′ 1 ,...,PWM' n Connected to all PWM signals PWM via corresponding electronic switches 1 ,...,PWM n , such as electronic switch SP 11 , SP 12 and SP 13 Used to convert PWM signal PWM' 1 Connect to PWM signal PWM 1 、PWM 2 、PWM 3 , electronic switch SP 21 , SP 22 and SP 23 Used to convert PWM signal PWM' 2 Connect to PWM signal PWM 1 、PWM 2 、PWM 3 wait.

[0164] Therefore, in the embodiment considered, the selection signal SEL may be a one-hot encoded signal that is encoded for each current sensing signal CS 1 ,...,CS n And each PWM signal PWM' 1 ,...,PWM' n Close only one electronic switch. For example, in Fig.14 and Fig.15 In the current sensing signal CS 1 and PWM signal PWM 1 is connected to the phase control circuit 2220 1 , current sensing signal CS 3 and PWM signal PWM 3 is connected to the phase control circuit 2220 2 , and the current sensing signal CS 2 and PWM signal PWM 2 Disconnect.

[0165] Usually, if Fig.16 As shown, at least a portion of the control circuit 22b may also be implemented via a digital processing circuit, such as a dedicated hardware circuit and / or a microprocessor configured to implement one or more operations of the control circuit 22a via software instructions.

[0166] For example, in Fig.16 In the embodiment, the control circuit 22b includes one or more analog-to-digital converters AD CS , which is configured to generate a current sensing signal CS 1 ,...,CS n Digital sample of CS D1 ,...,CS D2 Similarly, the control circuit 22b may include an analog-to-digital converter AD FB , which is configured to generate a digital sample of the feedback signal FB. For example, in a digital implementation, the control circuit 22b may include a circuit for receiving a reference signal V ref Therefore, generally, the circuits 30, 32, 34, 2220 and / or 2222 can be implemented via digital circuits that receive corresponding digital values. In fact, the PWM signal essentially corresponds to a digital / binary signal.

[0167] A possible embodiment of the selection control circuit 34 will be described below.

[0168] For example, in various embodiments, this may be particularly suitable when the control circuit 22b further includes a communication interface IF, such as a serial communication interface, for example, I 2C (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface Bus) communication interface, the selection control circuit 34 can be configured to use a predetermined allocation to convert the current sensing signal CS 1 ,...,CS n and PWM signal PWM 1 ,...,PWM n Connect to phase control circuit 2220 1 ,...,2220 n For example, the predetermined allocation may be received via the communication interface IF.

[0169] For example, about Fig.14 and Fig.15 , the selection control circuit 34 may receive data specifying the following via the communication interface IF:

[0170] Current sensing signal CS 1 and PWM signal PWM 1 is connected to the phase control circuit 2220 1 ,

[0171] Current sensing signal CS 3 and PWM signal PWM 3 Connected phase control circuit 2220 2 ,as well as

[0172] Current sensing signal CS 2 PWM signal 2 Disconnected.

[0173] For example, in various embodiments, the data may correspond to a bit sequence of the select signal SEL, such as “100 001000” or a coded sequence “01 11 00,” ie, corresponding to decimal values ​​“1, 3, 0,” which is decoded by the select control circuit 34 to generate the select signal SEL.

[0174] In various embodiments, the control circuit 22b may use only k phase control circuits 2220. 1 ,...,2220 n For example, as previously described, the regulator circuit 222 2 The number k may be varied based on the desired or expected load conditions. Thus, in various embodiments, the activation phase control circuit 2220 1 ,...,2220 n The number k is smaller than the number n of phases of the multi-phase buck converter.

[0175] For example, this is also Fig.13 and Fig.16 , where the selection control circuit 34 receives the value k from the regulator circuit 2222.

[0176] Specifically, in this case, the selection control circuit 34 may drive the selector circuits 30 and 32 to:

[0177] Compensating for a phase failure of a multi-phase buck converter by activating different phases of the multi-phase buck converter; and / or

[0178] The activated phase is dynamically switched to reduce the stress of the activated phase.

[0179] For example, Fig.13 and Fig.16 As shown, to determine the fault of a given phase, the selection control circuit 34 can monitor the current sensing signal CS 1 ,...,CS n (or corresponding digital samples). For example, in the case where a given phase is activated, i.e., connected to the activated phase control circuit 2220 1 ,...,2220 n And the corresponding current sensing signal CS 1 ,...,CS n If the value of is too small (load open circuit condition) and / or too high (short circuit condition), the selector circuit may connect the deactivated phase to the corresponding phase control circuit 2220. 1 ,...,2220 n .

[0180] For example, for the aforementioned embodiment, where phase 1 and phase 3 are activated and connected to the activated phase control circuit 2220 1 and 2220 2 , phase 2 is deactivated, i.e. k=2 (and n is at least 3), the selection control circuit 34 may be configured as follows:

[0181] Monitor (at least) the current sensing signal CS 1 and CS 3 ;

[0182] The current sensing signal CS 1 and CS 3 comparing with a lower threshold and / or an upper threshold;

[0183] In response to determining the current sensing signal CS 1 is less than the lower threshold or greater than the upper threshold, the selection signal SEL is set to deactivate phase 1 and connect the previously deactivated phase 2 to the activation control circuit 2220. 1 ;as well as

[0184] In response to determining the current sensing signal CS 3is less than the lower threshold or greater than the upper threshold, the selection signal SEL is set to deactivate phase 3 and connect the previously deactivated phase 2 to the activation control circuit 2220. 2 .

[0185] For example, Fig.17 An example is shown in which two of the three phases are active, i.e. k=2 and n=3, and the selection control circuit 34 is configured as:

[0186] Assign phase 1 to phase control circuit 2220 1 , and phase 2 is assigned to phase control circuit 2220 2 ;

[0187] When the corresponding current sensing signal CS 1 ,...,CS n When a fault is indicated, a corresponding fault condition signal FC is set for each of phases 1 to 3 3 , FC 2 , FC 3 ;as well as

[0188] In response to the determination signal FC 2 Indicates a fault in phase 2, changes the select signal to connect phase 3 to phase control circuit 2220 2 .

[0189] Specifically, if Fig.17 As shown, due to the phase control circuit 2220 2 First for phase 2, then for phase 3, so the signal PWM 2 and (once activated) the signal PWM 3 The same phase shift is used. Typically, once switching to another phase, the phase control circuit 2220 2 and / or regulator circuit 222 2 The regulation function may again be performed to obtain the requested output voltage.

[0190] For example, in this manner, by adding a single deactivated / unused phase that is not normally needed, the control circuit 22b can compensate for a failure of any one of the k activated phases by disconnecting the phase with the fault and connecting the previously deactivated / unused phase to the phase control circuit previously associated with the phase with the fault. In general, the selection control circuit 34 can also select the k phases from the k activated phase control circuits 2220. 1 ,...,2220 n Reorder all connections.

[0191] In fact, as mentioned above, the selection control circuit 34 can also be configured to dynamically reorder the activated phases. Specifically, as mentioned above, the regulator circuit 2222 can adapt the number k of activated phases to the current load conditions, for example, to optimize the efficiency of power conversion. However, in a conventional multi-phase converter, this may overstress the first phase that is usually always activated.

[0192] On the contrary, Fig.18 As shown, the phase selection circuit can be configured to periodically connect different subsets of the k phases to the k activated phase control circuits 2220. 1 ,...,2220 n to reorder the phases.

[0193] For example, in Fig.18 In the embodiment shown, the three phase control circuits 2220 1 ,...,2220n are in the active state, that is, k=2 and n=3. For example, in this case, it is assumed that no fault is detected (see, for example, Fig.17 ), the selection control circuit 34 may change the selection signal SEL to periodically repeat the following operations:

[0194] Connect phases 1 and 2 to activate phase control circuit 2220 1 and 2220 2 ;

[0195] Next, connect phases 2 and 3 to the active phase control circuit 2220 1 and 2220 2 ;

[0196] Next connect phases 3 and 1 to activate phase control circuit 2220 1 and 2220 2 .

[0197] Therefore, various embodiments of the present disclosure may have one or more of the following advantages:

[0198] Increased flexibility, since the external components (inductor L and optional electronic switch Q1 and electronic switch Q2 / diode D) are not constrained by the phase distribution;

[0199] Stress on external components can be reduced, thereby extending their life and improving system performance;

[0200] Improved fault management through redundancy of a minimum number of external components.

[0201] Of course, without prejudice to the principle of the present disclosure, the details of construction and of the embodiments may vary widely with respect to what is described and illustrated herein purely by way of example, without departing from the scope of the present disclosure.

[0202] For example, although in the foregoing description, the activated phase control circuit receives only one signal (i.e., the corresponding current sensing signal) from the corresponding stage of the multi-phase buck converter (in addition to the regulation signal REG), the phase control circuit may also receive further signals from the corresponding stage, such as a signal indicating the temperature of the corresponding stage. In this case, the selector circuit 32 may also be used to route additional signals associated with the same stage to a given phase control circuit.

[0203] Additionally or alternatively, the selection control circuit 34 may use such additional signals to determine a possible fault of a given stage, such as an overtemperature condition, and may connect a corresponding phase control circuit to another stage.

[0204] A control circuit (22b) for a multi-phase buck converter can be summarized as comprising: a feedback terminal configured to receive an output voltage (V out ) of the multi-phase buck converter; a plurality of current sensing terminals, wherein each current sensing terminal is configured to receive a corresponding first current sensing signal (CS) indicating a current flowing through an inductor of the corresponding stage from a corresponding stage of the multi-phase buck converter 1 , ..., CS n ); a plurality of control terminals, wherein the number (n) of the control terminals corresponds to the number (n) of the current sensing terminals, wherein each control terminal is configured to provide a corresponding first pulse width modulation (PWM) signal to a driver circuit (220) of a corresponding stage of the multi-phase buck converter 1 , ..., PWM n ), and each first PWM signal (PWM 1 , ..., PWM n ) and the corresponding first current sensing signal (CS 1 ,...,CS n ) is associated; a regulator circuit (2222) configured to adjust the regulation signal (REG) by changing the regulation signal (REG) until the feedback signal (FB) corresponds to the reference signal (V ref ) to generate a regulation signal (REG); a plurality of phase control circuits (2220 1 , ..., 2220 n ), where each phase control circuit (2220 1 , ..., 2220 n ) is configured to receive a corresponding second current sensing signal (CS'1 , ..., CS' n ) and by a corresponding second current sensing signal (CS' 1 , ..., CS' n ) and the regulating signal (REG) change the corresponding second PWM signal (PWM' 1 ,...,PWM' n ) to generate a corresponding second PWM signal (PWM' 1 ,...,PWM' n ); a first selector circuit (30) and a second selector circuit (32), which are configured to receive a selection signal (SEL) and, in response to the selection signal (SEL), select a given number (k) of the phase control circuits (2220 1 ,...,2220 n ) of each phase control circuit (2220 1 ,...,2220 n ) via the corresponding second PWM signal (PWM' 1 ,...,PWM' n ) is selectively connected to a first PWM signal (PWM 1 ,...,PWM n ) and via a corresponding second current sensing signal (CS' 1 ,...,CS' n ) is connected to the first PWM signal (PWM 1 ,...,PWM n ) associated with the first current sensing signal (CS 1 ,...,CS n ), the first PWM signal is connected to the corresponding second PWM signal (PWM' 1 ,...,PWM' n ); and a selection control circuit (34) configured to generate the selection signal (SEL), wherein the selection control circuit (34) is configured to set the selection signal (SEL) to set the given number (k) of the phase control circuits (2220) in the first switching mode. 1 ,...,2220 n ) is connected to the first PWM signal (PWM 1 ,...,PWM n ) and the associated first current sensing signal (CS 1 ,...,CS n ), and in a second switching mode, the selection signal (SEL) is set to set the given number (k) of the phase control circuits (2220 1, ..., 2220 n ) is connected to the first PWM signal (PWM 1 ,...,PWM n ) and the associated first current detection signal (CS 1 ,...,CS n )'s second set.

[0205] The regulator circuit (2222) may be configured to determine the phase control circuit (2220) to be activated according to the regulation signal (REG). 1 ,...,2220 n ) and activate the number of phase control circuits to be activated (2220 1 ,...,2220 n ); wherein the given number (k) corresponds to an activated phase control circuit (2220 1 , ..., 2220 n ) number.

[0206] Phase control circuit (2220 1 ,...,2220 n ) corresponds to or may be less than the number (n) of the current sensing terminals.

[0207] The control circuit (22b) may include a communication interface (IF), and wherein the selection control circuit (34) may be configured to activate the first switching mode or the second switching mode according to a control signal received via the communication interface (IF).

[0208] The selection control circuit (34) may be configured to select a first PWM signal (PWM) according to the control signal received via the communication interface (IF). 1 ,...,PWM n ) and the associated first current sensing signal (CS 1 ,...,CS n ) of the first set and / or the first PWM signal (PWM 1 , ..., PWM n ) and the associated first current sensing signal (CS 1 , ..., CS n ) of the second set.

[0209] The selection control circuit (34) may be configured to activate the first switching mode and monitor the phase control circuits (2220) associated with the given number (k). 1 ,...,2220 n ) connected to the first current sensing signal (CS1 ,...,CS n ) of the first subset; determining the monitored first current sensing signal (CS 1 , ..., CS n ) may be greater than an upper threshold and / or less than a lower threshold, and in response to determining whether the monitored first current sensing signal (CS 1 , ..., CS n ) can be greater than the upper threshold or less than the lower threshold, activating the second switching mode, wherein the first current sensing signal (CS 1 , ..., CS n ) does not include the monitored first current sensing signal (CS 1 , ..., CS n ).

[0210] The selection control circuit (34) may be configured to periodically activate the first switching mode and the second switching mode.

[0211] The first selector circuit (30) may include a first plurality of electronic switches for converting each second current sensing signal (CS') 1 , ..., CS' n ) is connected to each first current sensing signal (CS 1 , ..., CS n ) and wherein the second selector circuit (30) may include a second plurality of electronic switches for converting each second PWM signal (PWM' 1 , ..., PWM' n ) is connected to each first PWM signal (PWM 1 , ..., PWM n ).

[0212] The control circuit may include a plurality of driver circuits (220 1 ,...,220 n ), wherein the driver circuit (220 1 ,...,220 n ) corresponds to the number of control terminals, and each driver circuit (220 1 , ..., 220 n ) can be configured to receive the corresponding PWM signal (PWM 1 , ..., PWM n ) and generates a corresponding first drive signal (DRV) for the first electronic switch (Q1) of the corresponding stage 1 ), and optionally generating a corresponding second drive signal (DRV) for the second electronic switch (Q2) of the corresponding stage2 ).

[0213] The regulator circuit (2222) may be a regulator comprising an integral component (I) and optionally a proportional (P) and / or a differential (D) component.

[0214] Each phase control circuit (2220 1 , ..., 2220 n ) may include: a comparator configured to generate a second current sensing signal (CS') when the corresponding second current sensing signal (CS') is 1 ,...,CS' n ) in the conduction interval (T ON ) period reaches the adjustment signal (REG), notifies the corresponding second PWM signal (PWM' 1 , ..., PWM' n ) conduction interval (T ON ) ends, wherein the regulation signal (REG) represents the threshold value (TH); or another regulator having an integral component and / or a proportional component, which is configured to adjust the current according to the corresponding second current sensing signal (CS' 1 , ..., CS' n ) of the conduction interval (T ON ) during the period and the difference between the adjustment signal (REG), changing the corresponding second PWM signal (PWM' 1 ,...,PWM' n ), wherein the adjustment signal (REG) represents a reference value (REF).

[0215] The integrated circuit can be summarized as comprising the control circuit (22b) according to the aforementioned embodiments.

[0216] The multiphase buck converter can be summarized as comprising: first (200a) and second (200b) input terminals configured to receive an input voltage (V in ); first (202a) and second (202b) output terminals, configured to provide the output voltage (V out ); a capacitor (C ) connected between the first (202a) and the second (202b) output terminals out ); a feedback circuit (24) configured to generate an output voltage (V out) feedback signal (FB); a plurality of stages (20), each stage comprising an inductor (L), wherein a first terminal of the inductor (L) is connected to the first output terminal (202a); a first electronic switch (Q1) and a second electronic switch (Q2) or any one of a diode, connected between the first (200a) and the second (200b) input terminals and configured to selectively connect the second terminal of the inductor (L) to the first input terminal (200a) or the second input terminal (200b); a driver circuit (220), configured to receive a corresponding first PWM signal (PWM 1 , ..., PWM n ) and generates a corresponding first drive signal (DRV) for the first electronic switch (Q1) 1 ), and optionally generating a corresponding second drive signal (DRV) for the second electronic switch (Q2) 2 ); and a current sensor (26, 26a) configured to generate a corresponding first current sensing signal (CS) indicating a current flowing through a corresponding inductor (L) 1 ,...,CS n ); and a control circuit (222b) according to the aforementioned embodiment.

[0217] A method of operating a multi-phase buck converter by a control circuit according to any one of the preceding embodiments can be summarized as comprising: in a first switching mode, setting the selection signal (SEL) to set the given number (k) of the phase control circuits (2220 1 , ..., 2220 n ) is connected to the first PWM signal (PWM 1 , ..., PWM n ) and the associated first current sensing signal (CS 1 , ..., CS n ), and in a second switching mode, setting the selection signal (SEL) to switch the given number (k) of the phase control circuits (2220 1 , ..., 2220 n ) is connected to the first PWM signal (PWM 1 ,...,PWM n ) and the associated first current detection signal (CS 1 ,...,CS n )'s second set.

[0218] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments according to the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents required for protection by such claims. Therefore, the claims are not limited by the present disclosure.

Claims

1. A control circuit for a multi-phase buck converter, comprising: a feedback terminal configured to receive a feedback signal indicative of an output voltage generated by the multi-phase buck converter; a plurality of current sense terminals, each of the current sense terminals being configured to receive a respective first current sense signal from a respective stage of the multi-phase buck converter indicative of a current flowing through an inductor of the respective stage; a plurality of control terminals, wherein the number of the control terminals corresponds to the number of the current sensing terminals, wherein each control terminal is configured to provide a respective first pulse width modulation (PWM) signal to a driver circuit of a respective stage of the multi-phase buck converter, and each first PWM signal is associated with a respective first current sensing signal; a regulator circuit configured to generate the regulated signal by varying the regulated signal until the feedback signal corresponds to a reference signal; a plurality of phase control circuits, wherein each phase control circuit is configured to: receive a corresponding second current sensing signal, and generate a corresponding second PWM signal by changing a duty cycle of the corresponding second PWM signal according to the corresponding second current sensing signal and the adjustment signal; a first selector circuit and a second selector circuit configured to: receive a selection signal and, in response to the selection signal, selectively connect each phase control circuit in a subset of a given number of the phase control circuits to a first PWM signal via a corresponding second PWM signal and to the first current sensing signal associated with the first PWM signal via a corresponding second current sensing signal, the first PWM signal being connected to the corresponding second PWM signal; as well as A selection control circuit is configured to generate the selection signal, wherein the selection control circuit is configured to: in a first switching mode, setting the selection signal so as to connect the given number of the phase control circuits to a first set of a first PWM signal and an associated first current sensing signal, and In a second switching mode, the selection signal is set to connect the given number of the phase control circuits to a second set of first PWM signals and associated first current sensing signals.

2. The control circuit of claim 1 , wherein the regulator circuit is configured to: determining the number of phase control circuits to be activated according to the adjustment signal; and activating the number of said phase control circuits to be activated, The given number corresponds to the number of activated phase control circuits. 3 . The control circuit according to claim 1 , wherein the number of the phase control circuits corresponds to or is less than the number of the current sensing terminals. 4 . The control circuit of claim 1 , wherein the control circuit comprises a communication interface, and wherein the selection control circuit is configured to activate the first switching mode or the second switching mode according to a control signal received via the communication interface.

5. The control circuit of claim 4 , wherein the selection control circuit is configured to select a first set of the first PWM signal and the associated first current sensing signal, or select a second set of the first PWM signal and the associated first current sensing signal, based on the control signal received via the communication interface.

6. The control circuit according to claim 1, wherein the selection control circuit is configured to: activating the first switching mode and monitoring a first subset of the first current sense signals connected to the given number of the phase control circuits; determining whether the monitored first current sensing signal is greater than an upper threshold or less than a lower threshold; as well as In response to determining that the monitored first current sensing signal is greater than the upper threshold or less than the lower threshold, the second switching mode is activated, wherein the second set of the first current sensing signals does not include the monitored first current sensing signal. 7 . The control circuit of claim 1 , wherein the selection control circuit is configured to periodically activate the first switching mode and the second switching mode.

8. The control circuit of claim 1 , wherein the first selector circuit comprises a first plurality of electronic switches configured to connect each second current sensing signal to each first current sensing signal, and wherein the second selector circuit comprises a second plurality of electronic switches configured to connect each second PWM signal to each first PWM signal.

9. The control circuit according to claim 1, comprising: A plurality of driver circuits, wherein the number of the driver circuits corresponds to the number of the control terminals, and wherein each driver circuit is configured to receive a corresponding PWM signal and generate a corresponding first drive signal for a first electronic switch of a corresponding stage.

10. The control circuit of claim 9, wherein each of the driver circuits is configured to receive a respective second drive signal for a second electronic switch of a respective stage.

11. The control circuit of claim 1 , wherein the regulator circuit is a regulator, the regulator comprising: Integral components; and at least one of a proportional component or a derivative component.

12. The control circuit of claim 1 , wherein each of the phase control circuits comprises at least one of the following: a comparator configured to signal an end of an on-interval of the corresponding second PWM signal when an instantaneous value of the corresponding second current sensing signal reaches the regulation signal during the on-interval, wherein the regulation signal represents a threshold value, or Another regulator has an integral component or a proportional component, and is configured to change the duty cycle of the corresponding second PWM signal according to the difference between the average value of the corresponding second current sensing signal during the conduction interval and the adjustment signal, wherein the adjustment signal represents a reference value.

13. An integrated circuit comprising: A control circuit for a multi-phase buck converter, the control circuit comprising: a feedback terminal configured to receive a feedback signal indicative of an output voltage generated by the multi-phase buck converter; a plurality of current sense terminals, each of the current sense terminals being configured to receive a respective first current sense signal from a respective stage of the multi-phase buck converter indicative of a current flowing through an inductor of the respective stage; a plurality of control terminals, wherein the number of the control terminals corresponds to the number of the current sensing terminals, wherein each control terminal is configured to provide a respective first pulse width modulation (PWM) signal to a driver circuit of a respective stage of the multi-phase buck converter, and each first PWM signal is associated with a respective first current sensing signal; a regulator circuit configured to generate the regulated signal by varying the regulated signal until the feedback signal corresponds to a reference signal; a plurality of phase control circuits, wherein each phase control circuit is configured to: receive a corresponding second current sensing signal, and generate a corresponding second PWM signal by changing a duty cycle of the corresponding second PWM signal according to the corresponding second current sensing signal and the adjustment signal; a first selector circuit and a second selector circuit configured to: receive a selection signal and, in response to the selection signal, selectively connect each phase control circuit in a subset of a given number of the phase control circuits to a first PWM signal via a corresponding second PWM signal, and selectively connect to the first current sensing signal associated with the first PWM signal via a corresponding second current sensing signal, the first PWM signal being connected to the corresponding second PWM signal; and A selection control circuit is configured to generate the selection signal, wherein the selection control circuit is configured to: in a first switching mode, setting the selection signal so as to connect the given number of the phase control circuits to a first set of a first PWM signal and an associated first current sensing signal, and In a second switching mode, the selection signal is set to connect the given number of the phase control circuits to a second set of first PWM signals and associated first current sensing signals.

14. The integrated circuit of claim 13, wherein the regulator circuit is configured to: determining the number of phase control circuits to be activated according to the adjustment signal; and activating the number of phase control circuits to be activated, The given number corresponds to the number of activated phase control circuits. 15 . The integrated circuit of claim 13 , wherein the number of the phase control circuits corresponds to or is less than the number of the current sensing terminals. 16 . The integrated circuit of claim 13 , wherein the control circuit comprises a communication interface, and wherein the selection control circuit is configured to activate the first switching mode or the second switching mode according to a control signal received via the communication interface.

17. A multiphase buck converter comprising: A first input terminal and a second input terminal configured to receive an input voltage; A first output terminal and a second output terminal configured to provide an output voltage; a capacitor connected between the first output terminal and the second output terminal; a feedback circuit configured to generate a feedback signal indicative of the output voltage; as well as A plurality of stages, each of said stages comprising: an inductor, wherein a first terminal of the inductor is connected to the first output terminal, a first electronic switch, and at least one of a second electronic switch or a diode, connected between the first input terminal and the second input terminal and configured to selectively connect the second terminal of the inductor to the first input terminal or the second input terminal, a driver circuit configured to receive a corresponding first PWM signal and generate a corresponding first drive signal for the first electronic switch, and a current sensor configured to generate a respective first current sensing signal indicative of a current flowing through a respective said inductor; and Control circuit, including: a feedback terminal configured to receive a feedback signal indicative of an output voltage generated by the multi-phase buck converter; a plurality of current sensing terminals, each of the current sensing terminals being configured to receive a respective first current sensing signal from a respective stage of the multi-phase buck converter indicative of a current flowing through an inductor of the respective stage; a plurality of control terminals, wherein the number of the control terminals corresponds to the number of the current sensing terminals, wherein each control terminal is configured to provide a respective first pulse width modulation (PWM) signal to a driver circuit of a respective stage of the multi-phase buck converter, and each first PWM signal is associated with a respective first current sensing signal; a regulator circuit configured to generate the regulated signal by varying the regulated signal until the feedback signal corresponds to a reference signal; a plurality of phase control circuits, wherein each phase control circuit is configured to: receive a corresponding second current sensing signal, and generate a corresponding second PWM signal by changing a duty cycle of the corresponding second PWM signal according to the corresponding second current sensing signal and the adjustment signal; a first selector circuit and a second selector circuit configured to: receive a selection signal and, in response to the selection signal, selectively connect each phase control circuit in a subset of a given number of the phase control circuits to a first PWM signal via a corresponding second PWM signal, and selectively connect to the first current sensing signal associated with the first PWM signal via a corresponding second current sensing signal, the first PWM signal being connected to the corresponding second PWM signal; and A selection control circuit is configured to generate the selection signal, wherein the selection control circuit is configured to: in a first switching mode, setting the selection signal so as to connect the given number of the phase control circuits to a first set of a first PWM signal and an associated first current sensing signal, and In a second switching mode, the selection signal is set to connect the given number of the phase control circuits to a second set of first PWM signals and associated first current sensing signals.

18. The multi-phase buck converter of claim 17, wherein the driver circuit of each of the plurality of stages is configured to generate a respective second drive signal for the second electronic switch.

19. A method of operating a multiphase buck converter via a control circuit, the control circuit comprising: a feedback terminal configured to receive a feedback signal indicative of an output voltage generated by the multi-phase buck converter; a plurality of current sensing terminals, each of the current sensing terminals being configured to receive a respective first current sensing signal from a respective stage of the multi-phase buck converter indicative of a current flowing through an inductor of the respective stage; a plurality of control terminals, wherein the number of the control terminals corresponds to the number of the current sensing terminals, wherein each control terminal is configured to provide a respective first pulse width modulation (PWM) signal to a driver circuit of a respective stage of the multi-phase buck converter, and each first PWM signal is associated with a respective first current sensing signal; a regulator circuit configured to generate the regulation signal by varying the regulation signal until the feedback signal corresponds to a reference signal; a plurality of phase control circuits, wherein each phase control circuit is configured to: receive a corresponding second current sensing signal, and generate a corresponding second PWM signal by changing a duty cycle of the corresponding second PWM signal according to the corresponding second current sensing signal and the adjustment signal; a first selector circuit and a second selector circuit configured to: receive a selection signal and, in response to the selection signal, selectively connect each phase control circuit in a subset of a given number of the phase control circuits to a first PWM signal via a corresponding second PWM signal and to the first current sensing signal associated with the first PWM signal via a corresponding second current sensing signal, the first PWM signal being connected to the corresponding second PWM signal; as well as A selection control circuit is configured to generate the selection signal, wherein the selection control circuit is configured to: in a first switching mode, setting the selection signal so as to connect the given number of the phase control circuits to a first set of a first PWM signal and an associated first current sensing signal, and In a second switching mode, the selection signal is set to connect the given number of the phase control circuits to a second set of first PWM signals and associated first current sensing signals.

20. The method according to claim 19, further comprising: determining, by the regulator circuit based on the regulation signal, the number of phase control circuits to be activated; as well as activating the number of phase control circuits to be activated by the regulator circuit, The given number corresponds to the number of activated phase control circuits.

Images