Electronic circuit with thyristors

Abstract

Embodiments of the present disclosure relate to electronic circuits with thyristors. The present specification relates to a converter comprising an AC-DC conversion stage comprising: a first thyristor; a first power supply circuit delivering a first reference voltage between a first node and a second node; and a second power supply circuit delivering a second reference voltage between a third node and a fourth node, a cathode of the first thyristor being coupled to the first node of the first power supply circuit and connected to the fourth node through a first switch, the second power supply circuit comprising a first rectifying element coupled to the second node of the first power supply circuit and coupled to the third node.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to a French patent application filed on May 7, 2021, entitled “ELECTRONIC CIRCUIT WITHTHYRISTOR”, which is incorporated by application to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates generally to electronic circuits, and more specifically to AC-DC converters with thyristors. Background Technology

[0004] Examples of this type of circuit involve AD / DC converters equipped with power factor correction (PFC) functionality. For instance, AC-DC converters are used in motor control circuits, chargers, switching power supplies, etc.

[0005] In particular, there are AC-DC converters with a bridgeless architecture, such as "totem pole," H-bridge, or hybrid active bridge converters, which include two switches controlled by pulse width modulation. AC-DC converters with thyristors include at least one thyristor. One or more thyristors are specifically used to limit inrush current during converter operation or to shorten the inrush current limiting resistor after the pre-charge phase of the capacitor located at the DC voltage output.

[0006] The disadvantage is that a circuit must be provided to power each thyristor, and such a power supply circuit may have a complex structure, occupy a large surface area on the converter, and have a high cost. Summary of the Invention

[0007] The embodiments overcome all or some of the disadvantages of AC-DC converters with thyristors.

[0008] An embodiment provides a converter including an AC-DC conversion stage, comprising: a first thyristor; a first power supply circuit supplying a first reference voltage between a first node and a second node; and a second power supply circuit supplying a second reference voltage between a third node and a fourth node, wherein the cathode of the first thyristor is coupled to the first node of the first power supply circuit and connected to the fourth node via a first switch, and the second power supply circuit includes a first rectifier element coupled to the second node of the first power supply circuit and coupled to the third node.

[0009] According to an embodiment, the first rectifier element is a first diode.

[0010] According to an embodiment, the second power supply circuit includes a first capacitor, which includes a first electrode connected to the cathode of the first thyristor.

[0011] According to an embodiment, the first switch is a first MOS transistor.

[0012] According to an embodiment, the first switch is a second diode.

[0013] According to an embodiment, the AC-DC conversion stage includes: a first terminal and a second terminal for receiving AC voltage; and a third terminal and a fourth terminal for delivering DC voltage.

[0014] According to an embodiment, before the steady state, during the positive half-wave of the AC voltage, after the DC voltage exceeds a threshold, the first power supply voltage is activated so that subsequently, when the first switch is controlled to the on state, the first capacitor is charged by the current flowing through the first rectifier element.

[0015] According to an embodiment, the converter further includes a second MOS transistor that couples a first node of the first power supply circuit to a fourth terminal, and a third terminal is connected to the cathode of the first thyristor, and a second terminal is connected to the anode of the first thyristor.

[0016] According to an embodiment, the converter further includes a second MOS transistor that is inductively coupled to a first node of a first power supply circuit and connected to a fourth terminal, a third terminal connected to the cathode of a first thyristor, and a second terminal connected to the anode of a first thyristor.

[0017] According to an embodiment, the second terminal is connected to the anode of the first thyristor, and the first terminal is inductively coupled to the first node of the first power supply circuit.

[0018] According to an embodiment, the converter further includes a second MOS transistor coupled to a first node of a first power supply circuit, a second terminal connected to the cathode of a first thyristor, a first terminal inductively coupled to the second MOS transistor, and the anode of the first thyristor connected to a fourth terminal.

[0019] According to an embodiment, the converter further includes a second thyristor, the cathode of which is connected to the cathode of the first thyristor, and the first terminal is connected to the anode of the second thyristor.

[0020] According to an embodiment, the first terminal is inductively coupled to the first MOS transistor, and the second terminal is connected to the cathode of the first thyristor, while the anode of the first thyristor is coupled to the fourth terminal.

[0021] According to an embodiment, the converter includes a second switch that couples the cathode of the first thyristor to a fourth terminal.

[0022] According to an embodiment, the AC-DC conversion stage includes: a first terminal and a second terminal for receiving AC voltage; and a third terminal and a fourth terminal for delivering DC voltage.

[0023] According to an embodiment, the converter includes: a second thyristor connected in series with a first thyristor; a third power supply circuit that delivers a third reference voltage between a fourth terminal and a fifth node; and a fourth power supply circuit that delivers a fourth reference voltage between a sixth node and a seventh node, wherein the cathode of the second thyristor is connected to the seventh node, and the fourth power supply circuit includes a second rectifier element coupled to the fifth node of the third power supply circuit.

[0024] According to an embodiment, the second rectifier element is a third diode.

[0025] According to an embodiment, the fourth power supply circuit includes a second capacitor, which includes a first electrode connected to the midpoint between the first thyristor and the second thyristor.

[0026] According to an embodiment, the converter includes a fourth diode and a fifth diode, which are coupled in series between the third terminal and the fourth terminal.

[0027] According to an embodiment, the converter includes a second thyristor connected in series with the first thyristor, and the midpoint of the fourth and fifth diodes is coupled to the midpoint of the first and second thyristors through a first resistor.

[0028] According to an embodiment, the converter includes a first MOS transistor and a second MOS transistor, which are coupled in series between a third terminal and a fourth terminal. The second rectifier element is a third diode, and before the steady state, during the positive half-wave of the AC voltage, the second capacitor is charged by the current flowing through the first diode and the fifth diode.

[0029] According to an embodiment, the converter includes a second thyristor connected in series with a first thyristor, wherein the first thyristor is a cathode-gate thyristor and the second thyristor is a cathode-gate thyristor.

[0030] According to an embodiment, the converter includes a second thyristor connected in series with a first thyristor, the first thyristor being a cathode-gate thyristor, and the second thyristor being an anode-gate thyristor controlled by a positive gate current or a negative gate current.

[0031] According to the embodiment, the reference voltage is a voltage with a constant time average value of less than 10% under steady-state conditions, where the ripple factor is equal to the ratio of the RMS value of the AC component (ripple component) in the voltage to the DC component in the voltage. Attached Figure Description

[0032] The above-described features and advantages, as well as other features and advantages, will be described in detail below with reference to the accompanying drawings, in which:

[0033] Figure 1 An embodiment of the typical architecture of a so-called "totem pole" AC-DC power factor correction converter is shown in part and schematically.

[0034] Figure 2 Partially and schematically shown Figure 1 An example of the power supply circuit for the converter;

[0035] Figure 3 An embodiment based on converter operation is shown. Figure 1 Timing diagrams of voltage and current of the converter;

[0036] Figure 4 The diagram illustrates the operation phase. Figure 1 Current flow in the converter;

[0037] Figure 5 It shows Figure 3 A detailed view of the timing diagram;

[0038] Figure 6 It shows Figure 3 Another detailed view of the timing diagram;

[0039] Figure 7 Another embodiment of the converter operation is shown. Figure 1 Timing diagrams of voltage and current of the converter;

[0040] Figure 8 Another embodiment of the electronic circuit is shown in part and schematically, including a so-called "totem pole" AC-DC power factor correction converter and an arm with a downstream converter (which is of DC / DC or DC / AC type);

[0041] Figure 9 An embodiment based on circuit operation is shown. Figure 8 The timing diagram of voltage and current in the circuit;

[0042] Figure 10 Partially and schematically shown Figure 8 An example of a power supply circuit for a given circuit;

[0043] Figure 11 It shows Figure 9 Detailed views of the timing diagrams and other timing diagrams;

[0044] Figure 12Another embodiment of the electronic circuit is shown in part and schematically, including a so-called "totem pole" AC-DC power factor correction converter and a downstream DC / DC power converter stage.

[0045] Figure 13 An embodiment of a rectifier-type so-called "totem pole" AC-DC converter is shown in part and schematically.

[0046] Figure 14 An embodiment of the typical architecture of a so-called "totem pole" AC-DC power factor correction converter is shown in part and schematically.

[0047] Figure 15 An embodiment based on converter operation is shown. Figure 14 Timing diagrams of voltage and current of the converter;

[0048] Figure 16 The diagram illustrates the process during the first operational phase. Figure 14 The current flow of the converter;

[0049] Figure 17 The diagram illustrates the process during the second operation phase. Figure 14 The current flow of the converter;

[0050] Figure 18 Another embodiment of the so-called "totem pole" AC-DC power factor correction converter is shown in part and schematically.

[0051] Figure 19 Another embodiment of the so-called "totem pole" AC-DC power factor correction converter is shown in part and schematically.

[0052] Figure 20 An embodiment based on converter operation is shown. Figure 19 The timing diagram of voltage and current in the circuit;

[0053] Figure 21 An embodiment of an AC-DC power factor correction converter with a three-way switch is shown in part and schematically.

[0054] Figure 22 An embodiment based on converter operation is shown. Figure 21 Timing diagrams of voltage and current of the converter;

[0055] Figure 23 The diagram illustrates the process during the operation phase. Figure 1 The current flow of the converter;

[0056] Figure 24 It shows Figure 22 A detailed view of the timing diagram;

[0057] Figure 25 The diagram illustrates the process during the operation phase. Figure 21 The current flow of the converter;

[0058] Figure 26 It shows Figure 22 A detailed view of the timing diagram;

[0059] Figure 27 Another embodiment of an AC-DC power factor correction converter with a three-way switch is shown in part and schematically.

[0060] Figure 28 An embodiment based on converter operation is shown. Figure 27 Timing diagrams of voltage and current of the converter;

[0061] Figure 29 The diagram illustrates the process during the operation phase. Figure 27 The current flow of the converter;

[0062] Figure 30 It shows Figure 28 A detailed view of the timing diagram;

[0063] Figure 31 An embodiment based on converter operation is shown. Figure 27 Timing diagrams of voltage and current of the converter;

[0064] Figure 32 It shows Figure 31 A detailed view of the timing diagram;

[0065] Figure 33 The diagram illustrates the process during the operation phase. Figure 27 The current flow of the converter;

[0066] Figure 34 Another embodiment of an AC-DC converter with a three-way switch and power factor correction is shown in part and schematically.

[0067] Figure 35 Another embodiment of an AC-DC converter with a three-way switch and power factor correction is shown in part and schematically; and

[0068] Figure 36 An embodiment of the circuit, including a hybrid active bridge AC-DC converter, is shown in part and schematically. Detailed Implementation

[0069] In all the figures, the same features are specified by the same references. Specifically, structural and / or functional features common in various embodiments may have the same references and may all deal with the same structure, dimensions, and material properties.

[0070] For clarity, only steps and elements useful for understanding the embodiments described herein are detailed and described. Specifically, circuitry powered by the converter is not described in detail, and the described embodiments are compatible with general applications.

[0071] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected by one or more other elements or that they can be coupled by one or more other elements.

[0072] Unless otherwise stated, the expressions “approximately,” “about,” “generally,” and “approximately” indicate within 10%, and preferably within 5%.

[0073] Figure 1 An embodiment of a "totem pole" AC-DC power factor correction converter 10 is schematically illustrated. For example, converter 10 is used to deliver DC voltage to the on-board network of a motor vehicle.

[0074] The two input terminals 12 and 14 are designed to receive AC voltage V. ac For example, the voltage of a power distribution network (e.g., 230V or 120V, 50Hz or 60Hz). The two output terminals 16 and 18 deliver DC voltage V. dc Terminal 18 defines a reference potential, typically ground. Output terminals 16 and 18 can be connected to another circuit, such as a DC / DC converter or a DC / AC converter.

[0075] Terminal 12 is coupled to a first terminal of an inductor L_PFC, which has a second terminal coupled to the midpoint 20 of the series association of two switches M_HS and M_LS between terminals 16 and 18. According to an embodiment, each switch M_HS, M_LS corresponds to a enhancement-mode MOS transistor, such as an N-type transistor. The drain of the MOS transistor M_HS is coupled to, preferably connected to, terminal 16, and the source of the MOS transistor M_HS is coupled to, preferably connected to, midpoint 20. GS_HS This is the voltage between the gate of transistor M_HS and midpoint 20. The drain of MOS transistor M_LS is coupled to, preferably connected to, midpoint 20, and the source of transistor MOS M_LS is coupled to, preferably connected to, terminal 18. V is referred to as V. GS_LS This is the voltage between the gate of transistor M_LS and terminal 18.

[0076] Terminal 14 is connected to the midpoint 22 of the series connection between terminals 16 and 18 of two thyristors SCR_F1 and SCR_F2. The anode of thyristor SCR_F2 is connected to terminal 18, and the cathode of thyristor SCR_F1 is connected to terminal 16. Figure 1 In this embodiment, thyristor SCR_F1 has a cathode gate, and thyristor SCR_F2 has a cathode gate. The gate of thyristor SCR_F1 receives control signal G_F1. The gate of thyristor SCR_F2 receives control signal G_F2. (The last part, "V," appears to be a typo and can be omitted.) SCR_F2 This is the voltage between the cathode and anode of the thyristor SCR_F2.

[0077] Resistor R_ICL connects the midpoint 22 to the midpoint 24 of the series connection between terminals 16 and 18 of two diodes D1 and D2, with the anode of diode D2 connected to terminal 18 and the cathode of diode D1 connected to terminal 16. Storage and smoothing capacitor C_DC connects terminal 18 to terminal 16.

[0078] Converter 10 also includes: a power supply circuit SHS, which delivers a reference voltage V. DD_HS ; and power supply circuit 30, which supplies reference voltage V C_FL1 The power supply circuit 30 includes a diode DFL, a resistor RFL, a capacitor C_FL1, and a Zener diode DZ. In this embodiment, the negative terminal of the source SHS is coupled to, preferably connected to, midpoint 20, and the positive terminal of the source SHS is coupled to, preferably connected to, the anode of the diode DFL. The cathode of the diode DFL is coupled to, preferably connected to, a terminal of the resistor RFL. The other terminal of the resistor RFL is coupled to, preferably connected to, an electrode of the capacitor C_FL1. The other electrode of the capacitor C_FL1 is coupled to, preferably connected to, terminal 16. The diode DC is connected in parallel with the capacitor C_FL1, and the anode of the Zener diode DZ is coupled to, preferably connected to, terminal 16. The positions of the diode DFL and the resistor RFL can be reversed. The resistor RFL and the Zener diode DZ may be absent. Reference voltage V C_FL1 This corresponds to the voltage across capacitor C_FL1.

[0079] Converter 10 may include other power supply circuitry. Figure 1 The circuit ALIM is shown as an example for delivering a reference voltage V across capacitor C_LS. DD and the reference voltage V across capacitor C_FL2 DDins One electrode of capacitor C_FL2 is coupled to, preferably connected to, midpoint 22. The other electrode of capacitor C_FL2 is coupled to, preferably connected to, the terminal of circuit ALIM to deliver voltage V. DDinsOne electrode of capacitor C_LS is coupled to, preferably connected to, terminal 18. The other electrode of capacitor C_LS is coupled to, preferably connected to, a terminal of circuit ALIM to deliver voltage V. DD Another terminal of the circuit ALIM is coupled to, and preferably connected to, terminal 16. The circuit ALIM receives a DC voltage V. dc Then, based on this, the transmission voltage V is given. DD and V DDins As a variant, the ALIM circuit can receive rectified voltage from terminals 12 and 14.

[0080] In addition, the switch (not shown) can be inserted between terminals 12 and 14 on one hand, and between inductor L_PFC and midpoint 22 on the other hand.

[0081] Electronic circuit 50 (e.g., a microcontroller (μC)) receives a reference voltage V C_FL1 Generate pulses for controlling thyristor SCR_F1 and, for example, from reference voltage V DDins A pulse is generated to control thyristor SCR_F2. Microcontroller 50 controls the gates of thyristors G_F1 and G_F2 via one or both isolation couplers 52 using optical, magnetic, or capacitive techniques. As an example, coupler 52 includes a phototransistor that uses a reference voltage V. C_FL1 Power is supplied and coupled to the gate G_F1. This phototransistor is controlled by light pulses emitted by a light-emitting diode controlled by a microcontroller 50. The microcontroller 50 receives different setpoints CT or measurements to turn on thyristors SCR_F1 and SCR_F2 at the correct time, thereby performing full-wave control in steady state and / or phase angle change control during startup. Transistors MOS M_HS and M_LS are controlled by a control circuit (not shown) or the microcontroller 50.

[0082] Figure 2 An embodiment of the power supply circuit SHS is illustrated. The power supply circuit SHS includes a diode D_HS and a capacitor C_HS. One electrode of the capacitor C_HS is coupled to, preferably connected to, midpoint 20. The other electrode of the capacitor C_HS is coupled to, preferably connected to, the anode of the diode DFL. The anode of the diode D_HS is coupled to, preferably connected to, the terminal of the circuit ALIM. Figure 2 (not shown in the image) to transmit voltage V DD The cathode of diode D_HS is coupled to, and preferably connected to, the electrode of capacitor C_HS (not coupled to midpoint 20), and therefore also coupled to the anode of diode DFL. Reference voltage V DD_HS This corresponds to the voltage across capacitor C_HS. In the following description, generally, the power supply circuit SHS delivers the reference voltage V. DD_HSOr, capacitor C_HS delivers reference voltage V DD_HS .

[0083] Under steady-state conditions, the thyristor SCR_F1 is subjected to the voltage V referenced at terminal 14. ac It is turned on during each negative half-wave period, possibly intermittently, and keeps the thyristor SCR_F2 at the same voltage V. ac The transistor is switched on during each positive half-wave period, possibly intermittently. According to an embodiment, at least in the steady state, transistors M_HS and M_LS are controlled in opposite ways. This means that, at least in the steady state, when transistor M_LS is controlled to be on, transistor M_HS is controlled to be off, and when transistor M_LS is controlled to be off, transistor M_HS is controlled to be on. In the steady state, at voltage V... ac During the positive half-wave, thyristor SCR_F2 is turned on, and terminal 18, i.e., the output voltage V, is connected. dc The reference potential is coupled to terminal 14. Switch M_LS is controlled by pulse width modulation (PWM), and switch M_HS acts as a flywheel diode when switch M_LS is off. At voltage V ac During the negative half-wave, thyristor SCR_F1 is turned on and couples terminal 14 to terminal 16, i.e., the output voltage V... dc The high potential. Switch M_HS is controlled by pulse modulation, and switch M_LS acts as a flywheel diode when switch M_HS is off.

[0084] V DS_HS The drain-source voltage of transistor M_HS is called I. L The current flowing through inductor L_PFC is positive when it flows from terminal 12 to midpoint 20, and is called I. DFL The current flowing through the diode DFL is positive when it flows from the anode to the cathode.

[0085] The operation of circuit 10 will now be described in more detail.

[0086] Figure 3 Showing the target Figure 1 An embodiment of the operation method of circuit 10, during the first charging period after steady-state operation, the voltage V of circuit 10 is... C_FL1 V DD_HS V GS_HS V dc and V DS_HS and current I L and I DFL The timing diagram. Figure 3 In this context, times t0, t0', t1, t2, and t3 are continuous. Voltage V ac ( Figure 3 (Not shown in the figure) It exhibits a positive half-wave between times t0 and t1 and between times t2 and t3, and a negative half-wave between times t1 and t2.

[0087] Figure 4 It is similar to Figure 1 The diagram only shows some electronic components and illustrates the current I in the steady state. DFL Flow in converter 10.

[0088] Figure 5 yes Figure 3 The time series diagram is a magnified view at time t1, and Figure 6 During the negative half-wave Figure 3 A magnified view of the time sequence diagram after time t2.

[0089] Between times t0 and t1, during the first charge, switches M_HS and M_LS are not controlled to be turned on, and thyristors SCR_F1 and SCR_F2 are controlled to be turned off. Capacitor C_DC is charged at voltage V. ac The first positive half-wave pre-charges the system. Positive current I L The current I flows through the internal diode of transistor M_HS and diode D2. L The voltage increases from 0A, passes through its maximum value, and then decreases back to 0A. (Voltage V) dc It has risen to a stable level.

[0090] After the capacitor C_DC is charged and before steady-state operation begins, the power supply circuit SHS is activated, which leads to... Figure 3 The voltage V in DD_HS The time t0' between time t0 and t1 increases. In signal V ac When the first negative half-wave is in a stable state between times t1 and t2, when transistor M_HS is turned on for the first time at time t1, capacitor C_FL1, through diode DFL, resistor RFL, and transistor M_HS, is subjected to voltage V DD_HS Charging. Then, whenever transistor M_HS is turned on, or through the internal diode of transistor M_HS, capacitor C_FL1 is recharged. This internal diode guides current from node 20 to terminal 16, where the current is much greater than the current flowing in the opposite direction from DFL from terminal 16 to node 20. This ensures that the internal diode of transistor M_HS remains on, and transistor M_HS is not controlled to be turned on. This operation also ensures reduced turn-on losses when the channel of M_HS is activated.

[0091] The steady-state operation of circuit 10 begins at time t1.

[0092] In a steady state, at voltage Vac During each positive half-wave period, thyristor SCR_F2 is turned on, and voltage V SCR_F2 Then it equals 0V, and at voltage V ac During each negative half-wave period, thyristor SCR_F2 is deactivated, and voltage V SCR_F2 This is then equal to the voltage between terminals 16 and 18, for example, approximately -400V. At voltage V ac During each positive half-wave period, thyristor SCR_F1 is turned off, and at voltage V ac During each negative half-wave period, thyristor SCR_F1 is turned on. Additionally, transistor M_HS is turned on at voltage V. ac Each negative half-wave period is controlled by PWM, for example, a voltage V alternating between approximately 15V and 0V. GS_HS And is shown as at voltage V ac It is turned off during each positive half-wave period, with voltage VGS_HS at 0V, to simplify the timing diagram. Even in practice, it is controlled in the opposite way to transistor M_LS during each positive half-wave period, especially turning on during the flywheel phase, as previously described. Furthermore, transistor M_LS is turned on at voltage V... ac Each positive half-wave period is controlled by PWM, for example, alternating between approximately 5V and -10V, with the voltage V decreasing by 10V. GS_LS And is shown as at voltage V ac It is turned off during each negative half-wave period, voltage V GS_LS The voltage was reduced by 10V, then equaled to approximately -10V to simplify the timing diagram. Even in practice, it is controlled in the opposite manner to transistor M_HS during each negative half-wave, especially during the flywheel phase, as previously described. When thyristor SCR_F2 is on and switch M_LS is on, the current I... L The current flows from terminal 12, through inductor L_PFC, transistor M_LS and thyristor SCR_F2, all the way to terminal 14.

[0093] Advantageously, the Zener diode DZ makes it possible to set the voltage V across capacitor C_FL1. C_FL1 The maximum value. A different circuit for setting the voltage of capacitor C_FL1 can be used instead of Zener diode DZ.

[0094] Figure 7 It is similar to Figure 3 The diagram shows the target... Figure 1 In another embodiment of the operation method of circuit 10, during the first charging period after the steady state, the voltage V of circuit 10 is... C_FL1 V GS_HS V GS_LS V dc V acand V DS_HS and current I L and I DFL The timing diagram. Figure 7 In the example, at time t1, the steady-state operation of the circuit is determined by the voltage V. ac The positive half-wave begins, voltage V ac First, a positive half-wave is observed between times t0 and t1', and a negative half-wave is observed between t1' and t2.

[0095] In this embodiment, the first charging of capacitor C_FL1 is achieved by turning on transistor M_HS during the first positive half-wave of voltage Vac, which corresponds to the signal V before time t1'. GS_HS The high-state setting. The capacitor C_FL1 is then recharged in the steady state, as previously described, whenever transistor M_HS is turned on or through the internal diode of transistor M_HS, while transistor M_HS is not controlled to be turned on.

[0096] Figure 8 An embodiment of circuit 60 is shown in part and schematically, including an AC-DC converter 62 coupled to another circuit 64, only partially shown. Figure 8 The following are illustrated, for example, DC / DC converters or DC / AC converters. Converter 64 includes a series connection of two switches M1 and M2 between two terminals 16 and 18. Converter 62 includes all the elements of converter 10, except that, for converter 60, the electrode of capacitor C_HS of power supply circuit SHS is coupled to the midpoint 56 of the two switches M1 and M2, and for converter 10, this electrode is coupled to the midpoint 20 of the two switches M_HS and M_LS. According to an embodiment, each switch M1, M2 corresponds to a enhancement MOS transistor, such as an N-type. The drain of MOS transistor M1 is coupled to, preferably connected to, terminal 16, and the source of MOS transistor M1 is coupled to, preferably connected to, midpoint 56. The drain of MOS transistor M2 is coupled to, preferably connected to, midpoint 56, and the source of MOS transistor M2 is coupled to, preferably connected to, terminal 18.

[0097] V G_F1 The voltage at the gate G_F1 of the thyristor SCR_F1 is called V. G_F2 The voltage at the gate G_F2 of the thyristor SCR_F2 is called I. L The current flowing through inductor L_PFC is positive when it flows from terminal 12 to midpoint 20, and is called I. DHS This represents the current flowing through transistor M_HS.

[0098] The operation of circuit 60 will now be described in more detail.

[0099] Figure 9 It shows the manufacturing Figure 8 In an embodiment of the method of circuit 60, the voltage V of circuit 60 is during the first charge after steady-state operation. DD V DD_HS V Ddins V C_FL1 V G_F1 V ac V dc and V GS_HS and current I SCR_F2 I SCR_F1 and I R_ICL The timing diagram. Figure 9 In the equation, times t0, t1, t2, t3, t4, and t5 are continuous. The voltage Vac exhibits a positive half-wave between times t1 and t2, between times t2 and t3, and between times t4 and t5, and a negative half-wave between times t1 and t2, and between times t3 and t4.

[0100] Between times t0 and t1, during the first charge, switches M_HS and M_LS are not controlled to be turned on, and thyristors SCR_F1 and SCR_F2 are controlled to be turned off. Capacitor C_DC is charged at voltage V. ac The first positive half-wave pre-charges the system. Positive current I L The current I flows through the internal diode of transistor M_HS and diode D2. R_ICL The voltage increases from 0A, passes through its maximum value, and then decreases back to 0A. (Voltage V) dc It has risen to a stable level.

[0101] After charging capacitor C_DC and before the start of steady-state operation, circuit ALIM supplies voltage V. DD Then, the voltage V is supplied. DDins Voltage V DDins The setup allows thyristor SCR_F2 to be set to the ON state, which corresponds to the voltage V after time t2. G_F2 The pulse. In a steady state, at voltage V ac During the positive half-wave, thyristor SCR_F2 is turned on, and terminal 18, i.e., the output voltage V, is connected. dc The reference potential is coupled to terminal 14. Switch M_LS is controlled by pulse width modulation (PWM), and switch M_HS acts as a flywheel diode when switch M_LS is off.

[0102] Then, circuit 64 is activated, which causes voltage V to be applied. DD_HS This will increase the voltage V. C_FL1 Rise. Voltage V C_FL1The setup allows the thyristor SCR_F1 to be set to the ON state, which corresponds to the voltage V after time t3. G_F1 The pulse. Starting from time t4, circuit 60 operates fully in a steady state.

[0103] Figure 10 The diagram illustrates the conveying process. Figure 8 The voltage V of circuit 60 DD_HS An embodiment of the power supply circuit SHS. The source SHS includes a diode D_HS. The anode of the diode D_HS is coupled to, and preferably connected to, a terminal of the circuit ALIM (). Figure 10 (not shown in the image) to transmit voltage V DD The cathode of diode D_HS is coupled to, and preferably connected to, the electrode of capacitor C_HS (not coupled to midpoint 56), and therefore coupled to the anode of diode DFL. V is called V. DS_M2 I is the drain-source voltage of transistor M2, and is called I. D-HS This represents the current flowing through diode D_HS.

[0104] Figure 11 It is between time t2 and t3 Figure 9 voltage V C_FL1 and V DD_HS An enlarged view of the timing diagram, and also includes the power supply circuit SHS with Figure 10 The structure shown has a current I DFL and I D_HS and voltage V DS_M2 The timing diagram.

[0105] Transistors M1 and M2 are controlled in opposite ways. This means that, at least in a steady state, when transistor M2 is turned on, transistor M1 is turned off, and when transistor M2 is turned off, transistor M1 is turned on. When transistor M2 is turned on (voltage V... DS_M2 When the transistor M1 is in a low state and is controlled to be off, the capacitor C_HS is filled by the current I flowing through the diode D_HS and the transistor M2. D-HS Charging. When transistor M1 is controlled to be turned on and transistor M2 is controlled to be turned off (voltage V) DS_M2 When in the high state, capacitor C_FL1 is supplied with current I flowing through diode DFL, resistor RFL, capacitor C_HS, and transistor M1. DFL Charge.

[0106] Figure 12 A variant of circuit 60 is shown partially and schematically, wherein circuit 64 is a DC / DC converter. With Figure 8 compared to, Figure 12The converter 64 shown also includes an inductor Lp connected in series between the two switches M1 and M2; and the electrode of a capacitor C_HS coupled thereto is located between the inductor Lp and the switch M1. As an example, circuit 64 can correspond to a forward DC / DC converter, then including a transformer, diodes Drect and Dfws, an inductor Ls, a capacitor Cload, and a resistor Rload. The primary winding LT1 of the transformer is coupled in parallel with the inductor Lp. The first terminal of the secondary winding LT2 of the transformer is coupled to, preferably connected to, the anode of the diode Drect. The cathode of the diode Drect is coupled to, preferably connected to, the cathode of the diode Dfws. The anode of the diode Dfws is coupled to, preferably connected to, the second terminal of the secondary winding LT2. The first terminal of the inductor Ls is coupled to, preferably connected to, the cathode of the diode Drect. The first electrode of the capacitor Cload is coupled to, preferably connected to, the second terminal of the inductor Ls. The resistor Rload is connected in parallel with the capacitor Cload.

[0107] Figure 13 An embodiment of a rectifier-type "totem pole" AC-DC converter 65 is illustrated schematically and partially. The converter 65 includes... Figure 1 All components of converter 10 shown are different except that the inductor L_PFC is absent. The operation of converter 65 may be the same as that of converter 10, as previously described, except that switches M_HS and M_LS are controlled at full-wave (rather than PWM) for each positive and negative half-wave. Therefore, circuit 65 performs voltage rectification instead of boosting, potentially correcting the power factor of the current sampled from the mains, just as converter 10 can do.

[0108] exist Figure 1 , Figure 8 , Figure 12 and Figure 13 In the embodiments of converters 10, 60, and 65 shown, thyristor SCR_F2 is a cathode-gate thyristor. As a variant, thyristor SCR_F2 can be an anode-gate thyristor. In this case, capacitor C_FL2 may be absent.

[0109] Figure 14 An embodiment of a "totem pole" AC-DC power factor correction converter 66 is schematically illustrated. Converter 66 includes... Figure 14 The converter 10 shown includes all its components, and also includes: a power supply circuit SDD that delivers the reference voltage V. DD (Among them, the power supply circuit SDD can be formed) Figure 14 The circuit shown (part of ALIM) and the power supply circuit 40, based on the reference voltage V DD Transmit reference voltage V C_FL2(This can correspond to the aforementioned voltage V) DDins The capacitor C_FL2 includes a diode DFL', a resistor RFL', a capacitor C_FL2, and a Zener diode DZ'. The negative terminal of the source SDD is coupled to, preferably connected to, terminal 18. The positive terminal of the source SDD is coupled to, preferably connected to, the anode of the diode DFL'. The cathode of the diode DFL' is coupled to, preferably connected to, a terminal of the resistor RFL'. The other terminal of the resistor RFL' is coupled to, preferably connected to, the first electrode of the capacitor C_FL2. The second electrode of the capacitor C_FL2 is coupled to, preferably connected to, the midpoint 22. Voltage V C_FL2 This corresponds to the voltage across capacitor C_FL2. The anode of Zener diode DZ' is coupled to, preferably, the midpoint 22. The cathode of Zener diode DZ' is coupled to, preferably, the first electrode of capacitor C_FL2. The positions of diode DFL' and resistor RFL' can be reversed. Zener diode DZ' may not be present.

[0110] call I DFL’ The current flowing through diode DFL' is positive when it flows from the anode to the cathode. In steady state, for converter 10, thyristors SCR_F1 and SCR_F2, and transistors M_HS and M_LS, are controlled as previously described. The operation of circuit 66 will now be described in more detail.

[0111] Figure 15 Showing the target Figure 14 An embodiment of the operation method of circuit 66, in a steady state, during the first charging period after operation, the voltage V of circuit 66 is... C_FL2 V GS_HS V GS_LS V dc and V SCR_F2 and current I L and I DFL’ The timing diagram. In the timing diagram, the voltage V GS_LS It was shown as a drop of 10V. Figure 15 In this context, times t0, t1, t2, t3, and t4 are continuous. Voltage V ac ( Figure 15 (Not shown) There is a positive half-wave between time t0 and t1 and between time t2 and t3, and a negative half-wave between time t1 and t2 and between time t3 and t4.

[0112] Figure 16 It is similar to Figure 14 The figure illustrates the current I through converter 66 during the first charging of capacitors C_FL2 and C_DC between times t0 and t1. L and I DFL’The flow.

[0113] Between times t0 and t1, during the first charge, switches M_HS and M_LS are not controlled to be turned on, and thyristors SCR_F1 and SCR_F2 are controlled to be turned off. Capacitor C_DC is charged at voltage V. ac The first positive half-wave pre-charges the system. Positive current I L The current I flows through the internal diode of transistor M_HS and diode D2. L The voltage increases from 0A, passes through its maximum value, and then decreases back to 0A. (Voltage V) dc It has risen to a stable level.

[0114] Between time t0 and t1, capacitor C_FL2 is subjected to current I DFL’ Charging, the current I DFL’ The voltage V flowing from resistor RFL', diode DFL', resistor R_ICL, and diode D2 is determined by... DD The initial portion and the voltage V flowing from the capacitor through the source SDD, resistor RFL', and diode DFL'. ac Another part begins to form. Current I DFL’ The voltage increases from 0A, passes through its maximum value, and then decreases back to 0A. (Voltage V) C_FL2 It rises to its maximum value, then slowly decreases. Current I DFL’ Compared to the current I that it subtracts L It is much lower so that diode D2 remains on during this stage.

[0115] Advantageously, the Zener diode DZ' makes it possible to set the voltage V across capacitor C_FL2. C_FL2 The maximum value. A different circuit for setting the voltage of capacitor C_FL2 can be used instead of Zener diode DZ'.

[0116] The steady-state operation of circuit 66 begins at time t1.

[0117] Figure 17 It is similar to Figure 14 The figure illustrates an embodiment of the operation method for converter 66, in a steady state, at voltage V ac During the positive half-wave, through Figure 14 The current I of converter 66 L and I DFL’ The flow.

[0118] In a steady state, at voltage V ac During each positive half-wave period, turn on thyristor SCR_F2 (voltage V). SCR_F2 Then equals 0V), and in voltage V acDuring each negative half-wave period, the thyristor SCR_F2 is deactivated (voltage V). SCR_F2 Then equals the voltage between terminals 16 and 18 (e.g., approximately -400V). At voltage V ac During each positive half-wave period, thyristor SCR_F1 is turned off, and at voltage V ac During each negative half-wave period, thyristor SCR_F1 is turned on. Additionally, transistor M_HS is turned on at voltage V. ac Each negative half-wave period is controlled by PWM (voltage V alternating between approximately 15V and 0V). GS_HS ), and is shown as at voltage V ac It is turned off during each positive half-wave period (voltage VGS_HS is at 0V) to simplify the timing diagram, even though in practice it is controlled in the opposite way to transistor M_LS during each positive half-wave period, especially turning on during the flywheel phase, as previously described. Furthermore, transistor M_LS is turned on at voltage V ac Each positive half-wave period is controlled by PWM (alternating between approximately 5V and -10V, with a voltage drop of 10V). GS_LS ), and is shown as at voltage V ac It is turned off during each negative half-wave (voltage V) GS_LS The voltage was reduced by 10V, then equal to approximately -10V, to simplify the timing diagram. Even in practice, it is controlled in the opposite way to transistor M_HS during each negative half-wave, especially when it is turned on during the flywheel phase, as previously stated.

[0119] In a steady state, at voltage V ac During each positive half-wave period, the voltage V DD The resulting current I DFL’ When diode DFL' and thyristor SCR_F2 are turned on, current flows through them to recharge capacitor C_FL2. Figure 15 It can be seen from this that, between times t2 and t3, during the positive half-wave of voltage Vac, voltage V C_FL2 Slightly higher.

[0120] When thyristor SCR_F2 is turned on and switch M_LS is turned on, the current I L like Figure 17 As shown, the current flows from terminal 12, through inductor L_PFC, transistor M_LS and thyristor SCR_F2, all the way to terminal 14.

[0121] In the preceding section Figure 14In the described embodiment, thyristor SCR-F2 is a cathode-gate thyristor, and thyristor SCR-F1 is also a cathode-gate thyristor. However, it may be necessary to select thyristor SCR-F2 to have an anode gate so that it can be controlled from the control circuit referenced at terminal 18. Then, circuit 40 formed by electronic components C_FL2, DFL', RFL', and DZ' is not required. Control of the anode-gate thyristor SCR-F2 can be achieved via a negative gate current (i.e., this negative gate current is drawn from the gate), which corresponds to the general case. However, the gate of thyristor SCR-F2 is structurally configured to allow control of the thyristor via a positive gate current.

[0122] Figure 18 This is a diagram of another embodiment of the so-called "totem pole" AC-DC power factor correction converter 67, similar to... Figure 14 Converter 67 includes Figure 14 The converter 66 shown is different in that the thyristor SCR_F1 is an anode-gate thyristor, and the power supply circuit 30 is absent. The gate of the thyristor SCR_F1 is configured to allow control of the thyristor SCR_F1 by a positive gate current, whereas an anode-gate thyristor is typically controlled by a negative gate current, i.e., the negative gate current is drawn from the gate.

[0123] Thyristor SCR_F1 is an anode-gate thyristor, therefore its control signal is referenced at midpoint 22. Thyristor SCR_F2 is a cathode-gate thyristor. Therefore, its control signal is referenced at the same midpoint 22. Advantageously, this embodiment allows the power supply circuit 40 to be used for thyristor SCR_F2, and also for thyristor SCR_F1.

[0124] Figure 19 This is a diagram of another embodiment of the so-called "totem pole" AC-DC power factor correction converter 68, similar to... Figure 14 Converter 68 includes Figure 14 The converter 66 shown includes all its components, and also includes a resistor R_Rech connected between node 22 and terminal 18 in series with the thyristor SCR_Rech. The thyristor SCR_Rech is a cathode-gate thyristor, with its cathode connected to terminal 18 and its gate controlled by the signal Rech. Alternatively, the thyristor SCR_Rech can be replaced by any other switch capable of blocking AC voltages having a peak-to-peak amplitude corresponding to the mains voltage, for example, at least 400V peak-to-peak amplitude. As an example, the thyristor SCR_Rech can be replaced by a MOS transistor and a diode connected in series with its drain.

[0125] Figure 20 It is similar to Figure 15 The difference in the diagram is that here, the capacitor C_DC is initially charged at time t0, and the diagram shows the charging of capacitor C_DC at time t0. Figure 19 An embodiment of the operation method of circuit 68, wherein the voltage V of circuit 68 during the first charging period after steady-state operation. C_FL2 V GS_HS V GS_LS V dc and V SCR_F2 and current I L and I DFL’ The timing diagram. Figure 20 In this process, the first charging of capacitor C_FL2 is ensured by thyristor SCR_Rech, which then turns on between time t0' (the time for controlling the opening of thyristor SCR_Rech) and t1. In fact, due to the voltage V here... dc The voltage is very high, and no current flows through resistor R_ICL. If thyristor SCR_F2 is not conducting, this will not allow C_FL2 to recharge, which could happen, for example, during the circuit's standby phase. Recharging of C_FL2 is ensured by thyristor SCR_F2, which then operates at voltage V. ac During each positive half-wave, it turns on in a steady state, as previously described. The thyristor SCR_Rech is at voltage V... ac It can be optionally turned off during each negative half-wave period. This advantageously allows for better control over the voltage across capacitor C_FL2, for example, if the voltage across resistor R_ICL is too low or when the first charge is at voltage V. dc It has already been achieved at a very high level.

[0126] Figure 21 Another embodiment of an AC-DC converter 70 with a three-way switch and power factor correction is schematically shown. For example, the converter 70 is used to deliver DC voltage to the on-board network of a motor vehicle. Figure 18 The common elements between converter 70 and converter 67 shown are designated using the same reference numerals.

[0127] The two input terminals 12 and 14 are designed to receive AC voltage V. ac For example, the voltage of a power distribution network (e.g., 230V or 120V, 50Hz or 60Hz). The two output terminals 16 and 18 deliver DC voltage V. dc Terminal 12 is coupled to the first terminal of the inductor L_PFC, which has a second terminal coupled to the midpoint 20 of the series connection of two diodes D3 and D4 between terminals 16 and 18. The anode of diode D4 is connected to terminal 18, and the cathode of diode D3 is connected to terminal 16.

[0128] Terminal 14 is connected to the midpoint 22 of the series connection between terminals 16 and 18 of two thyristors, SCR_F1 and SCR_F2. The anode of thyristor SCR_F2 is connected to terminal 18, and the cathode of thyristor SCR_F1 is connected to terminal 16. Figure 21 In this embodiment, thyristor SCR_F1 is a cathode-gate thyristor, and thyristor SCR_F2 is a cathode-gate thyristor. The gate of thyristor SCR_F1 receives control signal G_F1. The gate of thyristor SCR_F2 receives control signal G_F2.

[0129] Resistor R_ICL connects the midpoint 22 to the midpoint 24 of the series connection between terminals 16 and 18 of diodes D1 and D2. The anode of diode D2 is connected to terminal 18, and the cathode of diode D1 is connected to terminal 16. Storage and smoothing capacitor C_DC connects terminal 18 to terminal 16.

[0130] The converter 70 also includes a series connection of two switches M_POS and M_NEG between two midpoints 20 and 22. According to an embodiment, each switch M_POS, M_NEG corresponds to a enhancement MOS transistor, such as an N-type transistor. The drain of the MOS transistor M_POS is coupled to, preferably connected to, midpoint 20, and the source of the MOS transistor M_POS is coupled to, preferably connected to, midpoint 26. GS_POS V is the voltage between the gate of transistor M_POS and midpoint 26. The drain of MOS transistor M_NEG is coupled to, preferably connected to, midpoint 22, and the source of MOS transistor M_NEG is coupled to, preferably connected to, midpoint 26. GS_NEG This is the voltage between the gate of transistor M_NEG and midpoint 26. Midpoint 26 defines the reference potential, typically ground (GND).

[0131] Converter 70 also includes: a power supply circuit SDD, which delivers a reference voltage V. DD ; and power supply circuit 40, which supplies reference voltage V C_FL2 It includes a diode DFL', a resistor RFL', and a capacitor C_FL2. The negative terminal of the source SDD is coupled to, preferably connected to, midpoint 26. The positive terminal of the source SDD is coupled to, preferably connected to, the anode of the diode DFL'. The cathode of the diode DFL' is coupled to, preferably connected to, a terminal of the resistor RFL'. The other terminal of the resistor RFL' is coupled to, preferably connected to, the first electrode of the capacitor C_FL2. The second electrode of the capacitor C_FL2 is coupled to, preferably connected to, midpoint 22. The positions of the diode DFL' and the resistor RFL' can be reversed. In this embodiment, the power supply circuit 40 is used to control the thyristor SCR_F2.

[0132] In addition, the switch (not shown) can be inserted between terminals 12 and 14 on one hand, and between inductor L_PFC and midpoint 22 on the other hand.

[0133] Electronic circuitry 50, such as a microcontroller (μC), generates pulses to control the gates of thyristors SCR_F1 and SCR_F2. The microcontroller 50 controls the gates of thyristors SCR_F1 and SCR_F2 via one or two insulated optical, magnetic, or capacitive couplers 52 powered by power supply circuitry 40, specifically controlling the gate of thyristor SCR_F2, and controls the gate of thyristor SCR_F1 via another power supply circuit (not shown). This can be combined with... Figure 8 The circuit 30 shown is identical. The microcontroller 50 receives different setpoint CTs or measurements to turn off thyristors SCR_F1 and SCR_F2 at the correct time, thus enabling full-wave control in steady state. MOS transistors M_POS and M_NEG are controlled by a control circuit (not shown) or the microcontroller 50.

[0134] According to an embodiment, at least in a steady state, during each positive half-wave, transistor M_POS is controlled to be turned on, specifically by pulse width modulation (PWM), and during each negative half-wave, transistor M_NEG is controlled to be turned on, specifically by PWM. In a steady state, at voltage V... ac During each positive half-wave period, when transistor M_POS is controlled to conduct, inductor L_PFC is coupled between terminals 12 and 14, turned on by transistor M_POS, and if voltage V GS_NEG Fully bias the channel to turn it on, and observe the voltage V. ac The transistor M_NEG is then turned on by its internal diode or through its channel. Current increases in the inductor L_PFC, which stores power. When the transistor M_POS is controlled to be non-conductive, the inductor L_PFC releases the power stored in the capacitor C_DC by the diode D3 and the thyristor SCR_F2. At voltage V... ac During each negative half-wave period, when transistor M_NEG is controlled to conduct, inductor L_PFC is coupled between terminals 12 and 14, turned on by transistor M_NEG, and if voltage V GS_POS Fully bias the channel to turn it on, and observe the voltage V. acThe transistor M_POS is then turned on by its internal diode or through its channel. Current increases in the inductor L_PFC, which stores power. When the transistor MOS M_NEG is controlled to be non-conductive, the inductor L_PFC releases the power stored in the capacitor C_DC by the diode D4 and the thyristor SCR_F1. Preferably, transistors M_POS and M_NEG are controlled simultaneously. This allows the resistance of each transistor M_POS and M_NEG to be reduced when their internal diodes are turned on.

[0135] In a steady state, thyristor SCR_F1 is turned on during each negative half-wave, possibly intermittently, and thyristor SCR_F2 is turned on during each positive half-wave, possibly intermittently.

[0136] In the following description, V is referred to as M_NEG The voltage between the drain and source of transistor M_NEG is called I. M_NEG The current flowing from the drain to the source of transistor M_NEG is called I. M_POS The current flowing from the drain to the source of transistor M_POS is called I. D3 The current flowing from the anode to the cathode of diode D3 is called V. D3 The voltage between the cathode and anode of diode D3 is called I. SCR_F1 Let I be the current flowing through the thyristor SCR_F1. SCR_F2 This represents the current flowing through the thyristor SCR_F2.

[0137] The operation of circuit 70 will now be described in more detail.

[0138] Figure 22 Showing the target Figure 21 An embodiment of the operation method of circuit 70, during the first charging period after steady-state operation, the voltage V of circuit 70 is... C_FL2 V GS_NEG V dc and V ac and current I DFL′ I SCR_F2 and I SCR_F1 The timing diagram. Figure 22 In this context, times t0, t0', t1, t2, t3, and t4 are continuous. Voltage V ac ( Figure 2 (Not shown in the diagram) There are positive half-waves between times t0 and t1 and between times t2 and t3, and negative half-waves between times t1 and t2 and between times t3 and t4. Steady-state operation essentially begins at time t2. Between times t0 and t1, capacitor C-DC, through diodes D3 and D2 and resistor R_ICL, is subjected to voltage V. acThe first positive half-wave pre-charge. Figure 22 Some timing diagrams are respectively for Figure 24 and Figure 26 The durations of the steady state, PI and PI, are shown in a magnified view.

[0139] Figure 23 It is similar to Figure 21 The figure illustrates the current I through converter 70 during the first charging of capacitor C_FL2 between times t0 and t1. DFL’ The flow. Between times t0 and t1, transistor M_POS is not controlled to be turned on. At time t0, transistor M_NEG is not controlled to be turned on. When the source SDD is activated and when the voltage V DD_HS When stable, at voltage V ac During the remaining positive half-wave, transistor M_NEG is controlled to be turned on during time t0' between time t0 and t1. Capacitor C_FL2 is then switched on by current I. DFL’ Charging, the current I DFL’ From voltage V DD_HS This current I is generated and flows through diode DFL', resistor RFL', and transistor M_NEG. DFL’ The voltage increases from 0A, passes through its maximum value, and then decreases back to 0A. (Voltage V) C_FL2 It rises to its maximum value and then slowly declines.

[0140] Figure 24 Within the duration PI Figure 22 voltage V C_FL2 and current I DFL’ Timing diagram and source-drain of transistor M_NEG, VM_NEG and current I M_POS and current I M_NEG The opposite current (denoted as -I) M_NEG A detailed view of the timing diagram. Duration PI starts after time t2, and the voltage V in steady state... ac The beginning of the positive half-wave. On the vertical axis, the scale from 6V to 14V applies to voltage V. C_FL2 And the scale from -15V to 5V is applicable to voltage V. M_NEG .

[0141] In a steady state, at voltage V ac During each positive half-wave period, the thyristor SCR_F2 is intermittently turned on, and at voltage V ac During each negative half-wave period, thyristor SCR_F2 is turned off. At voltage V ac During each positive half-wave period, thyristor SCR_F1 is turned off, and at voltage V acDuring each negative half-wave period, the thyristor SCR_F1 is intermittently turned on.

[0142] Figure 25 It is similar to Figure 21 The figure illustrates an embodiment of the operation method for converter 70, during a duration PI, by... Figure 21 The current I of the converter 70 DFL’ The flow.

[0143] Transistor M_NEG at voltage V ac (Voltage V alternating between approximately 15V and 0V) GS_NEG Each negative half-wave period of the signal is controlled by PWM and is shown as a voltage V. ac Non-on (voltage V) during each positive half-wave period GS_NEG Then approximately equal to 0V) to simplify the timing diagram, even though in practice, transistor M_NEG is controlled simultaneously with transistor M_POS during each positive half-wave. Furthermore, transistor M_POS is at voltage V ac Each positive half-wave period is controlled by PWM, and the voltage V ac It is non-conductive during each negative half-wave period, even though in practice it is preferably controlled simultaneously with transistor M_NEG during each negative half-wave period.

[0144] In a steady state, at each stage in which transistor M_POS is controlled to be turned on, at voltage V ac During each positive half-wave, capacitor C_FL2 is recharged. When transistor M_POS is turned on, the source-drain voltage V of transistor M_NEG... M_NEG From negative values ​​(basically equal to voltage V) DD_HS With V C_FL2 The difference between them increases to a value close to zero, most precisely, by causing the intrinsic diode of the MOS transistor M_NEG to operate at its voltage V. GS_NEG Maintain the required +0.6V when connected to a low level.

[0145] At voltage V ac The beginning of each positive half-wave, especially Figure 22 and Figure 24 During the duration PI shown, transistor M_POS is controlled to exhibit two consecutive sub-stages PI_1 and PI_2 during each stage of its on-state. In sub-stage PI_1, as long as voltage V... M_NEG Keeping the voltage below +0.6V, the charging of capacitor C_FL2 is mainly achieved through voltage V. DD_HS The resulting current I DFL’ This is achieved through the flow of diode DFL', resistor RFL', inductor L_PFC, voltage Vac, and transistor M_POS. Figure 25 The dashed line represents the voltage V. M_NEG When the voltage becomes greater than approximately +0.6V, in sub-stage PI_2, capacitor C_FL2 experiences a current I induced by voltage VDD_HS. DFL’ This is achieved through the internal diode flowing through diode DFL', resistor RFL', and transistor M_NEG, which is in Figure 25 The dashed line in the middle indicates that it is related to the previous part about Figure 23 The same way as described.

[0146] Figure 26 Within the duration PII after duration PI Figure 22 voltage V C_FL2 and current I DFL’ Timing diagram and source-drain V of transistor M_NEG M_NEG and current I M_NEG A detailed view of the timing diagram for the opposite current (denoted as -IM_NEG). On the vertical axis, the scale from 14V to 16V applies to voltage V. C_FL2 And the scale from -15V to 5V is applicable to voltage V. M_NEG Once transistor M_POS is turned on, the internal diode of transistor M_NEG will also turn on, and capacitor C_FL2 will be charged via voltage V. DD_HS The resulting current I DFL’ This is achieved by flowing through diode DFL', resistor RFL', and transistor M_NEG, which is in Figure 25 The middle part is represented by a dashed line.

[0147] In the preceding section Figure 21 In the described embodiment, thyristor SCR-F2 is a cathode-gate thyristor, and thyristor SCR-F1 is a cathode-gate thyristor. However, it may be necessary to select thyristors SCR-F1 and SCR-F2 so that their control signals are referenced to... Figure 18 The solution disclosed in the paper is similar to the same point.

[0148] Figure 27 Another embodiment of an AC-DC converter 80 with a three-way switch and power factor correction is schematically shown. The converter 80 includes... Figure 21 The converter 70 shown here has all the components except that it includes a power supply circuit 30, as previously mentioned. Figure 1 The described component is used to control the thyristor SCR_F1. According to an embodiment, the source SHS includes a capacitor C_HS, a diode DHS, a resistor RHS, and is coupled to a reference voltage V. DDThe source of the diode is SDD. The first electrode of the capacitor C_HS is coupled to, preferably connected to, midpoint 20. The second electrode of the capacitor C_HS is coupled to, preferably connected to, the anode of the diode DFL. The cathode of the diode DFL is coupled to, preferably connected to, the terminal of the resistor RFL. The other terminal of the resistor RFL is coupled to, preferably connected to, the electrode of the capacitor C_FL1. The other electrode of the capacitor C_FL1 is coupled to, preferably connected to, terminal 16. The positions of the diode DFL and the resistor RFL can be reversed. The resistor RFL, which acts as a current limiter, may not be present, but it is preferable to be present. The anode of the diode DHS is coupled to, preferably connected to, the positive terminal of the source SDD. The cathode of the diode DHS is coupled to, preferably connected to, the terminal of the resistor RHS. The other terminal of the resistor RHS is coupled to, preferably connected to, the anode of the diode DFL and the second electrode of the capacitor C_HS. The positions of the diode DHS and the resistor RHS can be reversed. The resistor RHS, which acts as a current limiter, may not be present, but it is preferable to be present. GS_POS This is the voltage between the gate of transistor M_POS and midpoint 26. The drain of transistor MOS M_NEG is coupled to, preferably connected to, midpoint 22, and the source of transistor MOS M_NEG is coupled to, preferably connected to, midpoint 26. (I is referred to as I) DHS This represents the current flowing through diode DHS.

[0149] Figure 28 It is similar to Figure 22 The diagram shows the target... Figure 27 An embodiment of the operation method of circuit 80, during the first charging period after steady-state operation, the voltage V of circuit 80 is... DD_HS V GS_POS V dc and V ac and current I DHS and I M_NEG The timing diagram. Figure 28 Some timing diagrams in Figure 30 The duration of the steady state in PIII is shown in a magnified view.

[0150] Figure 29 It is similar to Figure 27 The diagram illustrates the situation in Figure 28 The voltage V during the first charging period of capacitor C_HS between time t1 and t2, i.e., before the steady state. ac During the negative half-wave, the current I in converter 80 DHSThe flow of electricity. During the positive half-wave, in a steady state, transistor M_POS is controlled to be forward-biased. During the negative half-wave, it is reverse-biased from its source to its drain, which can be done via its internal diode if it is not controlled. When the source SDD is activated and the voltage V... DD_HS When stable, at voltage V ac During the remaining negative half-wave, transistor M_POS is controlled to be on for time t1' between times t1 and t2. Capacitor C_HS is then switched on by current I. DHS Loading, the current I DHS From voltage V DD This current I is generated and flows through diode DHS, resistor RHS, and transistor M_POS. DHS The voltage increases from 0A, passes through its maximum value, and then decreases back to 0A. (Voltage V) C_HS It rises to its maximum value.

[0151] In a steady state, at each stage where transistor M_NEG is controlled to turn on and transistor M_POS becomes reverse-biased through its internal diode or through its channel when turned on by its control signal, at voltage V ac During each negative half-wave period, the capacitor C_F is recharged.

[0152] Figure 30 Within duration PIII Figure 28 voltage V DD_HS and current I DHS Timing diagram (multiplied by a factor of 10) and drain-source voltage V of transistor M_POS M_POS The opposite voltage (denoted as -V) M_POS ) and current I M_POS The opposite current (denoted as -I) M_POS A detailed view of the timing diagram. On the vertical axis, the scale from 14V to 15V applies to voltage V. DD_HS And the scale from -3V to 1V is applicable to -V M_POS Once transistor M_NEG is turned on, the internal diode of transistor M_POS becomes on. If its gate is controlled, the capacitor C_HS is charged by the flow of current IDHS caused by voltage VDD, as well as through diode DHS, resistor RHS, and the internal diode or channel of transistor M_POS, as shown below. Figure 28 As shown in the image.

[0153] Figure 31 It is similar to Figure 28 The diagram shows the target... Figure 27 An embodiment of the operation method of circuit 80, during the first charging period after steady-state operation, the voltage V of circuit 80 is...DD_HS V C_FL1 V dc and V ac and current I DFL and I D3 The time series diagram. Within the duration PIV of the steady state, Figure 31 Some timing diagrams in Figure 32 The image is shown in a magnified view.

[0154] Figure 32 Within the duration PIV Figure 31 voltage V C_FL1 and current I DHS and I D3 Timing diagram and voltage V D3 A detailed view of the timing diagram. On the vertical axis, the scale from 7V to 11V applies to voltage V. C_FL1 And the scale from -400V to 100V is applicable to voltage V. D3 .

[0155] Capacitor C_FL1 is the voltage V under steady-state conditions. ac The first positive half-wave and the charge are generated after the capacitor C_HS is charged.

[0156] Figure 33 It is similar to Figure 27 The figure illustrates the voltage V in a steady state. ac During the positive half-wave, Figure 31 During the charging period of capacitor C_FL1 after time t2, the current I in converter 80 DFL and I D3 The flow. At voltage V ac During each positive half-wave period, when diode D3 becomes on, capacitor C_FL1 is induced by the voltage across capacitor C_HS and a current I flows through diode DFL, resistor RFL, and from its cathode to its anode through diode D3. DFL Charging. Current I DFL It can pass through diode D3 in reverse because the latter conducts the total current I. D3 The current remains positive from the anode to the cathode.

[0157] In the preceding section Figure 21 In the described embodiment, thyristor SCR-F2 is a cathode-gate thyristor, and thyristor SCR-F1 is a cathode-gate thyristor. However, it may be necessary to select thyristor SCR-F2 with an anode gate so that its control signal is referenced to terminal 18 when the converter's control circuitry is referenced at that point. Similarly, thyristor SCR-F1 may be selected with an anode gate so that circuit 40 supplies power to its gate control circuitry.

[0158] Figure 34 An embodiment of circuit 85, including an AC-DC converter with a three-way switch and a power factor correction, is partially and schematically shown, coupled to another circuit 88, only partially. Figure 34 The following are illustrated, for example, DC / DC converters or DC / AC converters. Converter 88 includes a series connection of two switches M1 and M2 between two terminals 16 and 18. Converter 86 includes all the elements of converter 80, except that, for converter 86, the electrode of capacitor C_HS of power supply circuit SHS is coupled to the midpoint 56 of the two switches M1 and M2, while for converter 80, this electrode is coupled to the midpoint 56 of the two switches M1 and M2. According to an embodiment, each switch M1, M2 corresponds to a enhancement MOS transistor, such as an N-type. The drain of MOS transistor M1 is coupled to, preferably connected to, terminal 16, and the source of MOS transistor M1 is coupled to the midpoint 56. For example, the drain of MOS transistor M2 is connected to, for example, through, terminal 16. Figure 12 The inductor element Lp and / or LT1 shown are coupled to or directly connected to the midpoint 56, and the source of the MOS transistor M2 is coupled to, preferably connected to, terminal 18. In this embodiment, the power supply circuit SHS has Figure 10 The structure shown.

[0159] Figure 35 This is a diagram of another embodiment of an AC-DC converter 90 with a three-way switch and power factor correction, similar to... Figure 21 Converter 90 includes Figure 21 All components of the converter 70 shown differ only in that thyristor SCR_F1 is an anode-gate thyristor. The gate of thyristor SCR_F1 is configured to allow control of thyristor SCR_F1 by a positive gate current, whereas anode-gate thyristors are typically controlled by a negative gate current, i.e., a negative gate current drawn from the gate. Since thyristor SCR_F1 is an anode-gate thyristor, its control signal is referenced at midpoint 22. Thyristor SCR_F2 is a cathode-gate thyristor. Therefore, its control signal is referenced at the same midpoint 22. Advantageously, this embodiment allows the power supply circuit 30 to be used for thyristor SCR_F2, and also for thyristor SCR_F1.

[0160] Figure 36 An embodiment of circuit 100 is shown in part and schematically, including a hybrid active bridge AC-DC converter 102 coupled to another circuit 104, only partially shown. Figure 36 As shown, such as a DC / DC converter or a DC / AC converter. Converter 104 includes a series connection of two switches M1 and M2 between two terminals 16 and 18.

[0161] AC-DC converter 102 includes Figure 8 The converter 62 shown in the diagram differs in the following ways:

[0162] Inductor L_PFC does not exist;

[0163] The two thyristors SCR_F1 and SCR_F2 are cathode-gate thyristors and are connected in reverse series between terminals 12 and 14, with the anode of thyristor SCR_F2 connected to terminal 14.

[0164] Diode D1 is connected in series with thyristor SCR_F1. The anode of diode D1 is connected to terminal 18, and the cathode of diode D1 is connected to the anode of thyristor SCR_F1. Terminal 12 is connected to the midpoint between thyristor SCR_F1 and diode D1.

[0165] Diode D2 is connected in series with thyristor SCR_F2. The anode of diode D2 is connected to terminal 18, and the cathode of diode D2 is connected to the anode of thyristor SCR_F2. Terminal 14 is connected to the midpoint between thyristor SCR_F2 and diode D2.

[0166] Transistors M_HS and M_LS are absent. The AC-DC converter 100 includes diodes D3 and D4. The anode of diode D3 is connected to terminal 12, the anode of diode D4 is connected to terminal 14, and the cathode of diode D4 is connected to the cathode of diode D3.

[0167] Resistor R_ICL is connected between the cathode of diode D3 and terminal 16.

[0168] The two thyristors, SCR_F2 and SCR_F1, are anode-gate thyristors powered by power supply circuit 30. As a variant, diodes D1 and D2 can be replaced with MOS transistors.

[0169] The initial charging and recharging of capacitors C_FL1 and C_HS in circuit 100 can be performed on circuit 60 as described above. Specifically, capacitor C_FL1 is charged with a power supply voltage V through resistor RFL and diode DFL. DD_HS Charging. Capacitor C_HS can be charged from the power supply voltage V. DD ( Figure 33 (Not shown in the image) Charge as previously described.

[0170] The power supply circuits 30 and 40 of the converter according to the foregoing embodiments advantageously have a simple structure and can be formed by circuits occupying a small surface area relative to the total surface area of ​​the converter. The power supply circuits 30 and 40 according to the foregoing embodiments can also advantageously be formed by circuits with low manufacturing costs.

[0171] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art. Finally, the actual implementation of the described embodiments and variations is based on the functional indications given above and is within the capabilities of those skilled in the art. Specifically, the programming of the microcontroller depends on the application, and the described embodiments are compatible with common applications that use microcontrollers, etc., to control converters.

[0172] As a variant, resistor R_ICL and / or diode D1 and / or diode D2 can be suppressed. Then, the pre-charging of capacitor C_DC can be performed with a regularly decreasing turn-on delay via phase-change control of thyristors SCR_F2 and SCR_F1 to ensure step-by-step charging of capacitor C_DC and limitation of inrush current when converter 10 is powered on.

[0173] In this embodiment, the thyristor SCR_F2 will preferably have an anode gate or a cathode gate and be controlled by an opto-Triac (as described in patent application FR20 / 09057) or any other solution within the capabilities of a person skilled in the art.

[0174] The converter can be summarized as including an AC-DC conversion stage (10, 60, 65, 66, 67, 68, 70, 80, 90, 100), comprising: a first thyristor (SCR_F1, SCR_F2); a first power supply circuit (SHS, SDD) that supplies a first reference voltage (V) between the first node (20, 26, 56, 18) and the second node. DD_HS V DD ); and a second power supply circuit (30, 40) that supplies a second reference voltage (V) between the third and fourth nodes. C_FL1 V C_FL2 The cathode of the first thyristor is coupled to the first node of the first power supply circuit through the first switch (D3, M_HS, M1, M_NEG, D2) and connected to the fourth node. The second power supply circuit includes a first rectifier element (DFL, DFL'), which is coupled to the second node of the first power supply circuit and coupled to the third node.

[0175] The first rectifier element (DFL) may be the first diode.

[0176] The second power supply circuit (30, 40) may include a first capacitor (C_FL1, C_FL2) with a first electrode connected to the cathode of the first thyristor (SCR_F1).

[0177] The first switch can be the first MOS transistor (M_HS, M_LS).

[0178] The first switch can be the second diode (D3, D2).

[0179] AC-DC converters (10, 60, 65, 66, 67, 68) may include: a first terminal and a second terminal (12, 14) for receiving AC voltage (V). ac ); and the third and fourth terminals (16, 18) for transmitting DC voltage (V dc ).

[0180] Before reaching a steady state, at AC voltage (V) ac During the positive half-wave of ), at DC voltage (V dc Once the threshold is exceeded, the first power supply circuit (SHS) can be activated so that, subsequently, when the first switch (M_HS) is controlled to the ON state, the first capacitor (C_FL1) can be powered by the current (I) flowing through the first rectifier element (DBL). DBL It is being charged.

[0181] The converter may also include a second MOS transistor (M_LS) that couples the first node (20) of the first power supply circuit (SHS) to a fourth terminal (18), wherein a third terminal (16) may be connected to the cathode of the first thyristor (SCR_F1) and a second terminal (14) may be connected to the anode of the first thyristor (SCR_F1).

[0182] The converter may also include a second MOS transistor (M2) coupled to a first node (56) of the first power supply circuit (SHS) via an inductor (Lp) and connected to a fourth terminal (18), wherein a third terminal (16) may be connected to the cathode of the first thyristor (SCR_F1) and a second terminal (14) may be connected to the anode of the first thyristor (SCR_F1).

[0183] The second terminal (14) can be connected to the anode of the first thyristor (SCR_F1), and the first terminal (12) can be coupled to the first node (20) of the first power supply circuit (SHS) through an inductor (L_PFC).

[0184] The converter may also include a second MOS transistor (M_POS) connected to a first node (26) of a first power supply circuit (SHS), wherein a second terminal (14) may be connected to the cathode of a first thyristor (SCR_F2), wherein a first terminal (12) may be coupled to the second MOS transistor (M_POS) via an inductor (L_PFC), and the anode of the first thyristor may be connected to a fourth terminal (18).

[0185] The converter may also include a second thyristor (SCR_F1), wherein the cathode of the second thyristor may be connected to the cathode of the first thyristor (SCR_F2), and the first terminal (12) may be connected to the anode of the second thyristor.

[0186] The first terminal (12) can be coupled to the first MOS transistor (M_LS) through an inductor (L_PFC), and the second terminal (14) can be connected to the cathode of the first thyristor (SCR_F2), and the anode of the first thyristor (SCR_F2) is coupled to the fourth terminal (18).

[0187] The converter may include a second switch (SW_Rech) that couples the cathode of the first thyristor (SCR_F2) to the fourth terminal (18).

[0188] AC-DC converters (70, 80, 90, 100) may include: a first terminal and a second terminal (12, 14) for receiving AC voltage (V). ac ); and the third and fourth terminals (16, 18) for transmitting DC voltage (V dc ).

[0189] The converter may include: a second thyristor (SCR_F2) connected in series with the first thyristor (SCR_F1); and a third power supply circuit (SDD) supplying a third reference voltage (V) between the fourth terminal (18) and the fifth node. DD ); and a fourth power supply circuit (40) that supplies a fourth reference voltage (V) between the sixth node and the seventh node (22). C_FL2 The cathode of the second thyristor is connected to the seventh node (22), and the fourth power supply circuit includes a second rectifier element (DFL') coupled to the fifth node of the third power supply circuit.

[0190] The second rectifier element (DFL') can be a third diode.

[0191] The fourth power supply circuit (40) may include a second capacitor (C_FL2) with a first electrode connected to the midpoint of the first thyristor and the second thyristor (SCR_F1, SCR_F2).

[0192] The converter may include a fourth diode and a fifth diode (D1, D2), which are coupled in series between the third terminal and the fourth terminal (16, 18).

[0193] The converter may include a second thyristor (SCR_F2) connected in series with the first thyristor (SCR_F1), and the midpoint of the fourth and fifth diodes (D1, D2) may be coupled to the midpoint of the first and second thyristors (SCR_F1, SCR_F2) through a first resistor (R_ICL).

[0194] The converter may include a first MOS transistor and a second MOS transistor (M_HS, M_LS), which are coupled in series between the third and fourth terminals (16, 18), wherein the second rectifier element (DFL') may be a third diode, and before reaching a steady state, at an AC voltage (V ac During the positive half-wave of the first diode (DFL') the second capacitor (C_FL2) can be charged by the current (IDFL') flowing through the first diode (DFL') and the fifth diode (D2).

[0195] The converter may include a second thyristor (SCR_F2) connected in series with a first thyristor (SCR_F1), and the first thyristor (SCR_F1) may be a cathode-gate thyristor, and the second thyristor (SCR_F2) may be a cathode-gate thyristor.

[0196] The converter may include a second thyristor (SCR_F2) connected in series with a first thyristor (SCR_F1), wherein the first thyristor (SCR_F1) may be a cathode-gate thyristor, and the second thyristor (SCR_F2) may be a cathode-gate thyristor controlled by a positive gate current or a negative gate current.

[0197] The various embodiments described above can be combined to provide other embodiments. If necessary, aspects of the embodiments can be modified to provide other embodiments using the concepts of the various embodiments.

[0198] These and other variations can be made to the embodiments as described above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A converter including an AC-DC conversion stage, said AC-DC conversion stage comprising: First thyristor, A first power supply circuit supplies a first reference voltage between a first node and a second node of the first power supply circuit, and A second power supply circuit supplies a second reference voltage between a third node and a fourth node of the second power supply circuit. The cathode of the first thyristor is coupled to the first node of the first power supply circuit via a first switch and is also coupled to the fourth node. The second power supply circuit includes a first rectifier element, which is coupled to the second node of the first power supply circuit and is also coupled to the third node.

2. The converter according to claim 1, wherein the first rectifier element is a first diode.

3. The converter of claim 1, wherein the second power supply circuit includes a first capacitor having a first electrode coupled to the cathode of the first thyristor.

4. The converter according to claim 1, wherein the first switch is a first MOS transistor.

5. The converter according to claim 1, wherein the first switch is a diode.

6. The converter of claim 4, wherein the AC-DC conversion stage comprises: A first terminal and a second terminal, the first terminal and the second terminal being configured to receive AC voltage; as well as The third and fourth terminals are configured to deliver DC voltage.

7. The converter of claim 6, wherein the second power supply circuit includes a first capacitor having a first electrode coupled to the cathode of the first thyristor, and wherein, prior to a steady state, during the positive half-wave of the AC voltage, the first power supply circuit is configured to be activated in response to the DC voltage exceeding a threshold, and the first capacitor is configured to be charged by current flowing through the first rectifier element in response to the first switch being controlled to be in an on state.

8. The converter of claim 6 further includes a second MOS transistor coupled between the first node of the first power supply circuit and the fourth terminal, wherein the third terminal is coupled to the cathode of the first thyristor, and wherein the second terminal is coupled to the anode of the first thyristor.

9. The converter of claim 6 further includes a second MOS transistor, the second MOS transistor being coupled to the first node of the first power supply circuit via an inductor and being coupled to the fourth terminal, wherein the third terminal is coupled to the cathode of the first thyristor, and wherein the second terminal is coupled to the anode of the first thyristor.

10. The converter of claim 6, wherein the second terminal is coupled to the anode of the first thyristor, and wherein the first terminal is coupled to the first node of the first power supply circuit via an inductor.

11. The converter of claim 6, further comprising a second MOS transistor coupled to the first node of the first power supply circuit, wherein the second terminal is coupled to the cathode of the first thyristor, wherein the first terminal is coupled to the second MOS transistor via an inductor, and wherein the anode of the first thyristor is connected to the fourth terminal.

12. The converter of claim 9, further comprising a second thyristor, wherein the cathode of the second thyristor is coupled to the cathode of the first thyristor, and wherein the first terminal is coupled to the anode of the second thyristor.

13. The converter of claim 6, wherein the first terminal is coupled to the first MOS transistor via an inductor, the second terminal is coupled to the cathode of the first thyristor, and the anode of the first thyristor is coupled to the fourth terminal.

14. The converter of claim 13, further comprising a second switch coupled between the cathode of the first thyristor and the fourth terminal.

15. The converter of claim 5, wherein the AC-DC conversion stage comprises: A first terminal and a second terminal, the first terminal and the second terminal being configured to receive AC voltage; as well as The third and fourth terminals are configured to deliver DC voltage.

16. The converter according to claim 6 or 15, comprising: The second thyristor is coupled in series with the first thyristor. The third power supply circuit is configured to deliver a third reference voltage between the fourth terminal and the fifth node, and A fourth power supply circuit, configured to deliver a fourth reference voltage between the sixth and seventh nodes, includes a second rectifier element coupled to the fifth node of the third power supply circuit. The cathode of the second thyristor is coupled to the seventh node.

17. The converter of claim 16, wherein the fourth power supply circuit includes a second capacitor having a first electrode coupled to the midpoint between the first thyristor and the second thyristor.

18. The converter according to claim 6 or 15, comprising: The fourth and fifth diodes are coupled in series between the third and fourth terminals; as well as The second thyristor is coupled in series with the first thyristor. The midpoint between the fourth diode and the fifth diode is coupled to the midpoint between the first thyristor and the second thyristor via a first resistor.

19. An AC-DC converter, comprising: The first and second input terminals are configured to receive AC signals; The DC output terminal is coupled to the ground terminal via the first capacitor; A first switch is coupled between the first input terminal and the DC output terminal; The second switch is coupled between the first input terminal and the ground terminal; The first thyristor is coupled between the second input terminal and the DC output terminal; as well as The second thyristor is coupled between the second input terminal and the ground terminal.

20. The AC-DC converter of claim 19, comprising a first diode and a second diode, wherein the first diode and the second diode are coupled in series between the DC output terminal and the ground terminal. The second input terminal is coupled to the midpoint between the diode and the second diode via a resistor.

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