Amplifier and lpddr3 input buffer

Abstract

An amplifier, an input stage of which comprises: a first current mirror; a first input differential pair coupled to the first current mirror; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage-controlled transmission circuit. Wherein when a predetermined voltage is higher than a first predetermined value, an extra current path is formed in the first current mirror and the current flowing through the extra current path in the first current mirror flows through the second current mirror to a ground potential. When the predetermined voltage is lower than a second predetermined value, an extra current path is formed in the second current mirror and the current flowing through the extra current path in the second current mirror flows through the first current mirror to the predetermined voltage source.

Description

Technical Field

[0001] This invention relates to amplifiers and LPDDR3 input buffers, and more particularly to amplifiers and LPDDR3 input buffers that can reduce the effects of reference voltage variations. Background Technology

[0002] In low-power DDR (Double Data Rate Synchronous Dynamic Random Access Memory) LPDDR3, the input buffer receives a reference voltage, and the input buffer generates an output voltage based on this reference voltage for subsequent circuitry. However, the output voltage may drift in response to changes in the reference voltage.

[0003] Therefore, a compensation mechanism is needed to improve this problem. Summary of the Invention

[0004] Therefore, one object of the present invention is to provide an amplifier that can compensate for output voltage drift caused by variations in the reference voltage.

[0005] Another object of the present invention is to provide an LPDDR3 input buffer that can compensate for output voltage drift caused by variations in the reference voltage.

[0006] An embodiment of the present invention discloses an amplifier having an input stage, the input stage comprising: a first current mirror coupled to a predetermined voltage source; a second current mirror coupled to ground potential; a first input differential pair coupled to the first current mirror; a first current source coupled to the first input differential pair; a second input differential pair coupled to the second current mirror, wherein the first input differential pair and the second input differential pair are used to receive a reference voltage and an input signal; a second current source coupled to the second input differential pair; and a voltage-controlled transmission circuit controlled by a reference voltage and coupled to the first current mirror and the second current mirror. The voltage-controlled transmission circuit is configured to: when the reference voltage is higher than a first predetermined value, control the formation of an additional current path in the first current mirror and the current flowing through the additional current path in the first current mirror flows through the second current mirror to the ground potential; when the reference voltage is lower than a second predetermined value, control the formation of an additional current path in the second current mirror and the current flowing through the additional current path in the second current mirror flows through the first current mirror to the predetermined voltage source.

[0007] In one embodiment, the aforementioned amplifier is used in an LPDDR3 buffer and the reference voltage varies with the ODT (on dietermination) resistor.

[0008] According to the above embodiments, the drift of the amplifier's output voltage caused by variations in the reference voltage can be compensated. Therefore, problems in the prior art can be improved. Attached Figure Description

[0009] Figure 1 A block diagram of an amplifier according to an embodiment of the present invention is shown.

[0010] Figure 2 To illustrate an embodiment of the present invention Figure 1 The circuit diagram of the amplifier in the image.

[0011] Figure 3 To illustrate an embodiment of the present invention Figure 1 The circuit diagram of the voltage-controlled transmission circuit in the image.

[0012] Figure 4 To illustrate an embodiment of the present invention Figure 2 The waveform diagram of the amplifier's operation.

[0013] Figure 5 To illustrate another embodiment of the present invention Figure 1 The circuit diagram of the voltage-controlled transmission circuit in the image. Detailed Implementation

[0014] The following description uses several embodiments as examples to illustrate the concept of the present invention. It should also be noted that the terms "first," "second," and similar descriptions in the following description are only used to define different components, parameters, data, signals, or steps, and are not intended to limit their order. For example, "first device" and "second device" simply mean that these devices may have the same structure but are different devices.

[0015] Figure 1 The block diagram illustrates an amplifier according to an embodiment of the present invention, which includes an input stage with a wide input range. Operational amplifiers typically consist of an input stage 100 and an output stage (not shown). Figure 1 As shown, the input stage 100 includes: a first current mirror CM1 coupled to a predetermined voltage source VDD, a first input differential pair DI1, a first current source CS1, a second current mirror CM2 coupled to ground potential, a second input differential pair DI2, a second current source CS2, and a voltage-controlled transmission circuit 101. The first input differential pair DI1 is coupled to the first current mirror CM1, and the first current source CS1 is coupled to the first input differential pair DI1. The second input differential pair DI2 is coupled to the second current mirror CM2, and the second current source CS2 is coupled to the second input differential pair DI2. The first input differential pair DI1 and the second input differential pair DI2 are used to receive the input signal IN and the reference voltage REF. The voltage-controlled transmission circuit 101 is controlled by the reference voltage REF.

[0016] In actual operation, when the reference voltage REF is higher than a first predetermined value, an additional current path is formed in the first current mirror CM1, and the current flowing through this additional current path flows to ground potential through the second current mirror CM2. Conversely, when the reference voltage REF is lower than a second predetermined value, an additional current path is formed in the second current mirror CM2, and the current flowing through this additional current path in the second current mirror CM2 flows through the first current mirror CM1 and to the predetermined voltage source VDD.

[0017] In one embodiment, an additional current path refers to a current path that the first current mirror CM1 and the second current mirror CM2 originally had. However, when the reference voltage REF is higher than a first predetermined value or lower than a second predetermined value, a new current path will be formed in the first current mirror CM1 or the second current mirror CM2.

[0018] In one embodiment, the first predetermined value and the second predetermined value are the turn-on / turn-off voltages of the transistors in the voltage-controlled transmission circuit 101. Details of the voltage-controlled transmission circuit 101 will be described in more detail later.

[0019] In one embodiment, input stage 100 is contained within an LPDDR3 input buffer. In this case, the reference voltage REF is the reference voltage for the DQ,DM inputs, and its voltage level varies with the ODT (on-die termination) resistor. The ODT resistor may conform to the LPDDR3 specification and operate in different modes, with different resistance values ​​in each mode. The reference voltage REF varies corresponding to the different resistance values ​​of the ODT resistor. As mentioned above, variations in the reference voltage REF can cause a drift in the output voltage Vo. In one embodiment, the output voltage Vo is also used as the input to an inverter (not shown), therefore a drift in the output voltage Vo will affect the inverter's output. Figure 1 The input stage 100 shown can compensate the output voltage Vo to improve the above-mentioned problem.

[0020] Figure 2 To illustrate an embodiment of the present invention Figure 1 The circuit diagram of amplifier 100 is shown. Please note that... Figure 2 This is merely an example; circuits capable of performing the same function should also fall within the scope of this invention. For example... Figure 2 As shown, the first current mirror CM1 includes PMOS transistors MPa and MPb, and the second current mirror CM2 includes NMOS transistors MNc and MNd. The operational amplifier includes an input stage 100 with a wide input range, which comprises a differential transistor pair with NMOS transistors MNc and MNb and a differential transistor pair with PMOS transistors MPc and MPd. These differential transistor pairs are connected in parallel to receive the parallel-transmitted input signals IN and REF.

[0021] exist Figure 2 In this embodiment, the gates of PMOS MPa and MPb are coupled to Figure 1 The voltage-controlled transfer circuit 101 shown has its terminal T1 connected to the transistor, and the gates of the NMOS transistors MNc and MNd are coupled to its terminal T2. The PMOS transistors MPa and MPb, and the NMOS transistors MNc and MNd can be replaced with other types of transistors. Therefore, such a connection can be described as follows: the first current mirror CM1 contains multiple transistors, and the voltage-controlled transfer circuit 101 is coupled to the control terminal (e.g., the gate terminal) of the transistors. Furthermore, such a connection can be described as follows: the second current mirror CM2 contains multiple transistors, and the voltage-controlled transfer circuit 101 is coupled to the control terminal of the transistors.

[0022] The voltage-controlled transmission circuit 101 is used to control the short circuit degree between endpoints T1 and T2, and can have various different structures. Figure 3 and Figure 5 According to different embodiments of the present invention Figure 1 The circuit diagram of the voltage-controlled transmission circuit is shown. Figure 3 This is a circuit diagram of the voltage-controlled transmission circuit 101. When the reference voltage REF is between VDD / 2 and VDD, the voltage-controlled transmission circuit 101 forms a transmission path. This transmission path serves as the additional current path mentioned above to reduce the output voltage Vo. Figure 3 As shown, the voltage-controlled transmission circuit 101 includes PMOS P1, NMOS N1, and NMOS N2. NMOS N1 is controlled by a reference voltage REF to be turned on (conducting) or off (not conducting). Specifically, NMOS N1 is turned on when the reference voltage REF is higher than a first predetermined value.

[0023] PMOS P1 is coupled between the first current mirror CM_1 and NMOS N1, and is also coupled to ground potential. Specifically, the source terminal of PMOS P1 acts as... Figure 1 Terminal T1 is shown, and the gate of PMOS P1 is coupled to ground. NMOS N2 is coupled between NMOS N1 and the second current mirror CM2 and is biased by the first bias voltage B1. Additionally, in Figure 3 In the embodiment, the source of NMOS N2 is used as Figure 1 Endpoint T2 is shown.

[0024] In one embodiment, in actual operation, when the reference voltage REF increases to 0.5... When VDD and VDD are between, the first bias voltage B1 drops to a lower voltage, for example, 0.75V. VDD is used to reduce the short circuit between terminals T1 and T2. More specifically, due to the lower first bias voltage B1, the on-resistance of NMOS N2 increases, and the short circuit between terminals T1 and T2 is correspondingly limited. In such a design, if the reference voltage REF increases to 0.5... VDD to 0.75 Between VDD, the degree of short circuit between terminals T1 and T2 is controlled by the reference voltage REF. Furthermore, if the reference voltage REF is further increased to 0.75... Between VDD and VDD, the short-circuit severity between endpoints T1 and T2 is reduced by 0.75. The first bias voltage B1 clamps VDD.

[0025] In addition, to avoid the effects of process drift, the voltage-controlled transmission circuit 101 may include a PMOS P1 to compensate for the short circuit of terminals T1 and T2 when too many NMOS are turned on and too few PMOS are turned on.

[0026] PMOS P1, NMOS N1, and NMOS N2 can be replaced by other types of transistors. Therefore, Figure 3 The illustrated embodiment can be described as including: a first type transistor (e.g., NMOS N1) controlled to turn on or off by a reference voltage REF, wherein the first type transistor is turned on when the reference voltage REF is higher than a first predetermined value. It also includes a second type transistor (e.g., PMOS P1) coupled between a first current mirror CM1 and the first type transistor, and coupled to ground potential. It may further include a second type transistor (NMOS N2). This second type transistor is biased by a first bias voltage B1 and coupled between the first type transistor and the second current mirror CM2.

[0027] Figure 4 To illustrate an embodiment of the present invention Figure 2 The waveform diagram of the operation of amplifier 100 in the middle corresponds to Figure 3 The embodiment is illustrated in the figure. GN is Figure 2 The waveform represents the voltage at the source of NMOS MNa and MNb, V_T1 is the voltage at terminal T1, Cur is the current flowing through NMOS MNa and MNb, and Vo is the aforementioned output voltage Vo. Furthermore, the waveform shown above is the waveform when the voltage-controlled transmission circuit 101 does not form a transmission path (i.e., terminals T1 and T2 are not conducting). For example, Figure 3 NMOS N1 or Figure 4 The waveform shown below is when PMOS P1 is turned off. Conversely, the waveform below is when the voltage-controlled transmission circuit 101 forms a transmission path (i.e., terminals T1 and T2 are short-circuited). For example, Figure 3 NMOS N1 or Figure 4 The waveform when PMOS P1 is turned on.

[0028] like Figure 4 As shown, when the reference voltage REF increases, GN, V_T1, and Cur rise. When the reference voltage REF increases and terminals T1 and T2 are not conducting, the output voltage Vo also increases. However, when terminals T1 and T2 are short-circuited, the output voltage Vo is pulled down. According to... Figure 2 As described, when the reference voltage is higher than a first predetermined value, an additional current path is formed in the first current mirror CM1 due to the short circuit between terminals T1 and T2. The current flowing through the additional current path in the first current mirror CM1 flows through the second current mirror CM2 to ground potential. Therefore, the current flowing through the PMOS MPa increases, causing the voltage VSG of the PMOS MPa to increase. The large voltage VSG of the PMOS MPa suppresses the voltage VDS of the NMOS MNa, thus reducing the current flowing through the NMOS MNa and lowering its voltage GN. Therefore, the output voltage Vo is pulled down. Furthermore, if the voltage at terminal T2 increases, the output voltage Vo will be directly pulled down.

[0029] and Figure 3 The embodiments shown are the opposite. Figure 5 To illustrate the circuit diagram of the voltage-controlled transmission circuit 101 when the reference voltage REF is between 0 and VDD / 2, the additional transmission path it forms increases the output voltage Vo. For example... Figure 5 As shown, the voltage-controlled transmission circuit 101 includes NMOS N1, PMOS P1, and PMOS P2. PMOS P1 is turned on or off by a reference voltage REF. Specifically, PMOS P1 is turned on when the reference voltage REF is lower than a second predetermined value.

[0030] NMOS N1 is coupled between the second current mirror CM_2 and PMOS P1, and is coupled to VDD, where VDD is... Figure 1 The amplifier 100 shown is operating voltage. Specifically, the source of NMOS N1 is used as... Figure 1 Terminal T2 is shown, and the gate of NMOS N1 is coupled to VDD. PMOS P2 is coupled between PMOS P1 and the first current mirror CM1, and is biased by the second bias voltage B2. Furthermore, in Figure 5 In the embodiment, the source of PMOS P2 is used as Figure 1 The endpoint T1 is shown.

[0031] In one embodiment, in actual operation, if the reference voltage REF decreases to 0.5... Between VDD and ground potential, a second bias voltage B2 can be added to reduce the short-circuit level between terminals T1 and T2. For example, the second bias voltage B2 can be increased to 0.25 × VDD to increase the turn-on resistance of PMOS P2, thereby reducing the short-circuit level between terminals T1 and T2.

[0032] In addition, to avoid the effects of process drift, the voltage-controlled transmission circuit 101 may also include an NMOS N1 to compensate for the short-circuit levels of terminals T1 and T2 in the event that the NMOS is turned on too little and / or the PMOS is turned on too much.

[0033] NMOS N1, PMOS P1, and PMOS P2 can be replaced by other types of transistors. Therefore, it is possible to... Figure 5 The illustrated embodiment is described as including: a second type transistor (e.g., PMOS P1) controlled by a reference voltage REF, which is turned on or off by the reference voltage REF, wherein the second type transistor is turned on when the reference voltage is lower than a second predetermined value; a first type transistor (e.g., NMOS N1) coupled between a second current mirror CM2 and the second type transistor, and coupled to a predetermined voltage level (e.g., VDD); and a second type transistor P2 coupled between the second type transistor and the first current mirror CM1 and biased by a second bias voltage B2.

[0034] according to Figure 2 As described, when the reference voltage is lower than a second predetermined value, an additional current path is formed in the second current mirror CM2 due to the short circuit between terminals T1 and T2. The current flowing through this additional current path in the second current mirror CM2 flows through the first current mirror CM1 to the predetermined voltage source VDD. In this way, the current flowing through the NMOS MNc increases, causing the voltage VGS of the NMOS MNc to increase. The large voltage VGS of the NMOS MNc suppresses the voltage VSD of the PMOS MPc, thus reducing the current flowing through the PMOS MPc and making its voltage GN higher. Therefore, the output voltage Vo is pulled up. Furthermore, if the voltage at terminal T1 decreases, the output voltage Vo is directly pulled up.

[0035] According to the above embodiments, the drift of the amplifier's output voltage caused by variations in the reference voltage can be compensated. Therefore, problems in the prior art can be improved.

[0036] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

[0037] [Symbol Explanation]

[0038] 100 input levels

[0039] 101 Voltage-Controlled Transmission Circuit

[0040] VDD Pre-defined voltage source

[0041] CM1 First Current Mirror

[0042] CM2 Second Current Mirror

[0043] DI1 First Input Differential Pair

[0044] DI2 Second Input Differential Pair

[0045] CS1 First Current Source

[0046] CS2 Second Current Source

[0047] T1 and T2 endpoints

[0048] MPa, MPb, P1, P2 PMOS

[0049] MNa, MNb, MNc, MNd, N1, N2 NMOS

Claims

1. An amplifier having an input stage comprising: A first current mirror is coupled to a predetermined voltage source; A second current mirror is coupled to a ground potential; A first input differential pair is coupled to the first current mirror; A first current source is coupled to the first input differential pair; A second input differential pair is coupled to the second current mirror, wherein the first input differential pair and the second input differential pair are used to receive a reference voltage and an input signal; A second current source is coupled to the second input differential pair; as well as A voltage-controlled transmission circuit is controlled by a reference voltage and coupled to the first current mirror and the second current mirror. The voltage-controlled transmission circuit is configured such that when the reference voltage is higher than a first predetermined value, an additional current path is formed in the first current mirror and the current flowing through the additional current path in the first current mirror flows through the second current mirror to the ground potential. When the reference voltage is lower than a second predetermined value, an additional current path is formed in the second current mirror, and the current flowing through the additional current path in the second current mirror flows through the first current mirror to the predetermined voltage source.

2. The amplifier of claim 1, wherein the voltage-controlled transmission circuit comprises: A first type transistor is turned on or off by the reference voltage, wherein the first type transistor is turned on when the predetermined voltage is higher than the first predetermined value.

3. The amplifier of claim 2, wherein the voltage-controlled transmission circuit further comprises: A second type transistor is coupled between the first current mirror and the first type transistor, and coupled to the ground potential.

4. The amplifier of claim 3, wherein the first current mirror comprises a plurality of transistors and the second type of transistor is coupled to the control terminal of the plurality of transistors.

5. The amplifier of claim 3, further comprising: A first type transistor is biased by a first bias voltage and coupled between the first type transistor and the second current mirror.

6. The amplifier of claim 1, wherein the voltage-controlled transmission circuit comprises: A second type transistor is turned on or off by the reference voltage, wherein the second type transistor is turned on when the predetermined voltage is lower than the second predetermined value.

7. The amplifier of claim 6, wherein the voltage-controlled transmission circuit further comprises: A first type transistor is coupled between the second current mirror and the second type transistor, and is coupled to the predetermined voltage source.

8. The amplifier of claim 7, wherein the second current mirror comprises a plurality of transistors and the first type of transistor is coupled to a control terminal of the plurality of transistors.

9. The amplifier of claim 6, further comprising: A second type transistor is biased by a second bias voltage and coupled between the second type transistor and the first current mirror.

10. An LPDDR3 input buffer, comprising: An amplifier having an input stage comprising: A first current mirror is coupled to a predetermined voltage source; A second current mirror is coupled to a ground potential; A first input differential pair is coupled to the first current mirror; A first current source is coupled to the first input differential pair; A second input differential pair is coupled to the second current mirror, wherein the first input differential pair and the second input differential pair are used to receive a reference voltage and an input signal; A second current source is coupled to the second input differential pair; as well as A voltage-controlled transmission circuit is controlled by a reference voltage and coupled to the first current mirror and the second current mirror. The voltage-controlled transmission circuit is configured such that when the reference voltage is higher than a first predetermined value, an additional current path is formed in the first current mirror and the current flowing through the additional current path in the first current mirror flows through the second current mirror to the ground potential. When the reference voltage is lower than a second predetermined value, an additional current path is formed in the second current mirror, and the current flowing through the additional current path in the second current mirror flows through the first current mirror to the predetermined voltage source.

11. The LPDDR3 input buffer of claim 10, wherein the voltage-controlled transmission circuit comprises: A first type transistor is turned on or off by the reference voltage, wherein the first type transistor is turned on when the predetermined voltage is higher than the first predetermined value.

12. The LPDDR3 input buffer as claimed in claim 11, wherein the voltage-controlled transmission circuit further comprises: A second type transistor is coupled between the first current mirror and the first type transistor, and coupled to the ground potential.

13. The LPDDR3 input buffer of claim 12, wherein the first current mirror comprises a plurality of transistors and the second type of transistor is coupled to the control terminal of the plurality of transistors.

14. The LPDDR3 input buffer of claim 12, further comprising: A first type transistor is biased by a first bias voltage and coupled between the first type transistor and the second current mirror.

15. The LPDDR3 input buffer of claim 10, wherein the voltage-controlled transmission circuit comprises: A second type transistor is turned on or off by the reference voltage, wherein the second type transistor is turned on when the predetermined voltage is lower than the second predetermined value.

16. The LPDDR3 input buffer of claim 15, wherein the voltage-controlled transmission circuit further comprises: A first type transistor is coupled between the second current mirror and the second type transistor, and is coupled to the predetermined voltage source.

17. The LPDDR3 input buffer of claim 16, wherein the second current mirror comprises a plurality of transistors and the first type of transistor is coupled to the control terminal of the plurality of transistors.

18. The LPDDR3 input buffer of claim 15, further comprising: A second type transistor is biased by a second bias voltage and coupled between the second type transistor and the first current mirror.

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