5 gbps low voltage differential signal driver circuit for high speed serial interface

Abstract

The application belongs to the technical field of integrated circuits, and discloses a 5Gbps low-voltage differential signal driving circuit for a high-speed serial interface. The circuit is suitable for a 1.8V power supply voltage, and the output voltage swings 350mV on a 0.9V reference voltage. The whole circuit is simulated after being completed by using a 40nm process on a platform Cadence Spectre. A high-speed level shifter for voltage domain conversion is designed, so that the high-speed transmission of the LVDS is ensured.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to a 5Gbps low-voltage differential signal driving circuit for high-speed serial interfaces. Background Technology

[0002] With the popularization of vehicle networking, the role of ranging sensors is becoming increasingly important [1-3]. The amount of data they need to process is increasing, and traditional interface technologies can no longer meet the requirements of high-speed serial interfaces for high-speed, low-power interface circuits. Low voltage differential signaling (LVDS) circuit [4] is a high-speed, low-power general-purpose interface circuit. Due to the use of differential structure, it has excellent anti-noise interference capability. At the same time, the low voltage swing of LVDS makes it faster than other standard transmission circuits [5]. Therefore, high-speed serial interface circuits generally adopt the LVDS circuit structure. In 2014, Tadeusz Based on the 40nm process, Gianluca Traversi et al. designed an LVDS transceiver circuit applicable to X-ray imaging systems, but its transmission rate was only 1Gbps[6]. In 2018, Gianluca Traversi et al. designed an LVDS transceiver circuit applicable to multifunctional identification chips based on the 28nm process[7], with a maximum transmission rate of 1Gbps. In 2021, Zhou You et al. designed a high-speed, low-power LVDS driver circuit for CIS with a transmission rate of 2Gbps. Currently, there are few LVDS transmission end circuits on the domestic market with a transmission rate exceeding 2Gbps.

[0003] Some relevant background technical documents are as follows:

[0004] [1] C.Niclass, M.Soga, H.Matsubara, et al. "A 100-m Range 10-Frame / s 340×96-Pixel Time-of-Flight Depth Sensor in 0.18-μm CMOS" in IEEE Journal ofSolid-State Circuits, 2013, 48(2): 559-572.

[0005] [2]M.Perenzoni,D.Perenzoni,D.Stoppa."6.5A 64×64-pixel digitalsilicon photomultiplier direct ToF sensor with 100Mphotons / s / pixel backgroundrejection and imaging / altimeter mode with 0.14%precision up to 6km forspacecraft navigation and landing,"2016 IEEE International Solid-StateCircuits Conference(ISSCC),2016:118-119.

[0006] [3]A.R.Ximenes,P.Padmanabhan,M.Lee,et al."A 256×256 45 / 65nm 3D-stacked SPAD-based direct TOF image sensor for LiDAR applications withoptical polar modulation for up to 18.6dB interference suppression,"2018 IEEEInternational Solid-State Circuits Conference-(ISSCC),2018:96-98.

[0007] [4]“IEEE Standard for Low-Voltage Differential Signals(LVDS)for Scal-able Coherent Interface(SCI),”IEEE Std 1596.3-1996,1996.

[0008] [5]Andrea.Boni,Andrea.Pierazzi,Davide.Vecchi,“LVDS I / O for Gb / s-per-Pin Operation in 0.35-um CMOS,”IEEE Journal of Solid State Circuits,2001,36.

[0009] [6]T. A.Drozd and P.Kmon, "Design of the ultrafast LVDS I / Ointerface in 40nm CMOS process," 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014: 200-204.

[0010] [7] G.Traversi, F.De Canio, V.Liberali and A.Stabile, "Characterization of an LVDS Link in 28nm CMOS for Multi-Purpose Pattern Recognition," 2018 IEEEInternational Symposium on Circuits and Systems (ISCAS), 2018: 1-4. Summary of the Invention

[0011] In view of this, the purpose of the present invention is to provide a 5Gbps low-voltage differential signal driving circuit for a high-speed serial interface.

[0012] This invention provides a 5Gbps low-voltage differential signal driving circuit for a high-speed serial interface, including a level shifter, a pre-drive circuit, a main drive module, and a pre-emphasis module. The input signal of the LVDS transmission end is generated by the signal voltage Data_in of the previous stage data processing signal. The signal voltage Data_in is converted by the level shifter to adapt to the operating voltage of the LVDS main drive. The main drive module and the pre-emphasis module have large load capacitances. The output signal of the level shifter cannot directly drive the main drive and the pre-emphasis module. The signal needs to pass through the pre-drive circuit to improve the driving capability of the signal. In order to achieve a 5Gbps transmission rate, the pre-emphasis circuit is added to the main drive circuit. After the input signal is output from the pre-drive circuit, it is input to the LVDS transmission end main drive and simultaneously input to the pre-emphasis circuit. The main drive output is combined with the pre-emphasis output to finally obtain the LVDS transmission end output signal LVDS_out.

[0013] Furthermore, the level shifter includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first buffer, a second buffer, a first inverter, and a second inverter. The first and second inverters are connected in series. The output signals of the first and second inverters serve as the input signals IN and IN_B of the level shifter, respectively. The sources of the first and second PMOS transistors are connected and connected to the power supply terminal VDDH. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor, and the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the MOS transistor is connected to the drain of the first NMOS transistor and the gate of the second PMOS transistor, and outputs a signal to the first buffer. The drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the first PMOS transistor, and outputs a signal to the second buffer. The sources of the first NMOS transistor and the second NMOS transistor are connected and connected to the power supply terminal VSS. The gate of the third PMOS transistor is connected to the gate of the first NMOS transistor and connected to the output terminal of the first inverter. The gate of the fourth PMOS transistor is connected to the gate of the second NMOS transistor and connected to the output terminal of the second inverter. The output signals of the first buffer and the second buffer are used as differential output signals.

[0014] Furthermore, the signal voltage of the previous level data processing signal is 1.1V, and the LVDS main drive operates at 1.8V.

[0015] Compared with existing technologies, this invention designs a 5Gbps low-power, low-jitter LVDS transmission terminal circuit to meet the high-speed, low-power requirements of high-speed serial interfaces. The LVDS transmission terminal main drive circuit adopts a dual current-mode drive circuit, utilizes a common-mode feedback circuit to stabilize the common-mode level, and increases the signal swing through pre-emphasis to reduce signal jitter. Simultaneously, a high-speed level shifter with voltage domain conversion is designed to ensure high-speed LVDS transmission. Attached Figure Description

[0016] Figure 1 LVDS structure diagram;

[0017] Figure 2 This is a diagram of a level shifter. Detailed Implementation

[0018] To facilitate understanding of the present invention, the technical solution of the present invention will be specifically described below with reference to examples.

[0019] like Figure 1As shown, the 5Gbps Low Voltage Differential Signaling (LVDS) driving circuit for high-speed serial interfaces provided by this invention includes a level shifter, a pre-drive circuit, a main drive module, and a pre-emphasis module. The LVDS transmission input signal is generated by the previous stage data processing signal (Data_in), with a signal voltage of 1.1V. This voltage cannot drive the LVDS main drive, which requires 1.8V to operate; therefore, a level shifter is needed to convert the voltage from 1.1V to 1.8V. The main drive module and the pre-emphasis module have large load capacitances, and the output signal of the level shifter cannot directly drive them. The signal needs to pass through the pre-drive circuit to improve its driving capability. During high-speed data signal transmission, due to factors such as channel imperfections, parasitic capacitance, and large capacitive load at the receiving end, the higher the transmission rate, the more severe the high-frequency attenuation of the signal. To achieve a 5Gbps transmission rate, a pre-emphasis circuit is added to the main drive circuit. After the input signal is output from the pre-drive circuit, it is input to the main drive of the LVDS transmission terminal and simultaneously input to the pre-emphasis circuit. The output of the main drive is combined with the output of the pre-emphasis circuit to finally obtain the output signal (LVDS_out) of the LVDS transmission terminal.

[0020] The transmission rate of LVDS is affected by the input signal rate. To ensure that the rate is not affected after the input signal is level-shifted, a high-speed level shifter was designed to achieve 5Gbps signal level shifting, such as... Figure 2 As shown. The level shifter includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first buffer, a second buffer, a first inverter, and a second inverter. The first and second inverters are connected in series. The output signals of the first and second inverters are used as the input signals (IN, IN_B) of the level shifter, respectively. The sources of the first and second PMOS transistors are connected and connected to the power supply terminal VDDH. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor, and the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor. The third PMOS transistor... The drain of the S-MOSFET is connected to the drain of the first NMOS transistor and the gate of the second PMOS transistor, and outputs a signal to the first buffer. The drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the first PMOS transistor, and outputs a signal to the second buffer. The sources of the first and second NMOS transistors are connected and connected to the power supply terminal VSS. The gate of the third PMOS transistor is connected to the gate of the first NMOS transistor and connected to the output terminal of the first inverter. The gate of the fourth PMOS transistor is connected to the gate of the second NMOS transistor and connected to the output terminal of the second inverter. The output signals of the first and second buffers are used as differential output signals. Two inverters are connected in series, and their respective output signals are used as the input signals (IN, IN_B) of the level shifter. Figure 2It can be seen that the input signals IN and IN_B must always be out of phase.

[0021] The two inverters operate at VDDL, transistors MP1 and MP2 are connected to the VDDH power supply, and MN1 and MN2 are connected to the VSS power supply.

[0022] A 1.1V input signal enters from the gate terminals of a pair of NMOS transistors (MN1, MN2). When the input signal IN_B is high and IN is low, MN1, MP2, and MP4 are all turned on, and the potential at point VP is quickly pulled up to 1.8V. Similarly, when the input signal INB is low and IN is high, the potential at point VN is pulled up to 1.8V. VN and VP are connected to two buffers operating at 1.8V. The buffers shape the signal, and their output signals serve as differential outputs LS_P and LS_N.

[0023] This invention presents a 5Gbps low-power, low-jitter LVDS transmission circuit, which incorporates a high-speed level shifter with voltage domain conversion to ensure high-speed LVDS transmission. The circuit is suitable for a 1.8V supply voltage, and the output voltage swings by 350mV over a 0.9V reference voltage. The entire circuit was simulated using a 40nm process on the Cadence Spectre platform.

[0024] This invention addresses the high-speed, low-power requirements of high-speed serial interfaces by employing a 40nm CMOS process to design a 5Gbps low-power, low-jitter LVDS transmission terminal circuit. The LVDS transmission terminal main drive circuit utilizes a dual current-mode drive circuit, employing a common-mode feedback circuit to stabilize the common-mode level and using pre-emphasis to increase the signal swing and reduce signal jitter. A high-speed level shifter with voltage domain conversion is also designed to ensure high-speed LVDS transmission. The circuit layout area is 0.025mm². 2 Under different process angles, power supply voltages and temperatures, with an output load of 1.5pF, the transmission rate can reach 5Gbps, the jitter is 17ps, the maximum power consumption is 30.6mW, and the power efficiency is 6.13nW / Gbps, effectively realizing high-speed and low-power data transmission.

[0025] The symbols in the above formulas have the common meanings in semiconductor / microelectronic devices, and can be found in relevant textbooks.

[0026] It should be noted that conventional structures or configurations will be omitted where they may cause confusion in understanding of the present invention.

[0027] Furthermore, the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only illustrative of embodiments of the present invention. Additionally, any reference signs placed between parentheses in the claims should not be construed as limiting the claims.

[0028] Unless otherwise expressly intended, the numerical parameters in this specification and the appended claims are approximate values ​​and can be changed according to the desired characteristics obtained from the content of this invention. Specifically, all figures used in the specification and claims to indicate the content of composition, reaction conditions, etc., should be understood to be modified by the term "about" in all cases.

[0029] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0030] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not imply that the element has any ordinal number, nor does it represent the order of one element with another element, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0031] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0032] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this inventive approach should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single embodiment of the foregoing invention. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0033] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A 5Gbps low-voltage differential signal driving circuit for a high-speed serial interface, characterized in that: Includes a level shifter, a pre-drive circuit, a main drive module, and a pre-emphasis module; The input signal to the LVDS transmitter is generated by the signal voltage Data_in from the previous stage data processing signal. The signal voltage Data_in is converted by a level shifter to adapt to the operating voltage of the LVDS main driver. The main driver module and the pre-emphasis module have large load capacitances, and the output signal of the level shifter cannot directly drive the main driver and the pre-emphasis module. The signal needs to pass through the pre-drive circuit to improve the driving capability of the signal. In order to achieve a 5 Gbps transmission rate, the pre-emphasis circuit is added to the main driver circuit. After the input signal is output from the pre-drive circuit, it is input to the LVDS transmitter main driver and simultaneously input to the pre-emphasis circuit. The output of the main driver is combined with the output of the pre-emphasis circuit to finally obtain the LVDS transmitter output signal LVDS_out. The level shifter includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first buffer, a second buffer, a first inverter, and a second inverter. The first and second inverters are connected in series. The output signals of the first and second inverters serve as the input signals IN and IN_B of the level shifter, respectively. The sources of the first and second PMOS transistors are connected together and connected to the power supply terminal VDDH. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor, and the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the second PMOS transistor, and outputs a signal to the first buffer. The drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the first PMOS transistor, and outputs a signal to the second buffer. The sources of the first NMOS transistor and the second NMOS transistor are connected and connected to the power supply terminal VSS. The gate of the third PMOS transistor is connected to the gate of the first NMOS transistor and connected to the output terminal of the first inverter. The gate of the fourth PMOS transistor is connected to the gate of the second NMOS transistor and connected to the output terminal of the second inverter. The output signals of the first buffer and the second buffer are used as differential output signals.

2. The driving circuit as described in claim 1, characterized in that: The signal voltage of the previous level data processing signal is 1.1V, and the LVDS main drive operates at 1.8V.

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