A clock convergence method and device

Abstract

The present invention relates to a clock convergence method, which is characterized by comprising the steps of: the FRAMER chip outputs a feedback signal to the FPGA according to the clock frequency point input by the clock chip and the standard clock frequency point of the service; after receiving the feedback signal once, the FPGA sends multiple pulses to the clock chip, and the multiple pulses are used to enable the clock chip to perform multiple fine-tuning on the clock output to the FRAMER chip. It can effectively improve the clock convergence speed and the stability of clock output when the service is switched.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and particularly to a clock convergence method and device. Background Art

[0002] Currently, some FRAMER chips have both the ODUk (optical channel data unit) layer network function of traditional OTN (optical transport network) and support the OSU (Optical Service Unit) layer network function. When configuring services for such FRAMER chips, the clock input source required by the chip serdes is implemented by an external clock chip. When switching services, it is accompanied by the switching of the external clock. There is a certain frequency offset between the clock value output by the clock chip and the standard value of the service, and it is necessary to adjust the clock waterline to ensure that the frequency offset of the clock is within 20 ppm. The current clock adjustment technology has problems such as excessive clock convergence jitter, slow clock convergence, and inability to recover in case of abnormal clocks, resulting in a very slow service switching time. Summary of the Invention

[0003] Embodiments of the present invention provide a clock convergence method and device, which can effectively improve the speed of clock convergence and the stability of clock output during service switching.

[0004] On the one hand, embodiments of the present invention provide a clock convergence method, which is characterized by including the steps of:

[0005] The FRAMER chip outputs a feedback signal to the FPGA according to the clock frequency point input by the clock chip and the standard clock frequency point of the service;

[0006] After receiving the feedback signal once, the FPGA sends multiple pulses to the clock chip, and the multiple pulses are used to make the clock chip finely adjust the clock output to the FRAMER chip multiple times.

[0007] In some embodiments, after the FPGA receives the feedback signal output by the FRAMER chip each time, it further includes the steps of:

[0008] Judging whether the absolute value of the received feedback signal value exceeds a preset limit value. If so, it is considered that the feedback signal is abnormal and discarded;

[0009] If the absolute value of the received feedback signal value does not exceed the preset limit value, the current feedback signal value is saved and compared with the previously saved feedback signal value, and when the difference between the current feedback signal value and the previously saved feedback signal value does not exceed the preset filtering condition threshold, the current feedback signal is used as a valid feedback signal;

[0010] The FPGA sends multiple pulses to the clock chip for clock adjustment only based on the feedback signal determined to be valid.

[0011] In some embodiments, after the FPGA receives the feedback signal once, it sends multiple pulses to the clock chip, including the steps of:

[0012] Performing division on the feedback signal to obtain the number of fine-tuning times;

[0013] Sending multiple pulses to the clock chip according to the number of fine-tuning times.

[0014] In some embodiments, the performing division on the feedback signal to obtain the number of fine-tuning times includes the steps of:

[0015] Obtaining the number of fine-tuning times according to X = |B| / C, where X is the number of fine-tuning times, |B| is the absolute value of the feedback signal, and C is the chip characteristic value of the FRAMER chip and the chip characteristic value is configured as needed.

[0016] In some embodiments, the multiple pulses are directional pulses, and their directions are consistent with the positive and negative of the feedback signal;

[0017] When the clock chip performs multiple fine-tunings on the clock output to the FRAMER chip, according to the number and direction of the received pulses, it configures and fine-tunes the clock output by itself, and the step size of a single fine-tuning is configured as needed.

[0018] In some embodiments, the making the clock chip perform multiple fine-tunings on the clock output to the FRAMER chip includes the steps of:

[0019] Setting the initial step size and the fast convergence threshold of the fine-tuning. When the fine-tuning time reaches the fast convergence threshold, a control pulse is sent to make the clock chip modify the fine-tuning step size and make the modified fine-tuning step size smaller than the initial step size.

[0020] In some embodiments, during the multiple fine-tunings, after the clock chip modifies the fine-tuning step size and makes the modified fine-tuning step size smaller than the initial step size, it further includes the steps of:

[0021] Adopting the median value average filtering method to perform stable wave processing on the subsequent clock convergence.

[0022] In some embodiments, the adopting the median value average filtering method to perform stable wave processing on the subsequent clock convergence includes the steps of:

[0023] Continuously collecting N feedback signal values, removing the maximum and minimum values, and calculating the arithmetic average of the N - 2 feedback signal values and using it as the input feedback signal value for subsequent clock adjustment;

[0024] Send pulses to the clock chip for fine-tuning according to the input feedback signal value corresponding to the arithmetic mean.

[0025] In some embodiments, after the FRAMER chip outputs a feedback signal to the FPGA each time, the method includes the steps of:

[0026] Determine whether the feedback signal value flips in both positive and negative directions within a preset time threshold. If not, it is considered that the feedback signal is abnormal, and the feedback signal sent by the FRAMER chip is reset.

[0027] On the other hand, an embodiment of the present invention provides a device, characterized in that the device includes: at least one processor; and a memory coupled to the at least one processor, the memory containing instructions stored therein, the instructions being loaded and executed by the processor to implement the method according to any one of the method embodiments.

[0028] The beneficial effects brought by the technical solution provided by the present invention include:

[0029] The purpose of this patent in the embodiments of the present invention is to provide a clock convergence method and device, which effectively improves the clock convergence speed and the stability of clock output during service switching. By performing multi-frequency adjustment and convergence on the single feedback signal sent by the FRAMER chip, the convergence speed can be increased while the number of adjustments can be reduced, effectively improving the clock convergence efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 It is a schematic flowchart of a clock convergence method provided by an embodiment of the present invention;

[0032] Figure 2 It is a schematic overall flowchart of service clock configuration and adjustment provided by an embodiment of the present invention;

[0033] Figure 3 It is a schematic diagram of implementing a clock configuration detection and verification mechanism provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0035] As Figure 1 shown, an embodiment of the present invention provides a clock convergence method, including the steps of:

[0036] S100: The FRAMER chip outputs a feedback signal to the FPGA according to the clock frequency point input by the clock chip and the standard clock frequency point of the service;

[0037] S200: After receiving the feedback signal once, the FPGA sends multiple pulses to the clock chip, and the multiple pulses are used to enable the clock chip to finely adjust the clock output to the FRAMER chip multiple times.

[0038] It can be understood that, as Figure 2 shown, before S100, the upper-layer software can configure the external clock chip to enable the clock chip to output a clock to the FRAMER chip and initialize the clock reference source of the FRAMER chip as an external input, and configure the access port clock source independently. Among them, the upper-layer software configures the clock chip by directly writing the registers of the clock chip through a configuration file, and generally does not judge the service type during the configuration process, but only configures according to the clock frequency point of the service. The independence of the access port means that the clocks between different ports of the FRAMER chip are independent, and the FRAMER can also be configured to share a clock source among multiple ports.

[0039] It should be noted that the standard clock frequency point of the service in S100 is specified by the industry standard of each service, and the FRAMER chip has written it into its internal register according to the industry standard. The feedback signal is the frequency difference between the clock frequency point input by the external clock and the standard clock frequency point of the service, that is, the difference between the actual frequency point received by the FRAMER chip and the industry standard of the service.

[0040] The embodiment of the present invention takes into account the problem that the convergence speed is slow when the waterline clock is adjusted in the way of single-signal single-step adjustment for the feedback signal sent by the FRAMER to the FPGA, and proposes a method for multi-frequency fine adjustment of a single feedback signal, enabling the FPGA to send multiple pulses according to the feedback signal received once to enable the clock chip to finely adjust the output clock multiple times, thereby improving the convergence speed while reducing the number of adjustments, and effectively improving the clock convergence efficiency.

[0041] Further optimally, before S100, the upper-layer software determines whether the clock needs to be switched before the service clock is switched; and after the clock configuration is switched, the stability of the clock output by the clock chip is verified. If the output clock is unstable, the clock output is reconfigured.

[0042] It should be noted that the service clock is derived from an external clock chip. Each time there is a new service configuration, the upper-layer software will judge the configured service clock. If the service is established for the first time, the configured clock is empty. Determining whether the clock needs to be switched is to determine whether the new service clock frequency point and the configured service clock frequency point need to be switched. If the new service clock frequency point and the configured service clock frequency point are different, the clock needs to be switched regardless of whether the services are the same.

[0043] It can be understood that when verifying the stability, after the upper-layer software configures the clock chip, the output status register of the clock chip is read. If there is an alarm in the register, it is unstable. If there is no alarm in the output status register, then the phase-locked loop register of the clock chip is read to check whether the phase-locked loop of the clock chip is locked. If it is not locked, it is unstable. When it is determined to be unstable, it is considered that there is an abnormality in the clock output of the clock chip, either a configuration error or a hardware error. Then, the configuration of the clock chip needs to be reflashed. When reflashing the configuration, the clock chip can be reset first.

[0044] As Figure 3 shown, in one embodiment, after configuring the clock input source of the FRAMER chip, the upper-layer software determines whether the clock chip needs to be reconfigured. If so, the input clock of the clock chip is reconfigured. If not, the stability of the output clock is continuously determined. If it is stable, the FRAMER chip outputs a feedback signal according to the service clock source and further adjusts the clock waterline according to the feedback signal; if it is unstable, the clock state is cleared and the clock chip is reconfigured.

[0045] It should be noted that after the service clock is switched, the upper-layer application software reads the configuration return of the clock chip to ensure that the clock chip is correctly configured, and according to the lock signal of the clock output, ensures that the clock chip is locked to the local clock source. Among them, the configuration return means that the clock chip will return a correct (0) or incorrect (-1) return value after responding to the clock configuration. The lock signal is output by the clock chip. The clock chip of the service single board needs to be locked to the clock source of the local device. When it is locked to the local clock source, a lock signal will be output. The local clock source is provided by the hardware clock single board of the entire device to ensure that the clocks of each service single board are of the same source and in the same direction.

[0046] In this embodiment, a clock configuration detection and verification mechanism is added, which avoids unnecessary clock switching. At the same time, the clock detection ensures the correctness of the clock output, improving the reliability for subsequent locking of the clock source.

[0047] In some embodiments, after the FPGA receives the feedback signal output by the FRAMER chip each time, the following steps are further included:

[0048] S211: Determine whether the absolute value of the received feedback signal value exceeds a preset limit value. If so, it is considered that the feedback signal is abnormal and discarded;

[0049] S212: If the absolute value of the received feedback signal value does not exceed the preset limit value, save the current feedback signal value and compare it with the previously saved feedback signal value, and use the current feedback signal as a valid feedback signal when the difference between the current feedback signal value and the previously saved feedback signal value does not exceed the preset filtering condition threshold;

[0050] The FPGA only sends multiple pulses to the clock chip for clock adjustment based on the feedback signals determined to be valid.

[0051] In this embodiment, considering the large jitter of the feedback signal, in order to prevent slow convergence caused by large jitter, a filtering scheme is adopted to discard the feedback signals determined to be abnormal (with too large jitter). Thus, the convergence efficiency is improved. It can be understood that the conditions for determining whether it is abnormal include: whether the feedback signal value exceeds the preset limit value and whether the positive-negative flip difference between the previous and current feedback signals exceeds the preset filtering condition threshold. The feedback signal values with too large jitter will be filtered and discarded, and the FPGA will not perform further processing (clock adjustment).

[0052] Preferably, the preset limit value can be set to 3000, and the preset filtering condition threshold can be set to 2000.

[0053] In some embodiments, in S200, after the FPGA receives the feedback signal once, it sends multiple pulses to the clock chip, including the following steps:

[0054] S220: Perform division on the feedback signal to obtain the number of fine-tuning times;

[0055] S230: Send multiple pulses to the clock chip according to the number of fine-tuning times.

[0056] It can be understood that by performing division on the feedback signal value to obtain the adjustment times, and performing fine-tuning on the clock chip by sending multiple pulses according to the adjustment times for one feedback signal, the convergence speed is improved and the adjustment times are reduced.

[0057] Preferably, in S220, the number of fine-tuning times can be obtained according to X = |B| / C, where X is the number of fine-tuning times, |B| is the absolute value of the feedback signal, and C is the chip characteristic value of the FRAMER chip and the chip characteristic value is configured as needed.

[0058] Preferably, the pulse in S230 is a pulsed signal with a direction, and the direction is consistent with the positive and negative of the feedback signal; when the clock chip performs multiple fine-tuning on the clock output to the FRAMER chip, according to the received number and direction of pulses, the clock output by itself is configured for fine-tuning, and the step size of each single fine-tuning is configured as required.

[0059] In some embodiments, in S200, making the clock chip perform multiple fine-tuning on the clock output to the FRAMER chip includes the steps of: setting an initial step size for fine-tuning and a fast convergence threshold value. When the fine-tuning time reaches the fast convergence threshold value, a control pulse is sent to cause the clock chip to modify the fine-tuning step size, and the modified fine-tuning step size is smaller than the initial step size, and the first pulse corresponding to each feedback signal is fine-tuned according to the initial step size.

[0060] It should be noted that the FPGA controls the clock chip to adjust upward or downward by sending a pulse signal (control pulse). After reducing the adjustment step size, each time a pulse signal is received, the adjustment amplitude of the clock frequency point is relatively small, just like taking small steps, so that the clock frequency point fluctuates within the range of the row standard (20ppm) and remains stable.

[0061] It can be understood that in this embodiment, by introducing the convergence step size rhythm control of frequency conversion, after quickly converging according to the initial step size, the convergence step size is then reduced, which can prevent excessive oscillation at the end of convergence, and ensure the long-term stability of services by refining the clock frequency offset.

[0062] In some embodiments, during the multiple fine-tuning process, after the clock chip modifies the fine-tuning step size and makes the modified fine-tuning step size smaller than the initial step size, a median value average filtering method can also be used to perform wave stabilization processing on the subsequent clock convergence. The wave stabilization processing can eliminate the deviation caused by pulse interference and ensure the smoothness of the service clock water line.

[0063] Furthermore, using the median value average filtering method to perform wave stabilization processing on the subsequent clock convergence includes the steps of:

[0064] S261: Continuously collect N feedback signal values, calculate the arithmetic mean of the N - 2 feedback signal values after removing the maximum and minimum values, and use it as the input feedback signal value for subsequent clock adjustment;

[0065] S262: Send a pulse to the clock chip for fine-tuning according to the input feedback signal value corresponding to the arithmetic mean.

[0066] In some embodiments, each time the FRAMER chip outputs a feedback signal to the FPGA, it is judged whether the feedback signal value flips in the positive and negative directions within a preset time threshold. If not, the feedback signal is considered abnormal, and the feedback signal sent by the FRAMER chip is reset.

[0067] It should be noted that resetting the FRAMER chip means that when the upper-layer application polls the reset flag register of the FPGA and finds that the reset flag register is set, it will send a control configuration to the FRAMER chip to reset the adjustment feedback function of the FRAMER chip.

[0068] It can be understood that in this embodiment, an exception recovery mechanism is added for abnormal scenarios. If the feedback signal is abnormal, the transmission of the feedback signal will be reset to its initial value.

[0069] In a specific embodiment, a clock convergence method includes the steps of:

[0070] S1. Before switching the service clock, add a clock configuration detection and verification mechanism;

[0071] S2. Filter the feedback signal output by the FRAMER chip;

[0072] S3. After the FPGA receives a feedback signal once, send multiple pulses to the clock chip for fine-tuning;

[0073] S4. Add an exception recovery mechanism to converge exceptions and reset the feedback signal;

[0074] S5. Perform variable-frequency convergence step rhythm control;

[0075] S6. At the end of convergence, use the median value average filtering method for wave stabilization processing.

[0076] Further, S1 includes:

[0077] S1.1. The upper-layer software configures the external clock chip, outputs the clock to the FRAMER chip, and initializes the clock reference source of the FRAMER chip as an external input, and configures the clock source independently.

[0078] S1.2. The upper-layer software determines whether the clock needs to be switched before switching the service clock.

[0079] S1.3. After switching the clock configuration, verify the stability of the clock output by the clock chip. If the output clock is unstable, reconfigure the clock output.

[0080] After adopting S1, unnecessary clock switching can be avoided, and the stability of the clock output can be detected after configuring the clock chip.

[0081] Further, to prevent excessive jitter from causing slow convergence, S2 also includes:

[0082] S2.1. The FPGA receives the feedback signal and determines whether the value of the feedback signal is the initial value A. If so, the adjustment starts, and at this time, the timer (which can be set to 5 s) is enabled to start timing.

[0083] S2.2. Process the received feedback signal and verify the value B of the feedback signal received at this time. If the absolute value of this feedback signal exceeds the preset limit value Z (the empirical value 3000 after repeated tests), then discard this feedback signal value (abnormal value).

[0084] S2.3. When it is verified that the value B of the received feedback signal does not exceed the preset limit value Z, then save this feedback signal value B, and compare it with the previously saved feedback signal value B'. If |B - B'| is greater than M (the filtering condition value, which can be set to the empirical value 2000), then consider this feedback signal value B as abnormal and discard it; if |B - B'| is less than or equal to M, then save this feedback signal value B and use it as the valid feedback signal value for the next step of processing (as the basis for sending multiple pulses for clock adjustment).

[0085] In a specific embodiment, after the service clock adjustment starts, the FRAMER chip sends a feedback signal (at this time, the value of the feedback signal sent for the first time is the base clock feedback value A, A = 0x8000000) to the FPGA. At this time, the FPGA receives the initial value A and enables the adjustment timer to start timing. Subsequently, the FPGA successively receives the feedback values B1(2000), B2(3400), B3(-500), B4(500). Among them, B2 exceeds the limit value Z(3000) and will be discarded. B1, B3, and B4 are all within the range and can be processed subsequently. After B1 is processed by the FPGA, it is saved as B'. B2 is discarded. When B3 is received, according to the judgment condition M = 2000 + |-500

[0086] | = 2500, which exceeds the adjustment range, and B3 is also discarded and not saved. When B4 is received, according to the judgment condition M = |2000 - 500| = 1500, which meets the normal range, the value of B4 is saved as the previous feedback value B';

[0087] Based on the above technical solutions, considering that service switching is very sensitive to time in applications and the convergence speed requirement for clock frequency point adjustment after clock switching is relatively high, the convergence solution S3 for dynamically adjusting the number of pulses according to the size of the feedback signal is proposed. S3 includes:

[0088] S3.1. The valid feedback signal value (after being filtered by S2) is received and processed by the internal module of the FPGA to obtain the adjustment times X = |B| / C, where C is the characteristic value of the FRAMER chip and can be flexibly configured.

[0089] S3.2. The FPGA sends X pulses with directions to the clock chip, and the directions are the same as the positive and negative of the feedback value B.

[0090] S3.3. The clock chip configures and fine-tunes its output clock according to the received number of pulses and directions. The step size of a single adjustment is configurable, and the initial value can be set to 0.2 ppm.

[0091] For example, assume C = 200, and the received feedback values are B1(1000), B2(-400), B3(300). Then the FPGA sends three groups of pulses, which are 5 positive pulses, 2 negative pulses, and 1 positive pulse respectively. After the clock chip receives 3 groups of pulses, it will adjust by 1 ppm, -0.4 ppm, and 0.2 ppm.

[0092] Based on the above technical solutions, S4 adds an exception recovery mechanism for abnormal scenarios. When the feedback signal is abnormal, the sending of the feedback signal will be reset to the initial value, and then the timer will be reset for a new round of feedback adjustment. S4 includes:

[0093] S4.1. After the FPGA first receives the initial value feedback value A, it sets the alarm flag F = 1;

[0094] S4.2. Before the FPGA saves the received feedback value B within the range as the previous feedback value B' each time after processing, it will perform a logical operation on B and B', and the rules are as follows:

[0095] if((B>0)&&(B'<0))

[0096] F = 0;

[0097] else if((B<0)&&(B'>0))

[0098] F = 0;

[0099] S4.3. After the FPGA timer reaches 5 s, it detects the flag F at this time. If F = 1, it means that there has been no continuous adjustment in the positive and negative directions within 5 s of adjustment time, which is regarded as an abnormality. At this time, the timer and the feedback signal of the FRAMER are reset for a new round of feedback adjustment.

[0100] Based on the above technical solutions, S5 introduces a variable-frequency convergence step rhythm control. After quickly converging at a 0.2 ppm step, the convergence step is reduced to 0.125 ppm to prevent excessive oscillation at the end of convergence and ensure the smoothness of the service clock waterline. S5 includes:

[0101] S5.1. After the FPGA timer reaches 5 s, it detects the flag F. If F = 0, it means that the fast convergence is completed. At this time, the FPGA sends a control pulse to the clock chip once;

[0102] S5.2 After the clock chip receives the control pulse from the FPGA, it changes the internal adjustment step from 0.02 ppm to 0.125 ppm and stops receiving the adjustment pulse signal from the FPGA;

[0103] S5.3 After the clock chip completes the step modification of 0.125 ppm, it continues to receive the pulse signal from the FPGA for clock adjustment.

[0104] Based on the above technical solutions, in order to eliminate the deviation caused by pulse interference and ensure the smoothness of the service clock waterline, a wave stabilization process is performed at the end of the clock waterline adjustment. The median value average filtering method is adopted at the end of the convergence period. S6 includes:

[0105] S6.1 Continuously collect N feedback values, remove one maximum value and one minimum value, and then calculate the arithmetic average of the N - 2 feedback values as the adjusted feedback signal value B, where the value of N can be any number selected from 3 to 8.

[0106] S6.2, S6.3 The FPGA sends a pulse to the clock chip for fine - tuning according to the adjusted feedback signal value B.

[0107] Specifically, it can be assumed that N = 5 is selected. The FPGA successively receives 5 groups of feedback values, which are feedback value B1(100), B2(200), B3(-100), B4(-50), B5(-20). According to the algorithm filtering conditions, the maximum value B2(200) and the minimum value (-100) do not participate in the calculation of the arithmetic average. The arithmetic average of B1(100), B4(-50), and B5(-20) is calculated to obtain the feedback value B = 30. Subsequently, the FPGA sends a pulse to the clock chip for fine - tuning according to the feedback value of 30.

[0108] The beneficial effects of the embodiments of the present invention include:

[0109] Based on the cooperation of the FRAMER, FPGA, and clock chip to achieve a feedback loop, a single - signal multiple - pulse adjustment mechanism is realized, which improves the clock convergence speed and has variable adjustment step sizes to adapt to different service types. At the same time, a filtering mechanism is added during the adjustment process of the feedback loop to ensure that the clock adjustment jitter is within a certain range, improving the stability of clock adjustment and the stability of the CBR service. It also further solves the problem that the new service clock cannot converge quickly after the service clock is switched.

[0110] On the other hand, an embodiment of the present invention further provides a device, which includes: at least one processor; and a memory coupled to the at least one processor, where the memory contains instructions stored therein, and the instructions, when loaded and executed by the processor, are used to implement the method described in any one of the foregoing method embodiments. It can be understood that the technical solutions that the device can implement and the technical effects that can be achieved are equivalent to the technical scope and technical effects covered by the foregoing method embodiments.

[0111] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof. In the hardware implementation, the division of the functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be executed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or be implemented as hardware, or be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable storage medium, which can include a computer-readable storage medium (or non-transitory medium) and a communication medium (or transitory medium).

[0112] It should be noted that in the present invention, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0113] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A clock convergence method, characterized in that It includes the steps: The FRAMER chip outputs a feedback signal to the FPGA according to the clock frequency point input by the clock chip and the standard clock frequency point of the service; After receiving the feedback signal once, the FPGA sends multiple pulses to the clock chip, and the multiple pulses are used to make the clock chip finely adjust the clock output to the FRAMER chip multiple times; After receiving the feedback signal once, the FPGA sends multiple pulses to the clock chip, including the steps: Performing division on the feedback signal to obtain the number of fine adjustments; Sending multiple pulses to the clock chip according to the number of fine adjustments; The multiple pulses are directional pulses, and their direction is consistent with the positive and negative of the feedback signal; The performing division on the feedback signal to obtain the number of fine adjustments includes the steps: Obtaining the number of fine adjustments according to X = |B| / C, where X is the number of fine adjustments, |B| is the absolute value of the feedback signal, and C is the chip characteristic value of the FRAMER chip and the chip characteristic value is configured as required; When the clock chip finely adjusts the clock output to the FRAMER chip multiple times, according to the number and direction of the received pulses, it configures and finely adjusts the clock output by itself, and the step size of each fine adjustment is configured as required.

2. The clock convergence method according to claim 1, characterized in that, After the FPGA receives the feedback signal output by the FRAMER chip each time, it further includes the steps: Judging whether the absolute value of the received feedback signal value exceeds a preset limit value. If so, it is considered that the feedback signal is abnormal and discarded; If the absolute value of the received feedback signal value does not exceed the preset limit value, the current feedback signal value is saved and compared with the previously saved feedback signal value, and when the difference between the current feedback signal value and the previously saved feedback signal value does not exceed the preset filtering condition threshold, the current feedback signal is used as a valid feedback signal; The FPGA only sends multiple pulses to the clock chip for clock adjustment based on the feedback signal determined to be valid.

3. The clock convergence method according to claim 1, wherein The making the clock chip finely adjust the clock output to the FRAMER chip multiple times includes the steps: Setting the initial step size of the fine adjustment and the fast convergence threshold value. When the fine adjustment time reaches the fast convergence threshold value, a control pulse is sent to make the clock chip modify the fine adjustment step size and make the modified fine adjustment step size smaller than the initial step size.

4. The clock convergence method according to claim 3, wherein During the multiple fine adjustments, after the clock chip modifies the fine adjustment step size and makes the modified fine adjustment step size smaller than the initial step size, it further includes the steps: Adopting the median value average filtering method to perform wave stabilization processing on the subsequent clock convergence.

5. The clock convergence method according to claim 4, characterized in that, The adopting the median value average filtering method to perform wave stabilization processing on the subsequent clock convergence includes the steps: Continuously collecting N feedback signal values, removing the maximum value and the minimum value, and calculating the arithmetic average of the N - 2 feedback signal values and using it as the input feedback signal value for subsequent clock adjustment; Sending pulses to the clock chip for fine adjustment according to the input feedback signal value corresponding to the arithmetic average.

6. The clock convergence method according to claim 1, characterized in that When the FRAMER chip outputs a feedback signal to the FPGA each time, it includes the steps: Determine whether the feedback signal value undergoes positive and negative reversals within a preset time threshold. If not, it is considered that the feedback signal is abnormal, and the feedback signal sent by the FRAMER chip is reset.

7. A device, characterized in that, The device includes: at least one processor; and a memory coupled to the at least one processor, the memory containing instructions stored therein, the instructions being loaded and executed by the processor to implement the method according to any one of claims 1-6.

Images