Encoders and Decoders

Abstract

An encoder and a decoder are disclosed. The encoder includes a processing circuit configured to: receive raw data; divide the raw data into a plurality of raw q-bit words; assemble a data packet including N raw q-bit words from the plurality of raw q-bit words; identify a first encoder value and a second encoder value missing from the values ​​of the N raw q-bit words; encode the N raw q-bit words based on a one-to-one mapping from q-bit raw values ​​to q-bit encoded values ​​according to the first encoder value and the second encoder value to generate N encoded q-bit payload words, the N encoded q-bit payload words not containing words that are all zeros and not containing words that are all ones; generate a key representing the first encoder value and the second encoder value; and transmit the key and the N encoded q-bit payload words.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 185,190 filed in the U.S. Patent and Trademark Office on May 6, 2021, and U.S. Non-Provisional Patent Application No. 17 / 389,146 filed in the U.S. Patent and Trademark Office on July 29, 2021, the disclosures of which are hereby incorporated by reference in their entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to systems and methods for implementing low-overhead transform coding in a communication link. Background Art

[0004] In electronic data communications, such as in serial data links, communications between a transmitter and a receiver can be synchronized using a clock recovery or clock data recovery (CDR) process. For example, a receiver can generate a clock from an approximate frequency reference using a phase-locked loop (PLL), and then use a CDR to phase-align the generated signal with transitions (between high and low signal levels) in the data stream. However, if the data run length (e.g., a sequence of consecutive 1s or 0s) exceeds a certain length due to insufficient transitions for the receiver to detect, recovery of the clock signal can fail. Summary of the invention

[0005] According to one embodiment of the present disclosure, an encoder includes a processing circuit configured to: receive original data; divide the original data into multiple original q-bit words; assemble a data packet including N original q-bit words from the multiple original q-bit words; identify a first encoder value D1 and a second encoder value D2 missing from the values ​​of the N original q-bit words; encode the N original q-bit words based on a one-to-one mapping from q-bit original values ​​to q-bit encoded values ​​according to the first encoder value D1 and the second encoder value D2 to generate N encoded q-bit payload words, the N encoded q-bit payload words do not contain words that are all zeros and do not contain words that are all ones; generate a key representing the first encoder value D1 and the second encoder value D2; and transmit the key and the N encoded q-bit payload words.

[0006] According to one embodiment of the present disclosure, a decoder includes a processing circuit configured to: receive a key and N encoded q-bit payload words; decode a first encoder value D1 and a second encoder value D2 from the key; and decode the N encoded q-bit payload words based on a one-to-one mapping from q-bit encoded values ​​to q-bit original values ​​according to the first encoder value D1 and the second encoder value D2 to generate N decoded original q-bit words. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings, together with the specification, illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the present invention.

[0008] Figure 1 is a schematic block diagram of a serial link between a transmitter and a receiver, the transmitter including an encoder according to an embodiment of the present disclosure and the receiver including a decoder according to an embodiment of the present disclosure.

[0009] Figure 2 is a depiction of binary data transmitted over a data link using a unipolar line code, where a logic 1 value is encoded as a logic level high (H) signal and a logic 0 value is encoded as a logic level low (L) signal.

[0010] Figure 3 is a schematic depiction of a data packet according to one embodiment of the present disclosure.

[0011] Figure 4 is a schematic depiction of maximum run length in the example case of six-bit words (q=6) when encoding data in a data packet according to an embodiment of the present disclosure.

[0012] Figure 5 is a flowchart depicting a method for encoding raw data to generate a data packet according to one embodiment of the present disclosure.

[0013] Figure 6 Mapping of a 4-bit value of an original word to a corresponding encoded word in binary representation and decimal representation based on an encoder value according to one embodiment of the present disclosure is shown.

[0014] Figure 7 is a flow chart depicting a method for decoding an encoded data packet according to one embodiment of the present disclosure.

[0015] Figure 8 Mapping of a 4-bit value of an encoded word to a corresponding decoded word or original word based on an encoder value is shown according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In the following detailed description, only certain exemplary embodiments of the present invention are shown and described by way of illustration. As will be appreciated by those skilled in the art, the invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Throughout the specification, the same reference numerals represent the same elements.

[0017] Aspects of embodiments of the present invention relate to systems and methods for reducing or minimizing the run length of digital data in a communication system. In more detail, some aspects of embodiments of the present disclosure relate to systems and methods for encoding digital data to ensure a limited run length or to ensure that the run length of a packet of digital data is less than or equal to a specific limit value in the form of a run length limited code.

[0018] According to one embodiment of the present disclosure, an encoder includes a processing circuit configured to: receive original data; divide the original data into multiple original q-bit words; assemble a data packet including N original q-bit words from the multiple original q-bit words; identify a first encoder value D1 and a second encoder value D2 missing from the values ​​of the N original q-bit words; encode the N original q-bit words based on a one-to-one mapping from q-bit original values ​​to q-bit encoded values ​​according to the first encoder value D1 and the second encoder value D2 to generate N encoded q-bit payload words, the N encoded q-bit payload words do not contain words that are all zeros and do not contain words that are all ones; generate a key representing the first encoder value D1 and the second encoder value D2; and transmit the key and the N encoded q-bit payload words.

[0019] The processing circuit may be configured to encode the q-bit original value x as a q-bit encoded value x′ based on a comparison of the q-bit original value x with the first encoder value D1 and the second encoder value D2 .

[0020] In some embodiments, the first encoder value D1 and the second encoder value D2 may have matching prefixes of length q-1, the calculated value E may correspond to the q-1 most significant bits of the first encoder value D1, and the key includes the calculated value E representing the first encoder value D1 and the second encoder value D2.

[0021] The processing circuit may be configured to encode the q-bit original value x as a q-bit encoded value x′ by computing an exclusive-OR operation on the q-bit original value x and the calculated value E.

[0022] In some embodiments, 2 of the q-bit original value q The space of values ​​may be divided into a plurality of groups, each group including a plurality of consecutive different q-bit original values, and the processing circuit may be configured to identify a first encoder value D1 and a second encoder value D2 by: identifying a group among the plurality of groups, the one group having two q-bit original values ​​missing from the values ​​of the N original q-bit words; and identifying one of the two q-bit original values ​​in the identified group as the first encoder value D1, and identifying the other q-bit original value of the two q-bit original values ​​in the identified group as the second encoder value D2.

[0023] q bits of the original value 2 qThe space of values ​​can be divided into G groups, and N can be less than or equal to 2. q -G-1.

[0024] In some embodiments, each group may include up to three consecutive different q-bit original values, and the processing circuit may be configured to select a middle q-bit original value among the three consecutive different q-bit original values ​​in the identified group as the calculated value E representing the first encoder value D1 and the second encoder value D2.

[0025] The processing circuit may be configured to encode the q-bit original value x as a q-bit encoded value x′ based on a comparison of the q-bit original value x and the calculated value E.

[0026] In some embodiments, each packet may include 2 consecutive r The first encoder value D1 and the second encoder value D2 may share qr most significant bits, and the processing circuit may be configured to generate a key representing the first encoder value D1 and the second encoder value D2 by: encoding the r least significant bits of the first encoder value D1 and the r least significant bits of the second encoder value D2 using 2r-1 bits to generate a least significant bit code, the least significant bit code having at least one transition; and concatenating the qr most significant bits with the least significant bit code.

[0027] The processing circuit may be configured to concatenate the qr most significant bits with the least significant bit code by: dividing the qr most significant bits into a first part and a second part; and concatenating the least significant bit code between the first part and the second part of the qr most significant bits.

[0028] The processing circuit may be configured to transmit a data packet comprising: N encoded q-bit payload words; and a header comprising a key.

[0029] According to one embodiment of the present disclosure, a decoder includes a processing circuit configured to: receive a key and N encoded q-bit payload words; decode a first encoder value D1 and a second encoder value D2 from the key; and decode the N encoded q-bit payload words based on a one-to-one mapping from q-bit encoded values ​​to q-bit original values ​​according to the first encoder value D1 and the second encoder value D2 to generate N decoded original q-bit words.

[0030] In some embodiments, the processing circuit may be configured to decode the q-bit encoded value x' into the q-bit original value x based on a comparison of the q-bit encoded value x' with the first encoder value D1 and the second encoder value D2.

[0031] The key may include a q-1 bit value E, the processing circuit may be configured to decode the first encoder value D1 by setting the q-1 most significant bits of the first encoder value D1 to the q-1 bit value E and setting the least significant bit of the first encoder value D1 to 0, and the processing circuit may be configured to decode the second encoder value D2 by setting the q-1 most significant bits of the second encoder value D2 to the q-1 bit value E and setting the least significant bit of the second encoder value D2 to 1.

[0032] The key may include a q-1 bit value E, and the processing circuit may be configured to decode the q-bit encoded value x' into the q-bit original value x based on a result of an XOR operation performed on the q-bit encoded value x' and the q-1 bit value E.

[0033] In some embodiments, 2 of the q-bit original value q The space of values ​​may be divided into a plurality of groups, each group comprising a plurality of consecutive different q-bit original values, each group comprising a maximum of three consecutive different q-bit original values, the key may comprise a q-1 bit value E, and the processing circuit may be configured to decode the first encoder value D1 and the second encoder value D2 based on a result of a modulo operation on the q-1 bit value E.

[0034] The processing circuit may be configured to decode the q-bit encoded value x' into the q-bit original value x based on a comparison of the q-bit encoded value x' and the q-1-bit value E.

[0035] In some embodiments, 2 of the q-bit original value q The space of values ​​can be divided into multiple groups, each group consists of 2 consecutive r different q-bit original values, the first encoder value D1 and the second encoder value D2 can share qr most significant bits, and the processing circuit can be configured to decode the first encoder value D1 and the second encoder value D2 from the key by the following operations: reading a 2r-1-bit least significant bit code from the key; decoding the least significant bit code into a first least significant bit and a second least significant bit; reading qr most significant bits from the key; concatenating the qr most significant bits with the first least significant bit to decode the first encoder value D1; and concatenating the qr most significant bits with the second least significant bit to decode the second encoder value D2.

[0036] The decoder may be configured to receive a data packet comprising: N encoded q-bit payload words; and a header comprising a key.

[0037] Figure 1 is a schematic block diagram of a serial link between a transmitter 1 and a receiver 2, the transmitter 1 including an encoder 100 according to an embodiment of the present disclosure and the receiver 2 including a decoder 200 according to an embodiment of the present disclosure. Figure 1 In the arrangement shown in FIG. 1 , original data 10 is transmitted from a transmitter 1 to a receiver 2, wherein the original data 10 is reconstructed by a decoder 200 as decoded data 18. The decoded data 18 may then be consumed by a data consumer 20. In more detail, the encoder 100 encodes the original data 10 into encoded data 30, and the encoded data 30 is transmitted to the decoder 200 via a data link 50. The decoder 200 then decodes the encoded data 30 to reconstruct the decoded data 18.

[0038] According to various embodiments of the present disclosure, the encoder 100 and the decoder 200 may be referred to as an encoder circuit or an encoder processing circuit and a decoder circuit or a decoder processing circuit, respectively, and may be implemented using various processing circuits, such as a central processing unit (CPU), an application processor (AP) or an application processing unit (APU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) such as a display driver integrated circuit (DDIC), and / or a graphics processing unit (GPU) of one or more computing systems. For example, the encoder 100 and the decoder 200 may be components of the same computer system (e.g., integrated in a single housing, such as in the case of a smart phone, a tablet computer, or a laptop computer), may be discrete components of a computer system (e.g., a desktop computer communicating with an external monitor), or may be a discrete computer system (e.g., two independent computer systems communicating via a data link 50), or a variation thereof (e.g., implemented in a dedicated processing circuit such as a microcontroller configured to communicate via a data link 50, wherein the microcontroller is a peripheral component within the computer system). As will be appreciated by those skilled in the art, the encoder circuit may be implemented using different types of processing circuits compared to the decoder circuit. Furthermore, as will be appreciated by those skilled in the art, the various processing circuits may be components of the same integrated circuit (e.g., as components of the same system on a chip (SoC)), or may be components of different integrated circuits that may be connected via pins and leads on a printed circuit board.

[0039] As a specific example, in the case of a data link 50 for controlling a display device, the transmitter 1 may include a graphics controller, such as a graphics processing unit (GPU) or an application processing unit (APU) of a computer system (e.g., a laptop, a smart phone, or a tablet computer, etc.), that generates image data as raw data 10. The image data or raw data 10 is then transmitted to a display panel (e.g., a liquid crystal display panel or an organic light emitting diode display panel) via the data link 50, and the display panel includes a decoder 200 for decoding the encoded data 30 into decoded data 18. The decoded data 18 may then be provided to a data consumer 20, such as a processing circuit configured to convert the received decoded data 18 into a signal that controls the display panel to display an image (e.g., a graphical user interface, video, and other display elements) as represented in the decoded data 18.

[0040] In digital communications, a transmitter 1 and a receiver 2 may be synchronized using a clock recovery or clock data recovery (CDR) process. A receiver using a CDR process typically operates by detecting the times of transitions between symbols on the physical layer of a data link (e.g., the voltage levels of a signal on a link) and phase aligning the receiver's clock based on the detected transitions.

[0041] Figure 2 is a depiction of binary data transmitted over data link 50 using a unipolar line code, wherein a logic 1 value is encoded as a logic level high (H) signal and a logic 0 value is encoded as a logic level low (L) signal. The logic level high signal and the logic level low signal may be physically encoded via data link 50 as a high voltage (e.g., 5 volts or 3.3 volts) and a low voltage (e.g., 0 volts), respectively. Figure 2 In the example shown in , the data bit sequence 101001110010 is transmitted via data link 50. The transitions between logic level low (L) voltage and logic level high (H) voltage are shown by arrows 51. A segment of repeated bits during which the signal does not change is called a run. Figure 2 Specifically, seven different runs and their corresponding run lengths, labeled 52, 53, 54, 55, 56, 57, and 58, are highlighted. Based on the data bit sequence 101001110010, runs 52, 53, 54, 55, 56, 57, and 58 have corresponding run lengths of 1, 1, 1, 2, 3, 2, and 1.

[0042] If the received signal contains an excessively long run length (e.g., a long sequence of data symbols having the same voltage level), the CDR process may fail due to an insufficient number of transitions in the received signal, which may cause problems in clock recovery. For example, in unipolar non-return-to-zero (NRZ) encoding, a logic level high value (e.g., a high voltage) may be used to encode a 1 and a logic level low value (e.g., a low voltage) may be used to encode a 0. Direct encoding of the value of any particular input data may result in arbitrarily long run lengths. For example, a long word sequence of all zeros (0) or a long word sequence of all ones (1) will result in a signal that is continuous at a logic level low value or a logic level high value, respectively, with no transitions between bits for CDR to use. Although some of the problems caused by long run lengths are described above in the context of unipolar NRZ encoding, similar problems may occur in other types of modulation that may have more than two signal amplitude levels (e.g., pulse amplitude modulation or PAM with more than two levels, such as PAM4 using four amplitude levels).

[0043] Thus, aspects of embodiments of the present disclosure relate to systems and methods for encoding input data to generate encoded data bits, wherein the encoded data bits are ensured to have a limited run length (e.g., a run length that is no longer than a certain limited number of bits). Limiting the run length of data encoded in this manner improves the ability of the decoder to perform CDR, thereby improving the quality of the communication link between the transmitter and the receiver. Aspects of embodiments of the present disclosure also relate to systems and methods for decoding the encoded data bits to recover the original input data.

[0044] More formally, aspects of embodiments of the present disclosure relate to encoding native or raw data by ensuring that transitions occur every K bits (eg, limiting run lengths) using a row encoding algorithm so that transitions occur regularly.

[0045] Some aspects of embodiments of the present disclosure relate to run-length limited codes, wherein input data is encoded into one or more data packets, each data packet comprising a plurality of words. In the following description, each data packet comprises N words (or at most N words), and wherein each word has q bits (in other words, each data packet may comprise at most N q-bit words). Figure 3 is a schematic depiction of a data packet. Each data packet 31 can therefore be viewed as comprising qN-bit payload words 32, which can be numbered or indexed from 0 to qN-1, such as in the following form: b[0:qN-1]. Each q-bit word x can take the value from 0 to 2 q -1, and can also be represented as an array of q bits, e.g., b[0:q-1]. The payload word 32 can thus be viewed as N words concatenated together into an array of qN bits:

[0046] x 1 , x2 , ..., x N

[0047] x 1 (b[0:q-1]), x 2 (b[q:2q-1]),...,x N (b[q(N-1):qN-1])

[0048] For illustration purposes, in the following examples, q is set to 6 so that each word is 6 bits long, with a value ranging from 0 to 63. However, the embodiments of the present disclosure are not limited thereto, and q may be set to other values ​​such as 8, 10, or 16, etc., according to design parameters and requirements of the encoding and decoding systems and based on the application.

[0049] like Figure 3 As shown in , the data packet 31 also includes a header 34 (having a length of h bits), which represents additional overhead information transmitted as part of the encoded data packet 31 and used by the decoder 200 to decode the encoded data packet 31. The header 34 may include a key that contains information used to decode the encoded data packet 31.

[0050] One measure of the efficiency of the encoding scheme is based on the number of payload bits (e.g., N words of q bits per word, totaling qN payload bits) divided by the total number of bits in the packet 31 (e.g., the sum of the number of payload bits qN and the number of header bits h). For example:

[0051]

[0052] For simplicity, the discussion herein assumes that all h bits of the header 34 are used by the key (e.g., the header 34 also does not include additional information such as parity bits for error detection or error correction). However, embodiments of the present disclosure are not limited thereto, and may also include situations in which the header 34 includes additional information.

[0053] Furthermore, while some embodiments of the present disclosure are described herein in which a key is transmitted in a header 34 of a data packet 31 containing N words (qN payload bits) of data associated with a particular key, embodiments of the present disclosure are not limited thereto, and in some embodiments, the key is transmitted in a packet separate from the data packet 31 containing the payload bits.

[0054] Some aspects of embodiments of the present disclosure relate to ensuring that there is at least one transition in each word of the encoded data by ensuring that none of the words in the encoded data 30 is all zero (e.g., q consecutive zeros) or all ones (e.g., q consecutive ones), such as 6'b000000 and 6'b111111 in the case where q=6. In other words, some aspects of embodiments of the present disclosure relate to removing all zero words and all ones words from the encoded data 30 or ensuring that the encoded data 30 does not include (e.g., does not contain) words that are all zeros and also does not include any words that are all ones. By removing all zero words and all ones words from the encoded data, the run length is limited to a worst case of 2(q-1) bits.

[0055] Figure 4 is a schematic depiction of the maximum run length in the example case of six-bit words (q=6) when encoding data in a data packet according to an embodiment of the present disclosure. Figure 4 As shown in , when the 6-bit word 6'b100000 (identified as word x i ) Next is the 6-bit word 6'b000001 (identified as word x i+1 ), then there is a run of ten zeros (2×(6-1)). Similarly, when the 6-bit word 6'b011111 is followed by the 6-bit word 6'b111110, then there is a run of ten ones. Because all-zero words and all-one words have been removed, any other pairing of consecutive words will result in a run length shorter than the finite maximum run length of 2(q-1) bits.

[0056] Thus, aspects of embodiments of the present disclosure are described in more detail below with respect to systems and methods for encoding original data 10 to generate encoded data 30, wherein the encoded data 30 does not contain words that are all zeros or words that are all ones (e.g., no words have q zeros and no words have q ones). In addition, aspects of embodiments of the present disclosure relate to systems and methods for decoding the encoded data 30 to generate decoded data 18 that matches the original data 10, which may include words that are all ones and / or words that are all zeros.

[0057] Figure 5 is a flowchart depicting a method 500 for encoding raw data to generate a data packet according to one embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 5 The operations are implemented in an encoder 100 configured to perform the operations described herein, such as implemented in instructions stored in a memory and executed by a processor or processing circuit to implement the encoder 100, where the processor and memory can be components of a microcontroller, an application processor, a central processing unit, a digital signal processor, a field programmable gate array, or an application specific integrated circuit, etc.

[0058] Reference Figure 5, raw data 10 is provided from a data source (e.g., image data generated by a graphics processing unit) to an encoder 100. In operation 510, the encoder 100 divides the raw data 10 into a plurality of q-bit words. The number of bits q in each word x can be set according to various design considerations, as discussed in more detail below. For convenience, the variable N will be used to represent the number of words, such that operation 510 divides the raw data 10 into N words, for a total of qN bits, with each word being q bits long. In cases where the raw data 10 includes fewer bits than qN, additional padding bits can be added to the raw data 10 to reach the total number of bits qN, or fewer words than N can be encoded in a particular data packet. If there are more bits in the raw data 10 than qN, the first qN bits of the raw data 10 can be encoded in a first data packet, and subsequent bits of the raw data 10 can be encoded in subsequent data packets (e.g., the next qN bits of the raw data 10 can be encoded in a second data packet, and so on).

[0059] In operation 530, the encoder 100 identifies two q-bit words that have values missing from the values of the N q-bit words divided from the raw data 10 in operation 510. The q-bit words can take on any one of 2 q different values in the range from 0 to 2 q - 1. For example, a 6-bit word can take on any one of 64 different values in the range from 0 to 63. Limiting the number of words N in a data packet ensures that there are at least two q-bit words that do not appear among the N q-bit words. For example, setting N to be less than or equal to 2 q - 2 provides this assurance (e.g., in the case of 6-bit words, setting N = 2 6 - 2 = 62 words ensures that at least two of the 64 possible values from 6-bit words will not appear among the 62 words). The two selected q-bit words will be referred to herein as encoder values D1 and D2, where D1 < D2. Aspects of embodiments of the present disclosure related to the selection of the encoder values D1 and D2 will be described in more detail below.

[0060] In operation 550, the encoder 100 encodes the raw data 10 based on the first encoder value D1 and the second encoder value D2 to generate encoded payload data having N encoded payload words, where the encoded payload data does not include any words that are all zeros or all ones (regardless of whether any of the original N q-bit words include any words that are all zeros or all ones). Continuing the above example of 6-bit words, there is no b000000 among the N encoded payload words, and there is no b111111 among the N encoded payload words (in the case where the N original words may or may not include b000000 and / or b111111).

[0061] In some embodiments, encoder 100 encodes the original data based on a one-to-one mapping function between the original value and the encoded value.

[0062] Figure 6 Depicted is encoding raw data based on two encoder values ​​D1 and D2 to generate encoded data according to one embodiment of the present disclosure. In some embodiments, the encoder 100 encodes N raw words by mapping the values ​​of the words to the encoded words according to the following function enc(x) for encoding the raw word x into the encoded word x':

[0063]

[0064] In other words, the original word x is incremented by one when the value of the original word x is less than the first encoder value D1, remains the same (identity) when its value is between the first encoder value D1 and the second encoder value D2, and is decremented by one when its value is greater than the second encoder value D2. (The cases where x=D1 or x=D2 need not be considered because, by construction, encoder values ​​D1 and D2 do not appear in the N original words to be encoded.) This mapping ensures that all-zero values ​​do not appear in the encoded data because all values ​​less than the first encoder value D1 are incremented by one, thereby representing any all-zero values ​​that appear in the N original words as a value of 1 (e.g., b000001 in the case of q=6). Likewise, this mapping also ensures that all-one values ​​do not appear in the encoded data because any all-one values ​​that appear in the N original words are represented as the next highest possible value (e.g., b111110 in the case of q=6).

[0065] exist Figure 6 In the example shown in , q=4 (e.g., each word is 4 bits long), and the values ​​4 (4b0100), 5 (4b0101), 10 (4b1010), and 13 (4b1101) are missing from the original input data, which may be the bit sequence: 0001 0011 0110 1001 1000 0111 1111 1111 1111 0000 1110 1100 0010 1011

[0067] Figure 6A table of all possible 4-bit values ​​of a word in decimal representation 601 and binary representation 602 is shown, and a white background is used to indicate the values ​​that appear in the original data, while the values ​​missing in the original data are shown with a shaded background. For illustration purposes, among the four candidate values, the value 4b0101 is selected as the first encoder value D1 and the value 4b1010 is selected as the second encoder value D2. The encoding function or encoding mapping (enc) 610 maps the values ​​in the binary representation 602 to the corresponding encoded values ​​630, as shown by the arrows. As a result, the all-zero value (4b0000) and the all-one value (4b1111) are not used in the encoded version of the data. In particular, the encoded version of the above example original data will be: 0010 0100 0110 1001 1000 0111 1110 1110 1110 0001 1101 1011 0011 1010

[0069] As can be seen above, the encoded version of the original data does not include any all-zero values ​​nor any all-one values. In addition, the maximum run length has been reduced from 15 in the original data to a worst-case maximum run length of 6 (e.g., 2(q-1)) in the encoded data.

[0070] In some embodiments, encoder 100 encodes the N original words by mapping the values ​​of the words to encoded words according to the following function enc(x) for encoding the original word x into the encoded word x':

[0071]

[0072] In other words, if the original word x is an all-zero value (e.g., q consecutive 0s), then the original word x is mapped to a first encoder value D1, and if the original word x is an all-one value (e.g., q consecutive 1s), then the original word x is mapped to a second encoder value D2. (Alternatively, in some embodiments, if the original word x is an all-one value, then the original word x is mapped to a first encoder value D1, and if the original word x is an all-zero value, then the original word x is mapped to a second encoder value D2) Otherwise, the encoded word x' has the same value as it had in the original word x. Therefore, when the value 4b0101 is selected as the first encoder value D1 and the value 4b1010 is selected as the second encoder value D2, the above original bit sequence can be converted to: 001 0011 0110 1001 1000 0111 1111 1111 1111 0000 1110 1100 0010 1011

[0074] Encoded as:

[0075] 0001 0011 0110 1001 1000 0111 1010 1010 1010 0101 1110 1100 00101011.

[0076] In operation 570, the encoder 100 generates a key representing encoder values ​​(e.g., the first encoder value D1 and the second encoder value D2), which is transmitted as the header 34, and in operation 590, the encoder 100 generates a data packet 31 including the header 34 and the N encoded payload words 32. The resulting data packet 31 can then be transmitted to the decoder 200 via the data link 50 as the encoded data 30.

[0077] Figure 7 is a flow chart depicting a method 700 for decoding an encoded data packet according to one embodiment of the present disclosure. The data packet 31 may include a header 34 and an encoded payload word 32. Figure 7 As shown in FIG. 7 , in operation 710, the decoder 200 reads a header from a received data packet (e.g., a data packet encoded by the encoder 100) to decode encoder values ​​(e.g., a first encoder value D1 and a second encoder value D2) from the header. The encoder values ​​D1 and D2 are used to determine a mapping from the encoded value of the encoded payload word to the decoded value of the original data.

[0078] In some embodiments, decoder 200 decodes the N encoded words by mapping the values ​​of the encoded words to decoded words according to the following function dec(x') for decoding the encoded word x' into the original word x:

[0079]

[0080] In other words, the encoded word x' is decremented when its value is less than or equal to the first encoder value D1, remains the same (identity) when its value is between the first encoder value D1 and the second encoder value D2, and is incremented when its value is greater than or equal to the second encoder value D2. This mapping restores any all-zero values ​​and any all-one values ​​that appeared in the original data.

[0081] Figure 8 1 shows a 4-bit value of an encoded word mapped to a corresponding decoded word or original word based on an encoder value according to one embodiment of the present disclosure. Figure 8 As shown in , a decoding function or decoding map (dec) calculates a mapping from an encoded value 830 to a reconstructed or decoded original value shown in binary representation 818 and also shown in decimal representation 819.

[0082] Similarly, where the encoder function (enc) performs a mapping in which instances of all zero words (e.g., 4b0000) are replaced with a first encoder value D1 and instances of all ones words (e.g., 4b1111) are replaced with a second encoder value D2, and all other values ​​remain the same, the decode function or decode mapping (dec) may be represented as follows:

[0083]

[0084] Thus, some aspects of embodiments of the present disclosure relate to systems and methods for encoding raw data to limit run lengths in the encoded data based on identifying unused values ​​within the raw data, selecting the unused values ​​as encoder values, and encoding the raw data based on the encoder values. Aspects of embodiments of the present disclosure also relate to decoding the encoded data based on the encoder values. Additional details regarding the selection of encoder values, the selection of the number N of words x in a data packet, and the number of bits q per word will be described in more detail below.

[0085] In the previous discussion, aspects of the present disclosure were described in the context of embodiments in which the number of words N in a data packet is constrained to be less than or equal to 2. q -2 to ensure that there are at least two values ​​that do not appear in the N words, so that the two missing or unused values ​​can be used as encoder values ​​D1 and D2 of the encoding system. Because the first encoder value D1 and the second encoder value D2 can be 2 q For any two values ​​in the space of possible values, the first encoder value D1 and the second encoder value D2 will be transmitted in their entirety as part of the header (as generated in operation 570) without compression, thereby resulting in an overhead of 2q bits (q bits for each of the first encoder value D1 and the second encoder value D2). As described above, the efficiency of the encoding scheme can be given as:

[0086]

[0087] In this case, h = 2q, so:

[0088]

[0089] More specifically, when q=6 and N=2 q In the case of -2, this is:

[0090]

[0091] Some aspects of embodiments of the present disclosure relate to selection of the number of words N in a data packet and the number of bits q in a word that can further improve efficiency, such as by reducing the number of header bits (or overhead bits) used to represent the encoder value or multiple encoder values ​​for decoding the encoded value of each word in the N-word data packet 31.

[0092] In more detail, some aspects of embodiments of the present disclosure relate to reducing the number of overhead bits used to transmit encoder values ​​(e.g., first encoder value D1 and second encoder value D2) by compressing to less than 2q bits. For example, if first encoder value D1 and second encoder value D2 are selected so that they have a common prefix (or most significant bit), then fewer bits can be used to transmit the two values ​​in the header. More generally, some aspects relate to combining 2 of the q-bit words based on the common prefix (or common most significant bit). q possible values ​​and select the number of words N in the data packet so that two unused values ​​(e.g., values ​​missing from the original data to be encoded) are in the same packet. This enables the two unused values ​​that fall into the same packet to be selected as encoder values ​​D1 and D2, and the two encoder values ​​D1 and D2 to be encoded based on an identifier associated with the packet (or packet identifier), wherein the encoding of the encoder values ​​D1 and D2 uses less than 2q overhead bits. When N≤2 q -G-1, a packet of N words will have two unused values ​​falling into the same packet, where 2 of the q-bit words q The space of values ​​is divided into G groups.

[0093] Some example embodiments presented in more detail below relate to encoding schemes where: N=30, q=6, with 5 bits of overhead (97.3% efficiency); N=40, q=6, with 6 bits of overhead (97.6% efficiency); N=47, q=6, with 7 bits of overhead (97.6% efficiency); and N=55, q=6, with 8 bits of overhead (97.6% efficiency), although embodiments of the present disclosure are not limited thereto. For example, embodiments of the present disclosure may be implemented with words of lengths other than 6 bits, such as q=8.

[0094] In one embodiment of the present disclosure, the space of possible values ​​of the q-bit original word x is divided into groups of two consecutive values ​​(value pairs). For example, group 0 may include values ​​0 and 1, group 1 may include values ​​2 and 3, and group 2 may include values ​​4 and 5 (typically, group k includes values ​​2k and 2k+1). Because each group contains consecutive values ​​with a common prefix, for example, q-1 most significant bits may be shared, and the two values ​​of each group differ only in their least significant bits. Therefore, when the first encoder value D1 and the second encoder value D2 fall into the same group, both the first encoder value D1 and the second encoder value D2 can be encoded using q-1 bits. This is where N≤2 q Therefore, in these embodiments of the present disclosure, in operation 530, the encoder 100 identifies two encoder values ​​D1 and D2 that fall within the same group.

[0095] Table 1 below provides an example in the case where q=6:

[0096] Table 1

[0097]

[0098] In Table 1 above, all of the 5-bit overhead and the keys representing the groups include at least one transition, except for group 0, which can be represented as 00-000 or 11-111 (including the character "-" for readability). In order to provide some transitions when transmitting the key representing group 0, the encoder according to some embodiments of the present disclosure determines whether to use 00-000 or 11-111 to represent group 0 based on the value of the bit transmitted immediately before the key, so as to generate the transition. For example, if the bit transmitted immediately before the key is 1, the encoder uses 00-000 as the key to indicate group 0, and if the bit transmitted before the key is 0, the encoder uses 11-111 to indicate group 0. However, because both 00-000 and 11-111 are used to represent group 0, there is no corresponding remaining key to represent group 31. However, there is no need to use D1=62 and D2=63. In particular, when N<=30, there is always another paired encoder value D1 and D2 that can be selected alternatively (which can be proven by contradiction). Therefore, no key is required to represent packet 31, which is indicated in Table 1 as "invalid".

[0099] In the case where q=6 and N=30, 5 bits can be used to identify each group, and therefore, in the case where the first encoder value D1 and the second encoder value D2 fall within the same group, the efficiency can be calculated as follows:

[0100]

[0101] In these embodiments of the present disclosure, the encoder 100 may implement an encoding function or a mapping from original values ​​to encoded values ​​in operation 550 using the above techniques (eg, based on equation (2) or equation (3)) or an equivalent thereof.

[0102] Furthermore, in some embodiments of the present disclosure, where the first encoder value D1 and the second encoder value D2 differ only in their least significant bits (e.g., D1=6b010010 and D2=6b010011), the encoder 100 encodes the raw data in operation 550 as follows: a value E is calculated based on the first encoder value D1, where E is D1 divided by 2 (or equivalently, right shifted by 1):

[0103]

[0104] For the case where q=6:

[0105]

[0106] The calculated value E is then used to encode the original word x into the corresponding encoded word x' based on E:

[0107] x′=enc(x)={XOR(XOR(x[q-1:1],E),{(q-1){x[0]}}),x[0]} (6)

[0108] where {(q-1){x[0]}} represents the bit value at x[0] repeated q-1 times. For the case where q=6:

[0109] x′=enc(x)={XOR(XOR(x[5:1],E),{5{x[0]}}),x[0]}

[0110] where {5{x[0]}} represents the bit value at x[0] repeated 5 times.

[0111] A (q-1)-bit value E is generated in the header 34 in operation 570, wherein the (q-1)-bit value E represents a packet containing both the selected encoder values ​​D1 and D2. The encoder 100 then generates a data packet 31 including the header 34 (containing the (q-1)-bit value E) and the encoded payload word 32 in operation 590. The resulting data packet 31 may then be transmitted to the receiver 2, which uses a decoder 200 configured to decode the encoded payload word 32 in the data packet 31.

[0112] In particular, in these embodiments, in operation 710, decoder 200 determines a packet based on the (q-1)-bit value E in header 34 of data packet 31. Because the packet contains only two values, these values ​​are adopted by decoder 200 as encoder values ​​D1 and D2, and are thereby used to determine a mapping used by decoder 200 (e.g., according to formula (4) or (5) as described above) to decode the encoded payload word in operation 750.

[0113] In an embodiment using XOR encoding as shown in equation (6) above, a similar XOR operation is performed at decoder 200 in operation 750 based on the packet identifier E transmitted in header 34:

[0114] x=dec(x′)={XOR(XOR(x′[q-1:1],E),{(q-1){x′[0]}}),x′[0]} (7)

[0115] In the specific case where q=6:

[0116] x={XOR(XOR(x′[5:1],E),{5{x′[0]}}),x′[0]}

[0117] According to another embodiment of the present disclosure, the value of the word is arranged into groups of these consecutive values. For example: group 0 may identify values ​​0, 1, and 2; group 1 may identify values ​​3, 4, and 5, etc. Therefore, the encoder 100 calculates the q-bit value E (e.g., when generating the header 34 in operation 570) used to identify the group and which two values ​​within the group correspond to the encoder values ​​D1 and D2 according to the following:

[0118]

[0119] Intuitively, this can be thought of as E representing the middle value of the grouping. In particular, by construction, D1≤E≤D2. If D2-D1=2 (in the case of the middle row of each grouping in Table 2 below), then E is the middle value (E=D1+1=D2-1). In the case of the row above this, D1=E and D2=E+1 (this is when the first encoder value D1 is a multiple of 3). In the following row, we get D1=E-1 and D2=E.

[0120] In these embodiments, the encoder 100 may be configured to perform a mapping or encoding from the original word x to the encoded word x' in operation 550 using, for example, formula (2) or formula (3) above. In these embodiments, the encoding scheme of formula (2) may be simplified based on the value E as follows:

[0121]

[0122] Table 2 below provides an example of mapping values ​​to packets and their corresponding overheads for the case where q=6:

[0123] Table 2

[0124]

[0125]

[0126] In some embodiments of the present disclosure using this encoding setting, the decoder 200 is configured to decode the encoder value from the header 34 containing the q-bit value E in operation 710 as follows:

[0127]

[0128] The decoder 200 can then decode the encoded value into the original value as described above with respect to formulas (4) and (5). In addition, the decoding according to formula (4) can be simplified in this case to:

[0129]

[0130] In the case of 6-bit words (q=6), this setting allows each packet to use up to 2 6 = -22-1 = 41 words. Therefore, in the case where q = 6 and N = 41, 6 bits can be used to identify each group, and therefore, in the case where the first encoder value D1 and the second encoder value D2 fall within the same group of three values, the efficiency can be calculated as:

[0131]

[0132] According to some embodiments of the present disclosure, the space of possible values ​​of a q-bit word is divided into 2 r In some embodiments, the space of possible values ​​for the q-bit word is divided into groups of four values ​​so that the values ​​in each group share a common prefix up to the r least significant bits (e.g., the values ​​may share the qr most significant bits so that the qr most significant bits are the same in each value). For example, when r is set to 2, then the space of possible values ​​for the q-bit word is divided into groups of four values ​​so that the values ​​in each group share a common prefix up to the two least significant bits (e.g., the first q-2 bits are the same). In some embodiments, 2r-1 additional bits are used to encode two selected values ​​from the group.

[0133] Table 3 below provides an example in the case where q=6 and r=2:

[0134] Table 3

[0135]

[0136]

[0137] Thus, a packet may be identified using q-2 bits (e.g., q-2 most significant bits (MSBs)) unique to each packet. The two values ​​corresponding to the first encoder value D1 and the second encoder value D2 within the packet differ by the remaining 2 bits (e.g., 2 least significant bits (LSBs)), and in some embodiments three additional bits are used to identify the value pair, such as by using the following Table 4:

[0138] Table 4

[0139]

[0140] In the particular encoding scheme shown above, the codes (e.g., 3-bit codes) used to encode the least significant bits of the encoder values ​​D1 and D2 within the group are designed so that each code includes at least one transition (e.g., the codes are not a string of three consecutive zeros or a string of three consecutive ones). This is possible because the number of possible pairings of a first encoder value D1 and a second encoder value D2 is less than the number of bits used to encode the pairings (e.g., using 3 bits to encode 6 different possibilities, where 3 bits can encode 2 3 possible values). On the other hand, the q-2 bits used to identify the packet may contain, for example, q-2 consecutive 0s or q-2 consecutive 1s. In this case, simply concatenating the q-2 bits used to identify the packet with the 3 bits used to identify the encoder values ​​D1 and D2 within the packet may result in a run of q consecutive 0s or q consecutive 1s. For example, in the case where q=6, if the packet identifier is 0000 and the LSB code is 001 (according to Table 4, the first encoder value D1 and the second encoder value D2 are identified as having values ​​of LSB 00 and 01), then concatenating 0000 with 001 results in a header of 0000001, which includes a run of 6 consecutive 0s. A similar problem may occur when the packet identifier is 1111 and the LSB code is 110, resulting in a run of 6 consecutive 1s. Therefore, in some embodiments, the packet identifier is split into two parts and the LSB code is placed between the two parts. Continuing with the example where q=6, the higher order bits common to the first encoder value D1 and the second encoder value D2 may be identified as D1[5:2] (e.g., the bits in positions 5 through 2 of the first encoder value D1, or equivalently, the bits in positions 5 through 2 of the second encoder value D2 as in D2[5:2]. These four higher order bits may be divided into a first portion D1[5:4] and a second portion D1[3:2], and the LSB code may be placed between the two portions, as in the following:

[0141] {D1[5:4], LSB code, D1[3:2]}

[0142] As described above, the LSB codes are designed so that each includes at least one transition. Therefore, by placing the LSB code between the two parts, the maximum run length of the header 34 is ((q-2)) / 2+2. For example, in the case of a packet identifier of 0000 and an LSB code of 001 above, the header is encoded as 0000100, which results in a run of four consecutive 0s.

[0143] The decoder 200 decodes the first encoder value D1 and the second encoder value D2 in operation 710 by reading the most significant bits (e.g., D1[5:4] concatenated with D1[3:2]) from the header 34 and reading the least significant bit code (LSB code) from the header 34 and then decoding the LSB code (e.g., based on the above table) to determine the least significant bits of the first encoder value D1 and the least significant bits of the second encoder value D2. The most significant bits read from the header 34 are then concatenated with the decoded least significant bits of the first encoder value D1 to decode the entire first encoder value D1, and the most significant bits read from the header 34 are then concatenated with the decoded least significant bits of the second encoder value D2 to decode the entire second encoder value D2.

[0144] Using this encoding scheme, the overhead is q-2 bits used to identify the packet plus 3 bits used to identify the two selected components of the packet, for a total of h=q+1 bits. For example, in this case of q=6, the overhead is 7 bits. In the case of q=6, when N<=47 (e.g., at most 2 per packet), the overhead is 7 bits. 6 -16-1=47 words) can ensure that valid encoder values ​​D1 and D2 are found in the group. Therefore, in the case where q=6 and N=47, 7 bits can be used to identify each group, and therefore, in the case where the first encoder value D1 and the second encoder value D2 fall into the same group of four values, the efficiency can be calculated as follows:

[0145]

[0146] In these embodiments, the encoder and decoder can be implemented in a manner similar to that described above. For example, in some embodiments of the present disclosure using this encoding arrangement, the decoder 200 is configured to decode the encoder value from the header 34 containing the q-bit encoder values ​​D1 and D2 according to formula (2) or (3). Similarly, the decoder 200 can then decode the encoded value into the original value as described above with respect to formula (4) or (5).

[0147] As another example, in some embodiments of the present disclosure where r=3, the space of possible values ​​is divided into groups of eight consecutive values. For example, group 0 may include values ​​0 to 7, group 1 may include values ​​8 to 15, and so on. In this setting, the values ​​within each group share a q-3 bit common prefix, and the difference may be only in their three least significant bits. Table 5 below provides an example in the case where q=6 and r=3 and value 9 is selected as the first encoder value D1 and value 11 is selected as the second encoder value D2 as an example. These rows corresponding to the first encoder value D1 and the second encoder value D2 are shown in bold in Table 5 below.

[0148] Table 5

[0149]

[0150] In a manner similar to that described above, a 5-bit long LSB code may be employed to uniquely identify two values ​​within a group of eight values ​​(e.g., there are 28 ways to select two values ​​from a set of eight possible values, and thus 5 bits (2 5 =32) is sufficient to specify any of those 28 possible pairings of two values, leaving room in the LSB code to exclude runs of five bits of all zeros and all ones). Thus, in some embodiments, the encoder values ​​D1 and D2 are encoded using the following code:

[0151] {LSB code, MSB}

[0152] For example, in the case where q=6, this can be expressed as:

[0153] {LSB code, D1[5:3]}

[0154] In some embodiments, in a manner similar to that described above, the MSB is split into two parts, and the LSB code is placed between the two parts of the MSB. For example, in the case where q=8, the MSB can be split into a first part (D1[7:5]) having the first three bits and a second part (D1[4:3]) having the next two bits. Thus, this can be expressed as:

[0155] {D1[7:5], LSB code, D1[4:3]}

[0156] At the decoder 200, in operation 710, the first encoder value D1 and the second encoder value D2 may be decoded from the header in a manner similar to that described above for the case where r=2 (e.g., by reading the MSB, decoding the LSB from the LSB code using a table, and concatenating the MSB with the two decoded LSBs).

[0157] Therefore, in the case of q=6, it can be ensured that when N<=2 6 When -8-1=55, the first encoder value D1 and the second encoder value D2 exist in the same group. Using a header length of q-3+5=6-3+5=8 bits, the efficiency of this encoding setting can be calculated as:

[0158]

[0159] In some embodiments, encoder 100 may implement an encoding function or mapping from an original value to an encoded value using the above techniques (e.g., based on formula (2) or formula (3)) or an equivalent thereof in operation 550. Similarly, decoder 200 may implement a decoding function or mapping from an encoded value to an original value using the above techniques (e.g., based on formula (4) or formula (5)) or an equivalent thereof in operation 750.

[0160] In some embodiments, the encoder 100 implements a two-level mapping from the original value to the encoded value using an XOR (^) operation in operation 550. In particular, in the first stage of encoding, the word x to be encoded is XORed with the first encoder value D1 to calculate the intermediate value y. In the second stage, one or more bits of y are XORed with a bit of y. In particular, x' is calculated by selecting any single bit position z of the value of y calculated for the second encoder value D2 having a value of 1, and XORing the value at the bit position z with the bit of y at a position other than z and copying the bit at the bit position z to the same position z of x'. Table 5 shows a specific example in which the first encoder value D1 and the second encoder value D2 correspond to the values ​​9 and 11, respectively. Here, in order to perform encoding of a particular word x, the word x is XORed with the value of the first encoder value D1 (9 or 001-001 in binary) to calculate y (see the column marked y=x^D1). For example, for a value x=7, y is calculated by XORing 7 (000-111 in binary) with the first encoder value D1 (001-001) to obtain y=001-110. Referring back to Table 5, the second encoder value D2 has exactly one bit position with a value of 1 (at z=2 or at the second least significant bit). Therefore, for x=7, x' is calculated by XORing its bit value at z=2 of y (001-110, which has a value of 1 at z=2) with the bit values ​​at all other positions of y (z≠2) to obtain x'=110-011. As another example, for x=8, its corresponding value y is 000-001, which has a bit value of 0 at position 2. Therefore, when the bit values ​​at bit positions other than 2 are XORed to calculate x', the values ​​remain unchanged from the values ​​of y so that x'=000-001.

[0161] Thus, aspects of embodiments of the present disclosure provide systems and methods for encoding data to reduce maximum run length, thereby improving the efficiency of conversions on a data link. Improving the efficiency of conversions can, for example, improve clock data recovery processing, thereby improving the quality of the connection between a transmitter and a receiver communicating via a data link. In more detail, some aspects of embodiments of the present disclosure relate to dividing the original data into data packets of N words, each word q bits long, encoding the original data so that the encoded data does not contain words that are all zero or all one, thereby ensuring that at least one conversion occurs per q bits. Encoding is performed based on a one-to-one mapping defined by two encoder values ​​corresponding to two values ​​that do not appear in the original data, wherein the two encoder values ​​are transmitted as overhead to be used by a decoder in a mapping defined for decoding the encoded data. Further improvement in efficiency is caused by reducing the data overhead associated with the encoding process by compressing the encoder values.

[0162] Although an example application of an embodiment of the present disclosure is described above in the context of a serial link between a graphics controller and a display device, the embodiments of the present disclosure are not limited thereto and may also be applied to other types of serial data links and serial data buses for connecting to other types of peripheral devices and computing devices, such as data storage devices (e.g., volatile or non-volatile memories and mass storage devices, etc.), external co-processing devices (e.g., external graphics processing units and artificial intelligence accelerators, etc.), network controllers, other computer systems, smart phones and other portable computing devices, etc.

[0163] Embodiments of the present invention may be implemented in various ways as will be understood by those of ordinary skill in the art, and the term "processor" as used herein may represent any computing device capable of performing the described operations, such as a programmed general-purpose processor (e.g., an ARM processor), a field programmable gate array (FPGA), and a custom application-specific integrated circuit (ASIC) having instructions stored in a memory connected to the general-purpose processor. Embodiments of the present invention may be integrated into a serial communication controller (e.g., a universal serial bus or USB controller), a graphics processing unit (GPU), an in-panel interface, and other hardware or software systems configured to transmit and receive digital data.

[0164] While the invention has been described in conjunction with certain exemplary embodiments, it should be understood that the invention is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. An encoder comprising a processing circuit, wherein the processing circuit is configured to: Receive raw data; Dividing the original data into a plurality of original q-bit words; assembling a data packet including N original q-bit words from the plurality of original q-bit words; identifying a first encoder value (D1) and a second encoder value (D2) missing from the values ​​of the N original q-bit words; encoding the N original q-bit words based on a one-to-one mapping from q-bit original values ​​to q-bit encoded values ​​according to the first encoder value (D1) and the second encoder value (D2) to generate N encoded q-bit payload words, the N encoded q-bit payload words having no words that are all zeros and no words that are all ones; generating a key representing the first encoder value (D1) and the second encoder value (D2); as well as The key and the N encoded q-bit payload words are transmitted.

2. The encoder according to claim 1, wherein The processing circuit is configured to encode the q-bit original value x as a q-bit encoded value x' based on a comparison of the q-bit original value x with the first encoder value (D1) and the second encoder value (D2).

3. The encoder according to claim 1, wherein the first encoder value (D1) and the second encoder value (D2) have a matching prefix of length q-1, wherein the calculated value E is set to the q-1 most significant bits of the first encoder value (D1), and Wherein, the processing circuit is configured to generate the key, the key comprising the calculated value E representing the first encoder value (D1) and the second encoder value (D2).

4. The encoder according to claim 3, wherein: The processing circuit is configured to encode the q-bit original value x and the calculated value E as a q-bit encoded value x′ by calculating an exclusive OR operation on the q-bit original value x and the calculated value E.

5. The encoder according to claim 1, wherein 2 of the q bits of the original value q The space of values ​​is divided into multiple groups, each group includes a continuous number of different q-bit original values, and The processing circuit is configured to identify the first encoder value (D1) and the second encoder value (D2) by: identifying packets having two q-bit original values ​​missing from said values ​​of said N original q-bit words; and One of the two q-bit original values ​​in the identified group is identified as the first encoder value (D1), and the other of the two q-bit original values ​​in the identified group is identified as the second encoder value (D2).

6. The encoder according to claim 5, wherein: The q bits of the original value are 2 q The space of values ​​is divided into G groups, and Where N is less than or equal to 2 q -G-1.

7. The encoder according to claim 6, wherein Each grouping contains up to three values, and The processing circuit is configured to generate a calculated value E representing the first encoder value (D1) and the second encoder value (D2) by selecting a middle value of a group in the G groups including the first encoder value (D1) and the second encoder value (D2).

8. The encoder according to claim 7, wherein: The processing circuit is configured to encode the q-bit original value x as a q-bit encoded value x′ based on a comparison of the q-bit original value x and the calculated value E.

9. The encoder according to claim 5, wherein: Each group includes 2 r values, wherein the first encoder value (D1) and the second encoder value (D2) share qr most significant bits, and The processing circuit is configured to generate the key representing the first encoder value (D1) and the second encoder value (D2) by: encoding the r least significant bits of the first encoder value (D1) and the r least significant bits of the second encoder value (D2) using 2r-1 bits to generate a least significant bit code, the least significant bit code having at least one transition; and The qr most significant bits are concatenated with the least significant bit code.

10. The encoder according to claim 9, wherein: The processing circuit is further configured to generate the key representing the first encoder value (D1) and the second encoder value (D2) by dividing the qr most significant bits into a first part and a second part, and The least significant bit code is serially connected between the first part and the second part of the qr most significant bits.

11. The encoder according to claim 1, wherein: The processing circuit is configured to transmit a data packet, the data packet comprising: said N encoded q-bit payload words; and A header including the key.

12. A decoder comprising a processing circuit, the processing circuit being configured to: receiving a key and N encoded q-bit payload words; decoding a first encoder value (D1) and a second encoder value (D2) from the key; and The N encoded q-bit payload words are decoded based on a one-to-one mapping from q-bit encoded values ​​to q-bit original values ​​according to the first encoder value (D1) and the second encoder value (D2) to generate N decoded original q-bit words.

13. The decoder according to claim 12, wherein: The processing circuit is configured to decode the q-bit encoded value x' into a q-bit decoded value x based on a comparison of the q-bit encoded value x' with the first encoder value (D1) and the second encoder value (D2).

14. The decoder according to claim 12, wherein: The key comprises a calculated value E, wherein the processing circuit is configured to decode the first encoder value (D1) by setting q-1 most significant bits of the first encoder value (D1) to the calculated value E and setting the least significant bit of the first encoder value (D1) to 0, and The processing circuit is configured to decode the second encoder value (D2) by setting q-1 most significant bits of the second encoder value (D2) to the calculated value E and setting the least significant bit of the second encoder value (D2) to 1.

15. The decoder according to claim 14, wherein: The processing circuit is configured to decode the q-bit encoded value x' into a q-bit original value x based on a result of an exclusive OR operation performed on the q-bit encoded value x' and the calculated value E.

16. The decoder according to claim 12, wherein: 2 of the q bits of the original value q The space of values ​​is divided into multiple groups, each group includes a continuous number of different q-bit original values, Each group contains up to three values. wherein a calculated value E representing the first encoder value (D1) and the second encoder value (D2) is generated by selecting a middle value of a group in the plurality of groups including the first encoder value (D1) and the second encoder value (D2), and Wherein, the processing circuit is configured to decode the first encoder value (D1) and the second encoder value (D2) based on the result of the modulo operation on the calculated value E.

17. The decoder according to claim 16, wherein: The processing circuit is configured to decode the q-bit encoded value x' into the q-bit original value x based on a comparison of the q-bit encoded value x' and the calculated value E.

18. The decoder according to claim 12, wherein: 2 of the q bits of the original value q The space of values ​​is divided into multiple groups, each of which consists of 2 consecutive r different q-bit original values, wherein the first encoder value (D1) and the second encoder value (D2) share qr most significant bits, and The processing circuit is configured to decode the first encoder value (D1) and the second encoder value (D2) from the key by: Read the 2r-1 least significant bits from the header of the key; Decoding the least significant bit code into a first least significant bit and a second least significant bit; reading qr most significant bits from a portion of the header of the key; Concatenating the qr most significant bits with the first least significant bit to decode the first encoder value (D1); and The qr most significant bits are concatenated with the second least significant bits to decode the second encoder value (D2).

19. The decoder according to claim 12, wherein: The decoder is configured to receive a data packet, the data packet comprising: said N encoded q-bit payload words; and A header including the key.

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