A cyclotron optimization startup method based on continuous closed-loop mode

Abstract

The present invention discloses a cyclotron optimization startup method based on a continuous closed-loop mode, the method comprising: initialization preparation work, entering a low-power tuning state in the continuous closed-loop mode and realizing a tuning closed loop in the low-power state; entering a pulse search state in the continuous closed-loop mode and realizing a tuning closed loop in the pulse search state; entering a power boost state in the continuous closed-loop mode and realizing an amplitude closed loop in the power boost state; entering a normal operating state in the continuous closed-loop mode and realizing cavity pressure balance in the normal operating state. The present invention improves the quality factor of the cavity through a pre-tuning point: a pre-tuning method is used before two power boosting stages. This allows the input power to the cavity to be maximized and the power reflected back from the cavity to be minimized when entering a pulse search state and increasing the power; and allows the input power to the cavity to be maximized and the power reflected back from the cavity to be minimized when entering a power boosting state.

Description

Technical Field

[0001] The invention relates to a cyclotron high-frequency low-level system design technology, and in particular to a cyclotron optimization startup method based on a continuous closed-loop mode. Background Art

[0002] There are two tasks in the process of starting the high-frequency cavity of a high-Q cyclotron accelerator: on the one hand, it is necessary to avoid the secondary electron multiplication effect area, because the secondary electron multiplication effect will limit the power increase of the high-frequency system; on the other hand, it is necessary to find the tuning point, because if the tuning point cannot be found, it will also limit the power increase of the high-frequency system. If the power of the high-frequency system cannot be increased to the predetermined value, the high-frequency cavity will not be able to accelerate particles after it is started. The tuning point is when the frequency of the high-frequency cavity and the frequency of the high-frequency signal are consistent.

[0003] The first method adopted by the prior art: only one of the above tasks is completed. Instead of finding the tuning point first, the pulse search method is used to directly cross the multi-electron effect region. During the pulse search process, the low-level control system outputs a series of short pulses with higher power, and at the same time controls the tuning capacitor to do reciprocating motion to track the cavity resonance point. However, this method requires that the landing point across the multi-electron effect region, that is, the point of the starting pulse must be near the tuning point. If it is started at a point deviating from the resonance point, the reciprocating range of the tuning capacitor is limited, and the system may not be able to start normally because the resonance point cannot be searched.

[0004] The second method adopted by the prior art is to first find the tuning point and then cross the multi-electron effect region. For example, the low-level start-up of the cyclotron of PSI in Switzerland is like this: first find the tuning point in the low-power region before the multi-electron effect region of less than 1 watt, and then use the pulse method to cross the multi-electron effect region. Although this method is feasible, it is limited to finding the tuning point under the condition of a minimum power of 1 watt. For applications where the power is less than 100 times that of 1 watt and is only tens of milliwatts, it is useless. For example, the compact cyclotron designed by the China Institute of Atomic Energy has a lower starting point power in the secondary electron multiplication region, which is nearly tens of milliwatts. Therefore, its power at the low-power tuning point is also lower, and the design is more difficult.

[0005] In summary, the difficulty in starting the high-frequency cavity of a compact cyclotron is how to find the tuning point under extremely low power conditions of nearly tens of milliwatts. Summary of the invention

[0006] In view of the problems existing in the prior art, the present invention proposes a cyclotron optimization startup method based on a continuous closed-loop mode, aiming to solve the problem that it is difficult to find a tuning point when a compact cyclotron high-frequency cavity is started under ultra-low power conditions.

[0007] The present invention proposes the following technical solutions to solve the technical problems:

[0008] A cyclotron optimization startup method based on a continuous closed-loop mode is characterized by comprising the following steps:

[0009] Step 1: Initialization preparation

[0010] 1) Establish a one-button start-up process for the cyclotron low-level system;

[0011] 2) Establish a CPU state machine, the state of the state machine is S0~S4;

[0012] Step 2: Enter the low power tuning state in the continuous closed loop mode and realize the tuning closed loop in the low power state;

[0013] Step 3: Enter the pulse search state in the continuous closed-loop mode and implement the tuning closed-loop in the pulse search state;

[0014] Step 4: Enter the power boost state in the continuous closed-loop mode and realize the amplitude closed-loop in the power boost state;

[0015] Step 5: Enter the normal operating state under the continuous closed-loop mode and achieve cavity pressure balance under the normal operating state.

[0016] The specific process of step 2 of entering the low-power tuning state in the continuous closed-loop mode and realizing the tuning closed-loop in the low-power state is as follows:

[0017] 1) The low-level modulation output module inputs a low-level continuous signal to the accelerator cavity, and the low-level continuous signal drives the accelerator cavity, and obtains the cavity forward signal Forward, cavity sampling signal Pickup1, and cavity sampling signal Pickup2 of the tuning module from the accelerator through the sampling cable;

[0018] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a continuous signal, and the continuous signal is input to the AND gate and CPU for AND operation, and the AND operation result outputs a low level;

[0019] 3) A low level signal is given to high frequency switch 1, high frequency switch 2, and high frequency switch 3;

[0020] 4) High-frequency switch 1 and high-frequency switch 2 are connected to the amplifier to ensure that the signal can enter the phase detection range of the phase detector; high-frequency switch 3 is connected to a 14db attenuator to ensure that the voltage of the low-level continuous signal output has not reached the secondary electron multiplication effect area of ​​the cavity;

[0021] 5) performing a subtraction operation on the ADC analog signal derived from the phase detector and the tuning parameter setting value, and sending the operation result to the digital controller through the ADC in one way and to the tuning comparator in the other way;

[0022] 6) When the tuning comparator determines that the cavity frequency and the high-frequency signal frequency are consistent, it outputs a tuning closed-loop signal PhaseOK to the CPU, realizing the tuning closed-loop in the low-power tuning state and entering the pulse search phase.

[0023] The specific process of step 3 of entering the pulse search state in the continuous closed-loop mode and realizing the tuning closed-loop in the pulse search state is as follows:

[0024] 1) After the CPU receives the tuning closed-loop signal PhaseOK in the low-power tuning state, its forced conversion signal ForceCW output is 1;

[0025] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a pulse with a gradually widened duty cycle. The pulse signal with a gradually widened duty cycle is input to the AND gate and CPU for AND operation, and the AND operation result outputs a pulse signal with a gradually widened duty cycle;

[0026] 3) The pulse signal with gradually widened duty cycle is sent to high frequency switch 3, and is also sent to high frequency switches 1 and 2;

[0027] 4) According to the pulse signal with gradually widened duty cycle, the high-frequency switch 3 selects one 3db attenuator when the pulse is at high level and one 14db attenuator when the pulse is at low level, so as to achieve the widening of the low-level output pulse signal; according to the pulse signal with gradually widened duty cycle, the high-frequency switch 1 and the high-frequency switch 2 of the tuning module select one attenuator when the pulse is at high level and one amplification when the pulse is at low level; because the power is increased in the pulse search state, the cavity forward signal Forward and the cavity sampling signal Pickup1 with increased power enter the phase detector through the attenuator;

[0028] 5) Subtracting the ADC analog signal derived from the phase detector from the tuning parameter setting value, and sending the result of the operation to the digital controller through the ADC and to the tuning comparator through the other path;

[0029] 6) When the tuning comparator determines that the cavity frequency and the high-frequency signal frequency are consistent, it outputs a tuning closed-loop signal PhaseOK to the CPU, implements the tuning closed-loop in the pulse search state, enters the power boost state, and closes the tuning comparator.

[0030] The specific process of step 4 of entering the power boost state in the continuous closed-loop mode and realizing the amplitude closed-loop in the power boost state is as follows:

[0031] 1) After the CPU receives the tuning closed-loop signal PhaseOK in the power search state, its forced conversion signal ForceCW output is 1;

[0032] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a high-level continuous signal, which is input into the AND gate and CPU for AND operation, and the AND operation result outputs a high-level continuous signal;

[0033] 3) A high-level continuous signal is sent to high-frequency switch 3, and a high-level continuous signal is sent to high-frequency switches 1 and 2 at the same time;

[0034] 4) The high-frequency switch 3 selects the 3db attenuator according to the high-frequency signal; the high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-frequency signal;

[0035] 5) The digital controller controls the digital controlled attenuator to continuously reduce the attenuation, and then continuously increase the power, until the amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed, the amplitude closed-loop is realized, and the normal operation state is entered.

[0036] The step 5 enters the normal operation state under the continuous closed-loop mode and realizes the cavity pressure balance under the normal operation state. The specific process is as follows:

[0037] 1) After the CPU receives the amplitude closed-loop signal VDee_OK in the power boost state, its forced conversion signal ForceCW output is 1;

[0038] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a high-level continuous signal. The continuous signal is input to the AND gate and CPU for AND operation, and the AND operation result outputs a high-level continuous signal;

[0039] 3) A high-level continuous signal is sent to high-frequency switch 3, and a high-level continuous signal is sent to high-frequency switches 1 and 2 at the same time;

[0040] 4) The high-frequency switch 3 selects the 3db attenuator according to the high-frequency signal; the high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-frequency signal;

[0041] 5) The numerically controlled attenuator is a constant value;

[0042] 6) The digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0043] The digital controller of process 6) starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities. The specific steps are as follows:

[0044] 1) When the two cavities of the accelerator are capacitively coupled, the ratio of the voltage imbalance between the two cavities due to factors such as processing design is shown in the following formula [1]:

[0045]

[0046] Wherein, C12 is the coupling capacitance value between the two groups of cavities, which is divided into two parts, C12" and C12', where C12" is the capacitance of the D1 cavity and C12' is the capacitance of the D2 cavity;

[0047] 2) The D voltage can be adjusted by changing the ratio of C12” and C12', and its balance control algorithm is as follows: The phase detector output result Tphase determines the movement frequency of the capacitor motor, and the motor movement step setting value Dsteps determines the movement steps of the motor. When Dsteps>0, Tphase>0, the motor of the D1 cavity group moves in the positive direction at 2 times the speed, and the motor of the D2 cavity group stops; when Dsteps>0, Tphase<0, the motor of the D2 cavity group moves in the reverse direction at 2 times the speed, and the motor of the D1 cavity group does not move; when Dsteps<0, TPhase>0, the motor of the D2 cavity group moves in the positive direction at twice the speed, and the motor of the D1 cavity group does not move; when Dsteps<0, TPhase<0, the motor of the D1 cavity group moves in the reverse direction at twice the speed, and the motor of the D2 cavity group does not move.

[0048] The closed-loop tuning of step 2 and step 3 is implemented by the PID tuning algorithm unit of the digital controller as follows:

[0049] 1) The digital PID algorithm is expressed as:

[0050] y(n)=y(n-1)+K0x(n)+K1x(n-1)+K2(n-2);

[0051] Where y(n) is the PID operation output, y(n-1) is the PID operation output at the previous moment, K0, K1, and K2 are PID adjustment coefficients, and x(n), x(n-1), and x(n-2) are the PID inputs at the current moment, the previous moment, and the previous two moments;

[0052] 2) Use R0 and R3 registers in the DSP's X memory, and read and write operations are performed by the global data bus;

[0053] 3) Store the PID inputs x(n), x(n-1) and x(n-2) of the current moment, the previous moment and the previous two moments into register R0, and store k0, k1, k2 into register R3;

[0054] 4) Use the global bus to read and write these two registers and use the accumulator and multiplication function in the DSP to implement y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

[0055] Advantages and effects of the present invention

[0056] 1. The present invention improves the quality factor of the cavity through the pre-tuning point: the pre-tuning method is adopted before the two power increase stages. The first pre-tuning is to find the tuning point before entering the pulse search state from the low-power tuning state, so that when entering the pulse search state to increase the power, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized, that is, the Q value of the cavity is the highest. The second pre-tuning is to find the tuning point before entering the power increase state from the pulse search state, that is, to find the tuning point for the second time in the pulse search stage, so that when entering the power increase state, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized.

[0057] 2. The present invention solves the long-standing problem of finding the tuning point at ultra-low power during the start-up of the accelerator cavity by organically combining the tuning module, the low-level modulation output module, the amplitude demodulation module, the PID tuning algorithm unit of the digital controller and the DSP balance algorithm unit, the CPU and the gate force signal. At the same time, it also solves the problem that the tuning point needs to be found twice during the cavity start-up process due to power changes: by setting the high-frequency switch 1 and the high-frequency switch 2, the amplifier, the attenuator and the phase detector of the tuning module, the problem that the low-power signal cannot be recognized by the phase detector under ultra-low power and the cavity signal under high-power signal enters the phase detector and exceeds the maximum input power of the phase detector, thereby burning the phase detector is solved; by organically combining the PID tuning algorithm unit, the tuning parameter setting module and the tuning comparator of the tuning module, the problem that the PID operation rate cannot keep up with the state change when finding the tuning point is solved; by the low-level output signal of the low-level modulation output module, the high-frequency switch 3, the 3db attenuation and the 14db attenuation and The organic combination of tuning modules not only realizes the tuning closed loop in the low-power tuning state, but also realizes the tuning closed loop in the high-power pulse search state; through the cavity sampling signal Pickup2 of the amplitude demodulation module, the detector, the pulse-to-continuous circuit, the amplitude modulation parameter setting module and the amplitude comparator, after the cavity sampling signal Pickup2 is three centimeters, one of the signals passes through the detector 1 and the pulse-to-continuous circuit, and the pulse signal or the continuous signal is input into the AND gate and the CPU for AND operation, which solves the control problem of high-frequency signals 1, 2, and 3 in the two stages of the tuning closed loop, so that the high-frequency switches 1 and 2 select a 25db amplifier and a 14db attenuator at ultra-low power, so that the weak signal can enter the phase detection range of the phase detector; at high power, the high-frequency signals 1 and 2 select a 23db attenuator and the high-frequency switch 3 selects a 3db attenuator, so that the high-power cavity sampling signal will not burn the phase detector due to exceeding the maximum input power of the phase detector. In short, through the organic combination of various modules, mutual support and reliance, new effects have been produced and substantial progress has been achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a schematic diagram of the cyclotron optimization starting device based on the continuous closed-loop mode of the present invention;

[0059] Figure 2 Schematic diagram of the PID tuning algorithm for the invented optimized starting device.

[0060] Figure 3 This is a flow chart of a cyclotron optimization startup method based on a continuous closed-loop mode of the present invention; DETAILED DESCRIPTION

[0061] Design principle of the present invention

[0062] 1. The innovation of the present invention is that it adopts a pre-tuning method to improve the quality factor of the cavity: the pre-tuning is to adopt a pre-tuning method before the two power increase stages. The first pre-tuning is to find the tuning point before entering the pulse search state from the low-power tuning state, so that when entering the pulse search state to increase the power, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized, that is, the Q value of the cavity is the highest. The second pre-tuning is to find the tuning point before entering the power boost state from the pulse search state, that is, to find the tuning point for the second time in the pulse search stage, so that when entering the power boost state, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized.

[0063] 2. Difficulties in the design of the present invention: One of the difficulties is to achieve tuning under ultra-low power. Compared with the lowest power of 1 watt in the prior art, the low power of the present invention is only tens of milliwatts, which is nearly 100 times different. Since the cavity signal voltage is very low under ultra-low power signals, the cavity signal voltage does not reach the minimum value of the phase detector input voltage and thus cannot be phase-detected. This is one of the difficulties; the second difficulty is that even if the tuning point is found under low power, it is still necessary to cross the secondary electron multiplication effect region under the high power of the pulse search. When tuning from low power to the pulse search state, the power has changed. The tuning point will also change slightly due to the power change, and it is necessary to find the tuning point again. When finding the tuning point again, the sampling cavity signal of the tuning module is already a high-power signal. The high-power signal causes the phase detector to burn out because the voltage exceeds the maximum input value of the phase detector input voltage. This is the second difficulty; the third difficulty is that the PID algorithm is required to adapt to the requirements of the data processing speed of the previous state and the next state. The PID output result is used to control the motor of the cavity so that the cavity signal and the high-frequency signal are consistent, thereby realizing a closed-loop tuning. Before the next state is reached, the PID is required to complete processing of the data of the previous state to avoid mixing the data of the next state with the data of the previous state because the data of the previous state has not been processed, resulting in motor control errors.

[0064] 3. Solution of the present invention: First, the solution to the first and second difficulties is: 1) Set up three high-frequency switches, set up two high-frequency switches 1 and 2 in the tuning module, and set up amplifiers and attenuators corresponding to the high-frequency switches 1 and 2. Set up a high-frequency switch 3 in the low-level modulation output module, and set up 3db and 14db attenuators. 2) When in low power tuning state, the amplifier is selected by high frequency switches 1 and 2, and the amplifier is 25db, so that the signal is amplified and enters the phase detector range, thereby solving the problem that the signal is weak and not easy to enter the phase detector range; at the same time, in order to ensure that the input to the cavity is an ultra-low power signal in the low power tuning state, the high frequency switch 3 is also required to select a 14db attenuator to ensure that the signal output to the cavity is an ultra-low power signal of tens of millivolts; 3) When switching to the power search state, in order to prevent the cavity sampling signal from burning the phase detector, the high frequency switches 1 and 2 select the attenuator all the way. This attenuation is only a weak attenuation, and the standard is not to burn the phase detector. Therefore, the design of the attenuator should adopt a moderate 23db attenuation; in order to ensure that the input to the cavity in the power search state is a high power signal, the high frequency switch 3 is also required to select a 3db attenuator, and the power can be increased or decreased by selecting different attenuators through the high frequency switch 3. Second, the solution to the third difficulty is to speed up the processing speed of PID. One way to speed up PID processing is to execute several instructions together, including addition instructions, multiplication instructions, data transfer instructions, shift instructions, etc., which speeds up the serial execution of instructions compared to conventional methods; the second way to speed up PID processing is to use assembly language, because assembly language is more basic than other languages, so the operation speed is fast; the third way to speed up PID processing is to use a multi-bus architecture, which further highlights the effect of parallel processing compared to an architecture with only one bus. The above three methods support and depend on each other, and none of them can be missing. Only the combination of the three can achieve the best effect.

[0065] 4. The invention discloses a cyclotron optimization startup device based on a continuous closed-loop mode. Figure 1As shown, the device includes a tuning module based on a continuous closed-loop mode for finding a tuning point, a low-level modulation output module based on a continuous closed-loop mode, an amplitude demodulation module based on a continuous closed-loop mode, a CPU based on a continuous closed-loop mode, and a digital controller based on a continuous closed-loop mode; the CPU based on a continuous closed-loop mode is provided with a state machine for controlling a high-frequency cavity startup process, and the state machine includes a shutdown state s0, a low-power tuning state s1, a pulse search state s2, a power boost state s3, and a normal operation state s4 during the high-frequency cavity startup process; the digital controller based on a continuous closed-loop mode is provided with a PID tuning algorithm unit, a DSP balancing algorithm unit, and a signal receiving unit from an analog circuit and realizing communication with the CPU; the PID tuning algorithm unit avoids cavity detuning by accelerating the PID operation rate; the DSP balancing algorithm unit ensures cavity pressure balance of two groups of cavities by adjusting the capacitor motor;

[0066] Its characteristics are: the tuning module for finding tuning points based on the continuous closed-loop mode makes the cavity frequency and the high-frequency signal frequency consistent by finding the tuning points in the low-power tuning stage and the pulse search stage to meet the conditions for accelerating particles, wherein the pulse search stage outputs a high-power pulse signal to cross the electron multiplication effect region and realize pulse broadening; the continuous closed-loop mode means that the closed-loop modes of the low-power tuning state, the pulse search state, and the power boost state are all continuous closed-loop modes.

[0067] Supplementary Note 1:

[0068] 1. Figure 1 It is divided into three parts: upper, middle and lower. The top layer is the tuning module, the bottom layer is the amplitude demodulation module, and the middle layer is the low-level output module. The top and bottom layers are sampling from the cavity, and the middle layer is inputting high-frequency signals to the cavity. The purpose of sampling from the cavity is to perform tuning closed loop and amplitude closed loop; the purpose of inputting high-frequency signals to the cavity is to increase the power of the cavity to the voltage that can accelerate particles, and to ensure that the cavity frequency is stable at the high-frequency signal frequency, so as to achieve the purpose of accelerating particles.

[0069] 2. However, the power increase must meet two conditions. The first is to find the tuning point, that is, the tuning loop is closed. At this time, the signal output to the cavity can increase the power; the second is the amplitude closed loop. Although the tuning loop finds the tuning point, the power may still not reach the set height, so it is necessary to realize the amplitude closed loop, that is, the amplitude reaches the set height. Therefore, the low-level output signal of the middle layer is a process of power from low to high.

[0070] Furthermore, in the continuous closed-loop mode, the low-power tuning state, the power boosting state, and the normal operating state are set as the continuous signal operating mode, and the pulse search state is set as the pulse signal operating mode, and the tuning closed loop in the low-power tuning state, the tuning closed loop in the power search state, and the amplitude modulation closed loop in the power boosting state are all closed loops under continuous signals.

[0071] Supplementary Note 2

[0072] The continuous closed-loop mode means that two stages of tuning closed-loop (low-power tuning state, power search state) and one stage of amplitude closed-loop (power boost state) are both closed-loop under the condition of continuous signals.

[0073] Furthermore, the tuning module for finding the tuning point based on the continuous closed-loop mode is provided with a cavity forward signal Forward, a cavity sampling signal Pickup1, a high-frequency switch 1 and a high-frequency switch 2, an amplifier and an attenuator, a phase detector, a tuning parameter setting module and a tuning comparator in sequence between the accelerator cavity and the CPU; in the low-power tuning state, the pulse-to-continuous circuit outputs a pulse signal with a duty cycle of 10%, and the CPU controls the ForceCW signal to output a low-level signal, and performs an AND operation with the output of the pulse-to-continuous circuit, and the result is still a low-level signal, and the AND operation output result is given to the high-frequency switch 1 and the high-frequency switch 2 of the tuning module, and the high-voltage switch 3 of the low-level modulation output module. The low-level signal, the forward signal Forward of the cavity and the cavity sampling signal Pickup1 are connected to their respective amplifiers through high-frequency switches 1 and 2, and the high-voltage switch 3 selects a 14db attenuator. In the power search state, the pulse-to-continuous circuit outputs a pulse signal with a duty cycle that is continuously widened from 10% to 50%. The CPU controls the ForceCW signal to output a high-level signal, and performs an AND operation with the pulse signal output by the pulse-to-continuous circuit. The result is still a pulse signal with a continuously widened duty cycle. High-frequency switches 1 and 2 select back and forth between the amplifier and the attenuator according to the pulse signal. At the same time, high-frequency switch 3 also selects back and forth between 3db attenuation and 14db attenuation, that is, when the pulse is high-level, the power supply is turned on and the power is turned off. Normally, switch 1 and switch 2 select the attenuator, and switch 3 selects 3db attenuation. When the pulse is at a low level, switch 1 and switch 2 select the amplifier, and switch 3 selects 14db attenuation. In the power boost state and normal operation state, the pulse-to-continuous circuit outputs a high-level continuous signal. The CPU controls the ForceCW signal to output a high-level signal, and performs an AND operation on the output result of the pulse-to-continuous circuit. The result is a high-level signal. The AND operation output result is given to high-frequency switch 1 and high-frequency switch 2, as well as high-frequency switch 3 of the low-level modulation output module. The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are connected to their respective attenuators through high-frequency switch 1 and high-frequency switch 2. The high-frequency switch 3 is connected to a 3db attenuator; the ADC analog signal derived from the phase detector is subtracted from the tuning parameter setting value, and the calculation result is sent to the digital controller through the ADC and to the tuning comparator in another way; in the low-power tuning and pulse search states, the tuning comparator uses a continuous signal to judge the tuning closed loop. When the tuning comparator judges that the cavity frequency and the high-frequency signal frequency are consistent, the tuning closed loop signal PhaseOK is output respectively, and the signal is sent to the CPU through the digital controller; the cavity forward signal Forward and the cavity sampling signal Pickup1 are obtained by sampling the sampling cable after the low-level modulation output module drives the accelerator cavity.

[0074] Supplementary Note 3

[0075] The relationship between the tuning module and the other two modules. Although it is an independent module, the tuning module is inseparable from the low-level output signal of the low-level output module: the low-level output signal drives the accelerator cavity to generate the cavity forward signal Forward and the cavity sampling signal Pickup1; the tuning module is also inseparable from the AND gate operation result of the amplitude demodulation module, because it is the AND gate operation result that controls the high-frequency switches 1 and 2 of the tuning module, and controls the high-frequency switch 3 at the same time. Although the high-frequency switch 3 belongs to the low-level output module, it will also affect the tuning closed loop of the second stage of the tuning module, that is, the power search stage: specifically, in the power search stage, the cavity signal power entering the high-frequency switches 1 and 2 is enhanced. At this time, it is not necessary to select an amplifier but an attenuator, because the signal is too strong, so it needs to be attenuated to facilitate the phase detector phase detection. Only when it enters the phase detector phase detection range can the tuning closed loop judgment under the subsequent power search state be performed. The cavity signal power entering the high-frequency switches 1 and 2 is enhanced because the high-frequency switch selects a 3db attenuator to enhance the signal power entering the cavity. In short, the tuning module is inseparable from the other two modules because the tuning module serves two stages. Only when the tuning module is organically combined with the other two modules can the tuning closed-loop judgment of the two stages be realized.

[0076] Furthermore, the amplitude demodulation module based on the continuous closed-loop mode is provided with a cavity sampling signal Pickup2, a detector, a pulse-to-continuous circuit, an amplitude modulation parameter setting module and an amplitude comparator in sequence between the accelerator cavity and the CPU; after three centimeters of the cavity sampling signal Pickup2, one path passes through a differential circuit for ignition detection judgment, and the other two paths, one path passes through the detector 1 and the pulse-to-continuous circuit, and the pulse signal or the continuous signal is input into the AND gate and the CPU for AND operation; one path is used for amplitude closed-loop judgment after being detected by the detector 2; in the power boost state, when the voltage value of the detection result of the detector 1 is subtracted from the amplitude modulation parameter setting and it is judged that if it is within the allowable range, it is judged as an amplitude closed-loop, and a continuous amplitude closed-loop signal VDee_OK signal is output to the CPU.

[0077] Furthermore, in the pulse-to-continuous circuit, in the low-power tuning stage, the input of the pulse-to-continuous circuit is a low-power signal, and the output is a signal with a 10% duty cycle. The signal is given to the AND gate and performs an AND operation with the ForceCW controlled by the CPU, and the result of the AND operation is a low level; in the pulse search stage, the pulse-to-continuous circuit determines that the current power has reached the power of the low-power tuning closed loop, and then outputs a pulse with a gradually widened duty cycle to the AND gate and performs an AND operation with the ForceCW controlled by the CPU. The AND gate gives the pulse with a gradually widened duty cycle to the high-frequency switch 3, and selects to connect a 14db attenuator when the pulse is at a low level, and selects a 3db attenuator when it is at a high level, thereby realizing pulse widening; in the power boost stage, the pulse-to-continuous circuit determines that the current power has reached the power of the pulse search state amplitude closed loop, and then outputs a continuous signal to the AND gate and performs an AND operation with the CPU, and the output of the AND gate is a continuous high level and is given to the high-frequency switch 3, and the high-frequency switch 3 is connected to the 3db attenuator according to the continuous high level signal.

[0078] Supplementary Note 4

[0079] The pulse-to-continuous circuit of the amplitude demodulation module is used for all four states. The output power signal in these four states is determined by the pulse-to-continuous circuit. However, the pulse-to-continuous circuit only determines whether to output a low-level continuous signal (low-power tuning state) or a pulse-stretched signal (pulse search state), or a high-level continuous signal (power boost state, normal operation state). The pulse-to-continuous circuit also needs to cooperate with the CPU to jointly output the signal to the AND gate. The operation result of the AND gate is a pulse or continuous signal on the one hand, and is used to control three high-frequency switches on the other hand.

[0080] Furthermore, the low-level modulation output module based on the continuous closed-loop mode is provided with a high-frequency signal digital-to-analog module, an amplitude-phase modulation module, a 3db attenuator and a 14db attenuator, a high-frequency switch 3, a digitally controlled attenuator, and a low-level output signal in sequence along the direction from the digital controller to the accelerator cavity; in the low-power tuning state, the low-level output signal drives the accelerator cavity, thereby obtaining the cavity forward signal Forward and the cavity sampling signal Pickup1 of the tuning module through the sampling cable; in the power search state, after the CPU receives the continuous tuning closed-loop PhaseOK signal in the low-power tuning state , the high-frequency switch 3 is connected to the 3db attenuator and the 14db attenuator at different times through the AND gate operation result to achieve pulse width broadening. At this time, the digital controlled attenuator is a fixed value and remains unchanged; in the power boost state, after the CPU receives the continuous tuning closed-loop signal PhaseOK of the pulse search phase, it controls the high-frequency switch 3 to connect to the 3db attenuator through the AND gate operation result, and instructs the digital controller to control the digital controlled attenuator to continuously reduce the attenuation, thereby continuously increasing the power, until the amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed and the normal operating state is entered.

[0081] Supplementary Note 5

[0082] The relationship between the low-level modulation output module and the other two types of modules: The purpose of setting up the low-level modulation output module is to input signals of different powers to the cavity under different states. At the same time, the low-level modulation output module also requires the cooperation of the other two modules: in the low-power tuning state, since the signal power output to the cavity is very low, the high-frequency switches 1 and 2 of the tuning module are required to amplify the signal through the amplifier, and the high-frequency switch 3 of the low-power output module is required to select 14db attenuation; in the power search stage, power boost state, and normal operating state, since the signal power output to the cavity is enhanced, all three high-frequency switches are required to select the detector or 3db attenuator; at the same time, the low-level modulation output module also requires the cooperation of the amplitude modulation module, and the cavity sampling signal of the amplitude modulation module is sampled and given to the AND gate, and the three high-frequency signal switches are controlled by the AND operation results.

[0083] Further, when the CPU receives the continuous amplitude closed-loop signal VDeeOK and enters a normal operating state, the digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0084] Furthermore, the PID tuning algorithm unit is arranged in the digital controller, using a PID operation module, a data arithmetic logic module, and a multi-bus architecture; the data arithmetic logic module is used to realize the addition and multiplication functions in the PID operation module, and the PID tuning algorithm unit describes the PID digital operation algorithm in the assembly language of DSP and uses parallel processing instructions under the multi-bus architecture to realize the synchronous execution of multiple operation instructions, thereby speeding up the PID operation rate and avoiding cavity detuning.

[0085] Furthermore, the PID operation module is as follows: Figure 2 As shown, there are provided a PID operation output y(n) submodule for driving the accelerator cavity motor, a PID operation output y(n-1) submodule at the previous moment, a PID adjustment coefficient K0, K1, K2 submodule, and a PID input submodule of x(n), x(n-1) and x(n-2) at the current moment, the previous moment and the previous two moments; the data arithmetic logic module includes a DSP5600 series digital signal processor, which stores the PID input x(n), x(n-1) and x(n-2) at the current moment, the previous moment and the previous two moments in register R0, stores the PID adjustment coefficients k0, k1, k2 in register R3, uses the global bus to read and write these two registers, and uses the DSP

[0086] The accumulator and multiplication functions in the , using assembly instructions to implement

[0087] y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

[0088] Supplementary Note 6

[0089] This parallel assembly instruction effectively improves the operation rate of the PID algorithm. The output result of the y(n) submodule is used to tune the movement of the motor to change the resonant frequency of the cavity, thereby affecting the phase difference between the cavity sampling signal and the forward signal, so that the output voltage of the phase detector approaches the set voltage of the parameter setting module. The set voltage of the parameter setting module is the voltage of the phase difference between the cavity sampling signal and the cavity forward signal when the preset cavity frequency and the high-frequency signal frequency are consistent. The output voltage of the phase detector is the voltage of the actual phase difference between the cavity sampling signal and the cavity forward signal.

[0090] Furthermore, the DSP balancing algorithm unit is provided with a voltage balancing ratio calculating unit and a voltage balancing adjusting unit; the voltage balancing ratio calculating unit is used for the ratio relationship: Among them, C12 is the coupling capacitance value between the two groups of cavities, which is divided into two parts C12" and C12', wherein C12" is the capacitance of the D1 cavity, and C12' is the capacitance of the D2 cavity; the voltage balancing unit can adjust the cavity D plate voltage by changing the ratio of C12" and C12'.

[0091] Furthermore, for the CPU based on the continuous closed-loop mode, when in the low-power tuning state, the forced conversion signal ForceCW of the CPU is 0, and when in the power search, power boost, and normal operation states, the forced conversion signal ForceCW of the CPU is 1.

[0092] Based on the above invention principles, the present invention designs a cyclotron optimization startup method based on a continuous closed-loop mode. The method is based on a cyclotron optimization startup device based on a continuous closed-loop mode in point 4 of [the design principle of the present invention]. The steps of the method are as follows:

[0093] A cyclotron optimization startup method based on continuous closed-loop mode Figure 3 As shown, its characteristic is that it includes the following steps:

[0094] Step 1: Initialization preparation

[0095] 1) Establish a one-button start-up process for the cyclotron low-level system;

[0096] 2) Establish a CPU state machine, the state of the state machine is S0~S4;

[0097] Step 2: Enter the low power tuning state in the continuous closed loop mode and realize the tuning closed loop in the low power state;

[0098] Step 3: Enter the pulse search state in the continuous closed-loop mode and implement the tuning closed-loop in the pulse search state;

[0099] Step 4: Enter the power boost state in the continuous closed-loop mode and realize the amplitude closed-loop in the power boost state;

[0100] Step 5: Enter the normal operating state under the continuous closed-loop mode and achieve cavity pressure balance under the normal operating state.

[0101] Furthermore, the step 2 of entering the low-power tuning state in the continuous closed-loop mode and realizing the tuning closed loop in the low-power state is specifically performed as follows:

[0102] 1) The low-level modulation output module inputs a low-level continuous signal to the accelerator cavity, and the low-level continuous signal drives the accelerator cavity, and obtains the cavity forward signal Forward, cavity sampling signal Pickup1, and cavity sampling signal Pickup2 of the tuning module from the accelerator through the sampling cable;

[0103] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a continuous signal, and the continuous signal is input to the AND gate and CPU for AND operation, and the AND operation result outputs a low level;

[0104] 3) A low level signal is given to high frequency switch 1, high frequency switch 2, and high frequency switch 3;

[0105] 4) High-frequency switch 1 and high-frequency switch 2 are connected to the amplifier to ensure that the signal can enter the phase detection range of the phase detector; high-frequency switch 3 is connected to a 14db attenuator to ensure that the voltage of the low-level continuous signal output has not reached the secondary electron multiplication effect area of ​​the cavity;

[0106] 5) performing a subtraction operation on the ADC analog signal derived from the phase detector and the tuning parameter setting value, and sending the operation result to the digital controller through the ADC in one way and to the tuning comparator in the other way;

[0107] 6) When the tuning comparator determines that the cavity frequency and the high-frequency signal frequency are consistent, it outputs a tuning closed-loop signal PhaseOK to the CPU, realizing the tuning closed-loop in the low-power tuning state and entering the pulse search phase.

[0108] Furthermore, the step 3 of entering the pulse search state in the continuous closed-loop mode and realizing the tuning closed-loop in the pulse search state is specifically performed as follows:

[0109] 1) After the CPU receives the tuning closed-loop signal PhaseOK in the low-power tuning state, its forced conversion signal ForceCW output is 1;

[0110] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a pulse with a gradually widened duty cycle. The pulse signal with a gradually widened duty cycle is input to the AND gate and CPU for AND operation, and the AND operation result outputs a pulse signal with a gradually widened duty cycle;

[0111] 3) The pulse signal with gradually widened duty cycle is sent to high frequency switch 3, and is also sent to high frequency switches 1 and 2;

[0112] 4) According to the pulse signal with gradually widened duty cycle, the high-frequency switch 3 selects one 3db attenuator when the pulse is at high level and one 14db attenuator when the pulse is at low level, so as to achieve the widening of the low-level output pulse signal; according to the pulse signal with gradually widened duty cycle, the high-frequency switch 1 and the high-frequency switch 2 of the tuning module select one attenuator when the pulse is at high level and one amplification when the pulse is at low level; because the power is increased in the pulse search state, the cavity forward signal Forward and the cavity sampling signal Pickup1 with increased power enter the phase detector through the attenuator;

[0113] 5) Subtracting the ADC analog signal derived from the phase detector from the tuning parameter setting value, and sending the result of the operation to the digital controller through the ADC and to the tuning comparator through the other path;

[0114] 6) When the tuning comparator determines that the cavity frequency and the high-frequency signal frequency are consistent, it outputs a tuning closed-loop signal PhaseOK to the CPU, implements the tuning closed-loop in the pulse search state, enters the power boost state, and closes the tuning comparator.

[0115] Furthermore, the step 4 of entering the power boost state in the continuous closed-loop mode and realizing the amplitude closed-loop in the power boost state is specifically performed as follows:

[0116] 1) After the CPU receives the tuning closed-loop signal PhaseOK in the power search state, its forced conversion signal ForceCW output is 1;

[0117] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a high-level continuous signal, which is input into the AND gate and CPU for AND operation, and the AND operation result outputs a high-level continuous signal;

[0118] 3) A high-level continuous signal is sent to high-frequency switch 3, and a high-level continuous signal is sent to high-frequency switches 1 and 2 at the same time;

[0119] 4) The high-frequency switch 3 selects the 3db attenuator according to the high-frequency signal; the high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-frequency signal;

[0120] 5) The digital controller controls the digital controlled attenuator to continuously reduce the attenuation, and then continuously increase the power, until the amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed, the amplitude closed-loop is realized, and the normal operation state is entered.

[0121] Furthermore, the step 5 of entering the normal operation state in the continuous closed-loop mode and achieving cavity pressure balance in the normal operation state is specifically performed as follows:

[0122] 1) After the CPU receives the amplitude closed-loop signal VDee_OK in the power boost state, its forced conversion signal ForceCW output is 1;

[0123] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a high-level continuous signal. The continuous signal is input to the AND gate and CPU for AND operation, and the AND operation result outputs a high-level continuous signal;

[0124] 3) A high-level continuous signal is sent to high-frequency switch 3, and a high-level continuous signal is sent to high-frequency switches 1 and 2 at the same time;

[0125] 4) The high-frequency switch 3 selects the 3db attenuator according to the high-frequency signal; the high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-frequency signal;

[0126] 5) The numerically controlled attenuator is a constant value;

[0127] 6) The digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0128] Furthermore, the digital controller of the process 6) starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities, and the specific steps are as follows:

[0129] 1) When the two cavities of the accelerator are capacitively coupled, the ratio of the voltage imbalance between the two cavities due to factors such as processing design is shown in the following formula [1]:

[0130]

[0131] Wherein, C12 is the coupling capacitance value between the two groups of cavities, which is divided into two parts, C12" and C12', where C12" is the capacitance of the D1 cavity and C12' is the capacitance of the D2 cavity;

[0132] 2) The D voltage can be adjusted by changing the ratio of C12” and C12', and its balance control algorithm is as follows: The phase detector output result Tphase determines the movement frequency of the capacitor motor, and the motor movement step setting value Dsteps determines the movement steps of the motor. When Dsteps>0, Tphase>0, the motor of the D1 cavity group moves in the positive direction at 2 times the speed, and the motor of the D2 cavity group stops; when Dsteps>0, Tphase<0, the motor of the D2 cavity group moves in the reverse direction at 2 times the speed, and the motor of the D1 cavity group does not move; when Dsteps<0, TPhase>0, the motor of the D2 cavity group moves in the positive direction at twice the speed, and the motor of the D1 cavity group does not move; when Dsteps<0, TPhase<0, the motor of the D1 cavity group moves in the reverse direction at twice the speed, and the motor of the D2 cavity group does not move.

[0133] Furthermore, the closed-loop tuning of step 2 and step 3 is implemented by the PID tuning algorithm unit of the digital controller as follows:

[0134] 1) The digital PID algorithm is expressed as:

[0135] y(n)=y(n-1)+K0x(n)+K1x(n-1)+K2(n-2);

[0136] Where y(n) is the PID operation output, y(n-1) is the PID operation output at the previous moment, K0, K1, and K2 are PID adjustment coefficients, and x(n), x(n-1), and x(n-2) are the PID inputs at the current moment, the previous moment, and the previous two moments;

[0137] 2) Use R0 and R3 registers in the DSP's X memory, and read and write operations are performed by the global data bus;

[0138] 3) Store the PID inputs x(n), x(n-1) and x(n-2) of the current moment, the previous moment and the previous two moments into register R0, and store k0, k1, k2 into register R3;

[0139] 4) Use the global bus to read and write these two registers and use the accumulator and multiplication function in the DSP to implement y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

[0140] It should be emphasized that the above specific embodiments are merely explanations of the present invention, and they are not limitations of the present invention. After reading this specification, those skilled in the art can make modifications to the above embodiments without any creative contribution as needed, but as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A cyclotron optimization startup method based on a continuous closed-loop mode, characterized in that it comprises the following steps: Step 1: Initialization preparation 1) Establish a one-button start-up process for the cyclotron low-level system; 2) Establishing a CPU state machine, the state of the state machine includes the shutdown state s0 during the high-frequency cavity startup process, the low-power tuning state s1, the pulse search state s2, the power boost state s3, and the normal operation state s4; Step 2: Enter the low power tuning state in the continuous closed loop mode and realize the tuning closed loop in the low power state; Step 3: Enter the pulse search state in the continuous closed-loop mode and implement the tuning closed-loop in the pulse search state; Step 4: Enter the power boost state in the continuous closed-loop mode and realize the amplitude closed-loop in the power boost state; Step 5: Enter the normal operation state in the continuous closed-loop mode and achieve cavity pressure balance in the normal operation state; The specific process of step 2 of entering the low-power tuning state in the continuous closed-loop mode and realizing the tuning closed-loop in the low-power state is as follows: 1) The low-level modulation output module inputs a low-level continuous signal to the accelerator cavity, and the low-level continuous signal drives the accelerator cavity, and obtains the cavity forward signal Forward, cavity sampling signal Pickup1, and cavity sampling signal Pickup2 of the tuning module from the accelerator through the sampling cable; 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a continuous signal, and the continuous signal is input to the AND gate and CPU for AND operation, and the AND operation result outputs a low level; 3) A low level signal is given to high frequency switch 1, high frequency switch 2, and high frequency switch 3; 4) High-frequency switch 1 and high-frequency switch 2 are connected to the amplifier to ensure that the signal can enter the phase detection range of the phase detector; high-frequency switch 3 is connected to a 14db attenuator to ensure that the voltage of the low-level continuous signal output has not reached the secondary electron multiplication effect area of ​​the cavity; 5) Subtract the ADC analog signal from the phase detector from the tuning parameter setting value, and send the result of the operation to the digital controller through the ADC and to the tuning comparator through the other path; 6) When the tuning comparator determines that the cavity frequency and the high-frequency signal frequency are consistent, it outputs a tuning closed-loop signal PhaseOK to the CPU, realizes the tuning closed-loop under the low-power tuning state, and enters the pulse search phase; The specific process of step 3 of entering the pulse search state in the continuous closed-loop mode and realizing the tuning closed-loop in the pulse search state is as follows: 1) After the CPU receives the tuning closed-loop signal PhaseOK in the low-power tuning state, its forced conversion signal ForceCW output is 1; 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a pulse with a gradually widened duty cycle. The pulse signal with a gradually widened duty cycle is input to the AND gate and CPU for AND operation, and the AND operation result outputs a pulse signal with a gradually widened duty cycle; 3) The pulse signal with gradually widened duty cycle is sent to high frequency switch 3, and is also sent to high frequency switches 1 and 2; 4) According to the pulse signal with gradually widened duty cycle, the high-frequency switch 3 selects one 3db attenuator when the pulse is at high level and one 14db attenuator when the pulse is at low level, so as to achieve the widening of the low-level output pulse signal; according to the pulse signal with gradually widened duty cycle, the high-frequency switch 1 and the high-frequency switch 2 of the tuning module select one attenuator when the pulse is at high level and one amplification when the pulse is at low level; because the power is increased in the pulse search state, the cavity forward signal Forward and the cavity sampling signal Pickup1 with increased power enter the phase detector through the attenuator; 5) The ADC analog signal derived from the phase detector is subtracted from the tuning parameter setting value, and the calculation result is sent to the digital controller through the ADC and to the tuning comparator in another way; 6) When the tuning comparator determines that the cavity frequency and the high-frequency signal frequency are consistent, it outputs a tuning closed-loop signal PhaseOK to the CPU, implements the tuning closed-loop in the pulse search state, enters the power boost state, and closes the tuning comparator.

2. The method for optimizing the startup of a cyclotron based on a continuous closed-loop mode according to claim 1, characterized in that: The specific process of step 4 of entering the power boost state in the continuous closed-loop mode and realizing the amplitude closed-loop in the power boost state is as follows: 1) After the CPU receives the tuning closed-loop signal PhaseOK in the power search state, its forced conversion signal ForceCW output is 1; 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a high-level continuous signal, which is input into the AND gate and CPU for AND operation, and the AND operation result outputs a high-level continuous signal; 3) A high-level continuous signal is sent to high-frequency switch 3, and a high-level continuous signal is sent to high-frequency switches 1 and 2 at the same time; 4) The high-frequency switch 3 selects the 3db attenuator according to the high-frequency signal; the high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-frequency signal; 5) The digital controller controls the digital controlled attenuator to continuously reduce the attenuation, and then continuously increase the power, until the amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed, the amplitude closed-loop is realized, and the normal operation state is entered.

3. The method for optimizing the startup of a cyclotron based on a continuous closed-loop mode according to claim 1, characterized in that: The step 5 enters the normal operation state under the continuous closed-loop mode and realizes the cavity pressure balance under the normal operation state, and the specific process is as follows: 1) After the CPU receives the amplitude closed-loop signal VDee_OK in the power boost state, its forced conversion signal ForceCW output is 1; 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a high-level continuous signal. The continuous signal is input to the AND gate and CPU for AND operation, and the AND operation result outputs a high-level continuous signal; 3) A high-level continuous signal is sent to high-frequency switch 3, and a high-level continuous signal is sent to high-frequency switches 1 and 2 at the same time; 4) The high-frequency switch 3 selects the 3db attenuator according to the high-frequency signal; the high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-frequency signal; 5) The numerically controlled attenuator is a constant value; 6) The digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

4. The method for optimizing the startup of a cyclotron based on a continuous closed-loop mode according to claim 3, characterized in that: The digital controller of process 6) starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities. The specific steps are as follows: 1) When the two cavities of the accelerator are capacitively coupled, the ratio of the voltage imbalance between the two cavities due to processing design factors is shown in the following formula [1]: Wherein, C12 is the coupling capacitance value between the two groups of cavities, which is divided into two parts, C12" and C12', where C12" is the capacitance of the D1 cavity and C12' is the capacitance of the D2 cavity; 2) The D voltage can be adjusted by changing the ratio of C12” and C12', and its balance control algorithm is as follows: the phase detector output result Tphase determines the movement frequency of the capacitor motor, and the motor movement step setting value Dsteps determines the movement steps of the motor; when Dsteps>0, Tphase>0, the motor of the D1 cavity group moves in the positive direction at 2 times the speed, and the motor of the D2 cavity group stops; when Dsteps>0, Tphase<0, the motor of the D2 cavity group moves in the reverse direction at 2 times the speed, and the motor of the D1 cavity group does not move; when Dsteps<0, TPhase>0, the motor of the D2 cavity group moves in the positive direction at twice the speed, and the motor of the D1 cavity group does not move; when Dsteps<0, TPhase<0, the motor of the D1 cavity group moves in the reverse direction at twice the speed, and the motor of the D2 cavity group does not move.

5. The method for optimizing the startup of a cyclotron based on a continuous closed-loop mode according to claim 1, characterized in that: The closed-loop tuning of step 2 and step 3 is implemented by the PID tuning algorithm unit of the digital controller as follows: 1) The digital PID algorithm is expressed as: y(n)=y(n-1)+K0x(n)+K1x(n-1)+K2(n-2); Where y(n) is the PID operation output, y(n-1) is the PID operation output at the previous moment, K0, K1, and K2 are PID adjustment coefficients, and x(n), x(n-1), and x(n-2) are the PID inputs at the current moment, the previous moment, and the previous two moments; 2) Use R0 and R3 registers in the DSP's X memory, and read and write operations are performed by the global data bus; 3) Store the PID inputs x(n), x(n-1) and x(n-2) of the current moment, the previous moment and the previous two moments into register R0, and store k0, k1, k2 into register R3; 4) Use the global bus to read and write these two registers and use the accumulator and multiplication function in the DSP to implement y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

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