A power energy monitoring and control circuit system for each power output port of a PDU device

Abstract

The present invention discloses an electric energy monitoring and control circuit system for each power output port of a PDU device, including a first step-down and voltage stabilization circuit unit, and the first step-down and voltage stabilization circuit unit outputs a first power supply; a second step-down and voltage stabilization circuit unit, and the second step-down and voltage stabilization circuit unit outputs a second power supply; a microprocessor, and the microprocessor can be electrically connected to a computer, a memory, and an external terminal device; a power supply and digital signal isolation circuit, and the first power supply output by the first step-down and voltage stabilization circuit unit is simultaneously electrically connected to the power supply and digital signal isolation circuit and the microprocessor, and the second power supply output by the second step-down and voltage stabilization circuit unit is electrically connected to a bus circuit in the power supply and digital signal isolation circuit; a main circuit metering module, and the main circuit metering module is electrically connected to the second power supply on the power supply and digital signal isolation circuit; a branch circuit metering module, and the branch circuit metering module is electrically connected to the second power supply on the power supply and digital signal isolation circuit and the main circuit metering module.

Description

Technical Field

[0001] The present invention relates to the technical field of PDU device monitoring, and particularly to an electric energy monitoring and control circuit system for each power output port of a PDU device. Background Art

[0002] Power Distribution Unit: The power distribution unit, that is, the power distribution socket for cabinets that we often mention, is the last control checkpoint for the power consumption of all digital devices in the computer room. If it is not stable enough and lacks sufficient protection functions, it may cause expensive digital devices to be damaged or even the entire digital system to collapse. The application of PDU can not only make the power distribution in the digital cabinet more tidy, reliable, safe, professional and beautiful, but also make the maintenance of the power supply in the digital cabinet more convenient and reliable.

[0003] With the development of computer network technology in China, the demand for key devices such as servers, switches, and various electronic devices has increased day by day, and the requirements for the environment where the devices are located (such as computer rooms, cabinets, etc.) are also higher. The business undertaken by PDU is becoming more and more critical, and the detection and control functions that need to be compatible are also increasing.

[0004] Among them, the requirements for functions such as monitoring, metering, and protection control of the electrical parameters of each power output port (socket) are particularly prominent. These power consumption information needs to be collected and transmitted stably and reliably, so that the background centers of computer rooms, sites, and on-site operation and maintenance operators can timely and effectively obtain the power consumption information and status of each power socket of the PDU. At the same time, by comparing and analyzing the collected historical data, the background center can realize environmental impact monitoring of the power consumption of lower-level power-consuming devices, timely discover problems, solve problems, and stably and effectively maintain the stable operation of the power-consuming devices in the digital computer room and site.

[0005] In the actual application of current PDU, the design of the acquisition and control links of each power output end mostly uses expensive imported core main control chips. Its high-speed computing power and the collaborative control capabilities of multi-threading and multi-interfaces are indeed excellent. However, its method of overly centralized acquisition, operation, and analysis and processing of the power consumption information of multiple sockets not only requires the efficient cooperation of a sampling circuit with high performance, a multi-stage filtering circuit, and a hierarchical protection circuit, but also requires the line laying design of its sampling network to have an efficient EMC protection design against interference.

[0006] In view of this, it is necessary to provide a new electric energy monitoring and control circuit system for each power output port of a PDU device to overcome the above defects. Summary of the Invention

[0007] The object of the present invention is to provide an electric energy monitoring and control circuit system for each power output port of a PDU device to solve the above-mentioned defects.

[0008] To achieve the above object, the present invention provides an electric energy monitoring and control circuit system for each power output port of a PDU device, including a first step-down and voltage stabilization circuit unit, and the first step-down and voltage stabilization circuit unit outputs a first power supply;

[0009] A second step-down and voltage stabilization circuit unit, and the second step-down and voltage stabilization circuit unit outputs a second power supply;

[0010] A microprocessor, and the microprocessor can be electrically connected to a computer, a memory, and an external terminal device;

[0011] A power supply and digital signal isolation circuit, the first power supply output by the first step-down and voltage stabilization circuit unit is simultaneously electrically connected to the power supply and digital signal isolation circuit and the microprocessor, and the second power supply output by the second step-down and voltage stabilization circuit unit is electrically connected to a bus circuit in the power supply and digital signal isolation circuit;

[0012] A main circuit metering module, and the main circuit metering module is electrically connected to the second power supply on the power supply and digital signal isolation circuit;

[0013] A branch circuit metering module, and the branch circuit metering module is electrically connected to the second power supply on the power supply and digital signal isolation circuit and the main circuit metering module.

[0014] Preferably, the first step-down and voltage stabilization circuit unit includes a capacitor C32, a resistor R14, a power management chip WD1, a resistor R13, a capacitor C3, an inductor L2, a capacitor C33, a capacitor C34, a resistor R16, a resistor R15, and a resistor R17;

[0015] The first end of the capacitor C32 is connected to a DC-12V power supply, the second end of the capacitor C32 is grounded, the first end of the resistor R14 is electrically connected to the first end of the capacitor C32 and the VIN pin of the power management chip WD1, the second end of the resistor R14 is electrically connected to the EN pin of the power management chip WD1, and the BST pin of the power management chip WD1 is electrically connected to the first end of the resistor R13,

[0016] The second end of the resistor R13 is electrically connected to the first end of the capacitor C3, the second end of the capacitor C3 is electrically connected to the first end of the inductor L2 and the SW pin of the power management chip WD1, the second end of the inductor L2 is electrically connected to the first end of the capacitor C33, and the second end of the capacitor C33 is grounded,

[0017] The first end of the capacitor C34 is electrically connected to the first end of the resistor R16 and the FB pin of the power management chip WD1. The second end of the resistor R16 is electrically connected to the first end of the resistor R15 and the first end of the resistor R17. The first end of the resistor R15 is also electrically connected to the microprocessor. The second end of the resistor R15 is electrically connected to the second end of the inductor L2. The second end of the resistor R17 is electrically connected to the second end of the capacitor C33.

[0018] Preferably, the power supply and digital signal isolation circuit includes a resistor RS3, a resistor RS2, an isolator, a serial communication chip U5, a transistor Q6, a resistor RS5, a resistor RS6, and a bidirectional TVS diode. The resistor RS3 is electrically connected to the microprocessor and the VIB pin of the isolator. The resistor RS2 is electrically connected to the microprocessor and the VOA pin of the isolator. The VDD1 of the isolator is grounded through a capacitor CS5, and a first power supply output by the first step-down and voltage regulation circuit unit is electrically connected to the capacitor CS5. The VDD2 of the isolator is grounded through a capacitor CS6, and the capacitor CS6 is electrically connected to a second power supply output by the second step-down and voltage regulation circuit unit. The GND1 pin of the isolator is connected to the power ground of the first power supply. The GND2 pin of the isolator is connected to the power ground of the second power supply. The VIA pin of the isolator is electrically connected to the R pin of the serial communication chip U5. The VOB pin of the isolator is electrically connected to the D pin of the serial communication chip U5.

[0019] The / RE pin and the DE pin of the serial communication chip U5 are electrically connected to the collector of the transistor Q6. The collector of the transistor Q6 is grounded through a resistor RS8. The D pin of the serial communication chip U5 is electrically connected to the base of the transistor Q6 through a resistor RS7. The emitter of the transistor Q6 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit.

[0020] The VCC pin of the serial communication chip U5 is electrically connected to the first end of the resistor RS5 and the second power supply output by the second step-down and voltage regulation circuit unit. The second end of the resistor RS5 is electrically connected to the A pin of the serial communication chip U5. The B pin of the serial communication chip U5 is electrically connected to the first end of the resistor RS6. The second end of the resistor RS6 is electrically connected to the GND pin of the serial communication chip U5 and grounded. The first pole of the bidirectional TVS diode is electrically connected to the second end of the resistor RS5. The second pole of the bidirectional TVS diode is electrically connected to the first end of the resistor RS6.

[0021] Preferably, the power monitoring and control circuit system for each power output port of the PDU device further includes a second step-down and voltage stabilization circuit unit, and the second step-down and voltage stabilization circuit unit includes a capacitor C16, a power management chip U5, a capacitor C17, a Schottky diode D2, an inductor L1, a capacitor C18, a capacitor EC1, a resistor R32, a resistor R33, a resistor R34, and a resistor R35.

[0022] The first end of the capacitor C16 is connected to the DC-12V power supply, the second end of the capacitor C16 is grounded, the VCC pin of the power management chip U5 is electrically connected to the first end of the capacitor C16 and the first end of the resistor R32, the second end of the resistor R32 is electrically connected to the first end of the resistor R33, the second end of the resistor R33 is grounded, the BST pin of the power management chip U5 is electrically connected to the first end of the capacitor C17, the second end of the capacitor C17 is electrically connected to the LX pin of the power management chip, the cathode of the Schottky diode D2, and the first end of the inductor L1, the anode of the Schottky diode D2 is electrically connected to the first end of the capacitor C18, the second end of the capacitor C18 is electrically connected to the second end of the inductor L1, the first end of the resistor R35, and the first end of the capacitor EC1, the second end of the resistor R35 is electrically connected to the first end of the resistor R34 and the FB pin of the power management chip, the second end of the resistor R34 is electrically connected to the first end of the resistor R33 and grounded, the second end of the resistor R33 is electrically connected to the EN pin of the power management chip and the first end of the resistor R32, the second end of the resistor R32 is electrically connected to the first end of the capacitor C16, and the capacitor EC1 outputs a second power supply.

[0023] Preferably, the total circuit metering module includes a total circuit communication circuit unit, a memory circuit unit, a total circuit voltage sampling unit, a total circuit current sampling unit, a total circuit metering pulse opto-isolation circuit unit, and an SOC chip 0U1. The total circuit communication circuit unit is electrically connected to the power supply and digital signal isolation circuit, and the total circuit communication circuit unit, the memory circuit unit, the total circuit voltage sampling unit, the total circuit current sampling unit, and the total circuit metering pulse opto-isolation circuit unit are electrically connected to the SOC chip 0U1.

[0024] Preferably, the total circuit communication circuit unit includes a serial communication chip 0U3, a capacitor 0C14, a resistor 0R17, a resistor 0R18, and a transistor 0Q2; the VCC pin of the serial communication chip 0U3 is electrically connected to the capacitor 0C14 and grounded, the capacitor 0C14 is electrically connected to the second power supply output by the second step-down and voltage stabilization circuit unit, the A pin of the serial communication chip 0U3 is electrically connected to the second end of the resistor RS5, the B pin of the serial communication chip 0U3 is electrically connected to the first end of the resistor RS6, the first end of the resistor 0R17 is electrically connected to the second power supply output by the second step-down and voltage stabilization circuit unit, the second end of the resistor 0R17 is electrically connected to the R pin of the serial communication chip 0U3 and the SOC chip 0U1, the first end of the resistor 0R18 is electrically connected to the second power supply output by the second step-down and voltage stabilization circuit unit, and the second end of the resistor 0R18 is electrically connected to the D pin of the serial communication chip 0U3;

[0025] The / RE pin and the DE pin of the serial communication chip 0U3 are both electrically connected to the emitter of the transistor 0Q2, the emitter of the transistor 0Q2 is grounded through the resistor 0R20, the collector of the transistor 0Q2 is electrically connected to the second power supply output by the second step-down and voltage stabilization circuit unit, and the base of the transistor 0Q2 is electrically connected to the SOC chip 0U1 through the resistor 0R19.

[0026] Preferably, the memory circuit unit further includes a resistor 0R14, a resistor 0R16, and a memory 0U2; the first ends of the resistor 0R14 and the resistor 0R16 are electrically connected, and the first ends of the resistor 0R14 and the resistor 0R16 are connected to the second power supply output by the second step-down and voltage stabilization circuit unit, the second end of the resistor 0R14 is electrically connected to the memory and the SOC chip 0U1, the second end of the resistor 0R16 is electrically connected to the memory 0U2 and the SOC chip 0U1, and the memory 0U2 is grounded.

[0027] Preferably, the total circuit voltage sampling unit includes a capacitor 0C1, a resistor 0R1, a resistor 0R2, a resistor 0R3, a resistor 0R4, a resistor 0R5, a resistor 0R6, and a resistor 0R7; the first end of the capacitor 0C1 is electrically connected to the SOC chip 0U1, the second end of the capacitor 0C1 is electrically connected to the first end of the resistor 0R7, the second end of the resistor 0R7 is electrically connected to the first end of the resistor 0R6 and the first end of the capacitor 0C1, and the second end of the resistor 0R6 is electrically connected to the resistors 0R5, 0R4, 0R3, 0R2, and 0R1 in sequence.

[0028] Preferably, the total circuit current sampling unit includes capacitor 0C8, capacitor 0C2, capacitor 0C3, resistor 0R8, resistor 0R9, resistor 0R21, resistor 0R15, and current transformer CT0; the first end of capacitor 0C8 is electrically connected to the SOC chip 0U1, the second end of capacitor 0C8 is electrically connected to the first end of resistor 0R9, the second end of resistor 0R9 is electrically connected to the first end of resistor R15 and current transformer CT0, the second end of resistor R15 is electrically connected to the first end of resistor 0R21, the second end of resistor 0R21 is electrically connected to current transformer CT0, the first end of capacitor 0C2 is electrically connected to the first end of capacitor 0C8, the second end of capacitor 0C2 is electrically connected to the first end of capacitor 0C3, the second end of capacitor 0C3 is electrically connected to the first end of resistor 0R9, the first end of resistor 0R8 is electrically connected to the first end of capacitor 0C2, and the first end of resistor 0R21 is electrically connected to the second end of capacitor 0C2 and connected to the power ground of the second power supply.

[0029] Preferably, the total circuit metering pulse opto-isolation circuit unit includes resistor 0R34, opto-isolator 0E3, pulse signal indicator 0LED1, and resistor 0R36; the first end of resistor 0R34 is electrically connected to the SOC chip 0U1, the second end of resistor 0R34 is electrically connected to the light-emitting end of opto-isolator 0E3, the light-receiving end of opto-isolator 0E3 is electrically connected to pulse signal indicator 0LED1, pulse signal indicator 0LED1 is electrically connected to resistor 0R36, and resistor 0R36 is connected to the power supply.

[0030] Compared with the prior art, the beneficial effects are as follows: 1) Each output port of the socket of each power supply of the PDU device has an independent shunt metering module for independent metering and output control. All shunt metering modules can independently complete core functions such as sampling of various electrical parameters, cumulative settlement of electric energy, storage of relevant data, and serial communication; and the shunt metering module and the total circuit metering module communicate and transmit data or control instructions with the microprocessor, and then display the collected data or transmit it to the upper-level management and control platform through the human-machine interface of the external terminal device or the external communication port for use.

[0031] The metering module uses low-cost and simple voltage and current sampling devices or circuit networks to very efficiently complete the metering and acquisition tasks of the electric energy meter. Based on the advantages of the above-mentioned device selection, its manufacturing cost and production cost have been greatly reduced, directly improving the performance-price ratio of the PDU device and facilitating market application and promotion. Description of the Drawings

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0033] Figure 1 It is a schematic diagram of the power monitoring and control circuit system for each power output port of the PDU device provided by the present invention.

[0034] Figure 2 It is a circuit diagram of the first step-down and voltage stabilization circuit unit.

[0035] Figure 3 It is a circuit diagram of the second step-down and voltage stabilization circuit unit.

[0036] Figure 4 It is a circuit diagram of the power supply and digital signal isolation circuit.

[0037] Figure 5 It is a circuit diagram of the main loop communication circuit unit.

[0038] Figure 6 It is a circuit diagram of the memory circuit unit.

[0039] Figure 7 It is a circuit diagram of the main loop voltage sampling unit.

[0040] Figure 8 It is a circuit diagram of the main loop current sampling unit.

[0041] Figure 9 It is a circuit diagram of the main loop metering pulse optoelectronic isolation circuit unit.

[0042] Figure 10 It is a circuit diagram of the first branch loop communication circuit unit.

[0043] Figure 11 It is a circuit diagram of the first branch loop memory circuit unit.

[0044] Figure 12 It is a circuit diagram of the first branch loop voltage sampling unit.

[0045] Figure 13 It is a circuit diagram of the first branch loop current sampling unit.

[0046] Figure 14 It is a circuit diagram of the first branch loop metering pulse optoelectronic isolation circuit unit.

[0047] Figure 15 It is a circuit diagram of the first relay control and drive circuit unit.

[0048] Figure 16 It is the circuit diagram of the photoelectric isolation circuit unit for the metering pulse of the first sub-circuit.

[0049] Reference numerals: 1. The first step-down and voltage stabilization circuit unit; 2. The microprocessor; 3. The power supply and digital signal isolation circuit; 4. The total amount metering module; 41. The total circuit communication circuit unit; 42. The memory circuit unit; 43. The total circuit voltage sampling unit; 44. The total circuit current sampling unit; 45. The total circuit metering pulse photoelectric isolation circuit unit; 5. The branch metering module; 51. The first branch circuit communication circuit unit; 52. The first branch circuit memory circuit unit; 53. The first branch circuit voltage sampling unit; 54. The first branch circuit current sampling unit; 55. The first branch circuit metering pulse photoelectric isolation circuit unit; 56. The first branch circuit relay control and drive circuit unit; 57. The first branch circuit relay photoelectric isolation detection circuit unit. Specific embodiments

[0050] In order to make the purpose, technical solutions and beneficial technical effects of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described in this specification are only for explaining the present invention and not for limiting the present invention.

[0051] It should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0052] It should also be noted that unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection", "fixation", "setting" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be determined according to specific circumstances.

[0053] In addition, the terms "left" and "right" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In addition, the meanings of "a plurality" and "several" refer to two or more, unless otherwise specifically defined.

[0054] Please refer to Figures 1 to 2 , the present invention provides an electric energy monitoring and control circuit system for each power output port of a PDU device, including a first step-down and voltage-regulating circuit unit, and the first step-down and voltage-regulating circuit unit outputs a first power supply (3.3V);

[0055] a second step-down and voltage-regulating circuit unit, and the second step-down and voltage-regulating circuit unit outputs a second power supply (3.3V);

[0056] a microprocessor 2, and the microprocessor 2 can be electrically connected to a computer, a memory, and an external terminal device;

[0057] a power supply and digital signal isolation circuit 3, the first power supply output by the first step-down and voltage-regulating circuit unit is simultaneously electrically connected to the power supply and digital signal isolation circuit 3 and the microprocessor 2, and the second power supply output by the second step-down and voltage-regulating circuit unit is electrically connected to a bus circuit in the power supply and digital signal isolation circuit 3;

[0058] a main circuit metering module 4, and the main circuit metering module 4 is electrically connected to the second power supply on the power supply and digital signal isolation circuit 3;

[0059] a branch circuit metering module 5, and the branch circuit metering module 5 is electrically connected to the second power supply on the power supply and digital signal isolation circuit 3 and the main circuit metering module 4.

[0060] Further, the first step-down and voltage-regulating circuit unit 1 includes a capacitor C32, a resistor R14, a power management chip WD1 (MP1652), a resistor R13, a capacitor C3, an inductor L2, a capacitor C33, a capacitor C34, a resistor R16, a resistor R15, and a resistor R17;

[0061] The first end of the capacitor C32 is connected to a DC-12V power supply, the second end of the capacitor C32 is grounded, the first end of the resistor R14 is electrically connected to the first end of the capacitor C32 and the VIN pin of the power management chip WD1, the second end of the resistor R14 is electrically connected to the EN pin of the power management chip WD1, and the BST pin of the power management chip WD1 is electrically connected to the first end of the resistor R13,

[0062] The second end of the resistor R13 is electrically connected to the first end of the capacitor C3. The second end of the capacitor C3 is electrically connected to the first end of the inductor L2 and the SW pin of the power management chip WD1. The second end of the inductor L2 is electrically connected to the first end of the capacitor C33. The second end of the capacitor C33 is grounded.

[0063] The first end of the capacitor C34 is electrically connected to the first end of the resistor R16 and the FB pin of the power management chip WD1. The second end of the resistor R16 is electrically connected to the first ends of the resistor R15 and the resistor R17. The first end of the resistor R15 is also electrically connected to the microprocessor 2. The second end of the resistor R15 is electrically connected to the second end of the inductor L2. The second end of the resistor R17 is electrically connected to the second end of the capacitor C33.

[0064] It should be noted that the maximum output current of the power management chip WD1 can reach 2000 mA. It has an internal reference voltage pump, and the reference voltage of the reference voltage pump is Vref = 0.807 V. When the feedback voltage signal at the output end of the power management chip WD1 is obtained through the resistors R15 and R17 and acts together with the reference voltage Vref, the regulated voltage value output V0ut of the power management chip WD1 is obtained. The calculation method of the regulated voltage value output V0ut of the power management chip WD1 is as follows:

[0065]

[0066] The power management chip WD1 also has an enable switch EN pin. The resistor R14 connected to the enable switch EN pin can control whether the internal circuit of the power management chip WD1 works properly. When the voltage at the EN pin of the power management chip WD1 is pulled up to more than 2.8 V, the power management chip WD1 can work. When the voltage at the EN pin is pulled down to less than 1.1 V, the power management chip WD1 stops working.

[0067] Please refer to Figures 3 to 16 further, the power monitoring and control circuit system for each power output port of the PDU device further includes a second step-down and voltage regulation circuit unit. The second step-down and voltage regulation circuit unit includes a capacitor C16, a power management chip U5 (BD9677), a capacitor C17, a Schottky diode D2, an inductor L1, a capacitor C18, a capacitor EC1, a resistor R32, a resistor R33, a resistor R34, and a resistor R35.

[0068] The first end of the capacitor C16 is connected to the DC - 12V power supply, the second end of the capacitor C16 is grounded, the VCC pin of the power management chip U5 is electrically connected to the first end of the capacitor C16 and the first end of the resistor R32, the second end of the resistor R32 is electrically connected to the first end of the resistor R33, the second end of the resistor R33 is grounded, the BST pin of the power management chip U5 is electrically connected to the first end of the capacitor C17, the second end of the capacitor C17 is electrically connected to the LX pin of the power management chip, the cathode of the Schottky diode D2, and the first end of the inductor L1, the anode of the Schottky diode D2 is electrically connected to the first end of the capacitor C18, the second end of the capacitor C18 is electrically connected to the second end of the inductor L1, the first end of the resistor R35, and the first end of the capacitor EC1, the second end of the resistor R35 is electrically connected to the first end of the resistor R34 and the FB pin of the power management chip, the second end of the resistor R34 is electrically connected to the first end of the resistor R33 and grounded, the second end of the resistor R33 is electrically connected to the EN pin of the power management chip and the first end of the resistor R32, the second end of the resistor R32 is electrically connected to the first end of the capacitor C16, and the capacitor EC1 outputs a second power supply of 3.3V.

[0069] The body of the power management chip U5 is relatively small (its size: 3.0mm×2.8mm×1.2mm). The maximum output current of the power management chip U5 can reach 500mA, and there is a reference voltage pump inside the chip. The reference voltage of the reference voltage pump is Vref = 0.75V. When the feedback voltage signal at the output end is obtained through the voltage - dividing sampling circuit composed of the resistors R34 and R35 and acts together with the reference voltage Vref, the regulated voltage value output V0ut of the power management chip U5 is obtained. The calculation method of the regulated voltage output V0ut of the power management chip U5 is as follows:

[0070]

[0071] The power management chip U5 also has an enable switch pin EN, which can control whether the internal circuit works properly. After power - on, the divided voltage level of the resistors R32 and R33 is connected to the EN pin. And only when the input level of the EN pin is greater than 1.8V, the power management chip U5 can work, otherwise it will stop working.

[0072] Further, the power supply and digital signal isolation circuit 3 includes a resistor RS3, a resistor RS2, an isolator U4, a serial communication chip U5, a transistor Q6, a resistor RS5, a resistor RS6, and a bidirectional TVS diode; the resistor RS3 is electrically connected to the microprocessor 2 and the VIB pin of the isolator U4, the resistor RS2 is electrically connected to the microprocessor 2 and the VOA pin of the isolator U4, the VDD1 of the isolator U4 is grounded through a capacitor CS5, a 3.3V first power supply is electrically connected to the capacitor CS5, the VDD2 of the isolator U4 is grounded through a capacitor CS6, the capacitor CS6 is electrically connected to a 3.3V second power supply output by the second step-down and voltage regulation circuit unit, the GND1 pin of the isolator U4 is connected to the power ground of the first power supply, the GND2 pin of the isolator U4 is connected to the power ground of the second power supply, the VIA pin of the isolator U4 is electrically connected to the R pin of the serial communication chip U5, and the VOB pin of the isolator U4 is electrically connected to the D pin of the serial communication chip U5;

[0073] The / RE pin and the DE pin of the serial communication chip U5 are electrically connected to the collector of the transistor Q6, the collector of the transistor Q6 is grounded through a resistor RS8, the D pin of the serial communication chip U5 is electrically connected to the base of the transistor Q6 through a resistor RS7, and the emitter of the transistor Q6 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit;

[0074] The VCC pin of the serial communication chip U5 is electrically connected to the first end of the resistor RS5 and the second power supply output by the second step-down and voltage regulation circuit unit, the second end of the resistor RS5 is electrically connected to the A pin of the serial communication chip U5, the B pin of the serial communication chip U5 is electrically connected to the first end of the resistor RS6, the second end of the resistor RS6 is electrically connected to the GND pin of the serial communication chip U5 and grounded, the first pole of the bidirectional TVS diode is electrically connected to the second end of the resistor RS5, and the second pole of the bidirectional TVS diode is electrically connected to the first end of the resistor RS6.

[0075] Further, the total circuit metering module 4 includes a total loop communication circuit unit 41, a memory circuit unit 42, a total loop voltage sampling unit 43, a total loop current sampling unit 44, a total loop metering pulse opto-isolation circuit unit 45, and an SOC chip 0U1 (V9821S). The total loop communication circuit unit 41 is electrically connected to the power supply and digital signal isolation circuit 3, and the total loop communication circuit unit 41, the memory circuit unit 42, the total loop voltage sampling unit 43, the total loop current sampling unit 44, and the total loop metering pulse opto-isolation circuit unit 45 are electrically connected to the SOC chip 0U1.

[0076] Specifically, the total circuit communication circuit unit 41 includes a serial communication chip 0U3 (MAX3085), a capacitor 0C14, a resistor 0R17, a resistor 0R18, and a transistor 0Q2; the VCC pin of the serial communication chip 0U3 is electrically connected to the capacitor 0C14 and grounded, the capacitor 0C14 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, the A pin of the serial communication chip 0U3 is electrically connected to the second end of the resistor RS5, the B pin of the serial communication chip 0U3 is electrically connected to the first end of the resistor RS6, the first end of the resistor 0R17 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, the second end of the resistor 0R17 is electrically connected to the R pin of the serial communication chip 0U3 and the SOC chip 0U1, the first end of the resistor 0R18 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, and the second end of the resistor 0R18 is electrically connected to the D pin of the serial communication chip 0U3;

[0077] The / RE pin and the DE pin of the serial communication chip 0U3 are both electrically connected to the emitter of the transistor 0Q2, the emitter of the transistor 0Q2 is grounded through the resistor 0R20, the collector of the transistor 0Q2 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, and the base of the transistor 0Q2 is electrically connected to the SOC chip 0U1 through the resistor 0R19.

[0078] Specifically, the memory circuit unit 42 further includes a resistor 0R14, a resistor 0R16, and a memory 0U2; the first ends of the resistor 0R14 and the resistor 0R16 are electrically connected, and the first ends of the resistor 0R14 and the resistor 0R16 are connected to the second power supply output by the second step-down and voltage regulation circuit unit, the second end of the resistor 0R14 is electrically connected to the memory and the SOC chip 0U1, the second end of the resistor 0R16 is electrically connected to the memory 0U2 and the SOC chip 0U1, and the memory 0U2 is grounded.

[0079] Specifically, the total circuit voltage sampling unit 43 includes capacitor 0C1, resistor 0R1, resistor 0R2, resistor 0R3, resistor 0R4, resistor 0R5, resistor 0R6, and resistor 0R7; the first end of capacitor 0C1 is electrically connected to the SOC chip 0U1, the second end of capacitor 0C1 is electrically connected to the first end of resistor 0R7, the second end of resistor 0R7 is electrically connected to the first end of resistor 0R6 and the first end of capacitor 0C1, the second end of resistor 0R6 is sequentially electrically connected to resistor 0R5, resistor 0R4, resistor 0R3, resistor 0R2, and resistor 0R1. Resistor 0R1 is used to connect to the neutral line of the mains AC power supply, and the first end of resistor 0R7 is used to connect to the live wire of the mains AC power supply and is connected to the power ground of the second power supply. In this way, it is convenient to implement voltage sampling of the mains AC power supply.

[0080] Specifically, the total circuit current sampling unit 44 includes capacitor 0C8, capacitor 0C2, capacitor 0C3, resistor 0R8, resistor 0R9, resistor 0R21, resistor 0R15, and current transformer CT0; the first end of capacitor 0C8 is electrically connected to the SOC chip 0U1, the second end of capacitor 0C8 is electrically connected to the first end of resistor 0R9, the second end of resistor 0R9 is electrically connected to the first end of resistor R15 and current transformer CT0, the second end of resistor R15 is electrically connected to the first end of resistor 0R21, the second end of resistor 0R21 is electrically connected to current transformer CT0, the first end of capacitor 0C2 is electrically connected to the first end of capacitor 0C8, the second end of capacitor 0C2 is electrically connected to the first end of capacitor 0C3, the second end of capacitor 0C3 is electrically connected to the first end of resistor 0R9, the first end of resistor 0R8 is electrically connected to the first end of capacitor 0C2, and the first end of resistor 0R21 is electrically connected to the second end of capacitor 0C2 and is connected to the power ground of the second power supply. The current transformer CT0 can be connected to the mains AC power supply, facilitating current sampling of the mains AC power supply.

[0081] Specifically, the total circuit metering pulse opto - isolation circuit unit 45 includes resistor 0R34, opto - isolator 0E3, pulse signal indicator 0LED1, and resistor 0R36; the first end of resistor 0R34 is electrically connected to the SOC chip 0U1, the second end of resistor 0R34 is electrically connected to the light - emitting end (light - emitting diode) of the opto - isolator 0E3, the light - receiving end (photoresistive semiconductor tube) of the opto - isolator 0E3 is electrically connected to the pulse signal indicator 0LED1 (light - emitting diode), the pulse signal indicator 0LED1 is electrically connected to resistor 0R36, and resistor 0R36 is connected to the power supply.

[0082] Further, the shunt metering module 5 includes a first branch circuit communication circuit unit 51, a first branch circuit memory circuit unit 52, a first branch circuit voltage sampling unit 53, a first branch circuit current sampling unit 54, a first branch circuit metering pulse opto-isolation circuit unit 55, a first relay control and drive circuit unit 56, a first branch circuit relay opto-isolation detection circuit unit 57, and an SOC chip 1U1 (V9821S). The first branch circuit communication circuit unit 51 is electrically connected to the power supply and digital signal isolation circuit 3, and the first branch circuit communication circuit unit 51, the first branch circuit memory circuit unit 52, the first branch circuit voltage sampling unit 53, the first branch circuit current sampling unit 54, the first branch circuit metering pulse opto-isolation circuit unit 55, the first relay control and drive circuit unit 56, and the first branch circuit relay opto-isolation detection circuit unit 57 are electrically connected to the SOC chip 1U1.

[0083] Specifically, the first branch circuit communication circuit unit 51 includes a serial communication chip 1U3 (MAX3085), a capacitor 1C14, a resistor 1R17, a resistor 1R18, and a transistor 1Q2. The VCC pin of the serial communication chip 1U3 is electrically connected to and grounded by the capacitor 1C14, and the capacitor 1C14 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit. The A pin of the serial communication chip 1U3 is electrically connected to the A pin of the serial communication chip 0U3, and the B pin of the serial communication chip 1U3 is electrically connected to the B pin of the serial communication chip 0U3. The first end of the resistor 1R17 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, the second end of the resistor 1R17 is electrically connected to the R pin of the serial communication chip 1U3 and the SOC chip 1U1, the first end of the resistor 1R18 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, and the second end of the resistor 1R18 is electrically connected to the D pin of the serial communication chip 1U3.

[0084] The / RE pin and the DE pin of the serial communication chip 1U3 are both electrically connected to the emitter of the transistor 1Q2. The emitter of the transistor 1Q2 is grounded through a resistor 1R20, the collector of the transistor 1Q2 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, and the base of the transistor 1Q2 is electrically connected to the SOC chip 1U1 through a resistor 1R19.

[0085] Specifically, the first sub-circuit memory circuit unit 52 further includes a resistor 1R14, a resistor 1R16, and a memory 1U2; the first ends of the resistor 1R14 and the resistor 1R16 are electrically connected, and the first ends of the resistor 1R14 and the resistor 1R16 are connected to the second power supply output by the second step-down and voltage regulation circuit unit. The second end of the resistor 1R14 is electrically connected to the memory 1U2 and the SOC chip 1U1. The second end of the resistor 1R16 is electrically connected to the memory and the SOC chip 1U1, and the memory 1U2 is grounded.

[0086] Specifically, the first sub-circuit voltage sampling unit 53 includes a capacitor 1C1, resistors 1R1, 1R2, 1R3, 1R4, 1R5, 1R6, and 1R7; the first end of the capacitor 1C1 is electrically connected to the SOC chip 1U1, the second end of the capacitor 1C1 is electrically connected to the first end of the resistor 1R7, the second end of the resistor 1R7 is electrically connected to the first end of the resistor 1R6 and the first end of the capacitor 1C1, the second end of the resistor 1R6 is sequentially electrically connected to the resistors 1R5, 1R4, 1R3, 1R2, and 1R1. The resistor 1R1 is used to connect to the neutral line of the mains AC power supply, and the first end of the resistor 1R7 is used to connect to the live wire of the mains AC power supply and is connected to the power ground of the second power supply. In this way, it is convenient to implement voltage sampling of the mains AC power supply.

[0087] Specifically, the first sub-circuit current sampling unit 54 includes a capacitor 1C8, capacitors 1C2 and 1C3, resistors 1R8 and 1R9, a manganin shunt 1R10, a relay Kn, and a socket; the first end of the capacitor 1C8 is electrically connected to the SOC chip 1U1, the second end of the capacitor 1C8 is electrically connected to the first end of the resistor 1R9, the second end of the resistor 1R9 is electrically connected to the first end of the manganin shunt 1R10 and is grounded, the second end of the manganin shunt 1R10 is electrically connected to the relay Kn, the relay Kn is electrically connected to the socket, the first end of the capacitor 1C2 is electrically connected to the first end of the capacitor 1C8 and the first end of the resistor 1R8, the second end of the capacitor 1C2 is electrically connected to the first end of the capacitor 1C3, the second end of the capacitor 1C3 is electrically connected to the first end of the resistor 1R9, and the second end of the resistor 1R8 is electrically connected to the relay Kn. Through the socket and the manganin shunt 1R10, it can be connected to the mains AC power supply, facilitating current sampling of the mains AC power supply.

[0088] Specifically, the first sub-circuit metering pulse opto-isolation circuit unit 55 includes resistor 1R34, opto-isolator 1E3, pulse signal indicator light 1LED1, and resistor 1R36; the first end of resistor 1R34 is electrically connected to the SOC chip 1U1, the second end of resistor 1R34 is electrically connected to the light-emitting end (light-emitting diode) of opto-isolator 1E3, the light-receiving end (photosensitive semiconductor tube) of opto-isolator 1E3 is electrically connected to the pulse signal indicator light 1LED1 (light-emitting diode), the pulse signal indicator light 1LED1 is electrically connected to resistor 1R36, and resistor 1R36 is connected to the power supply.

[0089] Specifically, the first sub-circuit relay control and drive circuit unit 56 includes resistor 1R32, transistor 1Q1, diode 1D2, resistor 1R31, and relay K1; the first end of resistor 1R32 is electrically connected to the SOC chip 1U1, the second end of resistor 1R32 is electrically connected to the base of transistor 1Q1, the emitter of transistor 1Q1 is grounded, the collector of transistor 1Q1 is electrically connected to the anode of diode 1D2, the anode of diode 1D2 is electrically connected to relay K1, the cathode of diode 1D2 is electrically connected to resistor 1R31 and relay K1, resistor 1R31 is connected to the DC-12V power supply, and relay K1 is used to be electrically connected to the manganese copper shunt 1R10 and the live wire on the socket.

[0090] Specifically, the first sub-circuit relay opto-isolation detection circuit unit 57 includes diode 1D3, opto-isolator 1E2, opto-isolator 1E1, indicator lights 1LED3, 1LED2, resistor 1R26, resistor 1R24, and resistor 1R25; the anode of diode 1D3 is electrically connected to relay K1 and the light-emitting end (light-emitting diode) of opto-isolator 1E2, and the cathode of diode 1D3 can be connected to the light-emitting end of opto-isolator 1E2 and the neutral wire of the AC power supply through resistors 1R28, 1R29, and 1R30.

[0091] The light-receiving end (photosensitive semiconductor tube) of opto-isolator 1E2 is electrically connected to the light-emitting end (light-emitting diode) of opto-isolator 1E1 and grounded, the light-emitting end of opto-isolator 1E1 is electrically connected to the cathodes of indicator lights 1LED2 and 1LED3, the anodes of indicator lights 1LED2 and 1LED3 are electrically connected to resistor 1R26, and resistor 1R26 is connected to the power supply.

[0092] The light-receiving end (photosensitive semiconductor tube) of the optoelectronic isolator 1E1 is electrically connected to the first ends of the resistor 1R24 and the resistor 1R25 and grounded. The second end of the resistor 1R24 is electrically connected to the second power supply output by the second step-down and voltage-stabilizing circuit unit, and the second end of the resistor 1R25 is electrically connected to the SOC chip 1U1.

[0093] It should be noted that the number of the shunt metering modules is eight in total, and the components of the eight shunt metering modules are the same, so they will not be elaborated one by one here.

[0094] Through such a design, each output port of the socket of each power supply of the PDU device has an independent shunt metering module for independent metering and output control. All shunt metering modules can independently complete core functions such as sampling of various electrical parameters, cumulative settlement of electric energy, storage of relevant data, and serial communication. Moreover, the shunt metering module and the main metering module communicate and transmit data or control instructions with the microprocessor through a group of RS485 buses with a power and digital signal isolation circuit. The microprocessor only needs to store the power consumption information collected from each metering module (shunt metering module, main metering module) in the memory 0U2 of the memory circuit unit according to a pre-designed data structure, and then display or transmit the collected data to a higher-level management and control platform through the human-machine interface of the external terminal device or the external communication port.

[0095] Also, since each metering module (shunt metering module, main metering module) has a high-performance and low-power SOC chip as a microcontroller, and the SOC chip itself integrates an analog front end and an electric energy metering module. Therefore, in the design of the current sampling circuit, except that the main metering unit does not consider the mechanical structure design of the external output interface and uses a high-precision level current transformer as the sampling source,

[0096] the remaining shunt metering modules use a manganin shunt as the current sampling source, which increases the overall reliability of the PDU device while realizing current sampling. In the design of the voltage sampling circuit, a multi-stage voltage-dividing resistor series network is used to attenuate the line voltage.

[0097] After obtaining the analog sampling signals of the AC voltage and current, the SOC chip can accurately measure and calculate electrical parameters such as voltage, current, active power, reactive power, active electric energy, and reactive electric energy, and store them in the memory (such as 1U2) inside the SOC chip.

[0098] Even when the PDU device is quickly powered off, the SOC chip can trigger a quick startup through the condition of a power-off detection I / O port of itself to perfectly save the current metering parameter data. When the device is powered on and works normally again, the SOC chips of each metering module will synchronously refresh and save the real-time data such as voltage, current, power factor, etc., and for the electric energy metering data, it will accumulate and save according to the electric energy metering data saved during the previous power-off and the current metering data, so as to ensure that each metering unit can effectively save the latest data of the electric energy parameters under extremely abnormal conditions.

[0099] The data in the memory (such as 1U2) on the SOC chip can be interconnected through the serial port of the serial port microprocessor via the RS485 bus. The microprocessor issues protocol instructions for reading data one by one and in a loop; all metering modules will pack and upload the data of their respective all electric energy parameters and status data to the microprocessor according to the data format and sequence set in the bus communication protocol message;

[0100] The core function of each metering module is the acquisition and metering of electric energy. Only by effectively implementing the work of calibrating the electric energy metering error can it be ensured that the metering error level of each metering parameter of each metering unit will not be lower than the error accuracy level of the Class A single-phase electric energy meter of the State Grid (accuracy class is 2.0).

[0101] Each metering module is designed with a port carrying a metering pulse output circuit unit with power and signal isolation on the hardware. Without changing the overall structure of the production equipment, only by adding a simple interface transfer tooling can the batch calibration production behavior of the PDU metering module be realized, expanding new product fields and new production capacity at the same time.

[0102] While the microprocessor orderly and cyclically reads the data blocks of each metering unit published on the bus through the RS485 bus, it can also write the protection threshold of the protection warning parameter items set on the external terminal (such as a computer) of the PDU device into the specified metering module through the RS485 bus. The SOC chips of each metering module will make timely analysis after effectively digitalizing the sampled real-time data, and make a conditional comparison with the set protection threshold parameter items to determine whether to operate the switch control relay;

[0103] Once the trigger condition is met (the parameters sampled by the metering module exceed the protection threshold parameter range), the on-off control of the relay will be effectively executed to timely and effectively block the abnormal output of electric energy and reliably protect the electrical equipment connected to the power socket controlled by the metering module; at the same time, the microprocessor will obtain the relay state data of the current metering module in the next cycle of reading and collecting data and synchronously refresh the content of the relay state data controlled by the microprocessor;

[0104] As described above, each metering module can implement the on-off control of the relay according to the protection threshold obtained in advance by its own SOC chip. However, for the PDU as a whole device, the microprocessor of the PDU can issue a mandatory control instruction to each metering module. This mandatory instruction may be inconsistent with the output determination of the metering module itself, but because it is a mandatory instruction from the superior controller, it must be executed.

[0105] In summary, the implementation of the embodiment of the present invention aims to simplify the functions of the microprocessor of the PDU for power parameter acquisition and settlement, and allocate this function to each metering module with an "SOC chip" as the microcontroller. The metering module then uses low-cost and simple voltage and current sampling devices or circuit networks to very efficiently implement the metering acquisition task of the watt-hour meter. Therefore, the functional requirements of the microprocessor of the PDU are reduced, and its manufacturing cost and production cost are greatly reduced based on the advantages of the device selection described above, effectively achieving the purpose of technological innovation, production capacity expansion and reuse, and directly improving the performance-price ratio of the PDU device, which is beneficial to market application and promotion.

[0106] The present invention is not limited only to what is described in the specification and embodiments. Therefore, for those skilled in the art, additional advantages and modifications can be easily achieved. Thus, without departing from the spirit and scope of the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details, representative devices, and examples shown and described herein.

Claims

1. A power monitoring and control circuit system for each power output port of a PDU device, characterized in that, It includes a first step-down and voltage-stabilizing circuit unit which outputs a first power supply; A second step-down and voltage-stabilizing circuit unit which outputs a second power supply; A microprocessor which can be electrically connected to a computer, a memory and an external terminal device; A power supply and digital signal isolation circuit. The first power supply output by the first step-down and voltage-stabilizing circuit unit is electrically connected to both the power supply and digital signal isolation circuit and the microprocessor. The second power supply output by the second step-down and voltage-stabilizing circuit unit is electrically connected to a bus circuit in the power supply and digital signal isolation circuit; A main circuit metering module which is electrically connected to the second power supply on the power supply and digital signal isolation circuit; A branch circuit metering module which is electrically connected to the second power supply on the power supply and digital signal isolation circuit and the main circuit metering module; The main circuit metering module includes a main circuit communication circuit unit, a memory circuit unit, a main circuit voltage sampling unit, a main circuit current sampling unit, a main circuit metering pulse optoelectronic isolation circuit unit and an SOC chip 0U1. The main circuit communication circuit unit is electrically connected to the power supply and digital signal isolation circuit, and the main circuit communication circuit unit, the memory circuit unit, the main circuit voltage sampling unit, the main circuit current sampling unit and the main circuit metering pulse optoelectronic isolation circuit unit are electrically connected to the SOC chip 0U1; The memory circuit unit further includes a resistor 0R14, a resistor 0R16 and a memory 0U2. The first ends of the resistor 0R14 and the resistor 0R16 are electrically connected, and the first ends of the resistor 0R14 and the resistor 0R16 are connected to the second power supply output by the second step-down and voltage-stabilizing circuit unit. The second end of the resistor 0R14 is electrically connected to the memory and the SOC chip 0U1. The second end of the resistor 0R16 is electrically connected to the memory 0U2 and the SOC chip 0U1, and the memory 0U2 is grounded; The main circuit voltage sampling unit includes a capacitor 0C1, a resistor 0R1, a resistor 0R2, a resistor 0R3, a resistor 0R4, a resistor 0R5, a resistor 0R6 and a resistor 0R7. The first end of the capacitor 0C1 is electrically connected to the SOC chip 0U1. The second end of the capacitor 0C1 is electrically connected to the first end of the resistor 0R7. The second end of the resistor 0R7 is electrically connected to the first end of the resistor 0R6 and the first end of the capacitor 0C1. The second end of the resistor 0R6 is electrically connected to the resistors 0R5, 0R4, 0R3, 0R2, 0R1 in sequence; 2. The power monitoring and control circuit system for each power output port of the PDU device according to claim 1, wherein The first step-down and voltage-stabilizing circuit unit includes a capacitor C32, a resistor R14, a power management chip WD1, a resistor R13, a capacitor C3, an inductor L2, a capacitor C33, a capacitor C34, a resistor R16, a resistor R15 and a resistor R17; The first end of the capacitor C32 is connected to a DC - 12V power supply, the second end of the capacitor C32 is grounded, the first end of the resistor R14 is electrically connected to the first end of the capacitor C32 and the VIN pin of the power management chip WD1, the second end of the resistor R14 is electrically connected to the EN pin of the power management chip WD1, and the BST pin of the power management chip WD1 is electrically connected to the first end of the resistor R13. The second end of the resistor R13 is electrically connected to the first end of the capacitor C3, the second end of the capacitor C3 is electrically connected to the first end of the inductor L2 and the SW pin of the power management chip WD1, the second end of the inductor L2 is electrically connected to the first end of the capacitor C33, and the second end of the capacitor C33 is grounded. The first end of the capacitor C34 is electrically connected to the first end of the resistor R16 and the FB pin of the power management chip WD1, the second end of the resistor R16 is electrically connected to the first end of the resistor R15 and the first end of the resistor R17, the first end of the resistor R15 is also electrically connected to the microprocessor, the second end of the resistor R15 is electrically connected to the second end of the inductor L2, and the second end of the resistor R17 is electrically connected to the second end of the capacitor C33.

3. The power monitoring and control circuit system for each power output port of the PDU device according to claim 1, characterized in that, The power - to - digital signal isolation circuit includes a resistor RS3, a resistor RS2, an isolator U4, a serial communication chip U5, a transistor Q6, a resistor RS5, a resistor RS6, and a bidirectional TVS tube; the resistor RS3 is electrically connected to the microprocessor and the VIB pin of the isolator U4, the resistor RS2 is electrically connected to the microprocessor and the VOA pin of the isolator U4, the VDD1 of the isolator U4 is grounded through a capacitor CS5, a first power supply is electrically connected to the capacitor CS5, the VDD2 of the isolator U4 is grounded through a capacitor CS6, the capacitor CS6 is electrically connected to the second power supply output by the second step - down and voltage - regulating circuit unit, the GND1 pin of the isolator U4 is connected to the power ground of the first power supply, the GND2 pin of the isolator U4 is connected to the power ground of the second power supply, the VIA pin of the isolator U4 is electrically connected to the R pin of the serial communication chip U5, and the VOB pin of the isolator U4 is electrically connected to the D pin of the serial communication chip U5. The / RE pin and the DE pin of the serial communication chip U5 are electrically connected to the collector of the transistor Q6, the collector of the transistor Q6 is grounded through a resistor RS8, the D pin of the serial communication chip U5 is electrically connected to the base of the transistor Q6 through a resistor RS7, and the emitter of the transistor Q6 is electrically connected to the second power supply output by the second step - down and voltage - regulating circuit unit. The VCC pin of the serial communication chip U5 is electrically connected to the first end of the resistor RS5 and the second power supply output by the second step-down and voltage regulation circuit unit. The second end of the resistor RS5 is electrically connected to the A pin of the serial communication chip U5. The B pin of the serial communication chip U5 is electrically connected to the first end of the resistor RS6. The second end of the resistor RS6 is electrically connected to the GND pin of the serial communication chip U5 and grounded. The first pole of the bidirectional TVS tube is electrically connected to the second end of the resistor RS5. The second pole of the bidirectional TVS tube is electrically connected to the first end of the resistor RS6.

4. The power monitoring and control circuit system for each power output port of the PDU device according to claim 1, characterized in that, The power energy monitoring and control circuit system of each power output port of the PDU device further includes a second step-down and voltage regulation circuit unit. The second step-down and voltage regulation circuit unit includes a capacitor C16, a power management chip U5, a capacitor C17, a Schottky diode D2, an inductor L1, a capacitor C18, a capacitor EC1, a resistor R32, a resistor R33, a resistor R34, and a resistor R35. The first end of the capacitor C16 is connected to the DC-12V power supply. The second end of the capacitor C16 is grounded. The VCC pin of the power management chip U5 is electrically connected to the first end of the capacitor C16 and the first end of the resistor R32. The second end of the resistor R32 is electrically connected to the first end of the resistor R33. The second end of the resistor R33 is grounded. The BST pin of the power management chip U5 is electrically connected to the first end of the capacitor C17. The second end of the capacitor C17 is electrically connected to the LX pin of the power management chip, the cathode of the Schottky diode D2, and the first end of the inductor L1. The anode of the Schottky diode D2 is electrically connected to the first end of the capacitor C18. The second end of the capacitor C18 is electrically connected to the second end of the inductor L1, the first end of the resistor R35, and the first end of the capacitor EC1. The second end of the resistor R35 is electrically connected to the first end of the resistor R34 and the FB pin of the power management chip. The second end of the resistor R34 is electrically connected to the first end of the resistor R33 and grounded. The second end of the resistor R33 is electrically connected to the EN pin of the power management chip and the first end of the resistor R32. The second end of the resistor R32 is electrically connected to the first end of the capacitor C16. The capacitor EC1 outputs the second power supply.

5. The power monitoring and control circuit system for each power output port of the PDU device according to claim 3, wherein The total loop communication circuit unit includes a serial communication chip 0U3, a capacitor 0C14, a resistor 0R17, a resistor 0R18, and a transistor 0Q2; the VCC pin of the serial communication chip 0U3 is electrically connected to the capacitor 0C14 and grounded, the capacitor 0C14 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, the A pin of the serial communication chip 0U3 is electrically connected to the second end of the resistor RS5, the B pin of the serial communication chip 0U3 is electrically connected to the first end of the resistor RS6, the first end of the resistor 0R17 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, the second end of the resistor 0R17 is electrically connected to the R pin of the serial communication chip 0U3 and the SOC chip 0U1, the first end of the resistor 0R18 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, and the second end of the resistor 0R18 is electrically connected to the D pin of the serial communication chip 0U3; The / RE pin and the DE pin of the serial communication chip 0U3 are both electrically connected to the emitter of the transistor 0Q2, the emitter of the transistor 0Q2 is grounded through a resistor 0R20, the collector of the transistor 0Q2 is electrically connected to the second power supply output by the second step-down and voltage regulation circuit unit, and the base of the transistor 0Q2 is electrically connected to the SOC chip 0U1 through a resistor 0R19.

6. The power monitoring and control circuit system for each power output port of the PDU device according to claim 5, characterized in that The total loop current sampling unit includes a capacitor 0C8, a capacitor 0C2, a capacitor 0C3, a resistor 0R8, a resistor 0R9, a resistor 0R21, a resistor 0R15, and a current transformer CT0; the first end of the capacitor 0C8 is electrically connected to the SOC chip 0U1, the second end of the capacitor 0C8 is electrically connected to the first end of the resistor 0R9, the second end of the resistor 0R9 is electrically connected to the first end of the resistor 0R15 and the current transformer CT0, the second end of the resistor 0R15 is electrically connected to the first end of the resistor 0R21, the second end of the resistor 0R21 is electrically connected to the current transformer CT0, the first end of the capacitor 0C2 is electrically connected to the first end of the capacitor 0C8, the second end of the capacitor 0C2 is electrically connected to the first end of the capacitor 0C3, the second end of the capacitor 0C3 is electrically connected to the first end of the resistor 0R9, the first end of the resistor 0R8 is electrically connected to the first end of the capacitor 0C2, and the first end of the resistor 0R21 is electrically connected to the second end of the capacitor 0C2 and is connected to the power ground of the second power supply.

7. The power monitoring and control circuit system for each power output port of the PDU device according to claim 6, characterized in that, The total circuit metering pulse opto-isolation circuit unit includes resistor 0R34, opto-isolator 0E3, pulse signal indicator lamp 0LED1, and resistor 0R36; the first end of the resistor 0R34 is electrically connected to the SOC chip 0U1, the second end of the resistor 0R34 is electrically connected to the light-emitting end of the opto-isolator 0E3, the light-receiving end of the opto-isolator 0E3 is electrically connected to the pulse signal indicator lamp 0LED1, the pulse signal indicator lamp 0LED1 is electrically connected to the resistor 0R36, and the resistor 0R36 is connected to the power supply.

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