Improved design method for booting of ZYNQ series chip

Abstract

This invention discloses an improved design method for booting ZYNQ series chips, comprising the following steps: the PMU resets and wakes up the ZYNQ chip management module and loads the BootROM code; the BootROM reads the boot image from an external storage device and performs a search and verification; tasks to be determined before image file relocation are completed; the PL bit stream is moved from the image file; the secondary boot APP is copied and moved from the image file; the secondary boot APP is used to complete the secondary booting of the business APP in the image file; and the execution address is translated to the entry start address of the business APP using assembly language. This invention replaces the ZYNQ chip boot FSBL with a smaller secondary boot APP and runs the program in AXI SRAM and AHB SRAM, effectively expanding the memory to 300K. Furthermore, running the program on AXI SRAM improves the program's running speed; additionally, it reduces the actual power consumption of the ZYNQ chip and shortens the program burning time.

Description

Technical Field

[0001] This invention relates to the field of boot technology, and in particular to an improved design method for booting ZYNQ series chips. Background Technology

[0002] The Zynq® UltraScale+™ MPSoC has both a PS side and a PL side. The PS side has two different multi-core processors that can run low-level code or operating systems and their applications. The OCM (On Chip RAM) memory space is mainly divided into 256K AXI SRAM and 128K AHB SRAM. The main purpose of booting is to move the program in FLASH to OCM. The boot program is placed in AXI SRAM and the business application is placed in AHB SRAM.

[0003] The ZYNQ boot process currently consists of three functional stages: pre-configuration, configuration, and post-configuration. The first two stages configure the ZYNQ's underlying chip, while the post-configuration stage, FSBL, boots the BIT and the application. After FSBL completes the BIT migration, the first two configuration stages are no longer needed. Therefore, it's advisable to release the AXI ARAM memory at this point and replace it with a smaller secondary boot application, thus increasing memory usage.

[0004] Currently, many feasible technical solutions have been proposed both domestically and internationally to address the issue of insufficient memory in ZYNQ processors. Each of these solutions has its own advantages and disadvantages.

[0005] The first solution involves modifying the ICF memory management file in ZYNQ. For each chip device, IAR has a default ICF directory corresponding to each device, which can be configured by the user. This allows a portion of the AXI SRAM memory to be allocated to the AHB SRAM. However, since the FSBL itself occupies 200K of space, this solution will only increase the application's memory by a maximum of 56K.

[0006] The second option is to use external DDR memory, which can directly expand the running memory by several gigabytes. However, DDR hardware is expensive and involves complex hardware circuit configurations. For business applications with a capacity of only a few hundred kilobytes, using external DDR memory results in a certain waste of resources.

[0007] The third option is to use XIP for local execution. When executing locally, the code segment does not need to be loaded into physical memory first. WINCE only allocates virtual address space to the code segment and maps it to Flash ROM, which greatly saves physical memory. However, XIP only supports Flash ROM that allows current access. The disadvantage of the XIP loading method is that the execution speed is relatively slow. Therefore, XIP is not suitable for occasions with high real-time requirements.

[0008] The final, fourth option is to optimize the business application code to reduce code complexity, i.e., simplify the code and remove redundant code. However, this approach may affect the overall functionality of the project.

[0009] Currently, the ZYNQ series chips have a certain memory shortage problem. A single business application mainly runs in AHBSRAM, which has a memory of 128K, while the general project size is about 200K. Therefore, an improved design method for booting is proposed to address this problem. Summary of the Invention

[0010] In view of this, the present invention provides an improved design method for booting ZYNQ series chips, which develops a secondary boot method to run business applications simultaneously in AXI SRAM and AHB SRAM, thereby indirectly expanding the running memory space. At the same time, AXI SRAM has a faster running speed and can reduce power consumption compared to AHB SRAM.

[0011] This invention discloses an improved design method for booting ZYNQ series chips, comprising the following steps:

[0012] Step 1: The PMU completes the reset and wake-up of the ZYNQ chip management module and loads the BootROM code;

[0013] Step 2: The BootROM reads the boot image from the external storage device and performs a search and verification.

[0014] Step 3: Complete the tasks to be confirmed before moving the image file;

[0015] Step 4: Move the PL end bit stream in the image file;

[0016] Step 5: Copy and move the secondary bootloader app from the image file;

[0017] Step 6: Use the secondary bootloader APP to complete the secondary bootloader of the business APP in the image file;

[0018] Step 7: Use assembly language to translate the execution address to the entry point address of the business APP.

[0019] Further, step 1 includes:

[0020] Step 11: After the POR is powered on, the PMU is initialized and reset; then the preprocessing code in the PMU's ROM is executed;

[0021] Step 12: After the PMU completes the reset and wake-up functions, it guides the CSU to reset and determines the hardware version and CPU boot method;

[0022] Step 13: After CSU reset, load the CSU ROM code, which includes the BootROM;

[0023] Step 14: The BootROM completes the initialization of the external device, enabling the ARM core to successfully access the external device; wherein, the external device includes SD card, NAND, NOR, and QSPI Flash.

[0024] Further, step 2 includes:

[0025] The boot method is determined to be QSPI Flash. The image file is searched and verified, and the first part of the image file, namely FSBL, is moved. At the same time, the starting address of the area in FLASH that stores FSBL, BIT, secondary boot APP, and business APP is allocated. Then, the ID and CheckSum of the image file are verified, as well as encrypted.

[0026] Further, step 3 includes:

[0027] Before moving an image file, it is necessary to determine whether it is encrypted, whether authentication is required, and whether it is an XIP. At the same time, the relevant key parameters of the image file need to be determined. These key parameters include the device loading address, the loading memory length, and the device execution address, i.e., the APP program startup address. The device execution address can be obtained through the starting address of the secondary boot APP and the configuration of the program ICF.

[0028] Furthermore, if the CSU detects that the partition is encrypted, the CSU will perform decryption and initialize the OCM, determine the boot mode setting, and perform FSBL loading and optional PMU firmware loading operations; after executing the CSU ROM code, control is handed over to the FSBL; the FSBL uses the PCAP interface to program the PL containing the bit stream.

[0029] Further, step 4 includes:

[0030] A DMA register is used to move the bit stream at the PL end. The main function of the DMA register is to realize the data transfer between the memory and external devices.

[0031] Further, step 5 includes:

[0032] Step 51: Determine the device ID and the size to copy;

[0033] Step 52: Set the data transmission mode and transmission rate according to the ZNYQ's QSPI register; the standard SPI transmission method is used.

[0034] Step 53: Use Memcpy to move data from memory addresses.

[0035] Furthermore, the initial guidance process is as follows:

[0036] Move the FSBL to AXI SRAM and move the secondary boot application memory to AHB SRAM;

[0037] The second guidance process is as follows:

[0038] After the FSBL completes the configuration phase, the memory space of AXI SRAM is cleared, and then the secondary boot application is used to move the business application to AXI SRAM and AHB SRAM, thereby starting the business application.

[0039] Furthermore, the entire memory space of ZYNQ is divided as follows:

[0040] Allocate 256K of AXI SRAM memory space to the ROM area of ​​the business application; allocate 64K of AHB SRAM memory space to the RAM area of ​​the business application; divide the specific memory size of the stack area; modify the starting address in the ICF and define it as a fixed address 0x20000.

[0041] Furthermore, in step 7, the entry start address can be set in the ICF memory management file, and the assembly part has been encapsulated into a function.

[0042] Due to the adoption of the above technical solution, this invention has the following advantages: First, by developing secondary boot technology, the available running memory can be greatly increased, improving the software's running speed; second, it saves the company the cost of replacing hardware, reducing the waste of manpower and resources; third, the secondary boot technology separates the PS and PL ends for programming, facilitating the management of software configuration items and allowing for better upgrades in subsequent version updates; finally, without modifying the PL end, it greatly shortens the programming time for software debugging personnel, reducing the original 10 minutes of programming to 1-2 seconds; this invention directly modifies the software program for improvement, without requiring additional hardware, and only requires ZYNQ series chips to implement the application, exhibiting good versatility. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0044] Figure 1 This is a schematic diagram of the first guided movement in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the second guided transfer in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the final memory allocation result in an embodiment of the present invention;

[0047] Figure 4 This is a flowchart illustrating an improved design method for booting ZYNQ series chips according to an embodiment of the present invention. Detailed Implementation

[0048] The present invention will be further described in conjunction with the accompanying drawings and embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0049] This invention provides an embodiment of an improved design method for booting ZYNQ series chips, the specific process of which is shown in the figure below.

[0050] This method first divides the original three parts of FLASH storage—FSBL, BIT, and business application—into four parts: FSBL, BIT, secondary boot application, and business application. During the first boot, the FSBL is moved to AXI SRAM, and the secondary boot application is moved to AHBSRAM, as detailed below. Figure 1 As shown.

[0051] Secondly, clear the memory space of AXI SRAM, and then use the secondary bootstrap APP to move the business APP to AXI SRAM and AHB SRAM, specifically as follows: Figure 2 As shown.

[0052] Finally, the overall OCM allocation is as follows: the business application occupies AXI SRAM and AHB SRAM, with 320K of usable space, greatly expanding the running space, as detailed below. Figure 3 As shown.

[0053] In addition, the secondary boot process is developed and designed based on the original ZYNQ boot method, which means a new step 6 is added, see [link to relevant documentation]. Figure 4The specific execution process is as follows:

[0054] Step 1: The PMU completes the reset and wake-up of the ZYNQ chip management module and loads the BootROM code;

[0055] Specifically, firstly, the PMU (Platform Management Unit) handles all reset and wake-up processes. Power-on reset is used to reset the CSU and PMU. This step executes the contents of the BootROM (a small mask ROM or write-protected flash memory embedded in the processor chip). Secondly, the entire system is initialized, determining whether to use QSPI (Queued SPI) or SD (Secure Digital Memory Card) as the boot mode. The software undergoes a full POR (Power-on Reset) reset to determine the hardware version and CPU boot mode. Finally, the BootROM initializes the SD card, NAND (computer flash memory), NOR (non-volatile flash memory), QSPI Flash, etc., enabling the ARM (Asynchronous Response Mode) core to successfully access and use these peripherals.

[0056] Step 2: The BootROM reads the boot image from the external storage device and performs a search and verification.

[0057] Specifically, the boot method (QSPI FLASH) is determined, the image file is searched and verified, and the first part of the image file, FSBL (First Stage Boot Loader), is moved. Simultaneously, the starting addresses of each partition are allocated. The search primarily uses the starting address + 32k to find valid boot images within a range of 16MB. Then, the image file's ID and CheckSum are verified, along with encryption verification.

[0058] Step 3: Complete the tasks to be confirmed before moving the image file;

[0059] Specifically, identity encryption verification is required before relocation. It needs to be determined whether encryption is needed, whether authentication is required, and whether it is XIP (Execute In Place). Simultaneously, the device load address, load memory length, and device execution address must be determined. This address is obtained automatically from the partition start address in the second stage, based on the program ICF (Memory Management File) configuration.

[0060] If the CSU (Configuration Security Unit) detects that the partition is encrypted, it will perform decryption and initialization of the OCM (On Chip Memory), determine the boot mode setting, and perform FSBL loading and optional PMU firmware loading operations. After executing the CSU ROM code, it will hand over control to the FSBL. The FSBL uses the PCAP (Popular Data Streaming) interface to program the bitstream-containing PL (FPGA part).

[0061] Step 4: Move the PL end bit stream in the image file;

[0062] Specifically, the PL-side BIT bitstream shifting is performed using the DMA (Direct Memory Access) register method. DMA is a direct memory access controller that enables data transfer between memory and peripherals.

[0063] Step 5: Copy and move the secondary boot APP from the image file;

[0064] Specifically, the secondary boot APP copy and move process first determines the device ID and the copy size, then sets the transmission mode and transmission rate according to the ZNYQ's QSPI register, using the standard SPI transmission method, and finally uses Memcpy to move the data in the memory address.

[0065] Step 6: Use the secondary bootloader APP to complete the secondary bootloader of the business APP in the image file;

[0066] Specifically, this process is an improvement, adding a second-level bootloader for APP migration. First, the AXI (bus protocol) SRAM (static random access memory) memory space is cleared, and then the business APP is migrated to the OCM again using a copy migration method. This reduces the actual power consumption of the ZYNQ chip; increases program execution speed; expands the actual running memory of the program; and shortens the program burning time.

[0067] Step 7: Use assembly language to translate the execution address to the entry point address of the business APP.

[0068] Specifically, the execution address is translated to the entry point address of the APP using assembly language. This address can be set in the ICF memory management file, and the assembly part has been encapsulated into a function.

[0069] In addition, the entire memory space of ZYNQ is roughly divided into the stack, heap, global (static) area, and program code area, etc., and its specific memory division is as follows:

[0070] First, allocate 256K of AXI SRAM memory space to the ROM area of ​​the business application:

[0071] define symbol __ICFEDIT_region_ROM_start__ = 0x20000;

[0072] define symbol __ICFEDIT_region_ROM_end __ = 0x5FFFF;

[0073] Secondly, allocate 64K of AHB (Advanced High Performance Bus) SRAM memory space to the RAM area of ​​the business application:

[0074] define symbol __ICFEDIT_region_RAM_start__= 0xE1FEFFFF;

[0075] define symbol __ICFEDIT_region_RAM_end__= 0xE1FFFFFF;

[0076] Then, the specific memory size of the stack area is allocated:

[0077] define symbol __ICFEDIT_size_vectors__ = 0x100;

[0078] define symbol __ICFEDIT_size_cstack__ = 0x9000;

[0079] define symbol __ICFEDIT_size_irqstack__ = 0x1000;

[0080] define symbol __ICFEDIT_size_fiqstack__ = 0x200;

[0081] define symbol __ICFEDIT_size_abtstack__= 0x120;

[0082] define symbol __ICFEDIT_size_undstack__ = 0x100;

[0083] define symbol __ICFEDIT_size_heap__= 0x500;

[0084] Finally, to ensure the general applicability of the entire secondary boot software, the starting address in the ICF was modified and defined as a fixed address 0x20000:

[0085] define region ROM_STARTUP_region = mem:[from __ICFEDIT_region_ROM_start__size __ICFEDIT_size_cstartup__];

[0086] place in ROM_STARTUP_region { section .cstartup};

[0087] Finally, verification was conducted through simulation using a certain type of project. First, BOOT.BIN was generated according to the standard process. BOOT.BIN contains Fsbl, Bit, and the secondary boot APP, and then it was burned to the starting address location 0 of the Flash memory. Next, the business APP.Bin was burned to the offset 0xE00000, which is 14M. Currently, after 300 room temperature tests, it is feasible.

[0088] The final remaining memory is analyzed using MAP (memory-mapped file) files. A MAP file is a mapping file generated after compilation, containing information about the program, data, and I / O space, including function sizes, entry addresses, and other important data. First, for the AXI SRAM memory space, it can be seen that only 0x0003c774 is used, using 113K, leaving 143K of memory space remaining. Second, for the AHB SRAM memory space, it can be seen that only 0xe1fffe68 is used, using 42K, leaving 24K of memory space remaining.

[0089] The memory analysis above shows that the program is currently using 156KB of memory, with 167KB remaining. The total memory usage is less than 70%, which meets the requirements of engineering software. Furthermore, this method is generally applicable to projects where the PS is not connected to DDR (Double Data Rate Synchronous Dynamic Random Access Memory) or where the application program is small.

[0090] With this, the system has completed the verification of secondary boot memory expansion for ZYNQ series chips.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. An improved design method for booting ZYNQ series chips, characterized in that, Includes the following steps: Step 1: The PMU completes the reset and wake-up of the ZYNQ chip management module and loads the BootROM code; Step 2: The BootROM reads the boot image from the external storage device and performs a search and verification. Step 3: Complete the tasks to be confirmed before moving the image file; Step 4: Move the PL end bit stream in the image file; Step 5: Copy and move the secondary bootloader app from the image file; Step 6: Use the secondary bootloader APP to complete the secondary bootloader of the business APP in the image file; Step 7: Use assembly language to translate the execution address to the entry point address of the business APP; The original three parts of FLASH storage (FSBL, BIT, and business application) are divided into four parts: FSBL, BIT, secondary boot application, and business application. For the first boot, the FSBL is moved to AXI SRAM, and the secondary boot application is moved to AHB SRAM. The memory space of AXI SRAM is cleared, and the business application is moved to both AXI SRAM and AHB SRAM using the secondary boot application. The BootROM reads the boot image from the external storage device and performs a search and verification. Specifically, it determines the boot method, searches and verifies the image file, and completes the migration of the first part (FSBL) of the image file. The secondary boot application is then used to complete the second boot of the business application in the image file. Specifically, a secondary boot application migration is added to the original setup, the memory space of AXI SRAM is cleared, and the business application is moved to OCM again using a copy migration method.

2. The method according to claim 1, characterized in that, Step 1 includes: Step 11: After the POR is powered on, the PMU is initialized and reset; then the preprocessing code in the PMU's ROM is executed; Step 12: After the PMU completes the reset and wake-up functions, it guides the CSU to reset and determines the hardware version and CPU boot method; Step 13: After CSU reset, load the CSU ROM code, which includes the BootROM; Step 14: The BootROM completes the initialization of the external device, enabling the ARM core to successfully access the external device; wherein, the external device includes SD card, NAND, NOR, and QSPI Flash.

3. The method according to claim 1, characterized in that, Step 2 includes: The boot method is determined to be QSPI Flash. The image file is searched and verified, and the first part of the image file, namely FSBL, is moved. At the same time, the starting address of the area in FLASH that stores FSBL, BIT, secondary boot APP, and business APP is allocated. Then, the ID and CheckSum of the image file are verified, as well as encrypted.

4. The method according to claim 1, characterized in that, Step 3 includes: Before moving an image file, it is necessary to determine whether it is encrypted, whether authentication is required, and whether it is an XIP. At the same time, the relevant key parameters of the image file need to be determined. These key parameters include the device loading address, the loading memory length, and the device execution address, i.e., the APP program startup address. The device execution address can be obtained through the starting address of the secondary boot APP and the configuration of the program ICF.

5. The method according to claim 4, characterized in that, If the CSU detects that the partition is encrypted, the CSU will decrypt and initialize the OCM, determine the boot mode setting, and perform FSBL loading and optional PMU firmware loading operations; after executing the CSU ROM code, control is handed over to the FSBL; the FSBL uses the PCAP interface to program the PL containing the bit stream.

6. The method according to claim 1, characterized in that, Step 4 includes: A DMA register is used to move the bit stream at the PL end. The main function of the DMA register is to realize the data transfer between the memory and external devices.

7. The method according to claim 1, characterized in that, Step 5 includes: Step 51: Determine the device ID and the size to copy; Step 52: Set the data transmission mode and transmission rate according to the ZNYQ's QSPI register; the standard SPI transmission method is used. Step 53: Use Memcpy to move data from memory addresses.

8. The method according to claim 1, characterized in that, The first guidance process is as follows: Move the FSBL to AXI SRAM and move the secondary boot application memory to AHB SRAM; The second guidance process is as follows: After the FSBL completes the configuration phase, the memory space of AXI SRAM is cleared, and then the secondary boot application is used to move the business application to AXI SRAM and AHB SRAM, thereby starting the business application.

9. The method according to claim 8, characterized in that, ZYNQ's entire memory space is divided as follows: Allocate 256K of AXI SRAM memory space to the ROM area of ​​the business application; allocate 64K of AHB SRAM memory space to the RAM area of ​​the business application; divide the specific memory size of the stack area; modify the starting address in the ICF and define it as a fixed address 0x20000.

10. The method according to claim 1, characterized in that, In step 7, the entry start address can be set in the ICF memory management file, and the assembly part has been encapsulated into a function.

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