An operator-based microprocessor architecture design method and system

Abstract

This invention discloses an operator-based microprocessor architecture design method and system. The invention includes: for a target instruction set architecture, determining the computational functions contained in the target instruction set it supports, and abstracting these computational functions as operators; for each operator in the operator set, establishing execution component libraries for the instructions of the target instruction set's computational functions mapped to those operators; and updating the execution pipeline template based on the execution component library to complete the design of the execution pipeline in the target instruction set architecture. This invention effectively reduces the coupling between the instruction set and the hardware architecture corresponding to the pipeline execution stage, enabling rapid completion of the execution pipeline design in the target instruction set architecture. It provides a lightweight and scalable implementation method for microprocessor design supporting multiple instruction sets, alleviating the area overhead problem caused by incremental design of multiple instruction sets, and reducing the design cycle of microprocessor architecture upgrades.

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