Detection structure, preparation and detection method for pad overetching

Abstract

The present invention provides a detection structure, preparation and detection method for pad over-etching, wherein a reference unit and a detection unit are formed in a wafer cutting area, and a reference capacitor and a detection capacitor are formed in combination with a dielectric layer. Since a dielectric layer detection window is provided above the dielectric layer in the detection capacitor, and the detection pad and the dielectric layer have a large selective etching ratio, the dielectric layer in the detection capacitor is etched during the etching process, so that the capacitance of the detection capacitor changes. By monitoring the changes in the electrical performance data of the detection capacitor and the reference capacitor, i.e., the capacitance value, the over-etching of the pad can be reflected, and the slicing confirmation is avoided.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and in particular relates to a detection structure, preparation and detection method for pad over-etching. Background Art

[0002] In the wafer manufacturing process, it is often necessary to connect the components formed in each film layer together to form a complete semiconductor device, or to connect the semiconductor device with other electronic components to form the required electronic circuit. To complete these connections, it is necessary to form many pads (PADs). It can be said that pads are important connecting components in the wafer manufacturing process. For this reason, in the semiconductor field, there are high requirements for the conductivity and reliability of pads.

[0003] In order to ensure that the pad is exposed for subsequent electrical connection, there is an over-etching process in the existing preparation process. In this etching process, the industry usually practices to capture the Ti / TiN signal on the upper layer of the pad, and then etch for a certain period of time to eat away the Ti / TiN, or directly etch for a certain period of time and assume that the pad is open. This etching process has certain risks, such as plasma accumulation or the formation of crystal defects, etc., so it is necessary to detect the over-etching of the pad. At present, the over-etching process of the pad can only be observed through failure analysis (FA) slicing, and the convenience of the test is extremely low. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a detection structure, preparation and detection method for pad over-etching, so as to solve the problem that it is difficult to conveniently operate pad over-etching detection in the prior art.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a detection structure for pad over-etching, the detection structure comprising:

[0006] A substrate, the substrate comprising a wafer active area and a wafer cutting area;

[0007] A reference unit, the reference unit is located in the wafer cutting area and is synchronously formed with the pad located in the wafer active area, the reference unit includes two reference pads arranged at intervals and a first detection pad connected to the reference pads in a one-to-one correspondence;

[0008] A detection unit, the detection unit is located in the wafer cutting area, is synchronously formed with the pad located in the wafer active area, and the detection unit has the same morphology as the reference unit, and the detection unit includes two detection pads arranged at intervals and a second detection pad connected to the detection pads in a one-to-one correspondence;

[0009] A dielectric layer, the dielectric layer is located on the substrate, covers the substrate, the reference unit and the detection unit, and has a dielectric layer detection window that exposes the first detection pad and the second detection pad, and a dielectric layer detection window that at least exposes the dielectric layer located between the detection pads, wherein the two corresponding reference pads are combined with the dielectric layer to form a reference capacitor, and the two corresponding detection pads are combined with the dielectric layer to form a detection capacitor.

[0010] Optionally, the reference unit and the detection unit are located in a wafer edge cutting area at the same time, located in a wafer center cutting area at the same time, or distributed in the entire wafer cutting area at the same time.

[0011] Optionally, the reference unit and the detection unit are located in a wafer cutting area of ​​adjacent chips.

[0012] Optionally, the dielectric layer includes a silicon oxide dielectric layer; and the pad includes an aluminum pad or an aluminum alloy pad.

[0013] Optionally, the dielectric layer detection window exposes the detection pad.

[0014] The present invention also provides a method for preparing a pad over-etching detection structure, comprising the following steps:

[0015] Providing a substrate, wherein the substrate includes a wafer active area and a wafer cutting area;

[0016] A reference unit and a detection unit having the same morphology are formed on the wafer cutting area of ​​the substrate, and the reference unit and the detection unit are formed synchronously with the pad located in the active area of ​​the wafer, wherein the reference unit includes two reference pads arranged at intervals and a first detection pad connected to the reference pads in a one-to-one correspondence, and the detection unit includes two detection pads arranged at intervals and a second detection pad connected to the detection pads in a one-to-one correspondence;

[0017] forming a dielectric layer on the substrate, wherein the dielectric layer covers the substrate, the reference unit and the detection unit;

[0018] forming a mask layer on the dielectric layer, and patterning the mask layer;

[0019] The dielectric layer is etched to form a dielectric layer detection window that exposes the first detection pad and the second detection pad, and a dielectric layer detection window that at least exposes the dielectric layer located between the detection pads, wherein the two corresponding reference pads are combined with the dielectric layer to form a reference capacitor, and the two corresponding detection pads are combined with the dielectric layer to form a detection capacitor.

[0020] Optionally, a bottom metal layer and a metal column connected to the bottom metal layer are also formed in the substrate.

[0021] The present invention also provides a method for detecting pad over-etching, comprising the following steps:

[0022] Providing any of the above detection structures;

[0023] In combination with the dielectric layer detection window, a reference capacitance of the reference capacitor is obtained through the first detection pad, and a detection capacitance of the detection capacitor is obtained through the second detection pad;

[0024] The obtained reference capacitance value is compared with the detection capacitance value to detect over-etching of the pad.

[0025] Optionally, the method of changing the detection capacitance includes changing one or a combination of the thickness, length, and spacing of the two corresponding detection pads and the size of the dielectric layer detection window.

[0026] Optionally, the method further includes comparing the detection capacitance values ​​of the detection capacitors located in different wafer cutting areas to reflect the differences in wafer process in different areas.

[0027] As described above, the detection structure, preparation and detection method for pad over-etching of the present invention form a reference unit and a detection unit in the wafer cutting area, and combine the dielectric layer to form a reference capacitor and a detection capacitor. Since there is a dielectric layer detection window above the dielectric layer in the detection capacitor, and the detection pad and the dielectric layer have a large selective etching ratio, the dielectric layer in the detection capacitor is etched during the etching process, so that the capacitance of the detection capacitor changes. By monitoring the changes in the electrical performance data of the detection capacitor and the reference capacitor, that is, the capacitance value, the over-etching of the pad can be reflected, avoiding the need for slicing confirmation. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic diagram of the wafer structure in Embodiment 1 of the present invention.

[0029] Figure 2 It is a schematic diagram of the enlarged structure of the reference capacitor in the first embodiment of the present invention.

[0030] Figure 3 Display as Figure 2 Schematic diagram of the cross-sectional structure along AA.

[0031] Figure 4 It is a schematic diagram of the enlarged structure of the detection capacitor in the first embodiment of the present invention.

[0032] Figure 5 Display as Figure 4Schematic diagram of the cross-sectional structure along BB.

[0033] Figure 6 Shown is a process flow chart for preparing a pad over-etching detection structure in Embodiment 2 of the present invention.

[0034] Figure 7 Shown is a flow chart for pad over-etching detection in Embodiment 3 of the present invention.

[0035] Component number description

[0036] 10 Wafer

[0037] 20 Wafer active area

[0038] 30 Wafer cutting area

[0039] 100 Base

[0040] 101 Bottom Metal Layer

[0041] 102 Metal Column

[0042] 211 Reference pad

[0043] 212 First detection pad

[0044] 221 Detection pad

[0045] 222 Second detection pad

[0046] 300 Dielectric layer

[0047] 301 Dielectric layer detection window

[0048] 302 Dielectric layer detection window

[0049] X Length

[0050] Y Thickness

[0051] L spacing

[0052] Steps S1 to S5, Sa to Sc DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0055] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers. Among them, when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element.

[0056] Here, expressions such as "between..." may be used, which indicates that the two end points are included, and expressions such as "plurality" may be used, which indicates two or more, unless otherwise clearly and specifically limited. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0057] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0058] Embodiment 1

[0059] like Figure 1 to Figure 5 This embodiment provides a detection structure for pad over-etching, the detection structure comprising:

[0060] A substrate 100, wherein the substrate 100 includes a wafer active area 20 and a wafer cutting area 30;

[0061] A reference unit, the reference unit is located in the wafer cutting area 30 and is synchronously formed with the pads located in the wafer active area 20, the reference unit includes two reference pads 211 arranged at intervals and a first detection pad 212 connected to the reference pads 211 in a one-to-one correspondence;

[0062] A detection unit, the detection unit is located in the wafer cutting area 30, is synchronously formed with the pad located in the wafer active area 20, and the detection unit has the same morphology as the reference unit, and the detection unit includes two detection pads 221 arranged at intervals and a second detection pad 222 connected to the detection pads 221 in a one-to-one correspondence;

[0063] A dielectric layer 300, wherein the dielectric layer 300 is located on the substrate 100, covers the substrate 100, the reference unit and the detection unit, and has a dielectric layer detection window 301 that exposes the first detection pad 212 and the second detection pad 222, and a dielectric layer detection window 302 that at least exposes the dielectric layer 300 located between the detection pads 221, wherein the two correspondingly arranged reference pads 211 are combined with the dielectric layer 300 to form a reference capacitor, and the two correspondingly arranged detection pads 221 are combined with the dielectric layer 300 to form a detection capacitor.

[0064] For details, see Figure 1 In the preparation process of the wafer 10, usually a piece of the wafer 10 will contain several to several thousand or even tens of thousands of chips, and cutting lanes will be set between adjacent chips to facilitate the subsequent chip segmentation. In this embodiment, the area occupied by the chips in the wafer 10 is called the wafer active area 20, and the area occupied by the cutting lanes is called the wafer cutting area 30, and the detection structure involved in the present application is preferably located in the wafer cutting area 30 to reduce the occupation of the effective area of ​​the wafer.

[0065] Among them, during the preparation process of the wafer 10, a pad will be set in the active area 20 of the wafer, such as the surface of the chip, to facilitate subsequent electrical connection. The material of the pad is preferably an aluminum pad or an aluminum alloy pad, but is not limited to this. During the preparation process, the surface of the pad will be covered with a passivation layer and other material layers. In order to avoid affecting the electrical performance, the material layer located on the surface of the pad needs to be etched to completely expose the conductive layer of the pad. In order to ensure that the surface of the pad is completely opened, over-etching is usually performed.

[0066] See also Figure 2 to Figure 5In this embodiment, in order to improve the detection of over-etching of the pad, while preparing the pad, the reference pad 211 and the first detection pad 212 in the reference unit, and the detection pad 221 and the second detection pad 222 in the detection unit are prepared in the wafer cutting area 30. The detection unit has the same morphology as the reference unit, the first detection pad 212 and the second detection pad 222 are needle test pads, and the reference pad 211 and the detection pad 221 are combined with the dielectric layer 300 to form a flat capacitor structure, that is, the reference pad 211 and the detection pad 221 can be regarded as the plates of a flat capacitor.

[0067] In the process of etching to expose the pad, since the dielectric layer 300 and the pad material have different etching selectivity ratios, the dielectric layer 300 is removed at a faster rate than the pad. For example, the dielectric layer 300 may include a silicon oxide dielectric layer, but is not limited thereto. Thus, through the dielectric layer detection window 302 in the dielectric layer 300, the dielectric layer 300 located in the detection capacitor will have a greater loss amount, so that according to the capacitance principle, the capacitance value of the detection capacitor will change, and since the dielectric layer 300 above the reference capacitor does not have The dielectric layer detection window 302, that is, the reference capacitor is covered by the dielectric layer 300, and the dielectric layer 300 in the reference capacitor is not etched during the etching process, so that the capacitance value of the reference capacitor will not change. Therefore, by comparing the capacitance values ​​corresponding to the reference capacitor and the detection capacitor obtained by the first detection pad 212 and the second detection pad 222, the over-etching situation of the pad can be known, so that the over-etching of the pad can be monitored by the change of electrical performance data, that is, the capacitance value, and the slicing operation can be avoided.

[0068] In this embodiment, the structure of the substrate 100 may include: Figure 2 and Figure 3 The bottom metal layer 101 and the metal pillar 102 are shown as being located in a passivation layer such as a silicon oxide layer, but are not limited thereto. Active or passive devices may be disposed in the substrate 100 as required, and no excessive limitation is imposed herein.

[0069] As an example, the reference unit and the detection unit may be located in a wafer edge cutting area at the same time, located in a wafer center cutting area at the same time, or distributed in the entire wafer cutting area at the same time.

[0070] Specifically, in response to the need for over-etching detection of the pads located in different areas on the wafer 10, the reference unit and the detection unit can be simultaneously set in the wafer edge cutting area, or simultaneously set in the wafer center cutting area, or simultaneously distributed in the entire wafer cutting area, without excessive restrictions here.

[0071] Furthermore, in order to improve the detection accuracy of the detection structure for over-etching of the pad, the reference unit, the detection unit and the pad to be detected are preferably arranged adjacent to each other, such as the reference unit and the detection unit are located in the wafer cutting area (cutting road) of adjacent chips to be tested. The specific spacing can be set as needed, and no excessive restrictions are made here.

[0072] Furthermore, when the detection capacitance values ​​of the detection capacitors located in different wafer cutting areas 30 are compared, the differences in wafer manufacturing processes in different areas, such as processing differences, can also be reflected, so as to optimize the wafer manufacturing process.

[0073] As an example, the dielectric layer inspection window 302 may expose the inspection pad 221 .

[0074] Specifically, as needed, when one wants to consider the etching condition of the pad metal more, the opening of the dielectric layer detection window 302 can be increased (to determine the amount of pad metal included); when one wants to reflect the etching condition of the pad through changes in the dielectric layer 300, the opening of the dielectric layer detection window 302 can be reduced. There is no excessive restriction on the specific size of the dielectric layer detection window 302, and the detection capacitance of the detection capacitor can be changed by changing the dielectric layer detection window 302.

[0075] like Figure 4 and Figure 5 The detection capacitance of the detection capacitor can also be changed by changing one or a combination of the thickness Y, length X, and spacing L of the two corresponding detection pads 221, or by changing the morphology of the detection pad 221 and the dielectric layer detection window 302 at the same time to change the detection capacitance of the detection capacitor. The specific settings can be made according to needs.

[0076] Embodiment 2

[0077] like Figure 6 This embodiment provides a method for preparing a pad overetching detection structure, which can be used to prepare the detection structure in Embodiment 1, but the preparation process of the detection structure is not limited thereto. In this embodiment, the following preparation process is used to prepare the above detection structure, so the description of the detection structure can refer to Embodiment 1, and will not be repeated here.

[0078] Specifically, the preparation method may include the following steps:

[0079] S1: providing a substrate, wherein the substrate comprises a wafer active area and a wafer cutting area;

[0080] S2: forming a reference unit and a detection unit having the same morphology on the wafer cutting area of ​​the substrate, and the reference unit and the detection unit are formed synchronously with the pad located in the active area of ​​the wafer, wherein the reference unit includes two reference pads arranged at intervals and a first detection pad connected to the reference pads in a one-to-one correspondence, and the detection unit includes two detection pads arranged at intervals and a second detection pad connected to the detection pads in a one-to-one correspondence;

[0081] S3: forming a dielectric layer on the substrate, wherein the dielectric layer covers the substrate, the reference unit and the detection unit;

[0082] S4: forming a mask layer on the dielectric layer, and patterning the mask layer;

[0083] S5: Etching the dielectric layer to form a dielectric layer detection window exposing the first detection pad and the second detection pad, and a dielectric layer detection window at least exposing the dielectric layer located between the detection pads, wherein the two corresponding reference pads combined with the dielectric layer constitute a reference capacitor, and the two corresponding detection pads combined with the dielectric layer constitute a detection capacitor.

[0084] Among them, a bottom metal layer and a metal column connected to the bottom metal layer may be formed in the substrate, but it is not limited thereto. Other active or passive devices may be arranged in the substrate as required, and no excessive restrictions are made here.

[0085] Embodiment 3

[0086] like Figure 7 This embodiment provides a method for detecting pad over-etching, which specifically includes the following steps:

[0087] Sa: providing the detection structure in embodiment 1;

[0088] Sb: in combination with the dielectric layer detection window, obtaining the reference capacitance of the reference capacitor through the first detection pad, and obtaining the detection capacitance of the detection capacitor through the second detection pad;

[0089] Sc: Compare the obtained reference capacitance value with the detection capacitance value to detect over-etching of the pad.

[0090] As an example, the method of changing the detection capacitance may include changing one or a combination of the thickness, length, spacing of the two corresponding detection pads and the size of the detection window. For details, please refer to Example 1, which will not be repeated here.

[0091] As an example, the method may further include comparing the detection capacitance values ​​of the detection capacitors located in different wafer cutting areas to reflect the differences in wafer process in different areas, such as processing differences.

[0092] As described above, the detection structure, preparation and detection method for pad over-etching of the present invention form a reference unit and a detection unit in the wafer cutting area, and combine the dielectric layer to form a reference capacitor and a detection capacitor. Since there is a dielectric layer detection window above the dielectric layer in the detection capacitor, and the detection pad and the dielectric layer have a large selective etching ratio, the dielectric layer in the detection capacitor is etched during the etching process, so that the capacitance of the detection capacitor changes. By monitoring the changes in the electrical performance data of the detection capacitor and the reference capacitor, that is, the capacitance value, the over-etching of the pad can be reflected, avoiding the need for slicing confirmation.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A detection structure for pad over-etching, characterized in that: The detection structure comprises: A substrate, the substrate comprising a wafer active area and a wafer cutting area; A reference unit, the reference unit is located in the wafer cutting area and is synchronously formed with the pad located in the wafer active area, the reference unit includes two reference pads arranged at intervals and a first detection pad connected to the reference pads in a one-to-one correspondence; A detection unit, the detection unit is located in the wafer cutting area, is synchronously formed with the pad located in the wafer active area, and the detection unit has the same morphology as the reference unit, and the detection unit includes two detection pads arranged at intervals and a second detection pad connected to the detection pads in a one-to-one correspondence; A dielectric layer, the dielectric layer is located on the substrate, covers the substrate, the reference unit and the detection unit, and has a dielectric layer detection window that exposes the first detection pad and the second detection pad, and a dielectric layer detection window that at least exposes the dielectric layer located between the detection pads, wherein the two corresponding reference pads are combined with the dielectric layer to form a reference capacitor, and the two corresponding detection pads are combined with the dielectric layer to form a detection capacitor.

2. The detection structure for pad over-etching according to claim 1, characterized in that: The reference unit and the detection unit are located at the edge cutting area of ​​the wafer, at the center cutting area of ​​the wafer, or distributed in the entire wafer cutting area.

3. The detection structure for pad over-etching according to claim 1, characterized in that: The reference unit and the detection unit are located in a wafer cutting area of ​​adjacent chips.

4. The detection structure for pad over-etching according to claim 1, characterized in that: The dielectric layer includes a silicon oxide dielectric layer; the pad includes an aluminum pad or an aluminum alloy pad.

5. The detection structure for pad over-etching according to claim 1, characterized in that: The dielectric layer inspection window exposes the inspection pad.

6. A method for preparing a pad over-etching detection structure, characterized in that: The following steps are involved: Providing a substrate, wherein the substrate includes a wafer active area and a wafer cutting area; A reference unit and a detection unit having the same morphology are formed on the wafer cutting area of ​​the substrate, and the reference unit and the detection unit are formed synchronously with the pad located in the active area of ​​the wafer, wherein the reference unit includes two reference pads arranged at intervals and a first detection pad connected to the reference pads in a one-to-one correspondence, and the detection unit includes two detection pads arranged at intervals and a second detection pad connected to the detection pads in a one-to-one correspondence; forming a dielectric layer on the substrate, wherein the dielectric layer covers the substrate, the reference unit and the detection unit; forming a mask layer on the dielectric layer, and patterning the mask layer; The dielectric layer is etched to form a dielectric layer detection window that exposes the first detection pad and the second detection pad, and a dielectric layer detection window that at least exposes the dielectric layer located between the detection pads, wherein the two corresponding reference pads are combined with the dielectric layer to form a reference capacitor, and the two corresponding detection pads are combined with the dielectric layer to form a detection capacitor.

7. The method for preparing a pad over-etching detection structure according to claim 6, characterized in that: A bottom metal layer and a metal column connected to the bottom metal layer are also formed in the substrate.

8. A method for detecting pad over-etching, characterized in that: The following steps are involved: Providing a detection structure as described in any one of claims 1 to 5; In combination with the dielectric layer detection window, a reference capacitance of the reference capacitor is obtained through the first detection pad, and a detection capacitance of the detection capacitor is obtained through the second detection pad; The obtained reference capacitance value is compared with the detection capacitance value to detect over-etching of the pad.

9. The method for detecting pad over-etching according to claim 8, characterized in that: The method for changing the detection capacitance includes changing one or a combination of the thickness, length, and spacing of the two corresponding detection pads and the size of the dielectric layer detection window.

10. The method for detecting pad over-etching according to claim 8, characterized in that: The method also includes a step of comparing the detection capacitance values ​​of the detection capacitors located in different wafer cutting areas to reflect the differences in wafer process in different areas.

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