Semiconductor package and manufacturing method thereof

Abstract

Semiconductor package and method of manufacturing the same. The present invention provides a semiconductor package and a method of manufacturing the same. As non-limiting examples, various aspects of the present invention provide a semiconductor package and a method of manufacturing the same, comprising shielding on multiple sides thereof.

Description

[0001] Cross-reference to related applications / incorporation by reference

[0002] This application references, claims priority from, and claims the benefit of Korean Patent Application No. 10-2015-0159058, filed on November 12, 2015, in the Korean Intellectual Property Office, entitled “Semiconductor package and method of manufacturing the same,” the contents of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The present invention relates to a semiconductor package and a method for manufacturing the same. Background Art

[0004] Current semiconductor packages and methods for forming semiconductor packages are inadequate, for example, resulting in excessive cost, reduced reliability, inadequate shielding, excessive package size, etc. Additional limitations and disadvantages of such methods will become apparent to those skilled in the art by comparing conventional and traditional methods with the present invention as set forth with reference to the drawings in the remainder of this disclosure. Summary of the Invention

[0005] Various aspects of the present invention provide a semiconductor package and a method of manufacturing a semiconductor package. As non-limiting examples, various aspects of the present invention provide a semiconductor package and a method of manufacturing a semiconductor package that include shielding on multiple sides thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0007] Figure 2 Is used to manufacture Figure 1 A flow chart of a method for semiconductor packaging is described in detail.

[0008] Figures 3A to 3E Is used to manufacture Figure 2 sectional views of various steps of the semiconductor packaging method described in .

[0009] Figure 4 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.

[0010] Figure 5A and 5B Is explained through Figure 2 The semiconductor package manufacturing method described in Figure 4 sectional views of various steps in semiconductor packaging described in .

[0011] Figure 6Shown in the description Figure 5A Plan view and cross-sectional view of the structure of the clamp described in.

[0012] Figure 7 This is a method for manufacturing a device according to another embodiment of the present invention. Figure 4 A flow chart of a method for semiconductor packaging is described in detail.

[0013] Figures 8A to 8C Is used to manufacture Figure 7 sectional views of various steps of the semiconductor packaging method described in . DETAILED DESCRIPTION

[0014] The following discussion presents various aspects of the present invention by providing examples. Such examples are non-limiting, and thus the scope of various aspects of the present invention should not necessarily be limited by any particular features of the examples provided. In the following discussion, the phrases "for example," "for example," and "exemplary" are non-limiting and generally synonymous with "by way of example and not limitation," "by way of example and not limitation," and the like.

[0015] As used herein, “and / or” means any one or more of the items in the list linked by “and / or”. As an example, “x and / or y” means any element in the three-element set {(x), (y), (x, y)}. In other words, “x and / or y” means “one or both of x and y”. As another example, “x, y and / or z” means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and / or z” means “one or more of x, y and z”.

[0016] The terms used herein are for the purpose of describing specific examples only and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will be further understood that the terms "comprises," "comprising," "having," etc., when used in this specification, represent the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0017] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of the present invention, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part. Similarly, various spatial terms, such as "upper," "lower," "side," etc., may be used to distinguish one element from another in a relative manner. However, it should be understood that the components can be oriented in different ways, for example, without departing from the teachings of the present invention, the semiconductor device can be rotated sideways so that its "top" surface is horizontally oriented and its "side" surface is vertically oriented.

[0018] In the drawings, the thickness or size of layers, regions and / or components may be exaggerated for clarity. Therefore, the scope of the present invention should not be limited by such thickness or size. In addition, in the drawings, similar reference numerals may refer to similar elements throughout the discussion.

[0019] Furthermore, it should be understood that when element A is referred to as being “connected to” or “coupled to” element B, element A may be directly connected to element B or indirectly connected to element B (e.g., intervening element C (and / or other elements) may be present between element A and element B).

[0020] Certain embodiments of the present invention relate to semiconductor packages and methods of manufacturing the same.

[0021] Various electronic devices for exchanging signals and a plurality of semiconductor packages manufactured in various structures are integrated in various electronic systems, and thus electromagnetic interference (EMI) may inevitably be generated when the semiconductor packages and the electronic devices are electrically operated.

[0022] EMI can be generally defined as the resultant radiation of electric and magnetic fields. EMI can be generated by electric fields formed by current flowing in conductive materials and magnetic fields.

[0023] If EMI is generated from semiconductor packages and electronic devices densely packed on a motherboard, other adjacent semiconductor packages may be directly or indirectly affected by the EMI and may be damaged.

[0024] Various aspects of the present invention provide a semiconductor package and a method of manufacturing the same that can prevent bending by forming a molded article on both surfaces of a substrate and can shield electromagnetic interference (EMI) by forming an EMI shielding layer to cover the molded article and the substrate.

[0025] According to one aspect of the present invention, a semiconductor package is provided, comprising: a substrate having a first surface and a second surface opposite to the first surface; at least one first electronic device formed on the first surface and electrically connected to the substrate; a first molded article formed on the first surface to cover the first electronic device; a second molded article formed to cover the second surface; a plurality of first conductive bumps formed on the second surface and electrically connected to the substrate and passing through the second molded article; an electromagnetic interference (EMI) shielding layer formed to surround a surface of the substrate, the first molded article, and the second molded article to be spaced apart from the first conductive bumps; and a plurality of second conductive bumps formed on one surface of the second molded article to be electrically connected to the plurality of first conductive bumps, respectively.

[0026] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, the semiconductor package comprising: a substrate having a first surface and a second surface opposite to the first surface; at least one first electronic device formed on the first surface and electrically connected to the substrate; and a plurality of first conductive bumps formed on the second surface and electrically connected to the substrate, the method comprising: forming a first mold on the first surface to cover the first electronic device and forming a second mold on the second surface to cover the first conductive bumps; grinding the second mold to expose the plurality of first conductive bumps to the outside; forming a plurality of second conductive bumps electrically connected to the exposed plurality of first conductive bumps respectively; placing a fixture under the second mold to surround the plurality of second conductive bumps; and forming an EMI shielding layer to cover the surface of the substrate, the first mold, and the second mold, the surface of the substrate, the first mold, and the second mold being exposed to the outside through the fixture.

[0027] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, which includes: a substrate having a first surface and a second surface opposite to the first surface; at least one first electronic device formed on the first surface and electrically connected to the substrate; and a plurality of first conductive bumps formed on the second surface and electrically connected to the substrate, the method including: forming a first molded product on the first surface to cover the first electronic device and forming a second molded product on the second surface to cover the first conductive bumps; grinding the second molded product to expose the plurality of first conductive bumps to the outside; forming an EMI shielding layer to completely cover the surface of the substrate, the first molded product, and the second molded product; forming a plurality of exposure holes in the EMI shielding layer to expose the plurality of first conductive bumps to the outside; and forming a plurality of second conductive bumps, which are electrically connected to the exposed plurality of first conductive bumps through the plurality of exposure holes, respectively.

[0028] As described above, in the semiconductor package and the manufacturing method thereof according to the present invention, bending can be prevented by forming a molded article on both surfaces of a substrate and electromagnetic interference (EMI) can be shielded by forming an EMI shielding layer to cover the molded article and the substrate.

[0029] Further embodiments, features, and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] refer to Figure 1 , a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention is shown.

[0031] like Figure 1 As illustrated in FIG, the semiconductor package 100 includes a substrate 110 , a first electronic device 120 , a second electronic device 130 , a first mold 140 , a second mold 150 , a first conductive bump 160 , a second conductive bump 170 , and an electromagnetic interference (EMI) shielding layer 180 .

[0032] The substrate 110 is formed as a panel having a first surface 110a and a second surface 110b opposite to the first surface 110a. Here, the first surface 110a of the substrate 110 may be a top surface, and the second surface 110b may be a bottom surface, and vice versa. The substrate 110 includes a plurality of first line patterns 111 formed on the first surface 110a and a plurality of second line patterns 112 formed on the second surface 110b. In addition, the substrate 110 may further include a plurality of conductive patterns 113 electrically connecting the first line patterns 111 formed on the first surface 110a of the substrate 110 and the second line patterns 112 formed on the second surface 110b. The conductive patterns 113 may be configured to penetrate or partially penetrate between the first surface 110a and the second surface 110b of the substrate 110 to connect the plurality of line patterns formed by the plurality of layers. That is, in the case where the substrate 110 is a single layer, the conductive pattern 113 may directly connect the first line pattern 111 and the second line pattern 112 or may use an additional line pattern to connect the first line pattern 111 and the second line pattern 112. That is, the first line pattern 111, the second line pattern 112, and the conductive pattern 113 of the substrate 110 may be implemented in various structures and types, but aspects of the present invention are not limited thereto.

[0033] (Multiple) first electronic devices 120 are mounted on the first surface 110a of the substrate 110 to be electrically connected to the first line pattern 111 of the substrate 110. (Multiple) first electronic devices 120 may include semiconductor dies 121 and passive components 122, which may be modified in various ways according to the type of semiconductor package 100, but aspects of the present invention are not limited thereto. In the following description, (multiple) first electronic devices 120 including two semiconductor dies 121 and two passive components 122 will be described by way of example. In addition, the semiconductor die 121 is formed in a flip-chip type and may be mounted so that the conductive bumps of the semiconductor die 121 are soldered to the first line pattern 111 of the substrate 110. The semiconductor die 121 may include bonding pads and may be connected to the first line pattern 111 by wire bonding. However, the present invention does not limit the connection relationship between the semiconductor die 121 and the first line pattern 111 to that disclosed herein.

[0034] The second electronic device(s) 130 are mounted on the second surface 110b of the substrate 110 to be electrically connected to the second line pattern 112 formed on the substrate 110. The second electronic device(s) 130 are described as being composed of a single semiconductor die. However, the second electronic device(s) 130 may be composed of a plurality of semiconductor dies or may further include passive elements, but aspects of the present invention are not limited thereto.

[0035] The first molded article 140 may be formed on the first surface 110a of the substrate 110 to cover the first electronic device 120 mounted on the first surface 110a of the substrate 110. The first molded article 140 may be made of a general molding compound resin, such as an epoxy-based resin, but the scope of the present invention is not limited thereto. The first molded article 140 may protect the first electronic device 120 from external conditions.

[0036] The second molding 150 may be formed on the second surface 110b of the substrate 110 to cover the second electronic device 130 mounted on the second surface 110b of the substrate 110. The second molding 150 exposes the first conductive bumps 160 formed on the second surface 110b of the substrate 110 to the outside while completely covering the second electronic device 130. The second molding 150 and the first conductive bumps 160 may have the same height. The second molding 150 and the first molding 140 may be made of the same material. The second molding 150 may protect the second electronic device 130 from external influences.

[0037] The first conductive bumps 160 may include a plurality of first conductive bumps formed on the second surface 110b of the substrate 110 to electrically connect to the second line pattern 112 formed on the substrate 110. The first conductive bumps 160 are configured such that their side portions are surrounded by the second mold 150 and portions of their bottom surfaces are exposed to the outside through the second mold 150. The exposed first conductive bumps 160 are electrically connected to the second conductive bumps 170. In other words, the first conductive bumps 160 electrically connect the second conductive bumps 170 and the second line pattern 112 formed on the substrate 110. The first conductive bumps 160 may include conductive pillars, copper pillars, conductive balls, or copper balls, but aspects of the present invention are not limited thereto.

[0038] The second conductive bumps 170 may be formed on the bottom surface of the second mold 150 to be electrically connected to the first conductive bumps 160 exposed to the outside through the second mold 150. In the case where the semiconductor package 100 is mounted on an external device (e.g., a motherboard), the second conductive bumps 170 may be used to electrically connect the semiconductor package 100 to the external device.

[0039] The EMI shielding layer 180 can be formed to a predetermined thickness sufficient to completely cover the semiconductor package 100, excluding the bottom surface of the second molded article 150. That is, the EMI shielding layer 180 is formed to cover the entire top surface and four side surfaces of the semiconductor package 100. In addition, the EMI shielding layer 180 can be made of a conductive material and can be electrically connected to the ground or external ground of the semiconductor package 100. The EMI shielding layer 180 can shield EMI induced to the semiconductor package 100 (or generated by the semiconductor package 100). In addition, the semiconductor package 100 can include a first mold 140 and a second mold 150 to cover both the first surface 110a and the second surface 110b of the substrate 110, thereby preventing the semiconductor package 100 from warping, which may occur when the molded article is formed on only one surface of the substrate 110.

[0040] refer to Figure 2 , shows the instructions for making Figure 1 A flow chart of a method for semiconductor packaging is shown in FIG. Figure 2 As described in , the method ( S10 ) of manufacturing the semiconductor package 100 includes forming a molded product ( S11 ), grinding a second molded product ( S12 ), forming a second conductive bump ( S13 ), placing a jig ( S14 ), and forming an EMI shielding layer ( S15 ).

[0041] refer to Figures 3A to 3E , shows the instructions for making Figure 2 sectional views of various steps of a method for semiconductor packaging are illustrated in FIG.

[0042] First, before forming a molded product (S11), a first electronic device 120 is mounted on a first surface 110a of a substrate 110 to be electrically connected to a first line pattern 111, a second electronic device 130 is mounted on a second surface 110b of the substrate 110 to be electrically connected to a second line pattern 112, and a plurality of first conductive bumps 160 are subsequently formed on the second surface 110b of the substrate 110 to be electrically connected to the second line pattern 112.

[0043] like Figure 3A As described in the foregoing, in forming the molded product (S11), the first molded product 140 is formed to cover the first surface 110a of the substrate 110 and the first electronic device 120, and the second molded product 150 is formed to cover the second surface 110b of the substrate 110, the second electronic device 130, and the plurality of first conductive bumps 160. The first molded product 140 and the second molded product 150 can be formed simultaneously. For example, a mold is placed around the substrate 110, including the first electronic device 120, the second electronic device 130, and the first conductive bumps 160, and a molding resin is injected into the space in the mold, thereby forming the first molded product 140 and the second molded product 150 at the same time. Here, the molding resin is injected into the mold in a state where the first electronic device 120, the second electronic device 130, the first conductive bumps 160, and the substrate 110 are spaced apart from the inner surface of the mold so as not to contact the inner surface of the mold, thereby forming the first molded product 140 and the second molded product 150. That is, the first mold 140 is formed to completely cover the first surface 110 a of the substrate 110 and the first electronic device 120 , and the second mold 150 is formed to completely cover the second surface 110 b of the substrate 110 , the second electronic device 130 , and the first conductive bumps 160 .

[0044] like Figure 3B As described in the figure, in the grinding (S12) of the second molded product, the bottom surface of the second molded product 150 is ground to expose the first conductive bump 160 to the outside of the second molded product 150. That is, in the grinding (S12) of the second molded product, the second molded product 150 is ground to expose the first conductive bump 160 to the outside. At this time, the bottom portion of the first conductive bump 160 may also be partially ground. The bottom surface of the first conductive bump 160 and the bottom surface of the second molded product 150 may be coplanar. In addition, the second electronic device 130 may be placed in the second molded product 150, and the second electronic device 130 may not be exposed to the outside, for example. The grinding can be performed using, for example, a diamond grinder and its equivalent, but aspects of the present invention are not limited thereto.

[0045] like Figure 3CAs described in the above, in the formation of the second conductive bumps (S13), a plurality of second conductive bumps 170 are formed to be electrically connected to the plurality of first conductive bumps 160 that are exposed to the outside in the grinding (S12) of the second molded product. The second conductive bumps 170 can be formed using ball dropping, screen printing, electroplating, vacuum evaporation, plating, and equivalents thereof, but aspects of the present invention are not limited thereto. In addition, the second conductive bumps 170 can be made of a metal material, for example, lead / tin (Pb / Sn) or lead-free Sn, and equivalents thereof, but aspects of the present invention are not limited thereto.

[0046] like Figure 3D As described in the above, in the placement of the jig (S14), the jig 10 is loaded and placed to cover the bottom surface 150b of the second molded product 150. The jig 10 is shaped as a substantially rectangular frame and may have an internal space 11 and a flat portion 12, the internal space having a predetermined depth in the top-to-bottom direction, the flat portion extending outwardly along the outer circumference by a predetermined length. The flat portion 12 may be brought into contact with the outer circumference of the bottom surface 150b of the second molded product 150 to be subsequently fixed, and the second conductive bump 170 formed on the bottom surface 150b of the second molded product 150 may be inserted into the internal space 11. That is, in the placement of the jig (S14), the jig 10 is placed to cover the bottom surface 150b of the second molded product 150, and the first molded product 140, the side surface of the substrate 110, and the side surface of the second molded product 150 are exposed to the outside.

[0047] like Figure 3E As described in the foregoing, during the formation of the EMI shielding layer (S15), EMI shielding layer 180 is formed on first molded product 140, the side surfaces of substrate 110, and the side surfaces of second molded product 150, which are exposed to the outside during the placement of the jig (S14). EMI shielding layer 180 is formed to completely cover all of first molded product 140, the side surfaces of substrate 110, and the side surfaces of second molded product 150, except for the bottom surface 150b of second molded product 150, which is covered by jig 10. In other words, EMI shielding layer 180 is formed to completely cover the four side surfaces and the top surface of semiconductor package 100, except for the bottom surface of semiconductor package 100. EMI shielding layer 180 can be formed to a predetermined thickness by plasma deposition or spraying, but aspects of the present invention are not limited thereto. Furthermore, after forming the EMI shielding layer (S15), cleaning may be performed to remove metal residue produced during the formation of EMI shielding layer 180 made of a conductive material. In addition, after the EMI shielding layer 180 is formed and cleaning is performed, the jig 10 placed under the second molded product 150 is separated to complete the semiconductor package 100 having the EMI shielding layer 180. Figures 3A to 3EIn the present invention, a single semiconductor package 100 is manufactured, but a plurality of semiconductor packages may be formed on the substrate 110 to be subsequently divided into discrete semiconductor packages 100 through a separation process.

[0048] refer to Figure 4 , a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention is shown.

[0049] like Figure 4 As described in FIG, the semiconductor package 200 includes a substrate 110, a first electronic device 120, a second electronic device 130, a first molded product 140, a second molded product 150, a first conductive bump 160, a second conductive bump 170, and an EMI shielding layer 280. The semiconductor package 200 including the substrate 110, the first electronic device 120, the second electronic device 130, the first molded product 140, the second molded product 150, the first conductive bump 160, and the second conductive bump 170 has the same Figure 1 Therefore, the following description of the semiconductor package 200 will focus on the EMI shielding layer 280, which is the same as the semiconductor package 100 described in FIG. Figure 1 The different features of the semiconductor package 100 are described in detail.

[0050] The EMI shielding layer 280 is formed to cover the top surface, four side surfaces, and bottom surface of the semiconductor package 200 to a predetermined thickness and can expose the second conductive bumps 170 to the outside. That is, the EMI shielding layer 280 can be formed to completely cover the semiconductor package 200 except for the second conductive bumps 170. In addition, the EMI shielding layer 280 can be made of a conductive material and can be electrically connected to the ground of the semiconductor package 200 or an external ground.

[0051] The EMI shielding layer 280 may include a plurality of exposure holes 280 a. The second conductive bumps 170 may be exposed to the outside of the EMI shielding layer 280 through the exposure holes 280 a. That is, the exposure holes 280 a of the EMI shielding layer 280 may be positioned to correspond to the second conductive bumps 170.

[0052] In addition, the exposure hole 280a may have a width greater than the diameter of the second conductive bump 170. That is, the EMI shielding layer 280 may be spaced apart from the second conductive bump 170 by a predetermined distance (d) through the exposure hole 280a and may be electrically disconnected from the second conductive bump 170 made of a conductive material. Here, a portion surrounding the second conductive bump 170 in the second molded product 150 may be exposed to the outside of the exposure hole 280a of the EMI shielding layer 280.

[0053] The EMI shielding layer 280 is formed to cover the entire surface of the semiconductor package 200 except for the second conductive bumps 170 serving as external terminals, thereby shielding EMI induced by (or on) the semiconductor package 200 .

[0054] Figure 4 The semiconductor package 200 described in the embodiment can be Figure 2 The semiconductor package manufacturing method described in the reference Figure 5A and 5B , shows the instructions for Figure 2 The semiconductor package manufacturing method described in Figure 4 The following is a cross-sectional view of each step in the method of semiconductor packaging described in Figure 2 、 5A 5B describe a method for manufacturing the semiconductor package 200 .

[0055] like Figure 2 As described in the , the method (S10) of manufacturing the semiconductor package 200 includes forming a molded product (S11), grinding a second molded product (S12), forming a second conductive bump (S13), placing a jig (S14), and forming an EMI shielding layer (S15). Here, the forming of the molded product (S11), grinding the second molded product (S12), and forming the second conductive bump (S13) are similar to those in Figures 3A to 3C The corresponding steps in the method for manufacturing the semiconductor package 100 are the same as those described in Figure 5A and 5B The following description of the method (S10) for manufacturing the semiconductor package 200 will focus on the placement of the jig (S14) and the formation of the EMI shielding layer (S15), which are related to the Figures 3A to 3C The method for manufacturing the semiconductor package 100 described in detail herein has different features.

[0056] like Figure 5A As described in FIG. 1 , in the placement of the jig ( S14 ), the jig 20 is loaded and placed to cover the bottom portion of the second molded product 150 . Figure 6 As described in the drawing, the jig 20 is shaped as a substantially rectangular frame and may have a plurality of grooves 21 having a depth from top to bottom. The jig 20 may include a plurality of grooves 21 positioned to correspond to the second conductive bumps 170 of the semiconductor package 200, and the second conductive bumps 170 may be inserted into the plurality of grooves 21 accordingly. That is, the second conductive bumps 170 may be surrounded by the jig 20. Here, in order to allow the second conductive bumps 170 to enter the plurality of grooves 21 of the jig 20, the plurality of grooves 21 preferably have a larger diameter than the second conductive bumps 170.

[0057] In addition, the jig 20 is formed into a rectangular ring, the center portion of which is opened by a hole 22 formed in the center. That is, the center portion of the bottom surface 150b of the second molded product 150 that is not adjacent to (or in close proximity to) the second conductive bump 170 is exposed to the outside through the hole 22 of the jig 20. The EMI shielding layer 280 can also be formed on the bottom surface of the semiconductor package 200 through the hole 22 of the jig 20.

[0058] In the placement of the jig ( S14 ), the jig 20 is placed under the second mold 150 to cover the second conductive bumps 170 and expose the first mold 140 , the substrate 110 , and the second mold 150 to the outside.

[0059] like Figure 5B As described in the foregoing, during the EMI shielding layer formation (S15), EMI shielding layer 280 is formed on first molded product 140, substrate 110, and second molded product 150, which are exposed to the outside during the placement of the jig (S14). Specifically, during the EMI shielding layer formation (S15), jig 20 is used as a mask, and EMI shielding layer 280 is formed to cover the top surface, four side surfaces, and bottom surface of semiconductor package 200, excluding second conductive bumps 170. EMI shielding layer 280 may be formed to a predetermined thickness by plasma deposition or spraying, but aspects of the present invention are not limited thereto. Furthermore, after forming EMI shielding layer 280 (S15), cleaning may be performed to remove metal residue produced during the formation of EMI shielding layer 280 made of a conductive material. Furthermore, after forming EMI shielding layer 280 and performing cleaning, jig 20, which is placed under second molded product 150, is detached to complete semiconductor package 200 having EMI shielding layer 280. In addition, once the jig 20 is separated, since the EMI shielding layer 280 is not formed on the second conductive bump 170 and the portion surrounding the second conductive bump 170 surrounded by the jig 20, the exposure hole 280a exposing the second conductive bump 170 is provided in the EMI shielding layer 280. Subsequently, the EMI shielding layer 280 can be electrically cut off from the second conductive bump 170 through the exposure hole 280a and can be spaced apart from the second conductive bump 170 by a predetermined distance (d).

[0060] refer to Figure 7 , showing an example of a method for manufacturing a Figure 4 A flow chart of a method for semiconductor packaging is shown in FIG. Figure 7 As described in , the method (S20) for manufacturing the semiconductor package 200 includes forming a molded product (S11), grinding a second molded product (S12), forming an EMI shielding layer (S23), forming an exposure hole (S24), and forming a second conductive bump (S25). Here, Figure 7 The forming of the molded product (S11) and the grinding of the second molded product (S12) are described in Figure 2 、 3A These steps are the same as the corresponding steps in the method for manufacturing the semiconductor package 100 described in FIG3B .

[0061] refer to Figures 8A to 8C , shows the description Figure 7 sectional view of the steps of forming an EMI shielding layer (S23), forming an exposure hole (S24) and forming a second conductive bump (S25). Figure 7 and 8A 8C describe a method ( S20 ) for manufacturing the semiconductor package 200 .

[0062] like Figure 8A As described in the forming of the EMI shielding layer (S23), the EMI shielding layer 280 is formed to completely cover the substrate 110, the first molded product 140, and the second molded product 150. The EMI shielding layer 280 may be formed to a predetermined thickness by plasma deposition or spraying, but aspects of the present invention are not limited thereto.

[0063] like Figure 8B As described in , in the formation of the exposure holes (S24), the EMI shielding layer 280 can be partially removed to expose the first conductive bump 160 to the outside. That is, the first conductive bump 160 is exposed to the outside by forming a plurality of exposure holes 280a in the EMI shielding layer 280. The plurality of exposure holes 280a of the EMI shielding layer 280 are formed by etching or laser removing a portion of the EMI shielding layer 280. In addition, the formation of the exposure holes 280a can be performed by any process known in the art, as long as the EMI shielding material can be patterned into a desired pattern, but is not limited to the etching or laser disclosed herein. Figure 8B As described in FIG, the width (d1) of each exposure hole 280a is preferably greater than the diameter (d2) of each first conductive bump 160. In order to electrically disconnect the first conductive bump 160 from the second conductive bump 170 as described later, the exposure hole 280a is preferably formed to have a sufficiently large width (i.e., d1). In addition, after forming the exposure hole 280a, a cleaning process for removing metal residues may be additionally performed.

[0064] like Figure 8CAs described in the above, in the formation of the second conductive bump (S25), the second conductive bump 170 is formed to be electrically connected to the first conductive bump 160 exposed to the outside through the exposure hole 280a. The second conductive bump 170 is preferably formed to have a larger diameter (d3) than the width (d1) of the exposure hole 280a. That is, the second conductive bump 170 can be spaced apart from the EMI shielding layer 280 by a predetermined distance to be electrically disconnected from the EMI shielding layer 280.

[0065] The discussion herein includes numerous illustrative figures illustrating various parts of electronic packaging assemblies and methods of making the same. For clarity, these figures do not illustrate all aspects of each example assembly. Any example assembly and / or method provided herein may share any or all features with any or all other assemblies and / or methods provided herein.

[0066] In summary, various aspects of the present invention provide a semiconductor package and a method for manufacturing a semiconductor package. As non-limiting examples, various aspects of the present invention provide a semiconductor package and a method for manufacturing a semiconductor package, the method including shielding on multiple sides thereof. Although the above has been described with reference to certain aspects and examples, it will be understood by those skilled in the art that various modifications may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt specific circumstances or materials to the teachings of the present invention without departing from the scope of the present invention. Therefore, it is intended that the present invention not be limited to the specific examples disclosed, but that the present invention will include all examples that fall within the scope of the appended claims.

Claims

1. A semiconductor package, characterized in that: include: A substrate comprising: a substrate top side including a first substrate top pad and a second substrate top pad; A substrate bottom side including a first substrate bottom pad and a second substrate bottom pad; and lateral side of the substrate; a first electronic device located on the substrate top side and coupled to the first substrate top pad, wherein the first electronic device comprises: a first device bottom side facing the substrate top side; first device top side; and a first device lateral side; a passive component located on the substrate top side and coupled to the second substrate top pad; a first encapsulation encapsulating at least the substrate top side, the passive components, and the first electronic device, wherein the first encapsulation comprises: a first encapsulation bottom side facing the substrate top side; first enclosure top side; and a first envelope lateral side; a second electronic device located on the substrate bottom side and coupled to the first substrate bottom pad, wherein the second electronic device comprises: a second device top side facing the substrate bottom side; second device bottom side; and a second device lateral side; an external interconnect located on the bottom side of the substrate and comprising: an upper interconnect terminal coupled to the second substrate bottom pad; and lower interconnect end; a second encapsulation member encapsulating at least the bottom side of the substrate and the second electronic device, wherein the second encapsulation member comprises: a second encapsulation top side facing the substrate bottom side; second enclosure bottom side; and The second envelope lateral side, wherein the lower interconnecting member ends below a bottom side of the second enclosure; and Electromagnetic interference shielding, which defines at least: the top side of the first enclosure; said first enclosure lateral side; and The lateral side of the substrate, wherein the electromagnetic interference shield is spaced apart from the external interconnect.

2. The semiconductor package according to claim 1, wherein The first device lateral side is vertically longer than the second device lateral side.

3. The semiconductor package according to claim 1, wherein: said first envelope comprising a first layer of molding material; and The second encapsulant includes a second layer of the molding material.

4. The semiconductor package according to claim 1, wherein The external interconnect comprises: an enclosure portion bounded by and contacted by the first portion of the second enclosure; and A protruding portion lower than the bottom side of the second packaging member.

5. The semiconductor package according to claim 1, wherein The electromagnetic interference shield includes a continuous conformal coating that conforms to respective contours of the first enclosure top side, the first enclosure lateral sides, the substrate lateral sides, and the second enclosure lateral sides.

6. A semiconductor package, characterized in that: include: A substrate comprising: a substrate top side including a first substrate top pad and a second substrate top pad; a substrate bottom side including a third substrate pad and a substrate interconnect pad; and lateral side of the substrate; a first device located on the substrate top side and coupled to the first substrate top pad, wherein the first device comprises: a first device bottom side facing the substrate top side; first device top side; and a first device lateral side; a second device located on the substrate top side and coupled to the second substrate top pad; a first encapsulation enclosing at least the substrate top side, the first device, and the second device, wherein the first encapsulation comprises: a first encapsulation bottom side facing the substrate top side; first enclosure top side; and a first envelope lateral side; a third device located on the bottom side of the substrate and coupled to the third substrate pad, wherein the third device comprises: a third device top side facing the substrate bottom side; a third device bottom side; and a third device lateral side; an interconnect located on the substrate bottom side and coupled to the substrate interconnect pad, wherein the interconnect provides an external interface to the semiconductor package and comprises: an upper interconnect terminal coupled to the substrate interconnect pad; and lower interconnect end; a second enclosure enclosing at least a portion of each of the substrate bottom side and the third device, wherein the second enclosure comprises: a second encapsulation top side facing the substrate bottom side; second enclosure bottom side; and a second envelope lateral side, and Electromagnetic interference shielding, which defines at least: the top side of the first enclosure; said first enclosure lateral side; and The lateral side of the substrate, in: The lower interconnection member end is lower than the bottom side of the second encapsulating member; At least one of the first device, the second device, or the third device is an electronic device; and At least one of the first device, the second device, or the third device is a passive component.

7. The semiconductor package according to claim 6, wherein: said first envelope comprising a first layer of molding material; and The second encapsulant includes a second layer of the molding material.

8. The semiconductor package according to claim 6, wherein The interconnect comprises: an enclosure portion bounded by and contacted by the first portion of the second enclosure; and A protruding portion lower than the bottom side of the second packaging member.

9. The semiconductor package according to claim 6, wherein: The electromagnetic interference shield includes a continuous conformal coating that conforms to respective contours of the first enclosure top side, the first enclosure lateral sides, the substrate lateral sides, and the second enclosure lateral sides.

10. The semiconductor package according to claim 6, wherein The first device lateral side is vertically longer than the third device lateral side.

11. A semiconductor package, characterized in that: include: a substrate comprising a substrate top side, a substrate bottom side, and substrate lateral sides; a first electronic device coupled to the top side of the substrate, wherein the first electronic device comprises: a first device bottom side facing the substrate top side; first device top side; and a first device lateral side; a passive component coupled to the top side of the substrate; a first encapsulation encapsulating at least the substrate top side, the passive components, and the first electronic device, wherein the first encapsulation comprises: a first encapsulation bottom side facing the substrate top side; first enclosure top side; and a first envelope lateral side; a second electronic device coupled to the bottom side of the substrate, wherein the second electronic device comprises: a second device top side facing the substrate bottom side; second device bottom side; and a second device lateral side; an external interconnect located on the bottom side of the substrate and comprising: a first interconnect portion having an upper interconnect end coupled to a bottom side of the substrate; and a second interconnect portion having a lower interconnect end; a second encapsulation member encapsulating at least the bottom side of the substrate and the second electronic device, wherein the second encapsulation member comprises: a second encapsulation top side facing the substrate bottom side; second enclosure bottom side; and The second envelope lateral side, wherein the lower interconnecting member ends below a bottom side of the second enclosure; and Electromagnetic interference shielding, which defines at least: the top side of the first enclosure; said first enclosure lateral side; and The substrate has lateral sides.

12. The semiconductor package according to claim 11, wherein The first device lateral side is vertically longer than the second device lateral side.

13. The semiconductor package according to claim 11, wherein: said first envelope comprising a first layer of molding material; and The second encapsulant includes a second layer of the molding material.

14. The semiconductor package according to claim 11, wherein: The first interconnect portion is bounded by and contacts the first portion of the second enclosure; and The second interconnect portion is lower than the second enclosure bottom side.

15. The semiconductor package according to claim 11, wherein The electromagnetic interference shield includes a continuous conformal coating that conforms to respective contours of the first enclosure top side, the first enclosure lateral sides, the substrate lateral sides, and the second enclosure lateral sides.

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