Method of forming a semiconductor element

Abstract

A method of forming a semiconductor device includes providing a substrate having a first device region and a second device region; depositing a metal nitride barrier layer covering the first device region and the second device region; depositing a titanium layer on the metal nitride barrier layer; selectively removing the titanium layer from the second device region, thereby exposing the metal nitride barrier layer in the second device region; and converting the titanium layer in the first device region to a titanium nitride layer, wherein the titanium nitride layer is a work function layer in the first device region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming semiconductor devices. Background Technology

[0002] Advanced complementary metal-oxide-semiconductor (CMOS) devices commonly employ metal gates to avoid polysilicon losses and boron infiltration effects. The choice of the specific metal used as the gate material is influenced by many factors, such as the desired work function and resistivity, the type of gate dielectric layer, and the thermal budget that the gate metal is expected to withstand. In dual-metal / dual-work-function CMOS fabrication methods, gate metals suitable for p-FETs (high work function) and those suitable for n-FETs (low work function) are typically used respectively.

[0003] Typically, the metal gate of a CMOS device consists of one or more layers of pure metal or alloy, metal or metal alloy silicide, or conductive oxide or silicide containing metal, with at least one of these layers in contact with the gate dielectric layer. A double-layer metal gate includes, for example, a thin bottom "capping" or "work function setting" layer (in contact with the underlying gate dielectric layer) and a thick upper "fill layer" that provides good conductivity.

[0004] For example, one existing approach is to first form a tantalum nitride barrier layer, then deposit a titanium nitride layer on the tantalum nitride barrier layer as a P work function layer, then cover the PMOS region with a photoresist layer, then remove the titanium nitride layer in the NMOS region by etching, and then perform the deposition of the N work function layer, etc. However, the disadvantage of the above approach is that when removing the titanium nitride layer in the NMOS region by etching, titanium nitride residue may be generated. In addition, removing the titanium nitride layer in the NMOS region by etching is prone to damaging the underlying tantalum nitride barrier layer. Summary of the Invention

[0005] The main objective of this invention is to provide a method for manufacturing semiconductor devices to overcome the shortcomings and disadvantages of the prior art.

[0006] The present invention provides a method for forming a semiconductor device, comprising: providing a substrate having a first device region and a second device region; depositing a metal nitride barrier layer covering the first device region and the second device region; depositing a titanium layer on the metal nitride barrier layer; selectively removing the titanium layer from the second device region to expose the metal nitride barrier layer in the second device region; and converting the titanium layer in the first device region into a titanium nitride layer, wherein the titanium nitride layer is a work function layer in the first device region.

[0007] According to an embodiment of the present invention, the method further includes: forming a dielectric layer on the substrate; and forming a trench in the dielectric layer.

[0008] According to an embodiment of the present invention, the metal nitride barrier layer conformally covers the dielectric layer and the inner surface of the trench.

[0009] According to an embodiment of the present invention, the method further includes: forming a high dielectric constant dielectric layer before depositing the metal nitride barrier layer.

[0010] According to an embodiment of the present invention, the first element region is a PMOS region, and the second element region is an NMOS region.

[0011] According to an embodiment of the present invention, the titanium layer is selectively removed from the second element region by using a diluted hydrofluoric acid solution or a hydrogen peroxide-sulfuric acid mixture (SPM).

[0012] According to an embodiment of the present invention, the method further includes: after converting the titanium layer in the first element region into the titanium nitride layer, depositing an N work function metal layer on the first element region and the second element region.

[0013] According to an embodiment of the present invention, the N-work function metal layer comprises titanium aluminum.

[0014] According to an embodiment of the present invention, the method further includes: depositing a gap-filling conductive layer on the N-work function metal layer.

[0015] According to an embodiment of the present invention, the gap-filling conductive layer comprises aluminum or tungsten. Attached Figure Description

[0016] Figures 1 to 7 This is a schematic diagram illustrating a method for forming a semiconductor device according to an embodiment of the present invention.

[0017] Explanation of main component symbols

[0018] 1. Semiconductor components

[0019] 100 base

[0020] 110 dielectric layer

[0021] 210 High Dielectric Constant Dielectric Layer

[0022] 220 Metal Nitride Barrier Layer

[0023] 230 titanium layer

[0024] 230a titanium nitride layer

[0025] 250 Bottom Anti-reflective Layer

[0026] 260 Photoresist Pattern

[0027] 280 N work function metal layer

[0028] 290 gap-filling conductive layer

[0029] 301 First Component Region

[0030] 302 Second Component Region

[0031] F1 Fin-like structure

[0032] F2 Fin-like structure

[0033] T-groove Detailed Implementation

[0034] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0035] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0036] Please see Figures 1 to 7 This is a schematic diagram illustrating a method for forming a semiconductor element 1 according to an embodiment of the present invention. According to an embodiment of the present invention, the semiconductor element 1 may be a CMOS element. For example... Figure 1 As shown, a substrate 100 is first provided, for example, a silicon substrate, but not limited thereto. The substrate 100 has at least a first element region 301 and a second element region 302. According to an embodiment of the present invention, for example, the first element region 301 is a PMOS region, and the second element region 302 is an NMOS region.

[0037] According to an embodiment of the present invention, a dielectric layer 110, such as a silicon oxide layer, but not limited thereto, is then formed on the substrate 100. Next, a trench T is formed in the dielectric layer 110. According to an embodiment of the present invention, the substrate 100 may include a fin structure F1 located in a first element region 301 within the trench T, and a fin structure F2 located in a second element region 302 within the trench T.

[0038] According to an embodiment of the present invention, a high-dielectric-constant dielectric layer 210 and a metal nitride barrier layer 220 are then sequentially deposited using, for example, a chemical vapor deposition process, to cover the first element region 301 and the second element region 302. The high-dielectric-constant dielectric layer 210 and the metal nitride barrier layer 220 conformally cover the inner surface of the trench T and the top surface of the dielectric layer 110. The high-dielectric-constant dielectric layer 210 is, for example, hafnium oxide, and the metal nitride barrier layer 220 is, for example, tantalum nitride, but is not limited thereto. Then, a titanium layer 230 is deposited on the metal nitride barrier layer 220.

[0039] like Figure 2 As shown, a bottom anti-reflective layer 250 is then formed on the substrate 100, and a photoresist pattern 260 is formed on the bottom anti-reflective layer 250. The photoresist pattern 260 covers the first element region 301.

[0040] like Figure 3 As shown, the bottom anti-reflective layer 250, which is not covered by the photoresist pattern 260, is then removed to expose the titanium layer 230 in the second element region 302.

[0041] like Figure 4 As shown, the titanium layer 230 is selectively removed from the second element region 302 using an etching process, such as a wet etching process, thereby exposing the metal nitride barrier layer 220 in the second element region 302. According to an embodiment of the present invention, the above-described wet etching process may involve selectively removing the titanium layer 230 from the second element region 302 using a diluted hydrofluoric acid solution or a hydrogen peroxide-sulfuric acid mixture (SPM).

[0042] Because the etching selectivity of titanium to tantalum nitride is higher than that of titanium nitride to tantalum nitride, this step is less likely to damage the metal nitride barrier layer 220. Furthermore, it is less likely to form residues.

[0043] like Figure 5 As shown, the photoresist pattern 260 and the bottom anti-reflective layer 250 are then removed to expose the titanium layer 230 in the first element region 301. A cleaning process can then be performed.

[0044] like Figure 6 As shown, the titanium layer 230 in the first element region 301 is then transformed into a titanium nitride layer 230a, serving as a P-work function metal layer in the first element region 301. According to an embodiment of the present invention, for example, the titanium layer 230 can be transformed into a titanium nitride layer 230a using a nitrogen-containing plasma.

[0045] like Figure 7As shown, next, an N-work function metal layer 280 is deposited on the first element region 301 and the second element region 302. According to an embodiment of the invention, the N-work function metal layer 280 may include titanium or aluminum, but is not limited thereto. Next, a gap-filling conductive layer 290 is deposited on the N-work function metal layer 280. The gap-filling conductive layer 290 may fill the trench T. According to an embodiment of the invention, the gap-filling conductive layer 290 includes aluminum or tungsten.

[0046] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: A substrate is provided, having a first element region and a second element region; A dielectric layer is formed on the substrate; A trench is formed in the dielectric layer, a portion of which is located in the first element region and another portion of which is located in the second element region; A metal nitride barrier layer is deposited to cover the first element region and the second element region, wherein the metal nitride barrier layer conformally covers the dielectric layer and the inner surface of the trench; A titanium layer is compliantly deposited on the metal nitride barrier layer; The titanium layer is selectively removed from the second element region to expose the metal nitride barrier layer in the second element region; as well as The titanium layer in the first element region is transformed into a titanium nitride layer, wherein the titanium nitride layer is a work function layer in the first element region.

2. The method according to claim 1, wherein, Also includes: A bottom anti-reflective layer is formed on the substrate, wherein the bottom anti-reflective layer is filled into the trench; A photoresist pattern is formed on the bottom anti-reflective layer, wherein the photoresist pattern covers the first element region and overlaps with the trench portion; and Remove the bottom antireflective layer that is not covered by the photoresist pattern to expose the titanium layer in the second element region located within the trench.

3. The method according to claim 1, wherein, Also includes: A high dielectric constant dielectric layer is formed before the metal nitride barrier layer is deposited.

4. The method according to claim 1, wherein, The first element region is a PMOS region, and the second element region is an NMOS region.

5. The method according to claim 1, wherein, The titanium layer is selectively removed from the second element region by using a diluted hydrofluoric acid solution or a hydrogen peroxide-sulfuric acid mixture (SPM).

6. The method according to claim 1, wherein, Also includes: After converting the titanium layer in the first element region into the titanium nitride layer, an N work function metal layer is deposited on the first element region and the second element region.

7. The method according to claim 6, wherein, The N-work function metal layer comprises titanium aluminum.

8. The method according to claim 6, wherein, Also includes: A gap-filling conductive layer is deposited on the N-work function metal layer.

9. The method according to claim 8, wherein, The gap-filling conductive layer comprises aluminum or tungsten.

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