Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a manufacturing method thereof are disclosed. The semiconductor memory device includes a substrate, a resistance structure, a bit line structure, and a bit line contact. The substrate includes an active region and a plurality of insulating regions. The resistance structure is disposed on the insulating regions and includes a first semiconductor layer, a first cap layer, and a first spacer. The bit line structure is disposed on the substrate, across the active region and the insulating regions, and includes a second semiconductor layer, a first conductive layer, a second cap layer, and a second spacer. The bit line contact is disposed in the substrate and partially extends into the second semiconductor layer. The bit line contact and the first semiconductor layer include the same semiconductor material. Thus, a resistor with structural reliability and stable surface resistance can be formed under a simplified manufacturing process.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor memory device and a method for fabricating the same. BACKGROUND

[0002] With the current level of semiconductor technology, the industry has been able to integrate control circuits, accessors, low-voltage operating circuits, and high-voltage operating circuits and other components on a single chip, thereby reducing costs while improving operating performance. In addition, as the size of semiconductor devices becomes smaller and smaller, there have been many improvements in the fabrication steps of transistors, accessors, and resistors and other components to produce various semiconductor components that are small in size and high in quality. However, as the size of devices continues to decrease, it becomes more difficult to provide multiple semiconductor components on the same device, and the fabrication process faces many limitations and challenges. Therefore, the prior art needs to be further improved to effectively improve the efficiency of the fabrication process and further improve the performance and reliability of the device. SUMMARY

[0003] One object of the present application is to provide a semiconductor memory device and a method for fabricating the same, which provides a resistor with structural reliability and stable surface resistance value while simplifying the fabrication process by providing a memory and a resistor on the same device.

[0004] To achieve the above object, one embodiment of the present application provides a semiconductor memory device, which includes a substrate, a resistor structure, a bit line structure, and a bit line contact. The substrate includes an active region and a plurality of insulating regions. The resistor structure is disposed on the insulating regions and includes a first semiconductor layer, a first cap layer disposed on the first semiconductor layer, and a first spacer disposed on sidewalls of the first semiconductor layer and the first cap layer. The bit line structure is disposed on the substrate and across the active region and the insulating regions and includes a second semiconductor layer, a first conductive layer disposed on the second semiconductor layer, a second cap layer disposed on the first conductive layer, and a second spacer directly physically contacting sidewalls of the second semiconductor layer, the first conductive layer, the second cap layer, and the second spacer. The bit line contact is disposed in the substrate and partially extends into the second semiconductor layer, wherein the bit line contact and the first semiconductor layer include the same semiconductor material.

[0005] To achieve the above object, one embodiment of the present application provides a method for manufacturing a semiconductor memory device, comprising the following steps. A substrate is provided, the substrate comprising an active region and a plurality of insulating regions. A resistance structure is formed on the insulating regions, the resistance structure comprising a first semiconductor layer, a first cap layer disposed on the first semiconductor layer, and a first spacer disposed on sidewalls of the first semiconductor layer and the first cap layer. A bit line structure is formed on the substrate and across the active region and the insulating regions, the bit line structure comprising a second semiconductor layer, a first conductive layer disposed on the second semiconductor layer, a second cap layer disposed on the first conductive layer, and a second spacer directly physically contacting sidewalls of the second semiconductor layer, the first conductive layer, the second cap layer, and the second spacer. A bit line contact is formed in the substrate and partially extends into the second semiconductor layer, wherein the bit line contact and the first semiconductor layer comprise the same semiconductor material. BRIEF DESCRIPTION OF DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of embodiments of the application, and are incorporated in and constitute a part of this specification. The drawings illustrate the principles of the application and, although not to be limited thereto, serve to explain the principles and its application. It is to be noted, that all drawings are schematic representations, which are intended to facilitate understanding of the principles of the application, and relative dimensions and proportions of various features are shown exaggerated or reduced for the sake of clarity. Like reference numerals are used to indicate like elements in the various embodiments.

[0007] Figures 1 to 10 A schematic diagram of the steps of a method for forming a semiconductor memory device in a first embodiment of the present application, wherein:

[0008] Figure 1 A schematic diagram of a cross-section of a semiconductor memory device after forming a contact opening;

[0009] Figure 2 A schematic diagram of a cross-section of a semiconductor memory device after performing a patterning process;

[0010] Figure 3 A schematic diagram of a cross-section of a semiconductor memory device after forming a conductive material layer;

[0011] Figure 4 A schematic diagram of a cross-section of a semiconductor memory device after forming a first mask layer;

[0012] Figure 5 A schematic diagram of a cross-section of a semiconductor memory device after forming a bit line contact;

[0013] Figure 6 A schematic diagram of a cross-section of a semiconductor memory device after forming a capping material layer;

[0014] Figure 7A cross-sectional view of a semiconductor memory device after forming a second mask layer;

[0015] Figure 8 A cross-sectional view of a semiconductor memory device after forming a bit line structure;

[0016] Figure 9 A cross-sectional view of a semiconductor memory device after forming a spacer;

[0017] Figure 10 A cross-sectional view of a semiconductor memory device after forming a plug.

[0018] Figure 11 A cross-sectional view of a semiconductor memory device according to another embodiment of the present application.

[0019] Figures 12 to 16 A cross-sectional view of a semiconductor memory device according to a second embodiment of the present application.

[0020] Figure 12 A cross-sectional view of a semiconductor memory device after forming a contact opening;

[0021] Figure 13 A cross-sectional view of a semiconductor memory device after forming a bit line contact;

[0022] Figure 14 A cross-sectional view of a semiconductor memory device after forming a first mask layer;

[0023] Figure 15 A cross-sectional view of a semiconductor memory device after forming a plug.

[0024] Figure 16 A cross-sectional view of a semiconductor memory device according to another embodiment of the present application.

[0025] Figure 17 A cross-sectional view of a semiconductor memory device according to a third embodiment of the present application.

[0026] Figure 18 A cross-sectional view of a semiconductor memory device according to a fourth embodiment of the present application.

[0027] Wherein, the reference numerals are explained as follows:

[0028] 10, 20, 30, 40, 50 semiconductor memory device

[0029] 10A first region

[0030] 10B second region

[0031] 10C third region

[0032] 11, 21, 31, 41 resistive structure

[0033] 12 bit line structure

[0034] 13 gate line structure

[0035] 51 capacitive structure

[0036] 100 substrate

[0037] 101, 102, 103 insulating region

[0038] 110 dielectric layer

[0039] 111 first silicon oxide layer

[0040] 113 silicon nitride layer

[0041] 115 second silicon oxide layer

[0042] 120 semiconductor material layer

[0043] 120a contact opening

[0044] 122 second semiconductor layer

[0045] 123 semiconductor layer

[0046] 130 capping material layer

[0047] 140 conductor material layer

[0048] 141 first semiconductor layer

[0049] 142 bit line contact

[0050] 150 first capping material layer

[0051] 151 first cap layer

[0052] 160 first masking layer

[0053] 162, 163 second masking layer

[0054] 170 first barrier material layer

[0055] 171 second barrier layer

[0056] 172 first barrier layer

[0057] 173 barrier layer

[0058] 180 conductive material layer

[0059] 181 second conductive layer

[0060] 182 first conductive layer

[0061] 183 conductive layer

[0062] 190 second cap layer

[0063] 191 third cap layer

[0064] 192 second cap layer

[0065] 193 cap layer

[0066] 201 first spacer

[0067] 202 second spacer

[0068] 203 third spacer

[0069] 210 ILD layer

[0070] 220 IMD layer

[0071] 231, 232, 233 plug

[0072] 231a, 531a metal silicide layer

[0073] 233a, 233b plug

[0074] 320a opening

[0075] 321 third semiconductor layer

[0076] 341, 341a first semiconductor layer

[0077] 350 cap layer

[0078] 351 first cap layer

[0079] 360 first mask layer

[0080] 401, 401a spacer

[0081] 421, 521 third semiconductor layer

[0082] 431, 531 plug

[0083] 441, 541 first semiconductor layer

[0084] 451, 453 cap layer

[0085] 501, 501a spacer

[0086] 551, 553 cap layer DETAILED DESCRIPTION

[0087] For the purpose of making the skilled in the art of the present application further understand the present application, the following preferred embodiments of the present application are listed, and the accompanying drawings show, detailed description of the present application constitutes the content and the desired effect. It is known that the following examples can be replaced, reorganized, mixed with features in several different embodiments to complete other embodiments without departing from the spirit of the present application.

[0088] Referring to Figures 1 to 10 The first embodiment of the present application is shown, the steps of the method for manufacturing semiconductor memory device 10. First, as shown in Figure 1 The substrate 100 is provided, for example, is a silicon substrate (silicon substrate), epitaxial silicon substrate (epitaxial silicon substrate) or silicon on insulation (silicon on insulation, SOI) substrate, etc., the substrate 100 is formed in a plurality of insulating regions 101, 102, 103, such as shallow trench isolation (shallow trench isolation, STI), and further in the substrate 100 defines a plurality of active regions (not shown). The substrate 100, for example, includes at least three regions, the first region 10A, the second region 10B and the third region 10C, to set different semiconductor components, respectively, and each of the insulating regions 101, 102, 103 is arranged in the first region 10A, the second region 10B and the third region 10C. In this embodiment, the first region 10A, for example, is a resistance region, which can be used in the setting of the resistor, the second region 10B, for example, is a storage region, which can be used in the setting of the memory, and the third region 10C, for example, is a transistor region, which can be used in the setting of the transistor component, but not limited to this. For those skilled in the art, the first region 10A, the second region 10B and the third region 10C can be selected to be directly adjacent to each other, or further arranged in other regions, for example, in the second region 10B and the third region 10C, an additional peripheral region (not shown) can be arranged, but not limited to this.

[0089] Then, on the substrate 100, a plurality of deposition processes are sequentially performed to form a dielectric layer 110, a semiconductor material layer 120 and a covering material layer 130 stacked from bottom to top, wherein the dielectric layer 110 preferably has a composite structure, for example, including a first silicon oxide layer 111-nitride silicon layer 113-second silicon oxide layer 115 structure arranged from bottom to top, the semiconductor material layer 120, for example, includes polysilicon and other semiconductor materials with dopant, and the covering material layer 130 includes silicon oxide, silicon nitride and other insulating materials, but not limited to this.

[0090] It is noted that the dielectric layer 110 is initially formed to cover the active regions and the insulating regions 101, 102, 103 in the first region 10A, the second region 10B and the third region 10C, and then, before the deposition process of the semiconductor material layer 120, the second silicon oxide layer 115 and the silicon nitride layer 113 in the third region 10C are removed, so that the active regions and the insulating region 103 in the third region 10C are only covered by the first silicon oxide layer 111, as shown in Figure 1 Thus, the semiconductor material layer 120 and the covering material layer 130 formed in the third region 10C can have a relatively lower position compared to the semiconductor material layer 120 and the covering material layer 130 formed in other regions. Alternatively, in another embodiment, the dielectric layer 110 in the third region 10C can be completely removed to expose the surface of the substrate 100, and then a thermal oxidation process is performed to form a silicon oxide layer (not shown) on the surface of the substrate 100.

[0091] Further, as shown in Figure 1 After the process of the covering material layer 130, an etching process is performed through a mask layer (not shown) to define a contact opening 120a in the second region 10B. In detail, the contact opening 120a sequentially penetrates the covering material layer 130, the semiconductor material layer 120 and the dielectric layer 110 to expose part of the substrate 100, so as to form a bit line contact in the subsequent process. Then, the mask layer is completely removed.

[0092] As shown in Figure 2 Another etching process is performed through another mask layer (not shown) to completely remove the covering material layer 130, the semiconductor material layer 120 and the dielectric layer 110 in the first region 10A to expose the insulating region 101 and the top surface of the substrate 100. Then, the another mask layer is completely removed.

[0093] Then, as shown in Figure 3As shown, a two-stage deposition process is performed to sequentially form a conductor material layer 140 and a first cover material layer 150 on a substrate 100. Specifically, both the conductor material layer 140 and the first cover material layer 150 integrally cover the first region 10A, the second region 10B, and the third region 10C. The conductor material layer 140 further fills the contact opening 120a within the second region 10B. In one embodiment, the conductor material layer 140 may include, for example, a doped semiconductor material such as polycrystalline silicon or silicon phosphide (SiP), preferably silicon phosphide; while the first cover material layer 150 may include, for example, an insulating material such as silicon nitride (SiN) or silicon carbonitride (SiCN), but is not limited thereto. It should be noted that the conductor material layer 140 and the first cover material layer 150 formed in the first region 10A are directly covered on the top surface of the insulating region 101 and the substrate 100, and have a relatively low setting position, compared with the conductor material layer 140 and the first cover material layer 150 formed in other regions, which have a relatively low top surface.

[0094] like Figure 4 As shown, a first mask layer 160 is formed in the first region 10A, covering the first cover material layer 150. Then, a patterning process is performed on the first mask layer 160 to transfer the pattern of the first mask layer 160 to the underlying first cover material layer 150 and conductor material layer 140, thus forming a pattern in the first region 10A as shown in the diagram. Figure 5 The first capping layer 151 and the first semiconductor layer 141 are shown. Meanwhile, as... Figure 5 As shown, the first cover material layer 150, conductor material layer 140, and cover material layer 130 in the second region 10B and the third region 10C are removed, while the conductor material layer 140 filling the contact opening 120a is retained to form a contact in the contact opening 120a, which is a bit line contact 142. Then, the first mask layer 160 is completely removed.

[0095] like Figure 6 As shown, multiple deposition processes are performed sequentially on the substrate 100 to form a barrier material layer 170, a conductive material layer 180, and a second cover material layer 190 stacked sequentially from bottom to top. The barrier material layer 170, the conductive material layer 180, and the second cover material layer 190 are conformally covered on the first region 10A, the second region 10B, and the third region 10C. The barrier material layer 170 may contain materials such as titanium (Ti) and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum nitride (TaN), etc. The conductive material layer 180 may contain low-resistivity metals such as aluminum (Al), titanium, copper (Cu), or tungsten (W), etc., and the second cover material layer 190 may contain materials such as silicon nitride or silicon carbonitride, but is not limited thereto.

[0096] likeFigure 7 As shown, second mask layers 162 and 163 are formed in the second region 10B and the third region 10C, respectively, covering the second cover material layer 190. Then, a further patterning process is performed on the second mask layers 162 and 163 to transfer the patterns of the second mask layers 162 and 163 to the underlying stacked layers (including the sequentially stacked second cover material layer 190, conductive material layer 180, barrier material layer 170, and semiconductor material layer 120), so as to form patterns in the second region 10B and the third region 10C as shown in the diagram. Figure 8 The stacked layer structure shown.

[0097] It should be specifically noted that the second mask layers 162 and 163 are only formed within the second region 10B and the third region 10C. Therefore, the second cover material layer 190, conductive material layer 180, and barrier material layer 170 covering the first region 10A can be completely removed, exposing the first capping layer 151 and the first semiconductor layer 141. On the other hand, the stacked layer structure in the second region 10B includes a second semiconductor layer 122, a first barrier layer 172, a first conductive layer 182, and a second capping layer 192 stacked sequentially from bottom to top, wherein the bit line contact 142 is partially located within the second semiconductor layer 122; while the stacked layer structure in the third region 10C includes a semiconductor layer 123, a barrier layer 173, a conductive layer 183, and a capping layer 193 stacked sequentially from bottom to top, as shown below. Figure 8 As shown. Then, completely remove the second mask layers 162 and 163.

[0098] like Figure 9 As shown, a deposition and etch-back fabrication process is performed sequentially to form a first spacer wall 201 on the sidewalls of the first semiconductor layer 141 and the first capping layer 151, which are stacked sequentially in the first region 10A; a second spacer wall 202 is formed on the sidewalls of the second semiconductor layer 122, the first barrier layer 172, the first conductive layer 182, and the second capping layer 192, which are stacked sequentially in the second region 10B; simultaneously, a spacer wall 203 is formed on the sidewalls of the semiconductor layer 123, the barrier layer 173, the conductive layer 183, and the capping layer 193, which are stacked sequentially in the third region 10C. Thus, the first spacer wall 201, the second spacer wall 202, and the spacer wall 203 can all be made of the same material, such as silicon nitride or silicon carbonitride, and preferably may be made of the same material as the second capping layer 192 and the capping layer 193, such as silicon nitride, but are not limited thereto.

[0099] In this way, a resistor structure 11 can be formed simultaneously in the first region 10A, a bitline (BL) structure 12 in the second region 10B, and a gate line structure 13 in the third region 10C, but this is not a limitation. Figure 9As shown, the resistor structure 11 is directly disposed on the insulating region 101 and has a relatively low bottom surface. The resistor structure 11 includes a first semiconductor layer 141, a first capping layer 151 disposed sequentially from bottom to top, and a first gap wall 201 that physically contacts the sidewalls of the first semiconductor layer 141 and the first capping layer 151.

[0100] Bit line structure 12 is directly disposed on dielectric layer 110 and extends along one direction (not shown) to simultaneously span the active region and insulating region 102. For example... Figure 9 As shown, the bit line structure 12 includes, from bottom to top, a second semiconductor layer 122, a first barrier layer 172, a first conductive layer 182, and a second capping layer 192 stacked sequentially. It also includes a second spacer wall 202 that physically contacts the sidewalls of the second semiconductor layer 122, the first barrier layer 172, the first conductive layer 182, and the second capping layer 192. Thus, the top surface of the bit line structure 12 can be significantly higher than the top surface of the resistor structure 11 or the gate line structure 13. It should be noted that a bit line contact 142 is also provided below the bit line structure 12. The bit line contact 142 is disposed within the active region of the substrate 100 and partially extends into the second semiconductor layer 122. The bit line contact 142 and the second semiconductor layer 122 of the bit line structure 12 are formed separately using different fabrication processes and may include different semiconductor materials. For example, the bit line contact 142 may include doped silicon-phosphorus, while the second semiconductor layer 122 may include doped polysilicon, but this is not a limitation. Furthermore, the bit line contact 142 and the first semiconductor layer 141 of the resistor structure 11 are formed together using the same fabrication process and include the same semiconductor material (such as silicon phosphide). It should be noted that, in addition to the bit line structure 12, the fabrication method of this embodiment may further provide multiple gates (not shown), at least one transistor assembly (not shown), and at least one capacitor assembly (not shown) within the second region 10B to jointly form a dynamic random access memory (DRAM, not shown) with a buried gate, but this is not a limitation.

[0101] On the other hand, the gate line structure 13 is directly disposed on the first silicon oxide layer 111, and includes, in detail, a semiconductor layer 123, a barrier layer 173, a conductive layer 183, and a capping layer 193 stacked sequentially from bottom to top, and also includes a spacer wall 203 that physically contacts the sidewalls of the semiconductor layer 123, the barrier layer 173, the conductive layer 183, and the capping layer 193. Thus, the spacer wall 203 of the gate line structure 13 may have a top surface slightly lower than the second spacer wall 202, such as... Figure 9As shown. In this embodiment, the gate line structure 13 and the bit line structure 12 are formed simultaneously using the same fabrication process. Therefore, the semiconductor layer 123, barrier layer 173, conductive layer 183, capping layer 193, and spacer 203 of the gate line structure 13 may have the same material and thickness as the second semiconductor layer 122, first barrier layer 172, first conductive layer 182, second capping layer 192, and second spacer 202 of the bit line structure 12, but this is not a limitation. However, the first semiconductor layer 141 and first capping layer 151 of the resistor structure 11 may have different material and thickness than the second semiconductor layer 122 and second capping layer 192 of the bit line structure 12, or the semiconductor layer 123 and capping layer 193 of the gate line structure 13.

[0102] Then, as Figure 10 As shown, an interlayer dielectric layer 210, an intermetal dielectric layer 220, and a plurality of plugs 231, 232, and 233 are sequentially formed on the substrate 100. The interlayer dielectric layer 210 completely covers the resistor structure 11 in the first region 10A and the gate line structure 13 in the third region 10C, and the top surface of the interlayer dielectric layer 210 is flush with the top surface of the second capping layer 192 of the bit line structure 12. In detail, each plug 231 electrically connected to the resistor structure 11 passes through the first capping layer 151 and directly contacts the first semiconductor layer 141 of the resistor structure 11. Since the first semiconductor layer 141 includes a semiconductor material such as polysilicon, a metal silicide layer 231a can be further formed between each plug 231 and the first semiconductor layer 141 to improve the electrical connection between the first semiconductor layer 141 and the plug 231. The plug 232, which is electrically connected to the second region 10B, passes through the second capping layer 192 and directly contacts the first conductive layer 182. The plug 233, which is electrically connected to the third region 10C, further includes a plug 233a that passes through the capping layer 193 and directly contacts the second conductive layer 183 of the gate line structure 13, and a plug 233b that passes through the first silicon oxide layer 111 and directly contacts the two doped regions (not shown) in the substrate 100 on both sides of the gate line structure 13.

[0103] Thus, the fabrication of the semiconductor storage device 10 in the first embodiment of the present application is completed. Through the aforementioned steps, the fabrication method in the present embodiment can integrate the fabrication of the resistance structure 11 in the general fabrication flow of the bit line structure 12, and form the first semiconductor layer 141 of the resistance structure 11 by using the fabrication process of fabricating the bit line contact 142 in the bit line structure 12. In this way, the resistance structure 11 can be composed of the first semiconductor layer 141 including silicon phosphorus, the first cap layer 151 including insulating material, and the first spacer 201, so that each plug 231 electrically connected to the resistance structure 11 can directly contact the first semiconductor layer 141, and thus high resistance quality can be provided. Under this operation, the fabrication method in the present embodiment can form the resistor in another area (i.e., the first area 10A) when forming the memory in the storage area (i.e., the second area 10B) of the semiconductor storage device 10, so as to effectively improve the fabrication efficiency of the resistance structure 11. Moreover, the fabrication method in the present embodiment can also form the gate line structure 13 in the third area 10C, that is, the fabrication of the gate line structure 13 is also integrated in the general fabrication flow of the bit line structure 12, so as to effectively improve the fabrication efficiency of the semiconductor storage device 10, and the fabricated semiconductor storage device 10 can also have optimized working performance and structural reliability.

[0104] For those skilled in the art, the semiconductor storage device 10 in the present application can also have other forms or be fabricated by other fabrication processes under the premise of meeting the actual product requirements, and is not limited to the aforementioned. For example, in another embodiment, the fabrication of the gate line structure 13 in the semiconductor storage device 10 can also not be integrated in the general fabrication flow of the bit line structure 12, for example, the gate line structure 13 is separately formed in the third area 10C after the formation of the bit line structure 12, but is not limited thereto. Further embodiments or variations of the semiconductor storage device and the fabrication method thereof in the present application will be further described below. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and the same parts will not be repeatedly described. Moreover, the same components in the embodiments of the present application are marked with the same reference numerals for the purpose of mutual comparison between the embodiments.

[0105] Please refer to Figure 11 which illustrates the fabrication method of a semiconductor storage device 20 in another embodiment of the present application. The first steps of the present embodiment are basically the same as those of the aforementioned first embodiment, as shown in Figures 1 to 6As shown, the details will not be repeated here. The main difference between the manufacturing process of this embodiment and the aforementioned first embodiment is that when the second mask layers 162 and 163 are formed in the second region 10B and the third region 10C, a mask layer (not shown) is also formed in the first region 10A. Then, a patterning process is performed simultaneously on the second mask layers 162 and 163 and the mask layer to transfer the patterns of the second mask layers 162 and 163 and the mask layer to the underlying stacked layers (including the second cover material layer 190, conductive material layer 180, barrier material layer 170 and semiconductor material layer 120 stacked in sequence). Thus, a pattern is formed in each region (including the first region 10A, the second region 10B and the third region 10C) as shown. Figure 11 The stacked layer structure shown.

[0106] In detail, the stacked layer structure formed in the second region 10B and the third region 10C is generally the same as that in the previous embodiment. The stacked layer structure formed in the first region 10A includes a first semiconductor layer 141, a first capping layer 151, a second barrier layer 171, a second conductive layer 181, and a third capping layer 191 stacked sequentially from bottom to top. The second barrier layer 171, the second conductive layer 181, and the third capping layer 191 may have the same material and thickness as the first barrier layer 172, the first conductive layer 182, and the second capping layer 192 of the bit line structure 12, or the barrier layer 173, the conductive layer 183, and the capping layer 193 of the gate line structure 13, but are not limited thereto. Then, as shown in the previous embodiment, a first gap wall 201, a second gap wall 202 and a gap wall 203 are formed on the sidewalls of each of the stacked layer structures, so as to form a resistor structure 21, a bit line structure 12 and a gate line structure 13 in the first region 10A, the second region 10B and the third region 10C, respectively. Then, an interlayer dielectric layer 210, an intermetallic dielectric layer 220 and a plurality of plugs 231, 232 and 233 are formed in sequence. The parts of the steps that are the same as those in the previous embodiment will not be repeated.

[0107] It is worth noting that, in this embodiment, when forming the second mask layers 162 and 163, the mask layers are also formed within the first region 10A to define the pattern position of the final resistor structure 21. Therefore, in this embodiment, when performing... Figure 3 During the deposition process, it is also possible to choose not to form the first cover material layer 150, so that the resistor structure 21 finally formed in the first region 10A only includes the first semiconductor layer 141, the second barrier layer 171, the second conductive layer 181, and the third cover layer 191 stacked sequentially from bottom to top, without including the first cover layer 151.

[0108] Thus, the fabrication of the semiconductor storage device 20 in another embodiment of the present application is completed. In this way, the resistance structure 21 can be composed of the first semiconductor layer 141, the first cap layer 151, the second barrier layer 171, the second conductive layer 181 and the third cap layer 191 stacked in sequence from bottom to top. In this embodiment, each plug 231 electrically connected to the resistance structure 21 can additionally include an insulating layer (not shown) formed on the sidewall of the plug hole (not shown) to ensure that each plug 231 only directly contacts the first semiconductor layer 141 including silicon phosphorus, thereby providing a higher resistance quality. In this operation, the fabrication method of this embodiment can also integrate the fabrication of the resistance structure 21 in the general fabrication process of the bit line structure 12, so that when the memory is formed in the storage area (i.e. the second area 10B) of the semiconductor storage device 20, the resistance structure 21 with high resistance quality is also formed in another area (i.e. the first area 10A). In this way, the fabrication efficiency of the semiconductor storage device 20 can also be improved, and the semiconductor storage device 20 produced can also have optimized working performance and structural reliability.

[0109] Please refer to Figures 12 to 16 , which shows the fabrication method of the semiconductor storage device 30 in the second embodiment of the present application. The steps of this embodiment are generally the same as those of the aforementioned first embodiment, and the same parts will not be described here. The main difference between the fabrication process of this embodiment and the aforementioned first embodiment is that when the contact opening 120a is defined in the second area 10B, at least one opening is also defined in the first area 10A, such as Figure 12 the plurality of openings 320a shown in .

[0110] In detail, as shown in Figure 12 , each opening 320a also penetrates the cover material layer 130, the semiconductor material layer 120 and the dielectric layer 110, exposing part of the insulating area 101. Then, the deposition fabrication process and the planarization fabrication process are sequentially performed on the substrate 100 to form the bit line contact 142 in the contact opening 120a, and to form the first semiconductor layer 341 in each opening 320a, so that the first semiconductor layer 341 includes a plurality of parts inlaid in the semiconductor material layer 120 and separated from each other, as shown in Figure 13 .

[0111] As shown in Figure 14 , the deposition fabrication process is further performed on the substrate 100 to form a cover material layer 350 covering the semiconductor material layer 120. Then, the first mask layer 360 is formed in the first area 10A, and the pattern of the first mask layer 360 is transferred to the underlying cover material layer 350, semiconductor material layer 120 and dielectric layer 110 in sequence through the patterned fabrication process performed through the first mask layer 360, to form the first cap layer 351 and the third semiconductor layer 321 in the first area 10A, as shown in Figure 15 .

[0112] Then, as in the aforementioned embodiments (for example, see also references) Figures 6 to 10 As shown, the stacked layer structure continues to be formed on the substrate 100, including first spacer 201, second spacer 202, and spacer 203, etc., to form a resistor structure 31, a bit line structure 12, and a gate line structure 13 in the first region 10A, the second region 10B, and the third region 10C, respectively. Figure 15 As shown. Then, an interlayer dielectric layer 210, an intermetallic dielectric layer 220, and a plurality of plugs 231, 232, and 233 are formed in sequence. The parts of the above steps that are the same as those in the above embodiments will not be repeated. Among them, a metal silicide layer 231a may be further formed between each plug 231 electrically connected to the resistor structure 31 and the third semiconductor layer 321 to improve the electrical connection between the third semiconductor layer 351 and the plug 231.

[0113] Thus, the fabrication of the semiconductor memory device 30 in the second embodiment of the present invention is completed. The resistor structure 31 in this embodiment is composed of a third semiconductor layer 321 including doped polysilicon, a first semiconductor layer 341 including doped silicon-phosphorus, a first capping layer 351 including insulating material, and a first spacer 201. This allows each plug 231 electrically connected to the resistor structure 31 to directly contact the third semiconductor layer 321, thereby providing high resistivity. It should be noted that in this embodiment, multiple portions of the first semiconductor layer 341 are, for example, embedded within the third semiconductor layer 321 and also include a material with high resistivity (doped silicon-phosphorus). Therefore, provided that actual product requirements are met, the plugs (not shown) electrically connected to the resistor structure 31 can also directly contact the first semiconductor layer 341 without contacting the third semiconductor layer 321, but this is not a limitation.

[0114] In this operation, the fabrication method of this embodiment can also integrate the fabrication of the resistor structure 31 into the general fabrication process of the bit line structure 12. The third semiconductor layer 321 of the resistor structure 31 is formed simultaneously through the fabrication process of the second semiconductor layer 122 of the bit line structure 12, and the first semiconductor layer 341 of the resistor structure 31 is formed simultaneously through the fabrication process of the bit line contacts 142 of the bit line structure 12. In this way, the fabrication efficiency of the semiconductor memory device 30 can also be improved, and the resulting semiconductor memory device 30 can also have optimized operating performance and structural reliability.

[0115] Furthermore, it should be noted that, in this embodiment, although multiple portions of the first semiconductor layer 341 (including silicon-phosphorus) are simultaneously disposed within the third semiconductor layer 321 including polysilicon as an example for illustration, the number of first semiconductor layers 341 disposed therein is not limited thereto. Figure 16As shown, in another embodiment, a single first semiconductor layer 341a including silicon phosphorus can also be disposed within a third semiconductor layer 321 including polysilicon, and a plug 231 electrically connected to the resistance structure 31 can also be selected to directly contact the first semiconductor layer 341a embedded within the third semiconductor layer 321 without contacting the third semiconductor layer 321. In this way, a high resistance quality can also be provided.

[0116] Referring to Figure 17 , a cross-sectional schematic view of a semiconductor memory device 40 in a third embodiment of the present application is shown. The structure of the present embodiment is substantially the same as the previous embodiments, and the same parts will not be described again. The main difference between the semiconductor memory device 40 of the present embodiment and the previous embodiments is that the resistance structure 41 having a double-layer semiconductor layer 421, 441 is disposed within the first region 10A to provide a high resistance quality.

[0117] In detail, as Figure 17 shown, the resistance structure 41 is formed by stacking a third semiconductor layer 421 including doped polysilicon, a cap layer 451 including an insulating material, a first semiconductor layer 441 including doped silicon phosphorus, and a cap layer 453 including an insulating material. The resistance structure 41 also includes a spacer 501 between the sidewalls of the third semiconductor layer 421 and the cap layer 451, and a spacer 501a between the sidewalls of the first semiconductor layer 441 and the cap layer 453. In the present embodiment, the resistance structure 41 can also be integrated into the general fabrication process of the bit line structure 12, for example, the third semiconductor layer 421 of the resistance structure 41 is formed by the fabrication process of the second semiconductor layer 122 of the bit line structure 12, and the first semiconductor layer 441 of the resistance structure 41 is formed by the fabrication process of the bit line contact 142 of the bit line structure 12, so that the first semiconductor layer 441 and the third semiconductor layer 421 of the resistance structure 41 can have the same material as the bit line contact 142 and the second semiconductor layer 122 of the bit line structure 12, respectively, but not limited thereto.

[0118] Under this arrangement, a plurality of plugs 231, 431 electrically connected to the resistance structure 41 can be connected to the third semiconductor layer 421 (including doped polysilicon) below and the first semiconductor layer 441 (including doped silicon phosphorus) above, respectively, so that the third semiconductor layer 421 below and / or the first semiconductor layer 441 above can individually function as a resistor to provide a high resistance quality, for example, the third semiconductor layer 421 below is disposed along an extension direction parallel to the paper (not shown), and the first semiconductor layer 441 above is disposed along an extension direction perpendicular to the paper (not shown), but not limited thereto. In this way, the semiconductor memory device 40 of the present embodiment can also have optimized working performance and structural reliability.

[0119] Referring to Figure 18 , a cross-sectional view of a semiconductor memory device 50 in a fourth embodiment of the present application is shown. The structure of the present embodiment is generally the same as the previous embodiments, and the same parts will not be described again. The main difference between the semiconductor memory device 50 of the present embodiment and the previous embodiments is that the semiconductor memory device 50 of the present embodiment has a capacitor structure 51 disposed in the first region 10A.

[0120] In detail, as Figure 18 shown, the capacitor structure 51 is formed by stacking a third semiconductor layer 521 including doped polysilicon, a cap layer 551 including insulating material, a first semiconductor layer 541 including doped silicon phosphorus, and a cap layer 553 including insulating material. The capacitor structure 51 also includes a spacer 501 between the sidewalls of the third semiconductor layer 521 and the cap layer 551, and a spacer 501a between the sidewalls of the first semiconductor layer 541 and the cap layer 553. In the present embodiment, the capacitor structure 51 can also be integrated into the general fabrication process of the bit line structure 12. For example, the third semiconductor layer 521 of the capacitor structure 51 can be formed by the fabrication process of the second semiconductor layer 122 of the bit line structure 12, and the first semiconductor layer 541 of the capacitor structure 51 can be formed by the fabrication process of the bit line contact 142 of the bit line structure 12, so that the first semiconductor layer 541 and the third semiconductor layer 521 of the capacitor structure 51 can have the same material as the bit line contact 142 and the second semiconductor layer 122 of the bit line structure 12, respectively, but not limited thereto.

[0121] Under this arrangement, the two plugs 231, 531 electrically connected to the capacitor structure 51 can be connected to the third semiconductor layer 521 (including doped polysilicon) below and the first semiconductor layer 541 (including doped silicon phosphorus) above, respectively, so that the third semiconductor layer 521 below and the first semiconductor layer 541 above can serve as the lower electrode layer and the upper electrode layer of the capacitor, respectively. In addition, a metal silicide layer 231a, 531a can be further formed between each plug 231, 531 and the first semiconductor layer 541, the third semiconductor layer 521 electrically connected to the capacitor structure 51 to improve the electrical connection between the third semiconductor layer 351 and the plug 231. In this way, the semiconductor memory device 50 of the present embodiment can also have optimized working performance and structural reliability.

[0122] The preferred embodiments of the present application have been described above with the aid of drawing figures, and are not limited to those embodiments; instead, they will include any modifications and variations of the preferred embodiments made by those having ordinary skill in the art. It is intended that any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should fall within the scope of the present application.

Claims

1. A semiconductor memory device, characterized in that... comprising: a substrate including an active region and a plurality of insulating regions; a resistance structure disposed on the insulating regions, the resistance structure further comprising: a first semiconductor layer; a first cap layer disposed on the first semiconductor layer; and a first spacer disposed on sidewalls of the first semiconductor layer and the first cap layer; a bit line structure disposed on a dielectric layer of the substrate and across the active region and the insulating regions, the bit line structure further comprising: a second semiconductor layer disposed on the dielectric layer; a first conductive layer disposed on the second semiconductor layer; a second cap layer disposed on the first conductive layer; and a second spacer directly physically contacting sidewalls of the second semiconductor layer, the first conductive layer, and the second cap layer; and a bit line contact disposed within the substrate and partially into the second semiconductor layer and the dielectric layer, wherein the bit line contact and the first semiconductor layer comprise a same semiconductor material as each other.

2. The semiconductor memory device according to claim 1, characterized by the resistance structure further comprising a third semiconductor layer, the first semiconductor layer and the third semiconductor layer comprising different semiconductor materials, respectively, the third semiconductor layer and the second semiconductor layer comprising a same semiconductor material as each other.

3. The semiconductor memory device according to claim 2, wherein the first semiconductor layer is disposed in a damascene manner within the third semiconductor layer and partially into the substrate.

4. The semiconductor memory device according to claim 3, wherein further comprising: a plurality of plugs electrically connected to the first semiconductor layer, respectively.

5. The semiconductor memory device according to claim 3, wherein further comprising: a plurality of plugs electrically connected to the third semiconductor layer, respectively.

6. The semiconductor memory device according to claim 3, wherein the first semiconductor layer comprises a plurality of portions separated from each other.

7. The semiconductor memory device according to claim 2, wherein the third semiconductor layer is disposed below the first semiconductor layer.

8. The semiconductor memory device according to claim 7, characterized by further comprising: a plurality of plugs electrically connected to the first semiconductor layer and the third semiconductor layer, respectively.

9. The semiconductor memory device according to claim 1, wherein the resistance structure further comprising: a second conductive layer and a third cap layer disposed on the first cap layer in sequence, the third cap layer and the second cap layer comprising a same material; and a plurality of plugs disposed on the substrate, one of the plugs directly physically contacting the first semiconductor layer of the resistance structure, another of the plugs directly physically contacting the first conductive layer of the bit line structure.

10. The semiconductor memory device according to claim 1, characterized by, further comprising: an interlayer dielectric layer disposed on the substrate, a top surface of the interlayer dielectric layer being flush with a top surface of the second cap layer and completely covering the resistance structure.

11. The semiconductor memory device according to claim 1, characterized by, a top surface of the first spacer is lower than a top surface of the second spacer, the first cap layer and the second cap layer comprising different materials.

12. The semiconductor memory device according to claim 1, characterized by further comprising: a plurality of plugs disposed on the substrate, one of the plugs directly physically contacting the first semiconductor layer of the resistance structure, another of the plugs directly physically contacting the first conductive layer of the bit line structure.

13. A method of manufacturing a semiconductor memory device, characterized by comprising: providing a substrate including an active region and a plurality of insulating regions; forming a resistance structure on the insulating regions, the resistance structure further comprising: a first semiconductor layer; a first cap layer formed on the first semiconductor layer; and a first spacer disposed on sidewalls of the first semiconductor layer and the first cap layer; and forming a bit line structure on a dielectric layer of the substrate and across the active region and the insulating regions, the bit line structure further comprising: a second semiconductor layer disposed on the dielectric layer; a first conductive layer formed on the second semiconductor layer; a second cap layer formed on the first conductive layer; a second spacer formed on sidewalls of the second semiconductor layer, the first conductive layer, and the second cap layer; and a bit line contact formed in the substrate, the bit line contact partially protruding into the second semiconductor layer and the dielectric layer, wherein the bit line contact and the first semiconductor layer comprise a same semiconductor material.

14. The method of producing a semiconductor memory device according to Claim 13, wherein Further comprising: sequentially forming a semiconductor material layer, a conductor material layer, and a first cap material layer on the substrate, while covering the active region and the insulating region; forming a contact opening in the semiconductor material layer before forming the conductor material layer, partially exposing the substrate; forming the conductor material layer to fill the contact opening; and forming the bit line contact while removing the conductor material layer outside the contact opening when forming the first semiconductor layer.

15. The method of producing a semiconductor memory device according to Claim 14, wherein Further comprising: performing a patterning process through a first mask layer to patternize the first cap material layer and the conductor material layer, forming the first cap layer and the first semiconductor layer; removing the first mask layer; and forming a plurality of plugs to respectively electrically connect the first semiconductor layer and the first conductive layer.

16. The method of producing a semiconductor memory device according to Claim 14, wherein Further comprising: forming at least one opening in the semiconductor material layer while forming the contact opening, partially exposing the insulating region; forming the conductor material layer to fill the opening; and forming the first semiconductor layer in the semiconductor material layer while removing the conductor material layer outside the opening when forming the bit line contact, the bit line contact and the first semiconductor layer comprising a same semiconductor material.

17. The method of producing a semiconductor memory device according to Claim 16, wherein Further comprising: performing a patterning process through a first mask layer to patternize the first cap material layer and the semiconductor material layer, forming the first cap layer and a third semiconductor layer, the first semiconductor layer being inlaid in the third semiconductor layer; removing the first mask layer; and forming a plurality of plugs to respectively electrically connect the first semiconductor layer or the third semiconductor layer.

18. The method of producing a semiconductor memory device according to Claim 14, wherein Further comprising: sequentially forming a conductive material layer and a second cap material layer on the substrate; forming a second mask layer on the substrate; performing another patterning process through the second mask layer to patternize the second cap material layer and the conductive material layer, forming the second cap layer and the first conductive layer; and removing the second mask layer.

19. The method of producing a semiconductor memory device according to Claim 18, wherein Further comprising: forming a plurality of plugs on the substrate, one of the plugs directly physically contacting the first semiconductor layer of the resistance structure, another of the plugs directly physically contacting the first conductive layer of the bit line structure.

20. The method of producing a semiconductor memory device according to Claim 13, wherein Further comprising: forming an interlayer dielectric layer on the substrate, a top surface of the interlayer dielectric layer being flush with a top surface of the second cap layer; and performing a deposition and etch-back process to simultaneously form the first spacer and the second spacer on the substrate. Further comprising: forming a plurality of plugs on the substrate, one of the plugs directly physically contacting the first semiconductor layer of the resistance structure, another of the plugs directly physically contacting the first conductive layer of the bit line structure. Further comprising: forming an interlayer dielectric layer on the substrate, a top surface of the interlayer dielectric layer being flush with a top surface of the second cap layer; and performing a deposition and etch-back process to simultaneously form the first spacer and the second spacer on the substrate.

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