Imaging element, laminated imaging element, and solid-state imaging device

Abstract

The present application relates to an imaging element, a laminated imaging element, and a solid-state imaging device. Among others, the imaging element can include a photoelectric conversion unit including a first electrode, a photoelectric conversion layer, and a second electrode laminated, wherein the photoelectric conversion unit further includes a charge storage electrode arranged to be separated from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and a thickness of an area of the insulating layer between the first electrode and the charge storage electrode is thinner than a thickness of an area of the insulating layer between the imaging element and an adjacent imaging element.

Description

[0001] This application is a divisional application of Patent Application No. 201880039926.8, filed on June 21, 2018, entitled “Imaging Element, Laminated Imaging Element, and Solid-state Imaging Device”. TECHNICAL FIELD

[0002] The present application relates to an imaging element, a laminated imaging element, and a solid-state imaging device. BACKGROUND

[0003] An imaging element including an organic semiconductor material in a photoelectric conversion layer is capable of photoelectric conversion of a specific color (wavelength band). Further, in a case where the imaging element is used in a solid-state imaging device, this feature allows a structure including laminated sub-pixels (laminated imaging element) to be obtained, which is not possible in a conventional solid-state imaging device. In this structure, a sub-pixel includes a combination of an on-chip color filter (OCCF) and an imaging element, and the sub-pixels are arranged two-dimensionally (see, for example, Japanese Patent Laid-Open No. 2011-138927). There is also an advantage that demosaicing is not required, and false colors do not occur. Note that, in the following description, for convenience, an imaging element including a photoelectric conversion unit provided on or on the upper side of a semiconductor substrate can be referred to as an “imaging element of a first type”. For convenience, a photoelectric conversion element included in the imaging element of the first type can be referred to as a “photoelectric conversion unit of a first type”. For convenience, an imaging element provided in a semiconductor substrate can be referred to as an “imaging element of a second type”. For convenience, a photoelectric conversion unit included in the imaging element of the second type can be referred to as a “photoelectric conversion unit of a second type”.

[0004] Figure 102 An example of the structure of a conventional laminated imaging element (laminated solid-state imaging device) is shown. In the example shown, a third photoelectric conversion unit 331 and a second photoelectric conversion unit 321, which are photoelectric conversion units of a second type included in a third imaging element 330 and a second imaging element 320, are laminated and formed in a semiconductor substrate 370. In addition, a first photoelectric conversion unit 311, which is a photoelectric conversion unit of a first type, is arranged on the upper side of the semiconductor substrate 370 (specifically, the upper side of the second imaging element 320). Here, the first photoelectric conversion unit 311 includes a first electrode 311, a photoelectric conversion layer 313 containing an organic material, and a second electrode 312. The first photoelectric conversion unit 311 is included in a first imaging element 310, which is an imaging element of a first type. Based on a difference in absorption coefficient, the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 photoelectrically convert blue light and red light, respectively. In addition, the first photoelectric conversion unit 311 photoelectrically converts, for example, green light. Figure 102 In the example shown, a third photoelectric conversion unit 331 and a second photoelectric conversion unit 321, which are photoelectric conversion units of a second type included in a third imaging element 330 and a second imaging element 320, are laminated and formed in a semiconductor substrate 370. In addition, a first photoelectric conversion unit 311, which is a photoelectric conversion unit of a first type, is arranged on the upper side of the semiconductor substrate 370 (specifically, the upper side of the second imaging element 320). Here, the first photoelectric conversion unit 311 includes a first electrode 311, a photoelectric conversion layer 313 containing an organic material, and a second electrode 312. The first photoelectric conversion unit 311 is included in a first imaging element 310, which is an imaging element of a first type. Based on a difference in absorption coefficient, the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 photoelectrically convert blue light and red light, respectively. In addition, the first photoelectric conversion unit 311 photoelectrically converts, for example, green light.

[0005] The electric charges generated by photoelectric conversion in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 are temporarily stored in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331. A vertical transistor (gate portion 322 is shown) and a transfer transistor (gate portion 332 is shown) transfer the electric charges to a second floating diffusion FD2 and a third floating diffusion FD3, respectively. The electric charges are further output to an external reading circuit (not shown). The transistors and the floating diffusions FD2 and FD3 are also formed on the semiconductor substrate 370.

[0006] The electric charges generated by photoelectric conversion in the first photoelectric conversion unit 311 are stored in a first floating diffusion FD1 formed on the semiconductor substrate 370 through the contact hole portion 361 and the wiring layer 362. In addition, the first photoelectric conversion unit 311 is also connected to a gate portion 318 of an amplification transistor that converts the amount of electric charges into a voltage through the contact hole portion 361 and the wiring layer 362. Further, the first floating diffusion FD1 includes a portion of a reset transistor (gate portion 317 is shown). Note that the reference numeral 371 denotes an element separation region. The reference numeral 372 denotes an oxide film formed on the surface of the semiconductor substrate 370. The reference numerals 376 and 381 denote interlayer insulating layers. The reference numeral 383 denotes a protective layer. The reference numeral 390 denotes an on-chip microlens.

[0007] Bibliographic search

[0008] Patent literature

[0009] Patent literature 1: Japanese Patent Laid-Open No. 2011-138927 SUMMARY

[0010] Technical problem to be solved by the invention

[0011] Meanwhile, in the imaging element having the configuration and structure, the electric charges generated by photoelectric conversion can flow into an adjacent imaging element. The so-called blooming phenomenon can occur, and the quality of a captured video (image) can be degraded.

[0012] Therefore, an object of the present disclosure is to provide an imaging element having a configuration and structure that is less likely to cause degradation in the quality of a captured video (image), a stacked imaging element including the imaging element, and a solid-state imaging device including the imaging element or the stacked imaging element.

[0013] Solution to the problem

[0014] Each of the imaging elements according to the first to seventh aspects of the present disclosure for achieving the object includes a photoelectric conversion unit including a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein the photoelectric conversion unit further includes a charge storage electrode arranged to be separated from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer.

[0015] Further, in the imaging element according to the first aspect, when photoelectric conversion occurs in the photoelectric conversion layer after light enters the photoelectric conversion layer, an absolute value of an electric potential applied to a portion of the photoelectric conversion layer facing the charge storage electrode is larger than an absolute value of an electric potential applied to a region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0016] Further, in the imaging element according to the second aspect of the present disclosure, a width of a region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is narrower than a width of a region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0017] Further, in the imaging element according to the third aspect of the present disclosure, the charge movement control electrode is formed in a region facing a region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element via the insulating layer.

[0018] Further, in the imaging element according to the fourth aspect of the present disclosure, instead of the second electrode, a charge movement control electrode is formed in a range of a region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0019] Further, in the imaging element according to the fifth aspect of the present disclosure, a value of a dielectric constant of an insulating material included in a region between the first electrode and the charge storage electrode is higher than a value of a dielectric constant of an insulating material included in a region between the imaging element and an adjacent imaging element.

[0020] Further, in the imaging element according to the sixth aspect of the present disclosure, a thickness of a region of the insulating layer located between the first electrode and the charge storage electrode is thinner than a thickness of a region of the insulating layer located between the imaging element and an adjacent imaging element.

[0021] Further, in the imaging element according to the seventh aspect of the present disclosure, a thickness of a region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is thicker than a thickness of a region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0022] Further, in the imaging element according to the eighth aspect of the present disclosure, the amount of fixed charge in a region of an interface between the photoelectric conversion layer and the insulating layer between the first electrode and the charge storage electrode is smaller than the amount of fixed charge in a region of an interface between the photoelectric conversion layer and the insulating layer between the imaging element and an adjacent imaging element.

[0023] Further, in the imaging element according to the ninth aspect of the present disclosure, the value of the charge mobility in a region of the photoelectric conversion layer between the first electrode and the charge storage electrode is larger than the value of the charge mobility in a region of the photoelectric conversion layer between the imaging element and an adjacent imaging element.

[0024] The laminated imaging element of the present disclosure for achieving the object includes at least one imaging element according to the first to ninth aspects of the present disclosure.

[0025] The solid-state imaging device according to the first aspect of the present disclosure for achieving the object includes a plurality of imaging elements according to the first to ninth aspects of the present disclosure. In addition, the solid-state imaging device according to the second aspect of the present disclosure for achieving the object includes a plurality of laminated imaging elements according to the present disclosure.

[0026] Advantages of the present disclosure

[0027] In each of the imaging element according to the first to ninth aspects of the present disclosure, the imaging element according to the first to ninth aspects of the present disclosure included in the laminated imaging element, and the imaging element according to the first to ninth aspects of the present disclosure included in the solid-state imaging device according to the first and second aspects of the present disclosure (hereinafter, in some cases, the imaging elements will be collectively referred to as “the imaging element and the like of the present disclosure”), a charge storage electrode is provided which is arranged separately from the first electrode and faces the photoelectric conversion layer via the insulating layer, and when light is applied to the photoelectric conversion unit and is photoelectrically converted by the photoelectric conversion unit, a charge can be stored in the photoelectric conversion layer. Therefore, it is possible to completely deplete the charge storage portion at the start of exposure to eliminate the charge. This can suppress the phenomenon of a decrease in imaging quality caused by the deterioration of random noise due to an increase in kTC noise.

[0028] Further, in each of the imaging element according to the first aspect of the present disclosure, the imaging element according to the first aspect of the present disclosure included in the stacked imaging element, and the imaging element according to the first aspect of the present disclosure included in the solid-state imaging device according to the first and second aspects of the present disclosure (hereinafter, the imaging elements will be collectively referred to as "the imaging element according to the first aspect of the present disclosure and the like" in some cases), when photoelectric conversion occurs in the photoelectric conversion layer after light enters the photoelectric conversion layer, the absolute value of the electric potential applied to the portion of the photoelectric conversion layer facing the charge storage electrode is greater than the absolute value of the electric potential applied to the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. Thus, the electric charge generated by the photoelectric conversion is strongly attracted to the portion of the photoelectric conversion layer facing the charge storage electrode. This can prevent the electric charge generated by the photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) does not decrease.

[0029] Further, in each of the imaging element according to the second aspect of the present disclosure, the imaging element according to the second aspect of the present disclosure included in the stacked imaging element, and the imaging element according to the second aspect of the present disclosure included in the solid-state imaging device according to the first and second aspects of the present disclosure (hereinafter, the imaging elements will be collectively referred to as "the imaging element according to the second aspect of the present disclosure and the like" in some cases), the width of the region of the photoelectric conversion layer between the first electrode and the charge storage electrode is narrower than the width of the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. Further, in this case, the region between the first electrode and the charge storage electrode is less likely to be affected by the voltage of the second electrode (upper electrode) than the portion between the imaging element and the adjacent imaging element. Thus, the electric potential becomes large, and this can prevent the electric charge generated by the photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) does not decrease.

[0030] Further, in each of the imaging element according to the third aspect of the present disclosure, the imaging element according to the third aspect of the present disclosure included in the stacked imaging element, and the imaging element according to the third aspect of the present disclosure included in the solid-state imaging device according to the first and second aspects of the present disclosure (hereinafter, the imaging elements will be collectively referred to as "the imaging element according to the third aspect of the present disclosure and the like" in some cases), the charge movement control electrode is formed in a region facing the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element via the insulating layer. This can control the electric field and the electric potential of the region of the photoelectric conversion layer on the upper side of the charge movement control electrode. As a result, the charge movement control electrode can prevent the electric charge generated by the photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) does not decrease.

[0031] Further, in each of the imaging element according to the fourth aspect of the present disclosure, the imaging element according to the fourth aspect of the present disclosure included in the stacked imaging element, and the imaging element according to the fourth aspect of the present disclosure included in the solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, the imaging elements will be collectively referred to as "the imaging element according to the fourth aspect of the present disclosure and the like" in some cases), a charge movement control electrode is formed on a region of the photoelectric conversion layer between the imaging element and the adjacent imaging element in place of the second electrode. Therefore, the charge movement control electrode can prevent the charge generated by the photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not reduced.

[0032] Further, in each of the imaging element according to the fifth aspect of the present disclosure, the imaging element according to the fifth aspect of the present disclosure included in the stacked imaging element, and the imaging element according to the fifth aspect of the present disclosure included in the solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, the imaging elements will be collectively referred to as "the imaging element according to the fifth aspect of the present disclosure and the like" in some cases), the value of the dielectric constant of the insulating material included in the region between the first electrode and the charge storage electrode is higher than the value of the dielectric constant of the insulating material included in the region between the imaging element and the adjacent imaging element. Therefore, the capacity of one kind of capacitor (for convenience, referred to as "capacitor A") formed in the region of the charge storage electrode between the first electrode and the charge storage electrode is larger than the capacity of one kind of capacitor (for convenience, referred to as "capacitor B") formed in the region of the charge storage electrode between the imaging element and the adjacent imaging element. The charge is more attracted to the region between the first electrode and the charge storage electrode than to the region between the imaging element and the adjacent imaging element. This can prevent the charge generated by the photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not reduced.

[0033] Further, in each of the imaging element according to the sixth aspect of the present disclosure, the imaging element according to the sixth aspect of the present disclosure included in the stacked imaging element, and the imaging element according to the sixth aspect of the present disclosure included in the solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, the imaging elements will be collectively referred to as "the imaging element according to the sixth aspect of the present disclosure and the like" in some cases), the thickness of the region of the insulating layer between the first electrode and the charge storage electrode is thinner than the thickness of the region of the insulating layer between the imaging element and the adjacent imaging element. Therefore, the capacity of the capacitor A is larger than the capacity of the capacitor B, and the charge is more attracted to the region of the insulating layer between the first electrode and the charge storage electrode than to the region of the insulating layer between the imaging element and the adjacent imaging element. This can prevent the charge generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not reduced.

[0034] Further, in each of the imaging element according to the seventh aspect of the present disclosure, the imaging element according to the seventh aspect of the present disclosure included in the stacked imaging element, and the imaging element according to the seventh aspect of the present disclosure included in the solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, the imaging elements will be collectively referred to as "the imaging element according to the seventh aspect of the present disclosure and the like" in some cases), the thickness of the region of the photoelectric conversion layer between the first electrode and the charge storage electrode is larger than the thickness of the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element. Further, in this case, the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element is more affected by the voltage of the second electrode (upper electrode), and the potential becomes smaller. This can prevent the charge generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not reduced.

[0035] Further, in each of the imaging element according to the eighth aspect of the present disclosure, the imaging element according to the eighth aspect of the present disclosure included in the stacked imaging element, and the imaging element according to the eighth aspect of the present disclosure included in the solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, the imaging elements will be collectively referred to as "the imaging element according to the eighth aspect of the present disclosure and the like" in some cases), the amount of fixed charge in the region of the interface between the photoelectric conversion layer and the insulating layer between the first electrode and the charge storage electrode is smaller than the amount of fixed charge in the region of the interface between the photoelectric conversion layer and the insulating layer between the imaging element and the adjacent imaging element. Further, in this case, the potential of the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element changes more according to the amount of fixed charge. This can prevent the charge generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not reduced.

[0036] Further, in each of the imaging element according to the ninth aspect of the present disclosure, the imaging element according to the ninth aspect of the present disclosure included in the stacked imaging element, and the imaging element according to the ninth aspect of the present disclosure included in the solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, in some cases, the imaging elements will be collectively referred to as "the imaging element according to the ninth aspect of the present disclosure and the like"), the value of the charge mobility in the region of the photoelectric conversion layer between the first electrode and the charge storage electrode is greater than the value of the charge mobility in the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element. In this case, charges flow more easily toward the first electrode than in the direction toward the adjacent imaging element. This can prevent the charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) does not decrease.

[0037] Note that the advantageous effects described in the present specification are merely illustrative and are not limiting. In addition, there can be other advantageous effects. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1A and Figure 1B are a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 1 and a schematic cross-sectional view of a modification example (modification example 6 of Example 1) of the imaging element (two imaging elements arranged side by side) of Example 1, respectively.

[0039] Figure 2 are schematic partial cross-sectional views of the imaging element and the stacked imaging element of Example 1.

[0040] Figure 3 are equivalent circuit diagrams of the imaging element and the stacked imaging element of Example 1.

[0041] Figure 4 are equivalent circuit diagrams of the imaging element and the stacked imaging element of Example 1.

[0042] Figure 5 is a schematic layout view of the transistor of the control unit included in the imaging element of Example 1.

[0043] Figure 6 is a schematic layout view of the first electrode and the charge storage electrode included in the imaging element of Example 1.

[0044] Figure 7 is a schematic layout view of a modification example (modification example of Example 1) of the first electrode and the charge storage electrode included in the imaging element of Example 1.

[0045] Figure 8 is a view schematically illustrating a state of electric potential in each portion during operation of the imaging element of Embodiment 1.

[0046] Figure 9A 9B and 9C are equivalent circuit diagrams of the imaging element and the stacked imaging element of Embodiment 1, Embodiment 11, and Embodiment 12, for describing each portion of Figure 8 (Embodiment 1), Figure 51 (Embodiment 11), and Figure 58 (Embodiment 12).

[0047] Figure 10 is a conceptual view of the solid-state imaging device of Embodiment 1.

[0048] Figure 11 is an equivalent circuit diagram of a modification example (modification example 2 of Embodiment 1) of the imaging element and the stacked imaging element of Embodiment 1.

[0049] Figure 12 is a schematic layout view of the transistor of the control unit included in the modification example (modification example 2 of Embodiment 1) of the imaging element of Embodiment 1 illustrated in Figure 11

[0050] Figure 13 is a schematic layout view of the first electrode and the charge storage electrode included in the modification example (modification example 3 of Embodiment 1) of the imaging element of Embodiment 1.

[0051] Figure 14A 14B is a schematic layout view of the first electrode and the charge storage electrode included in the modification example (modification example 4 of Embodiment 1) of the imaging element of Embodiment 1.

[0052] Figure 15A 15B is a schematic layout view of the first electrode and the charge storage electrode included in the modification example (modification example 5 of Embodiment 1) of the imaging element of Embodiment 1.

[0053] Figure 16A is a schematic cross-sectional view taken along the single-dot chain line B-B of Figure 15B in the modification example 5 of Embodiment 1 illustrated in Figure 15B Figure 16B is a schematic cross-sectional view taken along the single-dot chain line A-A of Figure 15A when the discharge electrode is replaced by the charge movement control electrode in the modification example 5 of Embodiment 1 illustrated in Figure 15A

[0054] Figure 17A 17B ​​​​​​​is a schematic sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Example 2.

[0055] Figure 18A and 18B is a schematic sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Example 3.

[0056] Figure 19 is a schematic plan view of a portion of the imaging element (2x2 imaging elements arranged side by side) of Example 3.

[0057] Figure 20 is a schematic plan view of a portion of a modification (Modification 1 of Example 3) of the imaging element (2x2 imaging elements arranged side by side) of Example 3.

[0058] Figure 21A and 21B is a view schematically illustrating a change in electric potential within the photoelectric conversion layer in the imaging element of Example 1 in which the charge storage electrode is provided on the lower side of the photoelectric conversion layer and a change in electric potential within the photoelectric conversion layer in the imaging element of Example 3 in which the charge storage electrode is provided on the upper side of the photoelectric conversion layer.

[0059] Figure 22A and 22B is a schematic plan view of a portion of a modification (Modification 2 of Example 3) of the imaging element of Example 3.

[0060] Figure 23A , 23B and 23C is a schematic plan view of a portion of a modification (Modification 3 of Example 3) of the imaging element of Example 3.

[0061] Figure 24A and 24B is a schematic sectional view of a portion of a modification (Modification 4A and Modification 4B of Example 3) of the imaging element (two imaging elements arranged side by side) of Example 3.

[0062] Figure 25A and 25B is a schematic plan view of a modification (Modification 4A of Example 3) of the imaging element of Example 3.

[0063] Figure 26A and 26B is a schematic plan view of a modification (Modification 4B of Example 3) of the imaging element of Example 3.

[0064] Figure 27A and 27B is a schematic plan view of a modification (Modification 4C of Example 3) of the imaging element of Example 3.

[0065] Figure 28A and 28B is a schematic plan view of a modification example of the imaging element of Example 3 (modification example 4D of Example 3).

[0066] Figure 29A , 29B and 29C are diagrams schematically illustrating a state of electric potentials of each part in modification example 4B of Example 3, modification example 4C of Example 3, and modification example 4D of Example 3, respectively.

[0067] Figure 30 is a schematic cross-sectional view of a part of the imaging element of Example 4 (two imaging elements arranged side by side).

[0068] Figure 31 is a schematic cross-sectional view of a part of a modification example of the imaging element of Example 4 (two imaging elements arranged side by side).

[0069] Figure 32 is a schematic cross-sectional view of a part of another modification example of the imaging element of Example 4 (two imaging elements arranged side by side).

[0070] Figure 33 is a schematic cross-sectional view of a part of still another modification example of the imaging element of Example 4 (two imaging elements arranged side by side).

[0071] Figure 34 is a schematic cross-sectional view of a part of the imaging element of Example 5 (two imaging elements arranged side by side).

[0072] Figure 35 is a schematic cross-sectional view of a part of a modification example of the imaging element of Example 5 (two imaging elements arranged side by side).

[0073] Figure 36 is a schematic cross-sectional view of a part of another modification example of the imaging element of Example 5 (two imaging elements arranged side by side).

[0074] Figure 37 is a schematic cross-sectional view of a part of the imaging element of Example 6 (two imaging elements arranged side by side).

[0075] Figure 38 is a schematic cross-sectional view of a part of a modification example of the imaging element of Example 6 (two imaging elements arranged side by side).

[0076] Figure 39 is a schematic cross-sectional view of a part of the imaging element of Example 7 (two imaging elements arranged side by side).

[0077] Figure 40is a schematic sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Example 8.

[0078] Figure 41 is a schematic sectional view of a portion of a modification of the imaging element (two imaging elements arranged side by side) of Example 8.

[0079] Figure 42 is a schematic partial sectional view of the imaging element and the stacked imaging element of Example 9.

[0080] Figure 43 is a schematic partial sectional view of the imaging element and the stacked imaging element of Example 10.

[0081] Figure 44 is a schematic partial sectional view of a modification of the imaging element and the stacked imaging element of Example 10.

[0082] Figure 45 is a schematic partial sectional view of another modification of the imaging element and the stacked imaging element of Example 10.

[0083] Figure 46 is a schematic partial sectional view of still another modification of the imaging element and the stacked imaging element of Example 10.

[0084] Figure 47 is a schematic partial sectional view of the imaging element and the stacked imaging element of Example 11.

[0085] Figure 48 is an equivalent circuit diagram of the imaging element and the stacked imaging element of Example 11.

[0086] Figure 49 is an equivalent circuit diagram of the imaging element and the stacked imaging element of Example 11.

[0087] Figure 50 is a schematic layout view of a transistor included in the first electrode, the transfer control electrode, the charge storage electrode, and the control unit of the imaging element of Example 11.

[0088] Figure 51 is a view schematically illustrating a state of potentials in the portions during a period of operation of the imaging element of Example 11.

[0089] Figure 52 is a view schematically illustrating a state of potentials in the portions during another period of operation of the imaging element of Example 11.

[0090] Figure 53is a schematic layout view of a transistor of the first electrode, the transfer control electrode, the charge storage electrode, and the control unit included in the imaging device of Example 11.

[0091] Figure 54 is a schematic partial sectional view of the imaging device and the stacked imaging device of Example 12.

[0092] Figure 55 is an equivalent circuit diagram of the imaging device and the stacked imaging device of Example 12.

[0093] Figure 56 is an equivalent circuit diagram of the imaging device and the stacked imaging device of Example 12.

[0094] Figure 57 is a schematic layout view of a transistor of the first electrode, the charge storage electrode, and the control unit included in the imaging device of Example 12.

[0095] Figure 58 is a view schematically illustrating a state of potentials in each portion during a period of operation of the imaging device of Example 12.

[0096] Figure 59 is a view schematically illustrating a state of potentials in each portion during another period of operation (charge transfer period) of the imaging device of Example 12.

[0097] Figure 60 is a schematic layout view of the first electrode and the charge storage electrode included in a modification example of the imaging device of Example 12.

[0098] Figure 61 is a schematic partial sectional view of the imaging device and the stacked imaging device of Example 13.

[0099] Figure 62 is a schematic partial enlarged sectional view of a portion in which the charge storage electrode, the photoelectric conversion layer, and the second electrode are stacked in the imaging device of Example 13.

[0100] Figure 63 is a schematic layout view of a transistor of the first electrode, the charge storage electrode, and the control unit included in a modification example of the imaging device of Example 13.

[0101] Figure 64 is a schematic partial enlarged sectional view of a portion in which the charge storage electrode, the photoelectric conversion layer, and the second electrode are stacked in the imaging device of Example 14.

[0102] Figure 65 is a schematic partial sectional view of the imaging device and the stacked imaging device of Example 15.

[0103] Figure 66 is a schematic partial sectional view of the imaging element and the stacked imaging element of Examples 16 and 17.

[0104] Figure 67A and 67B is a schematic plan view of the charge storage electrode section in Example 17.

[0105] Figure 68A and 68B is a schematic plan view of the charge storage electrode section in Example 17.

[0106] Figure 69 is a schematic layout view of the transistor of the first electrode, the charge storage electrode, and the control unit included in the imaging element of Example 17.

[0107] Figure 70 is a schematic layout view of the first electrode and the charge storage electrode included in the modified example of the imaging element of Example 17.

[0108] Figure 71 is a schematic partial sectional view of the imaging element and the stacked imaging element of Examples 18 and 17.

[0109] Figure 72A and 72B is a schematic plan view of the charge storage electrode section in Example 18.

[0110] Figure 73 is a schematic plan view of the first electrode and the charge storage electrode section in the solid-state imaging device of Example 19.

[0111] Figure 74 is a schematic plan view of the first electrode and the charge storage electrode section in the first modified example of the solid-state imaging device of Example 19.

[0112] Figure 75 is a schematic plan view of the first electrode and the charge storage electrode section in the second modified example of the solid-state imaging device of Example 19.

[0113] Figure 76 is a schematic plan view of the first electrode and the charge storage electrode section in the third modified example of the solid-state imaging device of Example 19.

[0114] Figure 77 is a schematic plan view of the first electrode and the charge storage electrode section in the fourth modified example of the solid-state imaging device of Example 19.

[0115] Figure 78 is a schematic plan view of the first electrode and the charge storage electrode section in the fifth modified example of the solid-state imaging device of Example 19.

[0116] Figure 79 is a schematic plan view of the first electrode and the charge storage electrode section in a sixth variant example of the solid-state imaging device of Embodiment 19.

[0117] Figure 80 is a schematic plan view of the first electrode and the charge storage electrode section in a seventh variant example of the solid-state imaging device of Embodiment 19.

[0118] Figure 81 is a schematic plan view of the first electrode and the charge storage electrode section in an eighth variant example of the solid-state imaging device of Embodiment 19.

[0119] Figure 82 is a schematic plan view of the first electrode and the charge storage electrode section in a ninth variant example of the solid-state imaging device of Embodiment 19.

[0120] Figure 83A , 83B and 83C are diagrams showing examples of reading and driving in the imaging element block of Embodiment 19.

[0121] Figure 84 is a schematic plan view of the first electrode and the charge storage electrode section of the solid-state imaging device of Embodiment 20.

[0122] Figure 85 is a schematic plan view of the first electrode and the charge storage electrode section in a variant example of the solid-state imaging device of Embodiment 20.

[0123] Figure 86 is a schematic plan view of the first electrode and the charge storage electrode section in a variant example of the solid-state imaging device of Embodiment 20.

[0124] Figure 87 is a schematic plan view of the first electrode and the charge storage electrode section in a variant example of the solid-state imaging device of Embodiment 20.

[0125] Figure 88 is a schematic partial cross-sectional view of another variant example of the imaging element and the stacked imaging element of Embodiment 1.

[0126] Figure 89 is a schematic partial cross-sectional view of still another variant example of the imaging element and the stacked imaging element of Embodiment 1.

[0127] Figure 90A , 90B and 90C are schematic partial enlarged cross-sectional views of parts of the first electrode and the like in still another variant example of the imaging element and the stacked imaging element of Embodiment 1.

[0128] Figure 91is a schematic partial sectional view of still another modification example of the imaging element and the stacked imaging element of Example 1.

[0129] Figure 92 is a schematic partial sectional view of still another modification example of the imaging element and the stacked imaging element of Example 1.

[0130] Figure 93 is a schematic partial sectional view of still another modification example of the imaging element and the stacked imaging element of Example 1.

[0131] Figure 94 is a schematic partial sectional view of another modification example of the imaging element and the stacked imaging element of Example 11.

[0132] Figure 95 is a schematic partial sectional view of still another modification example of the imaging element and the stacked imaging element of Example 1.

[0133] Figure 96 is a schematic partial sectional view of still another modification example of the imaging element and the stacked imaging element of Example 1.

[0134] Figure 97 is a schematic partial enlarged sectional view of a portion in which a charge storage electrode, a photoelectric conversion layer, and a second electrode are stacked in a modification example of the imaging element of Example 13.

[0135] Figure 98 is a schematic partial enlarged sectional view of a portion in which a charge storage electrode, a photoelectric conversion layer, and a second electrode are stacked in a modification example of the imaging element of Example 14.

[0136] Figure 99A and 99B is an equivalent circuit diagram of a modification example of a transistor that drives a charge storage electrode.

[0137] Figure 100A and 100B is a diagram schematically illustrating a pulse waveform of a transistor in the equivalent circuit shown in Figure 99A and 99B is a diagram schematically illustrating a pulse waveform of a transistor in the equivalent circuit shown in

[0138] Figure 101 is a conceptual diagram of an example in which a solid-state imaging device including the imaging element and the stacked imaging element of the present disclosure is used in an electronic device (camera).

[0139] Figure 102 is a conceptual diagram of a conventional stacked imaging element (stacked solid-state imaging device).

[0140] Description of Embodiments

[0141] Hereinafter, the present disclosure will be described based on embodiments with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments, and the various values and materials in the embodiments are illustrative. Note that the present disclosure will be described in the following order.

[0142] 1. General description of imaging elements and stacked imaging elements according to the first to ninth aspects of the present disclosure and solid-state imaging devices according to the first and second aspects of the present disclosure

[0143] 2. Embodiment 1 (imaging element according to the first to third aspects of the present disclosure, stacked imaging element of the present disclosure, and solid-state imaging device according to the second aspect of the present disclosure)

[0144] 3. Embodiment 2 (imaging element according to the second aspect of the present disclosure)

[0145] 4. Embodiment 3 (imaging element according to the fourth aspect of the present disclosure)

[0146] 5. Embodiment 4 (imaging element according to the fifth aspect of the present disclosure)

[0147] 6. Embodiment 5 (imaging element according to the sixth aspect of the present disclosure)

[0148] 7. Embodiment 6 (imaging element according to the seventh aspect of the present disclosure)

[0149] 8. Embodiment 7 (imaging element according to the eighth aspect of the present disclosure)

[0150] 9. Embodiment 8 (imaging element according to the ninth aspect of the present disclosure)

[0151] 10. Embodiment 9 (modification of the imaging elements of Embodiments 1 to 8)

[0152] 11. Embodiment 10 (modification of Embodiments 1 to 9, solid-state imaging device according to the first aspect of the present disclosure)

[0153] 12. Embodiment 11 (modification of Embodiments 1 to 10, imaging element including a transfer control electrode)

[0154] 13. Embodiment 12 (modification of Embodiments 1 to 11, imaging element including a plurality of charge storage electrode sections)

[0155] 14. Embodiment 13 (imaging element of the first configuration and the sixth configuration)

[0156] 15. Embodiment 14 (imaging element of the second configuration and the sixth configuration of the present disclosure)

[0157] 16. Embodiment 15 (imaging element of the third configuration)

[0158] 17. Example 16 (Imaging element of the fourth construction)

[0159] 18. Example 17 (Imaging element of the fifth construction)

[0160] 19. Example 18 (Imaging element of the sixth construction)

[0161] 20. Example 19 (Solid-state imaging device with first and second structures)

[0162] 21. Example 20 (a variation of Example 19)

[0163] 22. Other Detailed Implementation

[0164] <General description of the imaging elements and stacked imaging elements of the first to ninth aspects of this disclosure, and the solid-state imaging apparatus of the first to second aspects of this disclosure>

[0165] In the following description, for convenience, the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is referred to as "region A of the photoelectric conversion layer," and the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element is referred to as "region B of the photoelectric conversion layer." Furthermore, for convenience, the region of the insulating layer located between the first electrode and the charge storage electrode is referred to as "region A of the insulating layer," and the region of the insulating layer located between the imaging element and the adjacent imaging element is referred to as "region B of the insulating layer." Region B of the photoelectric conversion layer corresponds to region B of the insulating layer. Furthermore, for convenience, the region between the first electrode and the charge storage electrode is referred to as "region a," and the region between the imaging element and the adjacent imaging element is referred to as "region b." In region a, region A of the photoelectric conversion layer corresponds to region A of the insulating layer. In region b, region B of the photoelectric conversion layer corresponds to region B of the insulating layer.

[0166] In imaging elements and the like according to the first and second aspects of the present invention, in other words, region B of the photoelectric conversion layer refers to a portion of the photoelectric conversion layer that is positioned on the portion of the insulating layer located in the region (region b) between the charge storage electrode and the charge storage electrode included in the adjacent imaging element (region B of the insulating layer).

[0167] In the imaging element, etc. according to the third aspect of the present application, a charge movement control electrode is formed in a region of the region B facing the photoelectric conversion layer via the insulating layer. In other words, the charge movement control electrode is formed under a portion of the insulating layer (region B of the insulating layer) in a region (region b) of the insulating layer between the charge storage electrode and a charge storage electrode included in an adjacent imaging element. The charge movement control electrode is disposed away from the charge storage electrode. Or, in other words, the charge movement control electrode is disposed around and separated from the charge storage electrode, and the charge movement control electrode is arranged to face the region B of the photoelectric conversion layer via the insulating layer.

[0168] In the imaging element, etc. according to the fourth aspect of the present application, a charge movement control electrode is formed in a region of the photoelectric conversion layer between the imaging element and an adjacent imaging element, instead of the second electrode. The charge movement control electrode is disposed separately from the second electrode. In other words:

[0169] [A] The second electrode can be provided for each imaging element, and the charge movement control electrode can be disposed to surround at least a portion of the second electrode on the region B of the photoelectric conversion layer and separate from the second electrode,

[0170] [B] The second electrode can be provided for each imaging element, the charge movement control electrode can be disposed to surround at least a portion of the second electrode and separate from the second electrode, and a portion of the charge storage electrode can exist on the lower side of the charge movement control electrode, or

[0171] [C] The second electrode can be provided for each imaging element, the charge movement control electrode can be disposed to surround at least a portion of the second electrode and separate from the second electrode, a portion of the charge storage electrode can exist on the lower side of the charge movement control electrode, and in addition, the charge movement control electrode in the imaging element, etc. according to the third aspect can be formed on the lower side of the charge movement control electrode. The electric potential generated by the coupling of the charge movement control electrode and the second electrode is in some cases applied to a region of the photoelectric conversion layer below the region between the charge movement control electrode and the second electrode.

[0172] In the imaging element or the like according to the fifth aspect of the present application, the insulating material contained in the region A (referred to as "insulating material A" for convenience) can fill all of the region A from the planar surface, can fill a part of the region A, can include above the edge portion of the charge storage electrode facing the region A (edge portion facing the region A), or can be formed on a part or all of the charge storage electrode. Alternatively, the insulating material can fill all of the region A or can fill a part of the region A in the thickness direction of the insulating layer. The insulating material contained in the region B (region b) of the insulating layer (referred to as "insulating material B" for convenience) can fill all of the region B of the insulating layer from the planar surface, can fill a part of the region B (region b) of the insulating layer, or can include the region B (region b) of the insulating layer to the edge portion of the charge storage electrode facing the region B (region b) of the insulating layer. Alternatively, the insulating material can fill all of the region B (region b) of the insulating layer or can fill a part of the region B (region b) of the insulating layer in the thickness direction of the insulating layer.

[0173] In the imaging element or the like according to the sixth aspect of the present application, the thickness of the region A of the insulating layer is thinner than the thickness of the region B of the insulating layer. All of the region A of the insulating layer and the region B of the insulating layer can satisfy the requirement, or a part of the region can satisfy the requirement.

[0174] In the imaging element or the like according to the seventh aspect of the present application, the thickness of the region A of the photoelectric conversion layer is thicker than the thickness of the region B of the photoelectric conversion layer. All of the region A of the photoelectric conversion layer and the region B of the photoelectric conversion layer can satisfy the requirement, or a part of the region can satisfy the requirement. The thickness of the region B of the photoelectric conversion layer can be "0". That is, depending on the case, the region of the photoelectric conversion layer positioned between the imaging element and the adjacent imaging element can not exist.

[0175] In the imaging element or the like according to the eighth aspect of the present application, the amount of the fixed charge in the region of the interface between the region A of the photoelectric conversion layer and the region A of the insulating layer is smaller than the amount of the fixed charge in the region of the interface between the region B of the photoelectric conversion layer and the region B of the insulating layer. All of the region of the interface between the region A of the photoelectric conversion layer and the region A of the insulating layer and the region of the interface between the region B of the photoelectric conversion layer and the region B of the insulating layer can satisfy the requirement, or a part of the region can satisfy the requirement.

[0176] In the imaging element, etc. according to the ninth aspect of the present application, the value of the charge mobility in the region A of the photoelectric conversion layer (referred to as "charge mobility A" for convenience) is greater than the value of the charge mobility in the region B of the photoelectric conversion layer (referred to as "charge mobility B" for convenience). All of the region A of the photoelectric conversion layer and the region B of the photoelectric conversion layer can satisfy the requirement, or a part of the regions can satisfy the requirement. Alternatively, the region of the photoelectric conversion layer having the charge mobility A can extend over a part or all of the charge storage electrode.

[0177] The imaging element, etc. according to the third aspect of the present application can further include a control unit provided on the semiconductor substrate and including a drive circuit, in which

[0178] The first electrode, the second electrode, the charge storage electrode, and the charge movement control electrode are connected to the drive circuit,

[0179] During the charge storage, the drive circuit applies a potential V 11 to the first electrode, applies a potential V 12 to the charge storage electrode, and applies a potential V 13 to the charge movement control electrode, and charges are stored in the photoelectric conversion layer, and

[0180] During the charge transfer, the drive circuit applies a potential V 21 to the first electrode, applies a potential V 22 to the charge storage electrode, and applies a potential V 23 to the charge movement control electrode, and the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, in which

[0181] In a case where the potential of the first electrode is higher than the potential of the second electrode,

[0182] V 12 ≥ V 11 , V 12 > V 13 , and V 21 > V 22 > V 23 are maintained, and

[0183] In a case where the potential of the first electrode is lower than the potential of the second electrode,

[0184] V 12 ≤ V 11 , V 12 < V 13 , V 21 < V 22 < V 23The potential of the first electrode, the potential of the second electrode, the potential of the charge storage electrode, and the potential of the charge movement control electrode are maintained. The charge movement control electrode can be formed at the same level as the first electrode or the charge storage electrode, or can be formed at a different level.

[0185] The imaging element according to the fourth aspect of the present application can further include a control unit provided on the semiconductor substrate and including a drive circuit, wherein

[0186] The first electrode, the second electrode, the charge storage electrode, and the charge movement control electrode are connected to the drive circuit,

[0187] During the charge storage, the drive circuit applies a potential V2' to the second electrode and a potential V 13 ' to the charge movement control electrode, and charges are stored in the photoelectric conversion layer, and

[0188] During the charge transfer, the drive circuit applies a potential V2" to the second electrode and a potential V 23 " to the charge movement control electrode, and the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, wherein

[0189] In a case where the potential of the first electrode is higher than the potential of the second electrode

[0190] V2' ≥ V 13 ' and V2" ≥ V 23 " are maintained, and

[0191] In a case where the potential of the first electrode is lower than the potential of the second electrode

[0192] V2' ≤ V 13 ' and V2" ≤ V 23 " are maintained. The charge movement control electrode is formed at the same level as the second electrode.

[0193] Each of the imaging elements according to the present disclosure including the above-described preferred modes can further include a semiconductor substrate, wherein the photoelectric conversion unit is disposed on an upper side of the semiconductor substrate. Note that the first electrode, the charge storage electrode, the second electrode, and various electrodes are connected to the drive circuit described later.

[0194] Further, each of the imaging elements according to the present disclosure including the above-described various preferred modes can further include a transfer control electrode (charge transfer electrode) disposed between the first electrode and the charge storage electrode, disposed to be separated from the first electrode and the charge storage electrode, and disposed to face the photoelectric conversion layer via an insulating layer. Note that, for convenience, the imaging element according to the present disclosure in this mode is referred to as an "imaging element according to the present disclosure including a transfer control electrode" in some cases. Further, the imaging element according to the present disclosure including a transfer control electrode can further include:

[0195] A control unit provided on a semiconductor substrate and including a drive circuit, wherein

[0196] The first electrode, the charge storage electrode, and the transfer control electrode are connected to the drive circuit,

[0197] During charge storage, the drive circuit applies a potential V 11 to the first electrode, a potential V 12 to the charge storage electrode, and a potential V 14 to the transfer control electrode, and charges are stored in the photoelectric conversion layer, and

[0198] During charge transfer, the drive circuit applies a potential V 21 to the first electrode, a potential V 22 to the charge storage electrode, and a potential V 24 to the transfer control electrode, and charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, wherein

[0199] In a case where the potential of the first electrode is higher than the potential of the second electrode

[0200] V 12 > V 14 and V 22 ≤ V 24 ≤ V 21 are maintained, and

[0201] In a case where the potential of the first electrode is lower than the potential of the second electrode

[0202] V 12 < V 14 and V 22 ≥ V 24 ≥ V 21 are maintained.

[0203] Further, in each of the imaging element and the like of the present disclosure including the above-described various preferred modes, the charge storage electrode can include a plurality of charge storage electrode sections. Note that, for convenience, in some cases, the imaging element and the like of the present disclosure in the mode is referred to as the “imaging element and the like of the present disclosure including a plurality of charge storage electrode sections”. The number of the charge storage electrode sections can be equal to or greater than 2. Further, in a case where different potentials are applied to each of N charge storage electrode sections in the imaging element and the like of the present disclosure including a plurality of charge storage electrode sections,

[0204] In a case where the potential of the first electrode is higher than the potential of the second electrode, the potential applied to the charge storage electrode section positioned at the position closest to the first electrode (the first photoelectric conversion unit section) can be higher than the potential applied to the charge storage electrode section positioned at the position farthest from the first electrode (the Nth photoelectric conversion unit section) during the charge transfer, and

[0205] In a case where the potential of the first electrode is lower than the potential of the second electrode, the potential applied to the charge storage electrode section positioned at the position closest to the first electrode (the first photoelectric conversion unit section) can be lower than the potential applied to the charge storage electrode section positioned at the position farthest from the first electrode (the Nth photoelectric conversion unit section) during the charge transfer.

[0206] Further, in each of the imaging element S and the like of the present disclosure including the above-described various preferred modes, the size of the charge storage electrode can be larger than the size of the first electrode. Although not limited, it is preferable to satisfy

[0207] 4 ≤ S1' / S1,

[0208] where S1' is the area of the charge storage electrode, and S1 is the area of the first electrode.

[0209] In the imaging element according to the second aspect of the present disclosure, the width W of the region A of the photoelectric conversion layer A is narrower than the width W of the region B of the photoelectric conversion layer B , and (W A / W B ) has a value of

[0210] 1 / 2 ≤ (W A / W B ) < 1.

[0211] In the imaging element according to the fifth aspect of the present disclosure, a specific example of the insulating material A includes SiN, and a specific example of the insulating material B includes SiO2.

[0212] In the imaging element according to the sixth aspect of the present disclosure, the thickness t of the region A of the insulating layer In-A is thinner than the thickness t of the region B of the insulating layer In-B , and (t In-A / t In-B ) has a value of

[0213] 1 / 2 ≤ (t In-A / t In-B ) < 1.

[0214] In the imaging element according to the seventh aspect of the present disclosure, the thickness t of the region A of the photoelectric conversion layer Pc-AThe thickness t of the region B of the photoelectric conversion layer Pc-B thick, and (t Pc-A / t Pc-B ) has a value of

[0215] 1<(t Pc-A / t Pc-B )≤2.

[0216] In the imaging device according to the eighth aspect of the present application, the amount of fixed charge FC A in the region of the interface between the region A of the photoelectric conversion layer and the region A of the insulating layer is smaller than the amount of fixed charge FC B .

[0217] 1 / 10≤(FC A / FC B )<1.

[0218] Here, the amount of fixed charge in the region of the interface between the photoelectric conversion layer and the insulating layer can be controlled based on, for example, the method of depositing a thin film having fixed charge.

[0219] In the imaging device according to the ninth aspect of the present application, the value CT A of the charge mobility in the region A of the photoelectric conversion layer is larger than the value CT B of the charge mobility in the region B of the photoelectric conversion layer.

[0220] 1<(CT A / CT B )≤1×10 2 .

[0221] The material contained in the region A of the photoelectric conversion layer and the material contained in the region B of the photoelectric conversion layer can be appropriately selected from the materials contained in the photoelectric conversion layer. Alternatively, a part of the photoelectric conversion layer can have a double-layer structure of an upper layer / lower layer. The upper layer of the region A of the photoelectric conversion layer and the upper layer of the region B of the photoelectric conversion layer and the part of the photoelectric conversion layer positioned on the upper side of the charge storage electrode can contain the same material (referred to as "upper layer constituent material" for convenience). The lower layer of the region A of the photoelectric conversion layer and the lower layer of the part of the photoelectric conversion layer positioned on the upper side of the charge storage electrode can contain the same material (referred to as "lower layer constituent material" for convenience). The upper layer constituent material and the lower layer constituent material can be different.

[0222] In this way, the lower layer of the photoelectric conversion layer (which will be referred to as the "lower semiconductor layer" in some cases) can be provided to prevent, for example, recombination during the charge storage period. This can also improve the efficiency of the charge transfer of the charge stored in the photoelectric conversion layer to the first electrode. Furthermore, the charge generated in the photoelectric conversion layer can be temporarily held to control the timing of the transfer and the like. In addition, the generation of dark current can also be suppressed. Note that the upper layer of the photoelectric conversion layer will be referred to as the "upper photoelectric conversion layer" in some cases.

[0223] In addition to the imaging element and the like according to the fourth aspect of the present disclosure, the second electrode on the light incident side can be shared by a plurality of imaging elements. That is, the second electrode can be a so-called solid electrode. In the imaging element and the like of the present disclosure, the photoelectric conversion layer is shared by a plurality of imaging elements. That is, one photoelectric conversion layer is formed in a plurality of imaging elements.

[0224] Furthermore, in the imaging element and the like of the present disclosure including the above-described various preferred modes, the first electrode can extend in the opening portion provided in the insulating layer and can be connected to the photoelectric conversion layer. Alternatively, the photoelectric conversion layer can extend in the opening portion provided in the insulating layer and can be connected to the first electrode. In this case,

[0225] An edge portion of the top surface of the first electrode can be covered by the insulating layer,

[0226] The first electrode can be exposed on the bottom surface of the opening portion, and

[0227] The side surface of the opening portion can be inclined to extend from a first surface to a second surface, where the first surface is a surface of the insulating layer that is in contact with the top surface of the first electrode, and the second surface is a surface of the insulating layer that is in contact with a portion of the photoelectric conversion layer that faces the charge storage electrode. Furthermore, the side surface of the opening portion that extends obliquely from the first surface to the second surface can be on the charge storage electrode side. Note that another layer can also be formed between the photoelectric conversion layer and the first electrode (for example, a layer of a material suitable for charge storage can be formed between the photoelectric conversion layer and the first electrode).

[0228] Furthermore, in the imaging element and the like of the present disclosure including the above-described various preferred modes,

[0229] At least the floating diffusion layer and the amplification transistor included in the control unit can be provided on the semiconductor substrate, and

[0230] The first electrode can be connected to the gate portion of the floating diffusion layer and the amplification transistor. Furthermore, in this case,

[0231] The reset transistor and the selection transistor included in the control unit can be further provided on the semiconductor substrate,

[0232] The floating diffusion layer can be connected to one source / drain region of the reset transistor

[0233] One source / drain region of the amplification transistor can be connected to one source / drain region of the selection transistor, and the other source / drain region of the selection transistor can be connected to the signal line.

[0234] Alternatively, a variant of the imaging element and the like of the present disclosure including the above-described various preferred modes includes the first to sixth configurations of the imaging element described below. That is, in each of the first to sixth configurations of the imaging element in the imaging element and the like of the present disclosure including the above-described various preferred modes,

[0235] The photoelectric conversion unit includes N (where N ≥ 2) photoelectric conversion unit segments,

[0236] The photoelectric conversion layer includes N photoelectric conversion layer segments,

[0237] The insulating layer includes N insulating layer segments,

[0238] In each of the first to third configurations of the imaging element, the charge storage electrode includes N charge storage electrode segments,

[0239] In each of the fourth and fifth configurations of the imaging element, the charge storage electrode includes N charge storage electrode segments arranged apart from each other,

[0240] The nth (where n = 1, 2, 3, ·· N) photoelectric conversion unit segment includes the nth charge storage electrode segment, the nth insulating layer segment, and the nth photoelectric conversion layer segment, and

[0241] The larger the value of n of the photoelectric conversion unit segment, the farther the position of the photoelectric conversion unit segment from the first electrode.

[0242] Further, in the imaging element of the first configuration, the thickness of the photoelectric conversion layer segment gradually changes from the first photoelectric conversion unit segment to the Nth photoelectric conversion unit segment. Further, in the imaging element of the second configuration, the thickness of the photoelectric conversion layer segment gradually changes from the first photoelectric conversion unit segment to the Nth photoelectric conversion unit segment. Further, in the imaging element of the third configuration, the material included in the insulating layer segment is varied between adjacent photoelectric conversion unit segments. Further, in the imaging element of the fourth configuration, the material included in the charge storage electrode segment is varied between adjacent photoelectric conversion unit segments. Further, in the imaging element of the fifth configuration, the area of the charge storage electrode segment gradually decreases from the first photoelectric conversion unit segment to the Nth photoelectric conversion unit segment. Note that the area can continuously decrease or can decrease in steps.

[0243] Alternatively, in the imaging element of the sixth configuration of the present disclosure including the above-described various preferred modes, a cross-sectional area of a laminated portion of the charge storage electrode, the insulating layer, and the photoelectric conversion layer (when the laminated portion is cut in a YZ virtual plane) varies with a distance from the first electrode, where the Z direction is a laminating direction of the charge storage electrode, the insulating layer, and the photoelectric conversion layer, and the X direction is a direction away from the first electrode. Note that the variation in the cross-sectional area can be a continuous variation or a stepwise variation.

[0244] In each of the imaging elements of the first and second configurations, the N photoelectric conversion layer segments are continuously provided, the N insulating layer segments are also continuously provided, and the N charge storage electrode segments are further continuously provided. In each of the imaging elements of the third to fifth configurations, the N photoelectric conversion layer segments are continuously provided. Further, in each of the imaging elements of the fourth and fifth configurations, the N insulating layer segments are continuously provided. On the other hand, in the imaging element of the third configuration, the N insulating layer segments are provided so as to respectively correspond to the photoelectric conversion cell segments. Further, in each of the imaging elements of the fourth and fifth configurations and in the imaging element of the third configuration, the N charge storage electrode segments are provided so as to respectively correspond to the photoelectric conversion cell segments, as appropriate. Further, in each of the imaging elements of the first to sixth configurations, the same electric potential is applied to all of the charge storage electrode segments. Alternatively, in each of the imaging elements of the fourth and fifth configurations and in the imaging element of the third configuration, different electric potentials can be applied to each of the N charge storage electrode segments, as appropriate.

[0245] In each of the imaging elements of the first to sixth configurations and the laminated imaging element and the solid-state imaging device of the present disclosure to which the imaging element is applied, the thickness of the insulating layer segment is defined, the thickness of the photoelectric conversion layer segment is defined, the material included in each of the insulating layer segments is different, the material included in each of the charge storage electrode segments is different, the area of the charge storage electrode segment is defined, or the cross-sectional area of the laminated portion is defined. Thereby, a charge transport gradient is formed, and the charge generated by the photoelectric conversion can be more easily and more certainly transported to the first electrode. In addition, as a result, it is possible to prevent the generation of afterimage or charge transfer leftover.

[0246] A modification example of the laminated imaging element of the present disclosure includes a laminated imaging element including at least one of the imaging elements of the first to sixth configurations. Further, a modification example of the solid-state imaging device according to the first aspect of the present disclosure includes a solid-state imaging device including a plurality of the imaging elements of the first to sixth configurations. A modification example of the solid-state imaging device according to the second aspect of the present disclosure includes a solid-state imaging device including a plurality of laminated imaging elements each including at least one of the imaging elements of the first to sixth configurations.

[0247] In each of the imaging elements of the first to fifth configurations, the greater the n value of the photoelectric conversion unit section, the farther the photoelectric conversion unit section is from the first electrode. The direction in which the photoelectric conversion unit section is positioned away from the first electrode is determined depending on the X direction. Furthermore, in the imaging element of the sixth configuration, the direction away from the first electrode is the X direction, which is defined as follows. That is, the pixel region including the plurality of array imaging elements or the laminated imaging element includes a plurality of pixels arranged in a two-dimensional array, that is, systematically arranged along the X direction and the Y direction. In the case where the planar shape of the pixel is rectangular, the direction of extension of the side closest to the first electrode is the Y direction, and the direction orthogonal to the Y direction is the X direction. Alternatively, in the case where the planar shape of the pixel is an arbitrary shape, the overall direction including the straight line segment or the curve closest to the first electrode is the Y direction, and the direction orthogonal to the Y direction is the X direction.

[0248] Hereinafter, the case where the electric potential of the first electrode is higher than that of the second electrode will be described for the imaging elements of the first to sixth configurations. In the case where the electric potential of the first electrode is lower than that of the second electrode, it is only necessary to reverse the high and low of the electric potential.

[0249] In the imaging element of the first configuration, the thickness of the insulating layer section gradually changes from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. The thickness of the insulating layer section can gradually increase or gradually decrease. Thereby, a kind of charge transport gradient is formed.

[0250] In the case where the charge to be stored is an electron, the thickness of the insulating layer section can gradually increase. In the case where the charge to be stored is an electron hole, the thickness of the insulating layer section can gradually decrease. Furthermore, in these cases, when the state becomes |V 12 |≥|V 11 | during the charge storage period, the n-th photoelectric conversion unit section can store more charge than the (n+1)-th photoelectric conversion unit section. A strong electric field is applied, which of course prevents the flow of charge from the first photoelectric conversion unit section to the first electrode. Furthermore, when the state becomes |V 22 |<|V 21 | during the charge transport period, it is always guaranteed that the charge flow from the first photoelectric conversion unit section to the first electrode and the charge flow from the (n+1)-th photoelectric conversion unit section to the n-th photoelectric conversion unit section.

[0251] In the imaging element of the second configuration, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. The thickness of the photoelectric conversion layer section can gradually increase or gradually decrease. Thereby, a kind of charge transport gradient is formed.

[0252] In the case where the charge to be stored is an electron, the thickness of the photoelectric conversion layer section can be gradually increased. In the case where the charge to be stored is a hole, the thickness of the photoelectric conversion layer section can be gradually decreased. Further, in the case where the thickness of the photoelectric conversion layer section is gradually increased, when the state becomes V 12 ≥ V 11 during the charge storage, or in the case where the thickness of the photoelectric conversion layer section is gradually decreased, when the state becomes V 12 ≤ V 11 , the electric field applied to the nth photoelectric conversion unit section is stronger than the electric field applied to the (n+1)th photoelectric conversion unit section. This definitely prevents the flow of charge from the first photoelectric conversion unit section to the first electrode. Further, in the case where the thickness of the photoelectric conversion layer section is gradually increased, when the state becomes V 22 < V 21 , or in the case where the thickness of the photoelectric conversion layer section is gradually decreased, when the state becomes V 22 > V 21 , the flow of charge from the first photoelectric conversion unit section to the first electrode and the flow of charge from the (n+1)th photoelectric conversion unit section to the nth photoelectric conversion unit section are definitely ensured.

[0253] In the imaging device of the third configuration, the material included in the insulating layer section is different in the adjacent photoelectric conversion unit sections, thereby forming a charge transport gradient. It is preferable that the value of the dielectric constant of the material included in the insulating layer section gradually decreases from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. Further, by employing this configuration, when the state becomes V 12 ≥ V 11 during the charge storage, the nth photoelectric conversion unit section can store more charge than the (n+1)th photoelectric conversion unit section. Further, when the state becomes V 22 < V 21 during the charge transport period, the flow of charge from the first photoelectric conversion unit section to the first electrode and the flow of charge from the (n+1)th photoelectric conversion unit section to the nth photoelectric conversion unit section are definitely ensured.

[0254] In the imaging device of the fourth configuration, the material included in the charge storage electrode section is different in the adjacent photoelectric conversion unit sections. Thereby, a charge transport gradient is formed. It is preferable that the value of the work function of the material included in the insulating layer section gradually increases from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. Further, by employing this configuration, a potential gradient that is favorable for the transport of signal charge can be formed regardless of whether the voltage is positive or negative.

[0255] In the imaging device of the fifth configuration, the area of the charge storage electrode section gradually decreases from the first photoelectric conversion cell section to the Nth photoelectric conversion cell section. Thus, a charge transport gradient is formed. Therefore, when the state becomes V 12 ≥ V 11 in the charge storage period, the nth photoelectric conversion cell section can store more charges than the (n+1)th photoelectric conversion cell section. Also, when the state becomes V 22 < V 21 in the charge transport period, the charge flow from the first photoelectric conversion cell section to the first electrode and the charge flow from the (n+1)th photoelectric conversion cell section to the nth photoelectric conversion cell section are certainly ensured.

[0256] In the imaging device of the sixth configuration, the cross-sectional area of the stacked section varies depending on the distance from the first electrode. Thus, a charge transport gradient is formed. Specifically, the thickness of the cross-section of the stacked section can be constant, and the width of the cross-section of the stacked section can decrease as the distance from the first electrode increases. By employing this configuration, as described in the imaging device of the fifth configuration, when the state becomes V 12 ≥ V 11 in the charge storage period, the region close to the first electrode can store more charges than the region far from the first electrode. Therefore, when the state becomes V 22 < V 21 in the charge transport period, the charge flow from the region close to the first electrode to the first electrode and the charge flow from the region far from the first electrode to the region close to the first electrode are certainly ensured. On the other hand, the width of the cross-section of the stacked section can be constant, and the thickness of the cross-section of the stacked section, particularly the thickness of the insulating layer section, can gradually increase. By employing this configuration, as described in the imaging device of the first configuration, when the state becomes V 12 ≥ V 11 in the charge storage period, the region close to the first electrode stores more charges than the region far from the first electrode. By applying a strong electric field, the charge flow from the region close to the first electrode to the first electrode is certainly prevented. Furthermore, when the state becomes V 22 < V 21 in the charge transport period, the charge flow from the region close to the first electrode to the first electrode and the charge flow from the region far from the first electrode to the region close to the first electrode are certainly ensured. Furthermore, the thickness of the photoelectric conversion layer section can gradually increase. By employing this configuration, as described in the imaging device of the second configuration, when the state becomes V 12 ≥ V 11When the state becomes V at the time t, the electric field applied to the region close to the first electrode is stronger than the electric field applied to the region away from the first electrode. This certainly prevents the flow of electric charges from the region close to the first electrode to the first electrode. Further, when the state becomes V at the time t, the flow of electric charges from the region away from the first electrode to the region close to the first electrode is certainly ensured. 22 <V 21 When the state becomes V at the time t, the flow of electric charges from the region close to the first electrode to the first electrode and the flow of electric charges from the region away from the first electrode to the region close to the first electrode are certainly ensured.

[0257] Another modification example of the solid-state imaging device according to the first aspect of the present disclosure includes:

[0258] A solid-state imaging device including a plurality of imaging elements according to the first to ninth aspects of the present disclosure or the imaging elements according to the first to sixth configurations, wherein

[0259] The plurality of imaging elements are included in an imaging element block, and

[0260] The first electrode is shared by the plurality of imaging elements included in the imaging element block. Note that, for convenience, the solid-state imaging device configured in this way will be referred to as a "solid-state imaging device of a first configuration". Alternatively, another modification example of the solid-state imaging device according to the second aspect of the present disclosure includes:

[0261] A solid-state imaging device including a plurality of stacked imaging elements each including at least one of the imaging elements according to the first to ninth aspects of the present disclosure or the imaging elements according to the first to sixth configurations, wherein

[0262] The plurality of stacked imaging elements are included in an imaging element block, and

[0263] The first electrode is shared by the plurality of stacked imaging elements included in the imaging element block. Note that, for convenience, the solid-state imaging device configured in this way will be referred to as a "solid-state imaging device of a second configuration". Further, in this way, the first electrode can be shared by the plurality of imaging elements included in the imaging element block, to simplify and miniaturize the configuration and structure of a pixel region including a plurality of array imaging elements.

[0264] In each of the solid-state imaging devices of the first and second configurations, one floating diffusion layer is provided for a plurality of imaging elements (one imaging element block). The plurality of imaging elements provided for one floating diffusion layer can include the plurality of imaging elements of the first type described later, or can include at least one imaging element of the first type and one or two or more imaging elements of the second type described later. Further, the timing of the charge transfer period can be controlled as appropriate to allow the plurality of imaging elements to share one floating diffusion layer. The plurality of imaging elements operate together and are connected to the drive circuit described later as an imaging element block. That is, the plurality of imaging elements included in the imaging element block are connected to one drive circuit. However, the charge storage electrodes are controlled for each imaging element. In addition, the plurality of imaging elements can share one contact hole portion. With regard to the arrangement relationship between the first electrode shared by the plurality of imaging elements and the charge storage electrode of each imaging element, the first electrode can be arranged in the vicinity of the charge storage electrode of each imaging element. Alternatively, the first electrode can be arranged adjacent to the charge storage electrodes of a part of the plurality of imaging elements, and not adjacent to the charge storage electrodes of the remaining part of the plurality of imaging elements. In this case, the movement of the charge from the remaining part of the plurality of imaging elements to the first electrode is by the part of the plurality of imaging elements. It is preferable that the distance between the charge storage electrode included in the imaging element and the charge storage electrode included in the imaging element (referred to as "distance A" for convenience) be longer than the distance between the first electrode and the charge storage electrode in the imaging element adjacent to the first electrode (referred to as "distance B" for convenience) to ensure the movement of the charge from each imaging element to the first electrode. Further, it is preferable that the farther the imaging element is from the position of the first electrode, the greater the value of distance A.

[0265] Further, in each of the imaging elements and the like of the present disclosure including the above-described various preferred modes, light can be incident from the second electrode side, and a light-blocking layer can be formed on the light incident side closer to the second electrode. Alternatively, light can be incident from the second electrode side, and light can not be incident on the first electrode (the first electrode and the transfer control electrode as the case can be). Further, in this case, a light-blocking layer can be formed on the light incident side closer to the second electrode and the upper side of the first electrode (the first electrode and the transfer control electrode as the case can be). Alternatively, an on-chip microlens can be provided on the upper side of the charge storage electrode and the second electrode, and light incident on the on-chip microlens can be collected by the charge storage electrode. Here, the light-blocking layer can be provided on the upper side of the surface of the light incident side of the second electrode, or can be provided on the surface of the light incident side of the second electrode. The light-blocking layer can be formed on the second electrode as the case can be. Examples of the material included in the light-blocking layer include chromium (Cr), copper (Cu), aluminum (Al), tungsten (W), and a light-resistant resin (for example, a polyimide resin).

[0266] Specific examples of the imaging element of the present disclosure include: an imaging element sensitive to blue light (referred to as a "first type of blue light imaging element" for convenience) including a photoelectric conversion layer that absorbs blue light (light of 425 to 495 nm) (referred to as a "first type of blue light photoelectric conversion layer" for convenience); an imaging element sensitive to green light (referred to as a "first type of green light imaging element" for convenience) including a photoelectric conversion layer that absorbs green light (light of 495 to 570 nm) (referred to as a "first type of green light photoelectric conversion layer" for convenience); and an imaging element sensitive to red light (referred to as a "first type of red light imaging element" for convenience) including a photoelectric conversion layer that absorbs red light (light of 620 to 750 nm) (referred to as a "first type of red light photoelectric conversion layer" for convenience). Furthermore, for convenience, an imaging element sensitive to blue light that is a conventional imaging element not including a charge storage electrode will be referred to as a "second type of blue light imaging element". For convenience, a conventional imaging element sensitive to green light will be referred to as a "second type of green light imaging element". For convenience, a conventional imaging element sensitive to red light will be referred to as a "second type of red light imaging element". For convenience, a photoelectric conversion layer included in the second type of blue light imaging element will be referred to as a "second type of blue light photoelectric conversion layer". For convenience, a photoelectric conversion layer included in the second type of green light imaging element will be referred to as a "second type of green light photoelectric conversion layer". For convenience, a photoelectric conversion layer included in the second type of red light imaging element will be referred to as a "second type of red light photoelectric conversion layer".

[0267] The layered imaging element of the present disclosure includes at least one imaging element (photoelectric conversion element) of the present disclosure, and specific examples of the configuration and structure include:

[0268] [A] a configuration and structure in which a first type of blue light photoelectric conversion unit, a first type of green light photoelectric conversion unit, and a first type of red light photoelectric conversion unit are stacked in a vertical direction, and

[0269] a control unit provided with a first type of blue light imaging element, a first type of green light imaging element, and a first type of red light imaging element on a semiconductor substrate;

[0270] [B] a configuration and structure in which a first type of blue light photoelectric conversion unit and a first type of green light photoelectric conversion unit are stacked in a vertical direction,

[0271] a second type of red light photoelectric conversion unit is arranged on the lower side of the two layers of first type of photoelectric conversion units, and

[0272] a control unit provided with a first type of blue light imaging element, a first type of green light imaging element, and a second type of red light imaging element on a semiconductor substrate;

[0273] [C] the second type of blue light photoelectric conversion unit and the second type of red light photoelectric conversion unit are arranged on the lower side of the first type of green light photoelectric conversion unit in the configuration and the configuration, and

[0274] The control unit is provided with the first type of green light imaging element, the second type of blue light imaging element, and the second type of red light imaging element on the semiconductor substrate.

[0275] [D] the second type of green light photoelectric conversion unit and the second type of red light photoelectric conversion unit are arranged on the lower side of the first type of blue light photoelectric conversion unit in the configuration and the configuration, and

[0276] The control unit is provided with the first type of blue light imaging element, the second type of green light imaging element, and the second type of red light imaging element on the semiconductor substrate. Note that it is preferable that the arrangement order of the photoelectric conversion units of the imaging elements in the vertical direction is: from the light incident direction, the blue light photoelectric conversion unit, the green light photoelectric conversion unit, and the red light photoelectric conversion unit; or from the light incident direction, the green light photoelectric conversion unit, the blue light photoelectric conversion unit, and the red light photoelectric conversion unit. This is because the light of a shorter wavelength is effectively absorbed on the incident surface side. Among the three colors, red has the longest wavelength, and it is preferable that the red light photoelectric conversion unit is located in the lowermost layer from the light incident surface. The stacked structure of the imaging elements provides one pixel. Furthermore, a first type of infrared light photoelectric conversion unit can also be included. Here, it is preferable that the photoelectric conversion layer of the first type of infrared light photoelectric conversion unit includes, for example, an organic material and is arranged in the lowermost layer of the stacked configuration of the first type of imaging element and above the second type of imaging element. Alternatively, a second type of infrared light photoelectric conversion unit can also be included on the lower side of the first type of photoelectric conversion unit.

[0277] In the first type of imaging element, a first electrode is formed on, for example, an interlayer insulating layer provided on the semiconductor substrate. The imaging element formed on the semiconductor substrate can be a rear-illuminated type or a front-illuminated type.

[0278] In the case where the photoelectric conversion layer includes an organic material, the photoelectric conversion layer can be one of the following four modes.

[0279] (1) The photoelectric conversion layer includes a P-type organic semiconductor.

[0280] (2) The photoelectric conversion layer includes an n-type organic semiconductor.

[0281] (3) The photoelectric conversion layer includes a stacked structure of a p-type organic semiconductor layer / n-type organic semiconductor layer. The photoelectric conversion layer includes a stacked structure of a p-type organic semiconductor layer / a mixed layer (bulk hetero structure) of a p-type organic semiconductor and an n-type organic semiconductor / n-type organic semiconductor layer. The photoelectric conversion layer includes a stacked structure of a p-type organic semiconductor layer / a mixed layer (bulk hetero structure) of a p-type organic semiconductor and an n-type organic semiconductor. The photoelectric conversion layer includes a stacked structure of an n-type organic semiconductor layer / a mixed layer (bulk hetero structure) of a p-type organic semiconductor and an n-type organic semiconductor.

[0282] (4) The photoelectric conversion layer includes a mixed layer (bulk hetero structure) of a p-type organic semiconductor and an n-type organic semiconductor.

[0283] Here, the order of the stacking can be changed arbitrarily.

[0284] Examples of the p-type organic semiconductor include naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, pyrene derivatives, perylene derivatives, tetracene derivatives, pentacene derivatives, quinacridone derivatives, thiophene derivatives, thienothiophene derivatives, benzothiophene derivatives, benzothienobenzothiophene derivatives, triallylamine derivatives, carbazole derivatives, perylene derivatives, coronene derivatives, Derivatives, fluoranthene derivatives, phthalocyanine derivatives, subphthalocyanine derivatives, subporphyrin derivatives, metal complexes including heterocyclic compounds as ligands, polythiophene derivatives, polybenzothiadiazole derivatives, and polyfluorene derivatives. Examples of n-type organic semiconductors include fullerenes and fullerene derivatives (for example, fullerenes (higher fullerenes) such as C60, C70, and C74, or intercalated fullerenes, etc.) or fullerene derivatives (for example, fullerene fluoride, PCBM fullerene compounds, or fullerene polymers, etc.), organic semiconductors having a larger (deeper) HOMO and LUMO than p-type organic semiconductors, and transparent inorganic metal oxides. Specific examples of n-type organic semiconductors include organic molecules containing a heterocyclic compound as part of the molecular framework, the heterocyclic compound including nitrogen atoms, oxygen atoms, and sulfur atoms, such as pyridine derivatives, pyrazine derivatives, pyrimidine derivatives, triazine derivatives, quinoline derivatives, quinoxaline derivatives, isoquinoline derivatives, acridine derivatives, phenoxazine derivatives, phenanthroline derivatives, tetrazole derivatives, pyrazole derivatives, imidazole derivatives, thiazole derivatives, oxazole derivatives, imidazole derivatives, benzimidazole derivatives, benzotriazole derivatives, benzoxazole derivatives, benzoxazole derivatives, carbazole derivatives, benzofuran derivatives, dibenzofuran derivatives, subporphyrin derivatives, polystyryl derivatives, polybenzothiazole derivatives, and polyfluorene derivatives, organometallic complexes, and subphthalocyanine derivatives. Examples of groups included in fullerene derivatives and the like include halogen atoms; straight-chain, branched, or cyclic alkyl groups or phenyl groups; groups including straight-chain or condensed aromatic compounds; groups including halides; partially fluorinated alkyl groups; perfluorinated alkyl groups; silylalkyl groups; silylalkoxy groups; arylsilyl groups; arylsulfanyl groups; alkylsulfanyl groups; arylsulfonyl groups; alkylsulfonyl groups; arylsulfide groups; alkylsulfide groups; amino groups; alkylamino groups; arylamino groups; hydroxyl groups; alkoxy groups; acylamino groups; acyloxy groups; carbonyl groups; carboxyl groups; carboxamide groups; alkoxycarboxyl groups; acyl groups; sulfonyl groups; cyano groups; nitro groups; groups including sulfur compounds; phosphine groups; phosphon groups; and derivatives thereof. Although the thickness of the photoelectric conversion layer including an organic material (in some cases referred to as "organic photoelectric conversion layer") is not limited, the thickness may, for example, be 1 x 10 -8 m to 5 x 10 -7 m, preferably 2.5 x 10 -8 m to 3 x 10 -7 m, more preferably 2.5 x 10 -8 m to 2 x 10 -7 m, further preferably 1 x 10 -7 m to 1.8 x 10 -7m. Note that an organic semiconductor is generally classified into a p-type and an n-type. The p-type indicates that holes are easily transported, and the n-type indicates that electrons are easily transported. The organic semiconductor is not limited to the following explanation: holes or electrons are included as majority carriers of a thermally excited inorganic semiconductor.

[0285] Alternatively, examples of a material contained in an organic photoelectric conversion layer for photoelectric conversion of green light include rhodamine dye, merocyanine dye, quinacridone derivative, and subphthalocyanine dye (subphthalocyanine derivative). Examples of a material contained in an organic photoelectric conversion layer for photoelectric conversion of blue light include coumarin dye, tris(8-hydroxyquinoline)aluminum (Alq3), and merocyanine dye. Examples of a material contained in an organic photoelectric conversion layer for photoelectric conversion of red light include phthalocyanine dye and subphthalocyanine dye (subphthalocyanine derivative).

[0286] Alternatively, examples of an inorganic material contained in a photoelectric conversion layer include crystalline silicon, amorphous silicon, microcrystalline silicon, crystalline selenium, amorphous selenium, a chalcopyrite compound such as CIGS (CuInGaSe), cis (CuInSe2), CuInS2, CuAlS2, CuAlSe2, CuGaS2, CuGaSe2, AgAlS2, AgAlSe2, AgInS2, and AgInSe2, a III-V compound such as GaAs, InP, AlGaAs, InGaP, AlGaInP, and InGaAsP, and a compound semiconductor such as CdSe, Cds, In2S e3 , In2S3, Bi2Se3, Bi2S3, ZnSe, ZnS, PbSe, and PbS. Furthermore, a quantum dot containing such a material can also be used for a photoelectric conversion layer.

[0287] Alternatively, the photoelectric conversion layer can have a stacked structure of a lower semiconductor layer and an upper photoelectric conversion layer as described above. The lower semiconductor layer can be provided in this way to prevent, for example, recombination during charge storage. Furthermore, the charge transport efficiency of the charge stored in the photoelectric conversion layer to the first electrode can be improved. Furthermore, the charge generated in the photoelectric conversion layer can be temporarily held to control the timing of transport and the like. Furthermore, generation of dark current can also be suppressed. The material included in the upper photoelectric conversion layer can be appropriately selected from among various materials included in the photoelectric conversion layer. On the other hand, it is preferable that the material for the lower semiconductor layer be a material having a large value of band gap energy (e.g., a value of band gap energy equal to or greater than 3.0 eV) and having a mobility higher than the mobility of the material included in the photoelectric conversion layer. Specific examples of the material include: an oxide semiconductor material such as IGZO; a transition metal dihalide; silicon carbide; diamond; graphene; a carbon nanotube; and an organic semiconductor material, for example, a fused polycyclic hydrocarbon compound and a fused heterocyclic compound. Alternatively, other examples of the material included in the lower semiconductor layer include: in the case where the charge to be stored is an electron, a material having an ionization potential greater than the ionization potential of the material included in the photoelectric conversion layer; and in the case where the charge to be stored is a hole, a material having an electron affinity smaller than the electron affinity of the material included in the photoelectric conversion layer. Alternatively, it is preferable that the impurity concentration of the material included in the lower semiconductor layer be equal to or smaller than 1 x 1018cm-3. The lower semiconductor layer can have a single-layer structure or can have a multi-layer structure. Furthermore, the material included in the lower semiconductor layer located on the upper side of the charge storage electrode and the material included in the lower semiconductor layer located on the upper side of the first electrode can be different. 18 cm -3

[0288] The solid-state imaging device according to the first and second aspects of the present disclosure and the solid-state imaging device according to the first and second configurations can provide a single-board color solid-state imaging device.

[0289] ​In the solid-state imaging device according to the second aspect of the present disclosure or the solid-state imaging device including the second configuration of the stacked imaging element, unlike in the solid-state imaging device including the imaging element of the Bayer array (i.e., without using color filters to separate blue, green, and red), imaging elements sensitive to multiple wavelength types of light are stacked in the light incident direction within the same pixel to provide one pixel. Thus, it is possible to improve sensitivity and to increase the pixel density per unit volume. Furthermore, the absorption coefficient of an organic material is high, and the film thickness of the organic photoelectric conversion layer can be thinner than that of a conventional Si-based photoelectric conversion layer. This reduces light leakage from adjacent pixels and mitigates the restriction on the light incident angle. Furthermore, in a conventional Si-based imaging element, an interpolation process is performed on pixels of three colors to generate a color signal, and thus pseudo colors can be generated. In the solid-state imaging device according to the second aspect of the present disclosure or the solid-state imaging device including the second configuration of the stacked imaging element, generation of pseudo colors is suppressed. The organic photoelectric conversion layer also functions as a color filter, and it is possible to separate colors without arranging a color filter.

[0290] On the other hand, in the solid-state imaging device according to the first aspect of the present disclosure or the solid-state imaging device of the first configuration, a color filter can be used to mitigate the requirement for spectral characteristics of blue, green, and red, and mass productivity is high. Examples of the array of imaging elements in the solid-state imaging device according to the first aspect of the present disclosure or the solid-state imaging device of the first configuration include a Bayer array, and an interline array, a G-strip RB lattice array, a G-strip RB full lattice array, a lattice complementary color array, a stripe array, a diagonal stripe array, a primary color difference array, a field color difference sequence array, a frame color difference sequence array, a MOS array, a modified MOS array, a frame interlaced array, and a field interlaced array. Here, one imaging element provides one pixel (or sub-pixel).

[0291] A pixel region provided with a plurality of array imaging elements of the present disclosure or a plurality of array stacked imaging elements of the present disclosure includes a plurality of pixels arranged in a two-dimensional array. The pixel region generally includes an effective pixel region in which light is actually received to generate signal charges through photoelectric conversion, the signal charges are amplified and read out to a drive circuit, and a black reference pixel region for outputting optical black as a standard of a black level. The black reference pixel region is generally arranged at the periphery of the effective pixel region.

[0292] In the imaging element and the like of the present disclosure including the above-described various preferred modes and configurations, light is applied, and photoelectric conversion occurs in the photoelectric conversion layer. Carrier separation of electron holes (holes) and electrons is performed. Further, the electrode from which the holes are extracted is an anode, and the electrode from which the electrons are extracted is a cathode. There is a mode in which the first electrode provides the anode and the second electrode provides the cathode. Conversely, there is also a mode in which the first electrode provides the cathode and the second electrode provides the anode.

[0293] In the case where the layered imaging element is provided, the first electrode, the charge storage electrode, the charge movement control electrode, the transfer control electrode, and the second electrode can contain a transparent conductive material. Note that, in some cases, the first electrode, the charge storage electrode, the charge movement control electrode, the transfer control electrode are collectively referred to as "the first electrode and the like". Alternatively, in the case where the imaging element and the like of the present disclosure are arranged in a plane in a Bayer array, for example, the second electrode can contain a transparent conductive material, and the first electrode and the like can contain a metal material. In this case, specifically, the second electrode on the light incident side can contain a transparent conductive material, and the first electrode and the like can contain, for example, Al-Nd (an alloy of aluminum and neodymium) or ASC (an alloy of aluminum, samarium, and copper). Note that, in some cases, the electrode containing a transparent conductive material is referred to as a "transparent electrode". Here, it is desirable that the band gap of the transparent conductive material be equal to or greater than 2.5 eV, and preferably equal to or greater than 3.1 eV. Examples of the transparent conductive material contained in the transparent electrode include conductive metal oxides. Specifically, examples of the transparent conductive material include indium oxide, indium tin oxide (including ITO, indium tin oxide, Sn-doped In2O3, crystalline ITO, and amorphous ITO), indium zinc oxide (IZO, indium zinc oxide) obtained by adding indium as a dopant to zinc oxide, indium gallium oxide (IGO) obtained by adding indium as a dopant to gallium oxide, indium-gallium-zinc oxide (IGZO, In-GaZnO4) obtained by adding indium and gallium as dopants to zinc oxide, indium-tin-zinc oxide (ITZO) obtained by adding indium and tin as dopants to zinc oxide, IFO (fluorine-doped In2O3), tin dioxide (SnO2), ATO (antimony-doped SnO2), FTO (fluorine-doped SnO2), zinc oxide (including zinc oxide doped with other elements), aluminum zinc oxide (AZO) obtained by adding aluminum as a dopant to zinc oxide, gallium zinc oxide (GZO) obtained by adding gallium as a dopant to zinc oxide, titanium oxide (TiO2), niobium titanium oxide (TNO) obtained by adding niobium as a dopant to titanium oxide, antimony oxide, spinel oxide, and oxide having a YbFe2O4structure. Alternatively, the transparent electrode can contain gallium oxide, titanium oxide, niobium oxide, nickel oxide, or the like as a mother layer. Examples of the thickness of the transparent electrode include 2 x 10-6to 2 x 10-4cm.-8 m to 2 x 10 -7 m, preferably 3 x 10 -8 m to 1 x 10 -7 m. In the case where transparency is required for the first electrode, it is preferable that the other electrodes also contain a transparent conductive material from the viewpoint of simplifying the manufacturing process.

[0294] Alternatively, in the case where transparency is not required, it is preferable that a conductive material having a high work function (for example, 5.5 eV or more) be used as the conductive material contained in the anode having a function for extracting holes. Specifically, examples of the conductive material include gold (Au), silver (Ag), chromium (Cr), nickel (Ni), palladium (Pd), platinum (Pt), iron (Fe), iridium (Ir), germanium (Ge), osmium (Os), rhenium (Re), and tellurium (Te). Alternatively, in the case where transparency is not required, it is preferable that a conductive material having a low work function (for example, 4.5 eV or less) be used as the conductive material contained in the cathode having a function for extracting electrons. Specifically, examples of the conductive material include alkali metals (for example, Li, Na, K, and the like) and fluorides or oxides of alkali metals, alkaline earth metals (for example, Mg, Ca, and the like) and fluorides or oxides of alkaline earth metals, aluminum (Al), zinc (Zn), tin (Sn), thallium (Tl), sodium-potassium alloys, aluminum-lithium alloys, magnesium-silver alloys, indium, rare earth metals such as ytterbium, and alloys thereof. Alternatively, examples of the material contained in the anode or the cathode include metals such as platinum (Pt), gold (Au), palladium (PD), chromium (Cr), nickel (Ni), aluminum (Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe) cobalt (Co), and molybdenum (Mo), alloys containing these metal elements, conductive particles including these metals, conductive particles of alloys containing these metals, polycrystalline silicon containing impurities, carbon materials, oxide semiconductor materials, carbon nanotubes, and conductive materials such as graphene. The anode or the cathode can also have a multilayer laminated structure containing these elements. Furthermore, examples of the material contained in the anode or the cathode also include organic materials (conductive polymers) such as poly(3,4-ethylenedioxythiophene-poly(styrenesulfonate)) [PEDOT / PSS]. Furthermore, these conductive materials can be mixed with a binder (polymer) to obtain a paste or an ink, and the paste or the ink can be cured and used as an electrode.

[0295] A dry method or a wet method can be used as a deposition method of the first electrode or the like or the second electrode (cathode or anode). Examples of the dry method include a physical vapor deposition method (PVD method) and a chemical vapor deposition method (CVD method). Examples of the deposition method using the principle of the PVD method include a vacuum evaporation method using resistance heating or radio frequency heating, an EB (electron beam) evaporation method, various sputtering methods (magnetron sputtering method, RF-DC coupled bias sputtering method, ECR sputtering method, diode sputtering method, and RF sputtering method), ion plating method, laser ablation method, molecular beam epitaxy method, and laser transfer method. In addition, examples of the CVD method include a plasma CVD method, thermal CVD method, metal-organic (MO) CVD method, and optical CVD method. On the other hand, examples of the wet method include various methods such as an electroplating method, an electroless plating method, a spin coating method, an inkjet method, a spray coating method, an imprint method, a microcontact printing method, a flexographic printing method, a gravure printing method, a photogravure printing method, and a dip coating method. Examples of the patterning method include chemical etching such as a shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet rays or a laser or the like. Examples of the planarization method of the first electrode or the like and the second electrode include a laser planarization method, a reflow method, and a CMP (chemical mechanical polishing) method.

[0296] Examples of the material contained in the insulating layer, in addition to the insulating layer or the like in the imaging element according to the fifth aspect of the present disclosure, include not only inorganic insulating materials such as silicon oxide materials, silicon nitride (SiN y ) and aluminum oxide (Al203) similar to metal oxide high dielectric insulating materials, but also organic insulating materials (organic polymers) such as: polymethyl methacrylate (PMMA); polyvinyl phenol (PVP); polyvinyl alcohol (PVA); polyimide; polycarbonate (PC); polyethylene terephthalate (PET); polystyrene; silanol derivatives (silane coupling agents) such as N-(2-aminoethyl)-3-aminopropyltrimethoxysilane (AEAPTMS), 3-mercaptopropyltrimethoxysilane (MPTMS), and octadecyltrichlorosilane (OTS), novolac phenolic resin; fluororesin; and straight-chain hydrocarbons such as octadecyl mercaptan and dodecyl isocyanate, including a functional group that can bind to a control electrode at one end. Note that examples of the silicon oxide material include silicon oxide (SiOx), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin on glass), and low dielectric insulating materials (e.g., polyarylether, perfluorocarbon polymer, benzocyclobutene, fluororesin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon, and organic SOG). These materials can also be appropriately selected for the material contained in various interlayer insulating layers and insulating films.

[0297] The configuration and structure of the floating diffusion, the amplification transistor, the reset transistor, and the selection transistor included in the control unit can be similar to those of conventional floating diffusion, amplification transistor, reset transistor, and selection transistor. The drive circuit can also have a well-known configuration and structure.

[0298] The first electrode is connected to the gate portion of the floating diffusion and the amplification transistor, and a contact hole portion can be formed for connecting the first electrode to the gate portion of the floating diffusion and the amplification transistor. Examples of the material included in the contact hole portion include polysilicon doped with impurities, high-melting-point metals, and metal silicides such as tungsten, Ti, Pt, Pd, Cu, TiW, TiN, TiNW, WSi2, and MoSi2, and a laminated structure including these materials (e.g., Ti / TiN / W).

[0299] A first carrier blocking layer can be provided between the organic photoelectric conversion layer and the first electrode, and a second carrier blocking layer can be provided between the organic photoelectric conversion layer and the second electrode. Furthermore, a first charge injection layer can be provided between the first carrier blocking layer and the first electrode, and a second charge injection layer can be provided between the second carrier blocking layer and the second electrode. Examples of the material included in the electron injection layer include alkali metals such as lithium (Li), sodium (Na), and potassium (K), fluorides or oxides of alkali metals, alkaline earth metals such as magnesium (Mg) and calcium (Ca), and fluorides or oxides of alkaline earth metals.

[0300] Examples of the deposition method of the various organic layers include dry deposition methods and wet deposition methods. Examples of the dry deposition methods include vacuum evaporation methods using resistance heating, radio frequency heating, or electron beam heating, flash evaporation methods, plasma deposition methods, EB evaporation methods, various sputtering methods (bipolar sputtering methods, DC sputtering methods, DC magnetron sputtering methods, RF sputtering methods, magnetron sputtering methods, RF-DC coupled bias sputtering methods, ECR sputtering methods, diode sputtering methods, RF sputtering methods, and ion beam sputtering methods), DC (direct current) methods, RF methods, multi-cathode methods, activation reaction methods, electric field evaporation methods, various ion plating methods (for example, RF ion plating methods and reactive ion plating methods), laser ablation methods, molecular beam epitaxy methods, laser transfer methods, and molecular beam epitaxy methods (MBE methods). Furthermore, examples of the CVD methods include plasma CVD methods, thermal CVD methods, MOCVD methods, and optical CVD methods. On the other hand, specific examples of the wet methods include spin coating methods, dipping methods, casting methods, micro-contact printing methods, drop casting methods, various printing methods such as screen printing methods, inkjet printing methods, offset printing methods, gravure printing methods, flexographic printing methods, stamping methods, spray coating methods, and various coating methods such as air knife coating methods, doctor blade coating methods, bar coating methods, knife coating methods, extrusion coating methods, reverse roll coating methods, transfer roll coating methods, gravure coating methods, kiss coating methods, flow coating methods, spray coating methods, slit orifice coating methods, and calendar coater methods. Note that, in the coating methods, examples of the solvent include non-polar or low-polar organic solvents such as toluene, chloroform, hexane, and ethanol. Examples of the patterning methods include chemical etching, for example, shadow masking, laser transfer, and photolithography, and physical etching using ultraviolet light, a laser, and the like. Laser planarization methods, reflow methods, and the like can be used as planarization techniques for the various organic layers.

[0301] The two or more types of imaging elements and the like according to the first to ninth aspects of the present disclosure and the first to sixth configurations including the above-described preferred modes and configurations can be appropriately combined as needed.

[0302] As described above, an on-chip microlens and a light-blocking layer can be provided on the imaging element or the solid-state imaging device as needed, and a drive circuit and a wiring for driving the imaging element can be provided. A shutter for controlling light incident on the imaging element can be arranged as needed, and an optical cut filter can be provided depending on the purpose of the solid-state imaging device.

[0303] Furthermore, the solid-state imaging device of the first and second configurations can be in a mode in which one on-chip microlens is arranged on the upper side of one imaging element. Alternatively, two imaging elements can be included in an imaging element block, and one on-chip microlens can be arranged on the upper side of the imaging element block.

[0304] For example, in the case of a stacked solid-state imaging device and a readout integrated circuit (ROIC), a drive substrate having a readout integrated circuit and a connection portion containing copper (Cu) and an imaging element provided with a connection portion can be stacked on each other so that the connection portions contact each other. The connection portions can be bonded to stack the solid-state imaging device and the readout integrated circuit, or the connection portions can be joined using solder bumps or the like.

[0305] Further, a driving method for driving the solid-state imaging device according to the first and second aspects of the present disclosure can be a driving method of a solid-state imaging device in which the following steps are repeated:

[0306] In all of the imaging elements, the electric charges stored in the photoelectric conversion layers are all discharged to the system outside at once; and subsequently,

[0307] In all of the imaging elements, the electric charges stored in the photoelectric conversion layers are all transferred to the first electrodes at once, and after the transfer is completed, the electric charges transferred to the first electrodes in the respective imaging elements are sequentially read.

[0308] In the driving method of the solid-state imaging device, in the respective imaging elements, light incident from the second electrode side is not incident on the first electrodes. In all of the imaging elements, the electric charges are stored in the photoelectric conversion layers in all of the imaging elements, and the electric charges in the first electrodes are all released to the system outside at once. Therefore, in all of the imaging elements, the first electrodes can be certainly reset at the same time. Further, subsequently, in all of the imaging elements, the electric charges stored in the photoelectric conversion layers are all transferred to the first electrodes at once. After the transfer is completed, the imaging elements sequentially read the electric charges transferred to the first electrodes. Therefore, it is possible to easily achieve a so-called global shutter function.

[0309] Embodiment 1

[0310] Embodiment 1 relates to the imaging element and the like according to the first aspect of the present disclosure, the imaging element and the like according to the third aspect of the present disclosure, the stacked imaging element of the present disclosure, and the solid-state imaging device according to the second aspect of the present disclosure.

[0311] Figure 1A A schematic cross-sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Embodiment 1 is shown. Note that the schematic cross-sectional view of Figure 1A or Figure 1B is similar to, for example, a schematic cross-sectional view taken along a single-dot chain line A-A of Figure 15A . Further, Figure 2 A schematic partial cross-sectional view of the imaging element and the stacked imaging element of Embodiment 1 is shown. Figure 3 and Figure 4 An equivalent circuit diagram of the imaging element and the stacked imaging element of Embodiment 1 is shown. Figure 5A schematic layout diagram of the first electrode, the charge storage electrode, and the transistor of the control unit included in the imaging element of Embodiment 1 is shown. Furthermore, Figure 6 and Figure 7 A schematic layout diagram of the first electrode and the charge storage electrode included in the imaging element of Embodiment 1 is shown. Figure 8 The state of the electric potential in each part during the operation of the imaging element of Embodiment 1 is schematically illustrated. Figure 9A Equivalent circuit diagrams of the imaging element of Embodiment 1 and the stacked imaging element for describing Figure 8 each part are shown. Figure 10 A conceptual diagram of the solid-state imaging device of Embodiment 1 is shown. Note that, for convenience, various constituent elements of the imaging element located on the lower side of the interlayer insulating layer 81 can be collectively denoted by reference numeral 91 to simplify the drawing.

[0312] Each of the imaging element of Embodiment 1 (for example, the green light imaging element described later) and the imaging elements of Embodiments 2 to 8 described later includes a photoelectric conversion unit including a stacked first electrode 11, a photoelectric conversion layer 13, and a second electrode 12. The photoelectric conversion unit further includes a charge storage electrode 14 arranged away from the first electrode 11 and arranged to face the photoelectric conversion layer 13 through an insulating layer 82.

[0313] Note that, in the example shown in Figure 6 , one imaging element is provided with one charge storage electrode 14 corresponding to one first electrode 11. On the other hand, in the example shown in Figure 7 , two imaging elements are provided with one common first electrode 11 corresponding to two charge storage electrodes 14 (Variant 1 of Embodiment 1). Figure 1A A schematic cross-sectional view of a part of the imaging element of Embodiment 1 (two imaging elements arranged side by side) corresponds to Figure 7 .

[0314] In addition to the imaging element of Embodiment 3 described later and the like, the second electrode 12 located on the light incident side is shared by a plurality of imaging elements, that is, the second electrode 12 is a so-called solid electrode. The photoelectric conversion layer 13 is shared by a plurality of imaging elements. That is, one photoelectric conversion layer 13 is formed in a plurality of imaging elements.

[0315] The stacked imaging element of Embodiment 1 includes at least one of the imaging element of Embodiment 1 and the imaging elements of Embodiments 2 to 8 described later. In Embodiment 1, the stacked imaging element includes one of the imaging element of Embodiment 1 and the imaging elements of Embodiments 2 to 8 described later.

[0316] Furthermore, the solid-state imaging device of Embodiment 1 includes a plurality of stacked imaging elements of the imaging elements of Embodiment 1 and Embodiments 2 to 8 described later.

[0317] Furthermore, when light is incident on the photoelectric conversion layer 13, and photoelectric conversion occurs in the photoelectric conversion layer 13 of the imaging element in Embodiment 1, the portion 13 facing the charge storage electrode 14 of the photoelectric conversion layer 13 is applied. C The absolute value of the potential is greater than that applied to the photoelectric conversion layer 13 in the region 13 between the imaging element and the adjacent imaging element. B The absolute value of the potential of (region B of the photoelectric conversion layer).

[0318] Alternatively, in the imaging element of Embodiment 1, the charge motion control electrode 21 is formed in the region 13 located between the imaging element and adjacent imaging elements, facing the photoelectric conversion layer 13 via the insulating layer 82. B In the region of (region B of the photoelectric conversion layer). In other words, the charge movement control electrode 21 is located in part 82 of the insulating layer 82. B Region B of the insulating layer 82 is formed below the region (region b) between the charge storage electrode 14 and the charge storage electrode 14 of the adjacent imaging element. The charge motion control electrode 21 is configured to be separate from the charge storage electrode 14. Or, in other words, the charge motion control electrode 21 is disposed around and separate from the charge storage electrode 14, and the charge motion control electrode 21 is configured to face the photoelectric conversion layer region B (13) via the insulating layer 82. B Note that, although Figure 2 The charge motion control electrode 21 is not shown in the diagram; it is formed in the direction of arrow "A". The charge motion control electrode 21 is arranged in... Figure 5 Imaging elements in the left and right directions are shared and arranged in Figure 5 A pair of imaging elements in the vertical direction are shared.

[0319] For simplicity, the charge movement control electrode 21 (not shown), the connection hole 23, the pad portion 22, and the wiring V (described later) are shown. 0B The imaging element is referred to as "an imaging element having the basic structure of this disclosure". Figure 2 This is a schematic partial cross-sectional view of an imaging element having the basic structure of this disclosure. Figure 42 , 43 Numbers 44, 45, 46, 47, 54, 61, 62, 64, 65, 66, 71, 88, 89, 91, 92, 93, 94, 95, 96, 97, and 98 are... Figure 2 The diagram shows a schematic partial cross-sectional view of various variations of an imaging element having the basic structure of this disclosure, but does not show the charge motion control electrode 21, etc.

[0320] Further, a semiconductor substrate (more specifically, a silicon semiconductor layer) is also included, and the photoelectric conversion unit is provided on the upper side of the semiconductor substrate 70. Further, a control unit is also included, which is provided on the semiconductor substrate 70 and includes a drive circuit connected to the first electrode 11 and the second electrode 12. Here, the light incident surface in the semiconductor substrate 70 is the upper side, and the opposite side of the semiconductor substrate 70 is the lower side. A wiring layer 62 including a plurality of wirings is provided on the lower side of the semiconductor substrate 70.

[0321] The semiconductor substrate 70 is provided with at least one floating diffusion layer FD1 and an amplification transistor TR1 included in the control unit amp , and the first electrode 11 is connected to the gate portion of the floating diffusion layer FD1 and the amplification transistor TR1 amp . The semiconductor substrate 70 is also provided with a reset transistor TR1 rst and a selection transistor TR1 set included in the control unit. The floating diffusion layer FD1 is connected to one source / drain region of the reset transistor TR1 rst . The other source / drain region of the amplification transistor TR1 amp is connected to one source / drain region of the selection transistor TR1 set . The other source / drain region of the selection transistor TR1 set is connected to the signal line VSL1. The amplification transistor TR1 amp , the reset transistor TR1 rst , and the selection transistor TR1 set are included in the drive circuit.

[0322] Specifically, the imaging element and the stacked imaging element of Embodiment 1 are back-illuminated imaging elements and back-illuminated stacked imaging elements. The imaging element and the stacked imaging element have a stacked structure of three imaging elements, including a first type of green light imaging element (hereinafter, referred to as "first imaging element") in Embodiment 1 that is sensitive to green light and includes a first type of green light photoelectric conversion layer for absorbing green light, a second type of blue light imaging element (hereinafter, referred to as "second imaging element") that is sensitive to blue light and includes a second type of blue light photoelectric conversion layer for absorbing blue light, and a second type of red light imaging element (hereinafter, referred to as "third imaging element") that is sensitive to red light and includes a second type of red light photoelectric conversion layer for absorbing red light. Here, the red light imaging element (third imaging element) and the blue light imaging element (second imaging element) are provided in the semiconductor substrate 70, and the second imaging element is located on the light incident side with respect to the third imaging element. Further, the green light imaging element (first imaging element) is provided on the upper side of the blue light imaging element (second imaging element). The stacked configuration of the first imaging element, the second imaging element, and the third imaging element is included in one pixel. No color filter is provided.

[0323] In the first imaging element, the first electrode 11 and the charge storage electrode 14 are formed separately from each other on the interlayer insulating layer 81. Further, the charge movement control electrode 21 is formed on the interlayer insulating layer 81 separately from the charge storage electrode 14. The interlayer insulating layer 81, the charge storage electrode 14, and the charge movement control electrode 21 are covered with the insulating layer 82. The photoelectric conversion layer 13 is formed on the insulating layer 82, and the second electrode 12 is formed on the photoelectric conversion layer 13. The protective layer 83 is formed on the entire surface including the second electrode 12, and the on-chip microlens 90 is provided on the protective layer 83. For example, the first electrode 11, the charge storage electrode 14, the charge movement control electrode 21, and the second electrode 12 include a transparent electrode containing ITO (work function: about 4.4 eV). The photoelectric conversion layer 13 includes a layer containing at least a known organic photoelectric conversion material (for example, an organic substance such as a rhodamine dye, a merocyanine dye, and a quinacridone) that is sensitive to green light. Further, the photoelectric conversion layer 13 can also include a material layer suitable for charge storage. That is, a material layer suitable for charge storage can be further formed between the photoelectric conversion layer 13 and the first electrode 11 (for example, in the connection portion 67). The interlayer insulating layer 81, the insulating layer 82, and the protective layer 83 include a known insulating material (for example, SiO2or SiN). The photoelectric conversion layer 13 and the first electrode 11 are connected through the connection portion 67 provided on the insulating layer 82. The photoelectric conversion layer 13 extends in the connection portion 67. That is, the photoelectric conversion layer 13 extends in the opening portion 84 provided in the insulating layer 82 and is connected to the first electrode 11.

[0324] The charge storage electrode 14 is connected to the drive circuit, specifically, the charge storage electrode 14 is connected to the drive circuit through the connection hole 66, the pad portion 64, and the wiring V 0A to the vertical drive circuit 112 included in the drive circuit.

[0325] The charge movement control electrode 21 is also connected to the drive circuit. Specifically, the charge movement control electrode 21 is connected to the drive circuit through the connection hole 23, the pad portion 22, and the wiring V 0B to the vertical drive circuit 112 included in the drive circuit. More specifically, the charge movement control electrode 21 is formed in a region (a region B (82 B ) of the insulating layer 82) facing the photoelectric conversion layer 13 via the insulating layer 82 of the region B (13 B ). In other words, the charge movement control electrode 21 is formed in a region (a region b) between the charge storage electrode 14 and the charge storage electrode 14 included in the adjacent imaging element under a portion 82 B of the insulating layer 82. The charge movement control electrode 21 is provided separately from the charge storage electrode 14. Or, in other words, the charge movement control electrode 21 is provided around and separately from the charge storage electrode 14, and the charge movement control electrode 21 is arranged to face the region B (13 B ) of the photoelectric conversion layer 13 via the insulating layer 82.

[0326] The size of the charge storage electrode 14 is larger than the first electrode 11. Although not limited, it is preferable to satisfy

[0327] 4 ≤ S1' / S1

[0328] where S1' is the area of the charge storage electrode 14, and S1 is the area of the first electrode 11. Although not limited, for example, in the imaging element of Embodiment 1 and Embodiments 2 to 8 described later, it is set that

[0329] S1' / S1 = 8

[0330] Note that, in Embodiments 13 to 16 described later, the sizes of the three photoelectric conversion unit sections (101, 102, and 103) are the same, and the planar shapes are also the same.

[0331] The element separation region 71 is formed on the first surface (front surface) 70A side of the semiconductor substrate 70, and the oxide film 72 is formed on the first surface 70A of the semiconductor substrate 70. Further, the reset transistor TR1 rst , the amplification transistor TR1 amp , and the selection transistor TR1 selA first floating diffusion layer FD1 is further provided on the first surface side of the semiconductor substrate 70.

[0332] Reset transistor TR1 rst includes a gate portion 51, a channel formation region 51A, and source / drain regions 51B and 51C. The gate portion 51 of the reset transistor TR1 rst is connected to a reset line RST1, and the source / drain region 51C of the reset transistor TR1 rst also functions as the first floating diffusion layer FD1, and the other source / drain region 51B is connected to a power supply V DD .

[0333] The first electrode 11 is connected to the source / drain region 51C (first floating diffusion layer FD1) of the reset transistor TR1 rst through a contact hole portion 61 formed in the semiconductor substrate 70 and the interlayer insulating layer 76, and through a wiring layer 62 formed in the interlayer insulating layer 76.

[0334] Amplification transistor TR1 amp includes a gate portion 52, a channel formation region 52A, and source / drain regions 52B and 52C. The gate portion 52 is connected to the first electrode 11 and the source / drain region 51C (first floating diffusion layer FD1) of the reset transistor TR1 rst through the wiring layer 62. Further, one of the source / drain regions 52B is connected to a power supply V DD .

[0335] Selection transistor TR1 sel includes a gate portion 53, a channel formation region 53A, and source / drain regions 53B and 53C. The gate portion 53 is connected to a selection line SEL1. Further, one of the source / drain regions 53B shares this region with the other source / drain region 52C included in the amplification transistor TR1 amp , and the other source / drain region 53C is connected to a signal line (data output line) VSL1 (117).

[0336] The second imaging device includes an n-type semiconductor region 41 as a photoelectric conversion layer provided over the semiconductor substrate 70. A gate portion 45 of a transfer transistor TR2 trs extending to the n-type semiconductor region 41 and connected to a transfer gate line TG2. Further, a second floating diffusion layer FD2 is provided in a region 45C of the semiconductor substrate 70, which is close to the gate portion 45 of the transfer transistor TR2 trs . Charges stored in the n-type semiconductor region 41 are read out to the second floating diffusion layer FD2 through a transfer channel formed along the gate portion 45.

[0337] On the first surface side of the semiconductor substrate 70, the second imaging element is further provided with a reset transistor TR2 included in a control unit of the second imaging element rst , an amplification transistor TR2 amp , and a selection transistor TR2 sel .

[0338] The reset transistor TR2 rst includes a gate portion, a channel formation region, and source / drain regions. The gate portion of the reset transistor TR2 rst is connected to a reset line RST2, and one of the source / drain regions of the reset transistor TR2 rst is connected to a power supply V DD . The other source / drain region also serves as a second floating diffusion layer FD2.

[0339] The amplification transistor TR2 amp includes a gate portion, a channel formation region, and source / drain regions. The gate portion is connected to the other source / drain region (second floating diffusion layer FD2) of the reset transistor TR2 rst . Further, one of the source / drain regions is connected to a power supply V DD .

[0340] The selection transistor TR2 sel includes a gate portion, a channel formation region, and source / drain regions. The gate portion is connected to a selection line SEL2. Further, one of the source / drain regions shares the region with the other source / drain region included in the amplification transistor TR2 amp , and the other source / drain region is connected to a signal line (data output line) VSL2.

[0341] The third imaging element includes an n-type semiconductor region 43 provided on the semiconductor substrate 70 as a photoelectric conversion layer. A gate portion 46 of a transfer transistor TR3 trs is connected to a transfer gate line TG3. Further, a third floating diffusion layer FD3 is provided in a region 46C of the semiconductor substrate 70, which is close to the gate portion 46 of the transfer transistor TR3 trs . Charges stored in the n-type semiconductor region 43 are read out to the third floating diffusion layer FD3 through a transfer channel 46A formed along the gate portion 46.

[0342] In the third imaging element, on the first surface side of the semiconductor substrate 70, a reset transistor TR3 included in a control unit of the third imaging element rst , an amplification transistor TR3 amp , and a selection transistor TR3 sel are further provided.

[0343] Reset transistor TR3 rst includes a gate portion, a channel formation region, and a source / drain region. The gate portion of the reset transistor TR3 rst is connected to a reset line RST3. One of the source / drain regions of the reset transistor TR3 rst is connected to a power supply V DD . The other source / drain region also serves as a third floating diffusion layer FD3.

[0344] Amplification transistor TR3 amp includes a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to the other source / drain region (the third floating diffusion layer FD3) of the reset transistor TR3 rst . In addition, one of the source / drain regions is connected to a power supply V DD .

[0345] Selection transistor TR3 sel includes a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to a selection line SEL3. In addition, one of the source / drain regions shares the region with the other source / drain region included in the amplification transistor TR3 amp . The other source / drain region is connected to a signal line (a data output line) VSL3.

[0346] The reset lines RST1, RST2, and RST3, the selection lines SEL1, SEL2, and SEL3, and the transfer gate lines TG2 and TG3 are connected to a vertical drive circuit 112 included in the drive circuit. The signal lines (the data output lines) VSL1, VSL2, and VSL3 are connected to a column signal processing circuit 113 included in the drive circuit.

[0347] A p + layer 44 is provided between the n-type semiconductor region 43 and the front surface 70A of the semiconductor substrate 70 to suppress generation of dark current. A p + layer 42 is formed between the n-type semiconductor region 41 and the n-type semiconductor region 43, and in addition, part of the side surface of the n-type semiconductor region 43 is surrounded by the p + layer 42. A p + layer 73 is formed on the back surface 70B side of the semiconductor substrate 70, and an HfO2 film 74 and an insulating film 75 are formed at a portion where a contact hole portion 61 is to be formed from the p + layer 73 to the inside of the semiconductor substrate 70. In an interlayer insulating layer 76, a plurality of layers of a wiring are formed, but the wiring is not shown.

[0348] The Hf02film 74 is a film having a negative fixed charge, and can be provided to suppress generation of dark current. Note that, instead of the Hf02film, an aluminum oxide (Al203) film, a zirconium oxide (Zr02) film, a tantalum oxide (Ta205) film, a titanium oxide (Ti02) film, a lanthanum oxide (La203) film, a praseodymium oxide (Pr203) film, a cerium oxide (Ce02) film, a neodymium oxide (Nd203) film, a promethium oxide (Pm203) film, a samarium oxide (Sm203) film, an europium oxide (Eu203) film, a gadolinium oxide (Gd203) film, a terbium oxide (Tb203) film, a dysprosium oxide (Dy203) film, a holmium oxide (Ho203) film, a thulium oxide (Tm203) film, a ytterbium oxide (Yb203) film, a lutetium oxide (Lu203) film, a yttrium oxide (Y203) film, a hafnium nitride film, an aluminum nitride film, a hafnium oxynitride film, or an aluminum oxynitride film can be used. Examples of a deposition method of these films include a CVD method, a PVD method, and an ALD method.

[0349] Hereinafter, the operation of the imaging device of Example 1 (first imaging device) will be described with reference to Figure 8 and 9A The imaging device of Example 1 further includes a control unit provided on the semiconductor substrate 70 and including a drive circuit, and the first electrode 11, the second electrode 12, the charge storage electrode 14, and the charge movement control electrode 21 are connected to the drive circuit. Here, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, the first electrode 11 is set to a positive potential, and the second electrode 12 is set to a negative potential. Electrons generated by photoelectric conversion in the photoelectric conversion layer 13 are read out to the floating diffusion layer. The same applies to other examples. Note that, in a mode in which the first electrode 11 is set to a negative potential, the second electrode is set to a positive potential, and electron holes generated based on photoelectric conversion in the photoelectric conversion layer 13 are read out to the floating diffusion layer, it is only necessary to reverse the high and low of the potentials explained below.

[0350] In Figure 8 , the Figure 51 and 52 of Example 11 described later, and the Figure 58 and 59 of Example 12, the following marks are used. Note that, Figure 9A , 9B and 9C are equivalent circuit diagrams of the imaging device and the layered imaging device of Example 1, Example 11, and Example 12 for describing each site in Figure 8 (Example 1), Figure 51 (Example 11), and Figure 58 (Example 12).

[0351] P A...point P of the photoelectric conversion layer 13, which is located between the charge storage electrode 14 and the first electrode 11, or between the transport control electrode (charge transport electrode) 15 and the first electrode 11. A electric potential at

[0352] P B ...point P in the region of the photoelectric conversion layer 13 facing the charge motion control electrode 21 B electric potential at

[0353] P C ...point P in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 C electric potential at

[0354] P C1 ...point P in the region facing the charge storage electrode segment 14A of the photoelectric conversion layer 13 C1 electric potential at

[0355] P C2 ...point P in the region facing the charge storage electrode segment 14B of the photoelectric conversion layer 13 C2 electric potential at

[0356] P C3 ...point P in the region facing the charge storage electrode segment 14C of the photoelectric conversion layer 13 C3 electric potential at

[0357] P D ...point P in the region of the photoelectric conversion layer 13 facing the transport control electrode (charge transport electrode) 15 D electric potential at

[0358] FD····· Potential of the first floating diffusion layer FD1

[0359] V 0A The potential of charge storage electrode 14

[0360] V 0A-A The potential of the charge storage electrode section is 14A.

[0361] V 0A-B The potential of charge storage electrode section 14B

[0362] V 0A-C The potential of the charge storage electrode section 14C

[0363] V 0T The potential of the charge transfer control electrode (charge transfer electrode) 15

[0364] RST Reset transistor TR1 rst potential of the gate portion 51

[0365] V DD potential of the power supply

[0366] VSL1 Signal line (data output line) VSL1

[0367] TR1 rst Reset transistor TR1 rst

[0368] TR1 amp Amplification transistor TR1 amp

[0369] TR1 sel Selection transistor TR1 sel

[0370] During the charge storage, the drive circuit applies a potential V 11 to the first electrode 11, a potential V 12 to the charge storage electrode 14, and a potential V 13 to the charge movement control electrode 21. Light incident on the photoelectric conversion layer 13 causes photoelectric conversion in the photoelectric conversion layer 13. Electron holes generated by the photoelectric conversion are sent from the second electrode 12 to the drive circuit through the wiring V 0U . On the other hand, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, a positive potential is applied to the first electrode 11, and a negative potential is applied to the second electrode 12. Therefore, the potentials are set so that V 12 ≥ V 11 , preferably, V 12 > V 11 is maintained, and V 12 > V 13 is maintained. Therefore, the electrons generated by the photoelectric conversion are attracted to the charge storage electrode 14, and the electrons stop at the region 13 C of the photoelectric conversion layer 13 that faces the charge storage electrode 14. That is, the charges are stored in the photoelectric conversion layer 13. V 12 is greater than V 11 , therefore, the electrons generated within the photoelectric conversion layer 13 do not move toward the first electrode 11. Furthermore, V 12 is greater than V 13Therefore, the electrons generated within the photoelectric conversion layer 13 do not move toward the charge movement control electrode 21. That is, this can prevent the charges generated by the photoelectric conversion from flowing into the adjacent imaging element. During the time course of the photoelectric conversion, the potential in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 becomes a more negative value.

[0371] Subsequently, a reset operation is performed during the charge storage. This resets the potential of the first floating diffusion layer FD1, and the potential of the first floating diffusion layer FD1 becomes the potential V DD .

[0372] After the reset operation is completed, the charges are read out. That is, during the charge transfer, the drive circuit applies the potential V 21 to the first electrode 11, applies the potential V 22 to the charge storage electrode 14, and applies the potential V 23 to the charge movement control electrode 21. Here, the potentials are set so that V 21 > V 22 > V 23 is maintained. Therefore, the electrons in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 stop being read out to the first electrode 11 and further to the first floating diffusion layer FD1. That is, the charges stored in the photoelectric conversion layer 13 are read out to the control unit. Furthermore, V 22 is greater than V 23 , therefore, the electrons generated within the photoelectric conversion layer 13 do not move toward the charge movement control electrode 21. That is, this can prevent the charges generated by the photoelectric conversion from flowing into the adjacent imaging element.

[0373] This completes a series of operations including the charge storage, the reset operation, and the charge transfer.

[0374] The operation of the amplification transistor TR1 amp and the selection transistor TR1 sel after the electrons are read out to the first floating diffusion layer FD1 is the same as that of a conventional transistor. Furthermore, a series of operations including the charge storage, the reset operation, and the charge transfer of the second and third imaging elements are similar to the conventional series of operations including the charge storage, the reset operation, and the charge transfer. Furthermore, as in the conventional technology, the reset noise of the first floating diffusion layer FD1 can be removed in a correlated double sampling (CDS) process.

[0375] As described above, the charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via the insulating layer is provided in the imaging device of Embodiment 1 or Embodiments 2 to 8 described later. Thus, in the photoelectric conversion in the photoelectric conversion unit after light is applied to the photoelectric conversion unit, the photoelectric conversion layer, the insulating layer, and the charge storage electrode constitute a kind of capacitor. The charge can be stored in the photoelectric conversion layer. Thus, the charge storage portion can be completely depleted to remove the charge at the start of exposure. This can suppress the phenomenon of the decrease in the imaging quality caused by the degradation of the random noise due to the increase in KTC noise. Further, it is also possible to reset all the pixels at once, realizing a so-called global shutter function.

[0376] Further, when photoelectric conversion occurs in the photoelectric conversion layer in the imaging device of Embodiment 1 after light enters the photoelectric conversion layer, the absolute value of the potential applied to the portion of the photoelectric conversion layer facing the charge storage electrode is greater than the absolute value of the potential applied to the region B of the photoelectric conversion layer. Thus, the charge generated by the photoelectric conversion is strongly attracted to the portion of the photoelectric conversion layer facing the charge storage electrode. This can prevent the charge generated by the photoelectric conversion from flowing into the adjacent imaging device, and the quality of the video (image) captured is not reduced. Alternatively, the charge motion control electrode is formed in the region facing the region B of the photoelectric conversion layer via the insulating layer, and the electric field and the potential of the region B of the photoelectric conversion layer on the upper side of the charge motion control electrode can be controlled. Thus, the charge motion control electrode can prevent the charge generated by the photoelectric conversion from flowing into the adjacent imaging device, and the quality of the video (image) captured is not reduced.

[0377] Figure 10 A conceptual diagram of the solid-state imaging device of Embodiment 1 is shown. Embodiment 1 of the solid-state imaging device 100 includes an imaging region 111 including the stacked imaging devices 101 arranged in a two-dimensional array, a vertical drive circuit 112 as a drive circuit (peripheral circuit) of the stacked imaging devices 101, a column signal processing circuit 113, a horizontal drive circuit 114, an output circuit 115, a drive control circuit 116, and the like. Note that the circuit can include a publicly known circuit or other circuit configuration (for example, various circuits used in a conventional CCD solid-state imaging device or CMOS solid-state imaging device). Note that in Figure 10 In the drawing, the reference numeral "101" is shown only in one row of the stacked imaging devices 101.

[0378] The drive control circuit 116 generates clock signals and control signals that are the basis of the operation of the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114, based on a vertical synchronization signal, a horizontal synchronization signal, and a main clock. Further, the generated clock signals and control signals are input to the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114.

[0379] The vertical drive circuit 112 includes, for example, a shift register, and sequentially selects and scans the stacked imaging elements 101 of the imaging region 111 row by row in the vertical direction. Further, a pixel signal (image signal) based on a current (signal) generated in accordance with the amount of light reception in each of the stacked imaging elements 101 is sent to the column signal processing circuit 113 through a signal line (data output line) 117, VSL.

[0380] The column signal processing circuit 113, for example, is arranged for each column of the stacked imaging elements 101, for example, and is configured to use a signal from a black reference pixel (although not shown, formed around the effective pixel region) to signal process, for example, noise removal and signal amplification, the image signal output from a row of the stacked imaging elements 101 for each imaging element. A horizontal selection switch (not shown) is connected and provided between the output stage of the column signal processing circuit 113 and the horizontal signal line 118.

[0381] The horizontal drive circuit 114 includes, for example, a shift register, and sequentially outputs a horizontal scanning pulse to sequentially select the column signal processing circuit 113. The horizontal drive circuit 114 outputs a signal from each of the column signal processing circuits 113 to the horizontal signal line 118.

[0382] The output circuit 115 applies signal processing to a signal sequentially supplied from the column signal processing circuit 113 through the horizontal signal line 118 and outputs the signal.

[0383] Figure 11 An equivalent circuit diagram of a modification example of the imaging element and the stacked imaging element of Embodiment 1 (modification example 2 of Embodiment 1) is shown. Figure 12 A schematic layout view of the transistor of the first electrode, the charge storage electrode, and the control unit included in the modification example of the imaging element of Embodiment 1 (modification example 2 of Embodiment 1) is shown. In this way, the other source / drain region 51B of the reset transistor TR1 rst may be connected to the power supply V DD .

[0384] The imaging element and the stacked imaging element of Embodiment 1, for example, can be produced by the following method. That is, an SOI substrate is first prepared. Then, a first silicon layer is formed on the surface of the SOI substrate based on an epitaxial growth method, and a p + layer 73 and an n-type semiconductor region 41 are formed on the first silicon layer. Next, a second silicon layer is formed on the first silicon layer based on an epitaxial growth method, and an element separation region 71, an oxide film 72, a p + layer 42, an n-type semiconductor region 43, and a p +The layer 44. In addition, various transistors and the like included in the control unit of the imaging element are formed on the second silicon layer, and a wiring layer 62, an interlayer insulating layer 76, and various wirings are further formed on the top thereof. Then, the interlayer insulating layer 76 and a support substrate (not shown) are bonded together. Subsequently, the SOI substrate is removed to expose the first silicon layer. Note that the surface of the second silicon layer corresponds to the front surface 70A of the semiconductor substrate 70, and the surface of the first silicon layer corresponds to the back surface 70B of the semiconductor substrate 70. Furthermore, the first silicon layer and the second silicon layer are collectively denoted as the semiconductor substrate 70. Next, an opening portion for forming the contact hole portion 61 is formed on the back surface 70B side of the semiconductor substrate 70, and an HfO2 film 74, an insulating film 75, and the contact hole portion 61 are formed. Furthermore, the pad portions 63, 64, and 22, the interlayer insulating layer 81, the connection holes 65, 66, and 23, the first electrode 11, the charge storage electrode 14, the charge movement control electrode 21, and the insulating layer 82 are formed. Next, the connection portion 67 is opened, and the photoelectric conversion layer 13, the second electrode 12, the protective layer 83, and the on-chip microlens 90 are formed. In this way, the imaging element and the stacked imaging element of Embodiment 1 can be obtained.

[0385] Figure 13 (Embodiment 1, Modification Example 3), Figure 14A (Embodiment 1, Modification Example 4), Figure 14B , Figure 15A (Embodiment 1, Modification Example 5), and Figure 15B schematic layout diagrams of other modification examples of the first electrode and the charge storage electrode included in the imaging element of Embodiment 1 are shown. In the examples shown in these drawings, one common first electrode 11 is provided to correspond to four charge storage electrodes 14 in four imaging elements. Furthermore, in the example shown in Figure 13 , the charge movement control electrode 21 is formed under a portion 82 B of the insulating layer 82 in a region (region b) between the charge storage electrodes 14 and the charge storage electrodes 14. On the other hand, in the example shown in Figure 14A , the charge movement control electrode 21 is formed under a portion of the insulating layer 82 in a region surrounded by the four charge storage electrodes 14. Figure 15A The example shown in Figure 13 is a combination of the examples shown in Figure 14A , Figure 15B The example shown in Figure 14B is a combination of the examples shown in Figure 15A . Note that Figure 13 , 14A , 14B, 15A, and 15B also represent the solid-state imaging device of the first configuration and the second configuration.

[0386] In Figure 14BIn the example shown, a common first electrode 11 is provided to correspond to the four charge storage electrodes 14 in the four imaging elements, and a charge movement control electrode 21 is formed below a portion of the region of the insulating layer 82 surrounded by the four charge storage electrodes 14. Furthermore, a discharge electrode 25 is formed below a portion of the region of the insulating layer 82 surrounded by the four charge storage electrodes 14. The discharge electrode 25 can serve as, for example, a floating diffusion region or overflow port of the photoelectric conversion layer 13. The discharge electrode 25 and the photoelectric conversion layer 13 are connected through an opening provided in the insulating layer 82. That is, similar to the relationship between the photoelectric conversion layer 13 and the first electrode 11, the photoelectric conversion layer 13 extends in the opening provided in the insulating layer 82, and the extended portion of the photoelectric conversion layer 13 contacts the discharge electrode 25. The discharge electrode 25 is connected to the vertical drive circuit 112 included in the drive circuit through a connection hole 25A, a pad portion 25B, and wiring (not shown) provided in the interlayer insulating layer 81. The discharge electrode 25 can also be applied in other embodiments. Note that, for reference, Figure 16B It shows when Figure 15A When the discharge electrode 25 replaces the charge movement control electrode 21 in variant 5 of embodiment 1 shown, it moves along... Figure 15A A schematic cross-sectional view taken by a single-dotted line AA.

[0387] Or, in Figure 15B In the example shown, a common first electrode 11 is provided to correspond to the four charge storage electrodes 14 in the four imaging elements, and a charge movement control electrode 21 is formed below a portion of the insulating layer located in the region between the charge storage electrodes 14. Furthermore, a discharge electrode 25 is formed below a portion of the insulating layer 82 in the region surrounded by the four charge storage electrodes 14. The discharge electrode 25 and the photoelectric conversion layer 13 are connected through an opening provided in the insulating layer 82. That is, similar to the relationship between the photoelectric conversion layer 13 and the first electrode 11, the photoelectric conversion layer 13 extends in the opening provided in the insulating layer 82, and the extended portion of the photoelectric conversion layer 13 contacts the discharge electrode 25. Figure 16A It shows Figure 15B In the variant 5 of embodiment 1 shown, along Figure 15B A schematic cross-sectional view taken by a single-dash line BB.

[0388] or, Figure 1B A schematic cross-sectional view of a portion of a variant of the imaging element (two imaging elements arranged side by side) of Embodiment 1 is shown, and the photoelectric conversion layer may have a lower semiconductor layer 13. DN and photoelectric conversion layer 13 UP The layered structure. Upper photoelectric conversion layer 13 UP and the lower semiconductor layer 13 DNIt is shared by multiple imaging elements. That is, a photoelectric conversion layer 13 is formed among multiple imaging elements. UP and a lower semiconductor layer 13 DN This allows for the provision of the lower semiconductor layer 13 in this manner. DN This prevents, for example, recombination during charge storage. It also improves the charge transfer efficiency from the photoelectric conversion layer 13 to the first electrode 11. Furthermore, the charge generated in the photoelectric conversion layer 13 can be temporarily held to control the timing of transport, etc. Additionally, the generation of dark current can be suppressed. Upper photoelectric conversion layer 13 UP The materials contained in the lower semiconductor layer 13 can be appropriately selected from various materials contained in the photoelectric conversion layer 13. Alternatively, it is preferable that the lower semiconductor layer 13... DN The material contained therein is a material with a large bandgap energy value (e.g., a bandgap energy value equal to or greater than 3.0 eV) and higher fluidity than the material contained in the photoelectric conversion layer. Specifically, an example of such a material includes oxide semiconductor materials, such as IGZO. Alternatively, the lower semiconductor layer 13 DN Another example of materials included includes materials having an ionization potential greater than that of materials included in the photoelectric conversion layer when the charge to be stored is electrons. Alternatively, preferably, the impurity concentration of the material included in the lower semiconductor layer is preferably equal to or less than 1 × 10⁻⁶. 18 cm -3 Note that the construction and structure of Variation 6 of Example 1 can be applied to other examples.

[0389] Example 2

[0390] Example 2 relates to an imaging element, etc., according to a second aspect of the present invention. Figure 17A A schematic cross-sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Embodiment 2 is shown. In the imaging element of Embodiment 2, the region 13 of the photoelectric conversion layer 13 located between the first electrode 11 and the charge storage electrode 14 is shown. A The width W of (region A of the photoelectric conversion layer) A The region 13 of the photoelectric conversion layer 13 located between the imaging element and the adjacent imaging element B The width W of region B of the photoelectric conversion layer B Narrow. (W) A / W B An example of a value includes

[0391] 1 / 2≤(W A / W B )<1

[0392] Specifically, in Example 2, the value is

[0393] (W A / W B ) = 2 / 3

[0394] In addition, the construction and structure of the imaging element in Embodiment 2 may be similar to those of an imaging element having the basic structure of this disclosure, and details will not be described further.

[0395] Thus, in the imaging element of Embodiment 2, the width of the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is greater than the width W of the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. B Narrow. This prevents the charge generated by photoelectric conversion from flowing into adjacent imaging elements, and the quality of the captured video (image) is not degraded.

[0396] Example 3

[0397] Example 3 relates to an imaging element, etc., according to the fourth aspect of the present invention. Figure 17B A schematic cross-sectional view of a portion of the imaging elements (two imaging elements arranged side by side) of Embodiment 3 is shown. Figure 19 and Figure 20 A schematic plan view of a portion of the imaging element (a 2×2 imaging element arranged side-by-side) of Embodiment 3 is shown. In the imaging element of Embodiment 3, instead of the second electrode 12, in the region 13 of the photoelectric conversion layer 13 located between the imaging element and the adjacent imaging element. B A charge movement control electrode 24 is formed on the surface. The charge movement control electrode 24 is disposed separately from the second electrode 12. In other words, the second electrode 12 is provided for each imaging element, and the charge movement control electrode 24 is disposed separately from the second electrode 12 in region B of the photoelectric conversion layer 13, surrounding at least a portion of the second electrode 12. The charge movement control electrode 24 is formed at the same level as the second electrode 12.

[0398] In addition, such as Figure 18A As shown, a schematic cross-sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Embodiment 3 is presented. The second electrode 12 can be divided into multiple second electrodes 12, and different potentials can be applied individually to the divided second electrodes 12. Furthermore, as shown in 18B, a charge motion control electrode 24 can be disposed between the divided second electrodes 12 and the second electrode 12.

[0399] Note that in Figure 19 In the example shown, a charge storage electrode 14 is provided to correspond to a first electrode 11 in an imaging element. On the other hand, in Figure 20 In the example shown in (Variant Example 1 of Embodiment 3), a common first electrode 11 is provided to correspond to the two charge storage electrodes 14 in the two imaging elements.Figure 17B A schematic cross-sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Embodiment 3 shown corresponds to Figure 20 .

[0400] In Embodiment 3, the second electrode 12 on the light-incident side is shared by the imaging elements arranged in the left-right direction of Figure 19 , and is shared by a pair of imaging elements arranged in the up-down direction of Figure 19 . Furthermore, the charge movement control electrode 24 is also shared by the imaging elements arranged in the left-right direction of Figure 19 , and is shared by a pair of imaging elements arranged in the up-down direction of Figure 19 . The second electrode 12 and the charge movement control electrode 24 can be obtained by depositing a material layer of the second electrode 12 and the charge movement control electrode 24 on the photoelectric conversion layer 13 and then patterning the material layer. The second electrode 12 and the charge movement control electrode 24 are connected to a wiring (not shown) respectively, and the wiring is connected to a drive circuit. The wiring connected to the second electrode 12 is shared by a plurality of imaging elements. The wiring connected to the charge movement control electrode 24 is also shared by a plurality of imaging elements.

[0401] In the imaging element of Embodiment 3, the drive circuit applies the potential V2' to the second electrode 12 and the potential V 13 ' to the charge movement control electrode 24, and the charge is stored in the photoelectric conversion layer 13 during the charge storage period. During the charge transfer period, the drive circuit applies the potential V2" to the second electrode 12 and the potential V 23 " to the charge movement control electrode 24, and the charge stored in the photoelectric conversion layer 13 is read out to the control unit through the first electrode 11. Here, the potential of the first electrode 11 is higher than the potential of the second electrode 12, and thus,

[0402] V2' ≥ V 13 ' and V2" ≥ V 23 " are maintained.

[0403] Meanwhile, the following problem can occur in the configuration in which the charge movement control electrode 21 is provided adjacent to the first electrode 11 as shown in Fig. 1. That is, during the charge storage period, the drive circuit applies the potential V 11 to the first electrode 11, the potential V 12 to the charge storage electrode 14, the potential V 13 to the charge movement control electrode 21, and the potential V2 to the second electrode 12. Here, for example, V 12 > V 11 > V2 and V 12 > V 13 > V2 are maintained. Figure 21A andFigure 21B In this context, "A" represents the potential within the photoelectric conversion layer 13 located above the first electrode 11. On the other hand, at potential V... 13 When the potential is applied to the charge movement control electrode 21 but not to the charge storage electrode 14, the potential within the photoelectric conversion layer 13 located above the charge movement control electrode 21 will be as follows: Figure 21A It changes as simply as indicated by "B" in the diagram. However, the potential V... 12 A potential is applied to the charge storage electrode 14, and due to the influence of the charge storage electrode 14, the potential is as follows: Figure 21A The change is as indicated by "C". That is, within the insulating layer 82, the potential decreases toward the charge movement control electrode 21. Therefore, during charge storage, electrons and holes are stored in the region of the insulating layer 82 located above the charge storage electrode 14, and the charge generated by photoelectric conversion can be weakly attracted to the portion of the photoelectric conversion layer facing the charge storage electrode.

[0404] On the other hand, in embodiment 3, the charge motion control electrode 24 is formed at the same level as the second electrode 12, and the potential V 13 'Applied to the charge movement control electrode 24. Therefore, the potential within the photoelectric conversion layer 13 located on the lower side of the charge movement control electrode 24 is as follows...' Figure 21B The increase is as simple as indicated by "B" in the diagram. Furthermore, there is no charge movement control electrode 21 below the photoelectric conversion layer 13 located below the charge movement control electrode 24, and the potential increases even more simply within the insulating layer 82. Therefore, during charge storage, electrons and holes are not stored in the region of the insulating layer 82 located below the charge movement control electrode 24, and this prevents the phenomenon where charges generated by photoelectric conversion are weakly attracted to the portion of the photoelectric conversion layer facing the charge storage electrode. This more definitively prevents degradation of the quality of the captured video (image).

[0405] In this way, in the imaging element of Embodiment 3, instead of a second electrode, a charge motion control electrode is formed in the region of the photoelectric conversion layer located between the imaging element and adjacent imaging elements. Therefore, the charge motion control electrode can prevent the charge generated by photoelectric conversion from flowing into adjacent imaging elements, and the quality of the captured video (image) is not degraded.

[0406] Figure 22A and 22B A schematic plan view of a portion of a variant of the imaging element of Embodiment 3 (Variation 2 of Embodiment 3) is shown. Note that... Figure 22A , 23A, 25A, 26A, 27A, and 28A show an example in which one common first electrode 11 is provided to correspond to four charge storage electrodes 14 of four imaging elements. Further, as shown in Figure 22B , a second electrode 12 is provided on the upper side of the charge storage electrodes 14 with substantially the same size as the charge storage electrodes 14. The second electrode 12 is surrounded by a charge motion control electrode 24. The charge motion control electrode 24 is common to the four imaging elements. An insulating film (not shown) is formed on the photoelectric conversion layer 13 including the second electrode 12 and the charge motion control electrode 24, and a contact hole (not shown) connected to the second electrode 12 is formed on the insulating film on the upper side of the second electrode 12. A wiring V 0U (not shown) connected to the contact hole is provided on the insulating film. Note that the configuration and structure of the second electrode 12, the insulating film, the contact hole, and the wiring V 0U are similar in the following variants. Further, Figure 22A , 22B , 23A, 23B, 23C, 25A, 25B, 26A, 26B, 27A, 27B, 28A, and 28B show examples in which the first and second configurations are also applied to the solid-state imaging device.

[0407] Figure 23A , 23B , and 23C show a schematic plan view of a part of Variant 3 of Embodiment 3. As shown in Figure 23B and 23C , a second electrode 12 is provided on the upper side of the charge storage electrodes 14 with substantially the same size as the charge storage electrodes 14. The second electrode 12 is surrounded by a charge motion control electrode 24. The charge motion control electrode 24 is common to the four imaging elements. A common part is formed on the photoelectric conversion layer 13. Note that in the example shown in Figure 23C , the second electrode 12 extends to the second electrode of the adjacent imaging element.

[0408] Figure 24A shows a schematic sectional view of a part of a variant of the imaging element (two imaging elements arranged side by side) of Embodiment 3 (Variant 4A of Embodiment 3), Figure 25A and 25B shows a schematic plan view of the part. In Variant 4A of Embodiment 3, a second electrode 12 is provided for each imaging element, and a charge motion control electrode 24 is provided around at least a part of the second electrode 12 and separated from the second electrode 12. A part of the charge storage electrode 14 is present on the lower side of the charge motion control electrode 24. The second electrode 12 is provided on the upper side of the charge storage electrode 14 with a size smaller than that of the charge storage electrode 14.

[0409] Figure 24BA schematic cross-sectional view of a part of a modification of the imaging element of Embodiment 3 (two imaging elements arranged side by side) is shown. This modification is Embodiment 3 Modification 4A. Figure 26A and 26B A schematic plan view of this part is shown. In Modification 4A, the second electrode 12 is provided for each imaging element, and the charge movement control electrode 24 surrounds at least a part of the second electrode 12 and is separate from the second electrode 12. A part of the charge storage electrode 14 exists on the lower side of the charge movement control electrode 24, and in addition, the charge movement control electrode (upper charge movement control electrode) 24 is provided on the lower side of the charge movement control electrode (lower charge movement control electrode) 21. The size of the second electrode 12 is smaller than the size in Modification 4B. That is, the region of the second electrode 12 facing the charge movement control electrode 24 is closer to the first electrode 11 than the region of the second electrode 12 facing the charge movement control electrode 24 in Modification 4B. The charge storage electrode 14 is surrounded by the charge movement control electrode 21.

[0410] Figure 27A and Figure 27B A schematic plan view of a part of a modification of the imaging element of Embodiment 3 (two imaging elements arranged side by side) is shown. This modification is Embodiment 3 Modification 4A. In Modification 4A, the second electrode 12 is provided for each imaging element, and the charge movement control electrode 24 surrounds at least a part of the second electrode 12 and is separate from the second electrode 12. A part of the charge storage electrode 14 exists on the lower side of the charge movement control electrode 24, and in addition, the charge movement control electrode (upper charge movement control electrode) 24 is provided on the lower side of the charge movement control electrode (lower charge movement control electrode) 21. The size of the second electrode 12 is smaller than the size in Modification 4B. That is, the region of the second electrode 12 facing the charge movement control electrode 24 is closer to the first electrode 11 than the region of the second electrode 12 facing the charge movement control electrode 24 in Modification 4B. The charge storage electrode 14 is surrounded by the charge movement control electrode 21.

[0411] Figure 28A and Figure 28BA schematic plan view of a portion of a modification of the imaging element of Embodiment 3 (Embodiment 3 Modification Example 4D) is shown. In Embodiment 4D, as in Embodiment 3 Modification Example 4B, the charge motion control electrode (lower charge motion control electrode) 21 is disposed on the lower side of the charge motion control electrode (upper charge motion control electrode) 24. The size of the second electrode 12 is smaller than in Modification Example 4B. That is, the region of the second electrode 12 facing the charge motion control electrode 24 is closer to the first electrode 11 than in Modification Example 4B. Furthermore, the spacing between the charge motion control electrode 24 and the second electrode 12 is wider than in Modification Example 4B. The charge storage electrode 14 is surrounded by the charge motion control electrode 21. The electric potential generated by the coupling of the charge motion control electrode 24 and the second electrode 12 is applied to the region of the photoelectric conversion layer 13 that is below the region between the charge motion control electrode 24 and the second electrode 12.

[0412] Figure 29A 、 29B FIGS. 29A, 29B, and 29C schematically illustrate the electric potential state in each portion (during charge transport) of Embodiment 3 Modification Example 4B, Embodiment 3 Modification Example 4C, and Embodiment 3 Modification Example 4D, respectively.

[0413] Embodiment 4

[0414] Embodiment 4 relates to an imaging element, etc. according to the fifth aspect of the present disclosure. Figure 30 A schematic cross-sectional view of a portion of the imaging element of Embodiment 4 (two imaging elements arranged side by side) is shown. In the imaging element of Embodiment 4, the region (region a) 82 A between the first electrode 11 and the charge storage electrode 14 contains an insulating material (insulating material A) 82 A with a value ε A of the dielectric constant that is higher than the value ε A of the dielectric constant of the insulating material (insulating material B) 82 B between the imaging element and the adjacent imaging element. That is, the region of the second electrode 12 facing the charge motion control electrode 24 is closer to the first electrode 11 than in Modification Example 4B. Furthermore, the spacing between the charge motion control electrode 24 and the second electrode 12 is wider than in Modification Example 4B. The charge storage electrode 14 is surrounded by the charge motion control electrode 21. The electric potential generated by the coupling of the charge motion control electrode 24 and the second electrode 12 is applied to the region of the photoelectric conversion layer 13 that is below the region between the charge motion control electrode 24 and the second electrode 12. B B B . The insulating material A (82 A ) and the insulating material B (82 B ​​The insulating material A(82) is formed at the level of the insulating layer 82 covering the charge storage electrode 14. That is, when the insulating layer 82 is represented by two layers including a lower insulating layer filling the gap between the charge storage electrode 14 and the charge storage electrode 14, and an upper insulating layer covering the charge storage electrode 14 and formed on the lower insulating layer, the insulating material A(82) is formed in the horizontal plane of the insulating layer 82 covering the charge storage electrode 14. A ′) and insulating material B(82) B A portion of the upper insulating layer is filled (specifically, the region 82 of the upper insulating layer located between the first electrode 11 and the charge storage electrode 14). A A portion of the middle and the upper insulating layer in the region between the imaging element and the adjacent imaging element (region b) 82 B (part of the text).

[0415] The imaging element of Example 4 and the stacked imaging element can also be further formed by forming an insulating material A (82) during the manufacturing process of the imaging element and the stacked imaging element of Example 1. A ′) and insulating material B(82) B Region 82 of the insulating layer 82 of ′) A and 82 B To obtain.

[0416] In the imaging element of Embodiment 4, the dielectric constant of the insulating material contained in the region between the first electrode and the charge storage electrode is higher than that of the insulating material contained in the region between the imaging element and adjacent imaging elements. Therefore, the capacitance of capacitor A is greater than that of capacitor B, and more charge is attracted to the region between the first electrode and the charge storage electrode compared to the region between the imaging element and adjacent imaging elements. This prevents charge generated by photoelectric conversion from flowing into adjacent imaging elements, and the quality of the captured video (image) is not degraded.

[0417] Figure 31 A schematic cross-sectional view of a portion of the imaging elements (two imaging elements arranged side by side) of Embodiment 4 is shown, and Figure 32 and 33 A schematic cross-sectional view of a portion of another variant example is shown. Note that... Figure 30 , 31 Insulating material A (82) shown in 32 and 33 A ′) and insulating material B(82) B The formation positions of ′) can be appropriately combined.

[0418] exist Figure 31 In the example shown, insulating material A (82 A From the region 82 of the insulating layer 82 located between the first electrode 11 and the charge storage electrode 14 AA portion of the charge storage electrode 14 begins to be filled with an insulating layer, the insulating material B (82) B ′) The region between the imaging element and the adjacent imaging element filled with an insulating layer (region b) 82 B Part of it.

[0419] exist Figure 32 In the example shown, insulating material A (82 A The region 82 between the first electrode 11 and the charge storage electrode 14 filled with insulating layer 82 A Part of the lower insulating layer, and insulating material B (82) B ′) Fill the region between the imaging element and the adjacent imaging element (region b) 82 B Part of the lower insulating layer.

[0420] exist Figure 33 In the example shown, insulating material A (82 A ′) The region 82 of the interlayer insulation layer 81 located in the insulation layer 82 A The lower part, area 82 A Located between the first electrode 11 and the charge storage electrode 14, and with insulating material B (82 B ′) The region (region b) 82 of the interlayer insulating layer 81 located between the imaging element and the adjacent imaging element. B The part below.

[0421] Example 5

[0422] Example 5 relates to an imaging element, etc., according to the sixth aspect of this disclosure. Figure 34 A schematic cross-sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Embodiment 5 is shown. In the imaging element of Embodiment 5, the region 82 of the insulating layer 82 located between the first electrode 11 and the charge storage electrode 14 is shown. A The thickness t of (region A of the insulating layer) In-A The region 82 of the insulating layer 82 located between the imaging element and the adjacent imaging element B The thickness t of (region B of the insulating layer) In-B Thin. (t) In-A / t In-B Examples of values ​​include

[0423] 1 / 2≤(t In-A / t In-B )<1,

[0424] Specifically, the value is

[0425] (t In-A / t In-B) = 0.9.

[0426] The imaging element and the stacked imaging element of Embodiment 5 can be obtained by controlling the thickness of the region 82 A and 82 B of the insulating layer 82 (for example, controlling the thickness based on etching) when forming the insulating layer 82 in the manufacturing process of the imaging element and the stacked imaging element of Embodiment 1.

[0427] In the imaging element of Embodiment 5, the thickness of the region of the insulating layer between the first electrode and the charge storage electrode is thinner than the thickness of the region of the insulating layer between the imaging element and the adjacent imaging element. Therefore, the capacity of the capacitor A is larger than the capacity of the capacitor B, and charges are more attracted to the region of the insulating layer between the first electrode and the charge storage electrode than to the region of the insulating layer between the imaging element and the adjacent imaging element. This can prevent the charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not reduced.

[0428] Figure 35 A schematic cross-sectional view of a part of a modification example of the imaging element (two imaging elements arranged side by side) of Embodiment 5 is shown, and Figure 36 a schematic cross-sectional view of a part of another modification example is shown.

[0429] In Figure 35 the modification example shown, the thickness t A of the region 82 In-A of the insulating layer 82 between the first electrode 11 and the charge storage electrode 14 (region A of the insulating layer) is thinner than the thickness t B of the region 82 In-B of the insulating layer 82 between the imaging element and the adjacent imaging element (region B of the insulating layer).

[0430] In Figure 36 the modification example shown, the level of the top surface of the insulating layer 82 in the region B of the insulating layer is the same as the level of the top surface of the insulating layer 82 above the charge storage electrode 14 included in one imaging element (the imaging element located on the right in Figure 36 . However, this top surface is at a lower level than the level of the top surface of the insulating layer 82 above the charge storage electrode 14 included in the other imaging element (the imaging element located on the left in Figure 36The top surface of the insulating layer 82 in the region A is at a level higher than the level of the top surface of the insulating layer 82 above the charge storage electrode 14 included in the other imaging element. In addition, the level of the top surface of the insulating layer 82 in the region A is the same as the level of the top surface of the insulating layer 82 above the charge storage electrode 14 included in the other imaging element. However, the top surface is at a level lower than the level of the top surface of the insulating layer 82 above the charge storage electrode 14 included in the one imaging element.

[0431] Embodiment 6

[0432] Embodiment 6 relates to an imaging element and the like according to the seventh aspect of the present disclosure. Figure 37 A schematic cross-sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Embodiment 6 is shown. In the imaging element of Embodiment 6, the thickness t of the region 13A of the photoelectric conversion layer 13 (the region of the photoelectric conversion layer 13 between the first electrode 11 and the charge storage electrode 14) is thicker than the thickness t of the region 13B of the photoelectric conversion layer 13 (the region of the photoelectric conversion layer 13 between the imaging element and the adjacent imaging element). A The thickness t of the region 13A of the photoelectric conversion layer 13 (the region of the photoelectric conversion layer 13 between the first electrode 11 and the charge storage electrode 14) Pc-A The thickness t of the region 13B of the photoelectric conversion layer 13 (the region of the photoelectric conversion layer 13 between the imaging element and the adjacent imaging element) B The thickness t of the region 13A of the photoelectric conversion layer 13 (the region of the photoelectric conversion layer 13 between the first electrode 11 and the charge storage electrode 14) Pc-B The thickness t of the region 13A of the photoelectric conversion layer 13 (the region of the photoelectric conversion layer 13 between the first electrode 11 and the charge storage electrode 14) Pc-A The thickness t of the region 13A of the photoelectric conversion layer 13 (the region of the photoelectric conversion layer 13 between the first electrode 11 and the charge storage electrode 14) Pc-B Examples of the value of (t

[0433] 1 < (t Pc-A / t Pc-B ) ≤ 2

[0434] Specifically, the value is

[0435] (t Pc-A / t Pc-B ) = 1.25.

[0436] The imaging element and the stacked imaging element of Embodiment 6 can be obtained by controlling the thicknesses (for example, controlling the thicknesses based on etching) in the regions 13A and 13B of the photoelectric conversion layer 13 when the photoelectric conversion layer 13 is formed in the manufacturing process of the imaging element and the stacked imaging element of Embodiment 1. A The thickness t of the region 13A of the photoelectric conversion layer 13 (the region of the photoelectric conversion layer 13 between the first electrode 11 and the charge storage electrode 14) B The thickness t of the region 13A of the photoelectric conversion layer 13 (the region of the photoelectric conversion layer 13 between the first electrode 11 and the charge storage electrode 14)

[0437] In the imaging element of Embodiment 6, the thickness of the region of the photoelectric conversion layer between the first electrode and the charge storage electrode is thicker than the thickness of the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element. This can prevent the charge generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) does not decrease.

[0438] Figure 38A schematic cross-sectional view of a part of a modification example of the imaging element (two imaging elements arranged side by side) of Embodiment 6 is shown, and t Pc-B The value of FC

[0439] Embodiment 7

[0440] Embodiment 7 relates to an imaging element and the like according to the eighth aspect of the present disclosure. Figure 39 A schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Embodiment 7 is shown. In the imaging element of Embodiment 7, the amount of fixed charge in the region of the interface between the photoelectric conversion layer 13 A (region A of the photoelectric conversion layer 13) and the insulating layer 82 A (region A of the insulating layer 82) is smaller than the amount of fixed charge in the region of the interface between the photoelectric conversion layer 13 A (region B of the photoelectric conversion layer 13) and the insulating layer 82 B (region B of the insulating layer 82) between the imaging element and the adjacent imaging element. B (region B of the insulating layer 82) between the imaging element and the adjacent imaging element. B (region B of the insulating layer 82) between the imaging element and the adjacent imaging element. A (region B of the insulating layer 82) between the imaging element and the adjacent imaging element. B Examples of the value of (FC

[0441] 1 / 10 ≤ (FC A / FC B ) < 1.

[0442] In Figure 39 , the black circles represent charges (electron holes) generated at the interface of the insulating layer. The amount of fixed charge in the region of the interface between the photoelectric conversion layer 13 and the insulating layer 82 may, for example, be controlled based on the method of depositing a thin film having a fixed charge.

[0443] In the imaging element of Embodiment 7, the amount of fixed charge in the region of the interface between the photoelectric conversion layer and the insulating layer located between the first electrode and the charge storage electrode is smaller than the amount of fixed charge in the region of the interface between the photoelectric conversion layer and the insulating layer located between the imaging element and the adjacent imaging. This can prevent the charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not reduced.

[0444] Embodiment 8

[0445] Embodiment 8 relates to an imaging element and the like according to the ninth aspect of the present disclosure. Figure 40A schematic cross-sectional view of a portion of the imaging element (two imaging elements arranged side by side) of Embodiment 8 is shown. In the imaging element of Embodiment 8, the value of the charge mobility CT in the region 13 of the photoelectric conversion layer located between the first electrode 11 and the charge storage electrode 14 A is greater than the value of the charge mobility CT in the region 13 of the photoelectric conversion layer located between the imaging element and the adjacent imaging element (region B of the photoelectric conversion layer 13) A . B The value of the charge mobility CT in the region A of the photoelectric conversion layer 13 B is greater than the value of the charge mobility CT in the region B of the photoelectric conversion layer 13 A . B Examples of the value of (CT

[0446] 1 < (CT A / CT B ) ≤ 1 x 10 2 .

[0447] Specifically, the value is

[0448] (CT A / CT B ) = 2.

[0449] The imaging element and the stacked imaging element of Embodiment 8 can be obtained by forming the regions 13 A and 13 B of the photoelectric conversion layer 13 using materials having the relationship of the charge mobility CT A and the charge mobility CT B described above, which is the same as the relationship of the charge mobility CT A and the charge mobility CT B included in the regions 13 A and 13 B of the photoelectric conversion layer 13 in the manufacturing process of the imaging element and the stacked imaging element of Embodiment 1 when forming the photoelectric conversion layer 13.

[0450] In the imaging element of Embodiment 8, the value of the charge mobility in the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is greater than the value of the charge mobility in the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. This can prevent the charge generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) does not decrease.

[0451] Figure 41 A schematic cross-sectional view of a portion of a modification of the imaging element (two imaging elements arranged side by side) of Embodiment 8 is shown. In Figure 41 the modification shown, a portion of the photoelectric conversion layer 13 has an upper layer (upper photoelectric conversion layer) 13 UP ' / lower layer (lower semiconductor layer) 13 DNThe two-layer structure of the photoelectric conversion layer 13. Region A(13) of the photoelectric conversion layer 13. A Region B(13) of the upper layer and photoelectric conversion layer 13 B ) on the upper layer 13 UP The portion of the photoelectric conversion layer 13 located above the charge storage electrode 14 contains the same material (upper layer composition material). Furthermore, region A(13) of the photoelectric conversion layer... A The lower layer 13 DN The lower layer 13 of the photoelectric conversion layer 13 located above the charge storage electrode 14. DN It contains the same material (lower layer constituent material). However, the upper layer constituent material and the lower layer constituent material are different. It is possible to provide the lower layer 13 in this way. DN This prevents, for example, recombination during charge storage. It also improves the charge transfer efficiency from the photoelectric conversion layer 13 to the first electrode 11. Furthermore, the charge generated in the photoelectric conversion layer 13 can be temporarily held to control the timing of transport, etc. Additionally, the generation of dark current can be suppressed.

[0452] Example 9

[0453] Example 9 is a modification of Examples 1 to 8. Figure 42 The imaging element and stacked imaging element of Embodiment 9 shown in the schematic partial cross-sectional view are front-illuminated imaging elements and stacked imaging elements. The imaging element and stacked imaging element have a stacked structure of three imaging elements, including: a first type of green light imaging element (first imaging element) sensitive to green light, as in Embodiment 1, which includes a first type of green light photoelectric conversion layer for absorbing green light; a second type of conventional blue light imaging element (second imaging element) sensitive to blue light, which includes a second type of blue light photoelectric conversion layer for absorbing blue light; and a second type of conventional red light imaging element (third imaging element) sensitive to red light, which includes a second type of red light photoelectric conversion layer for absorbing red light. Here, the red light imaging element (third imaging element) and the blue light imaging element (second imaging element) are disposed in the semiconductor substrate 70, and the second imaging element is located on the light incident side relative to the third imaging element. Additionally, the green light imaging element (first imaging element) is disposed above the blue light imaging element (second imaging element).

[0454] As in Embodiment 1, various transistors included in the control unit are disposed on the front surface 70A side of the semiconductor substrate 70. Each transistor may have a configuration and structure substantially similar to that described in Embodiment 1. Furthermore, a second imaging element and a third imaging element are disposed in the semiconductor substrate 70, and the imaging elements may also have a configuration and structure substantially similar to those described in Embodiment 1.

[0455] The interlayer insulating layers 77 and 78 are formed on the front surface 70A of the semiconductor substrate 70, and the photoelectric conversion unit (the first electrode 11, the photoelectric conversion layer 13, and the second electrode 12) and the charge storage electrode 14 included in the imaging element of Embodiment 1 are provided on the interlayer insulating layer 78.

[0456] Thus, the configuration and structure of the imaging element and the stacked imaging element of Embodiment 9 can be similar to those of the imaging element and the stacked imaging element of Embodiment 1 except that the imaging element and the stacked imaging element are front-illuminating imaging elements and stacked imaging elements, and details will not be described again.

[0457] Embodiment 10

[0458] Embodiment 10 is a modification of Embodiments 1 to 9.

[0459] Figure 43 The imaging element and the stacked imaging element of Embodiment 10 shown in the schematic partial cross-sectional view are back-illuminating imaging elements and stacked imaging elements. The imaging element and the stacked imaging element have a stacked structure including two imaging elements of the first imaging element of the first type and the second imaging element of the second type in Embodiment 1. In addition, Figure 44 The modification of the imaging element and the stacked imaging element of Embodiment 10 shown in the schematic partial cross-sectional view provides front-illuminating imaging elements and stacked imaging elements. The imaging element and the stacked imaging element have a stacked structure including two imaging elements of the first imaging element of the first type and the second imaging element of the second type in Embodiment 1. Here, the first imaging element absorbs primary color light, and the second imaging element absorbs complementary color light. Alternatively, the first imaging element absorbs white light, and the second imaging element absorbs infrared rays.

[0460] Figure 45 The modification of the imaging element of Embodiment 10 shown in the schematic partial cross-sectional view is a back-illuminating imaging element. The imaging element includes the first imaging element of the first type in Embodiment 1. In addition, Figure 46 The modification of the imaging element of Embodiment 10 shown in the schematic partial cross-sectional view is a front-illuminating imaging element. The imaging element includes the first imaging element of the first type in Embodiment 1. Here, the first imaging element includes three types of imaging elements including an imaging element that absorbs red light, an imaging element that absorbs green light, and an imaging element that absorbs blue light.

[0461] In addition, the solid-state imaging device according to the first aspect of the present disclosure includes a plurality of imaging elements. An example of the arrangement of the plurality of imaging elements includes a Bayer array. Color filters for separating blue, green, and red are arranged on the light incident side of the imaging elements as needed.

[0462] Note that, as an alternative to providing one first-type imaging element in Embodiment 1, two imaging elements (i.e., two photoelectric conversion units are stacked, and control units of the two imaging elements are provided on the semiconductor substrate) can be stacked or three imaging elements (i.e., three photoelectric conversion units are stacked, and control units of the three imaging elements are provided on the semiconductor substrate) can be stacked. The following table illustrates a stacked structure of the first-type imaging element and the second-type imaging element.

[0463]

[0464]

[0465] Embodiment 11

[0466] Embodiment 11 is a modification of Embodiments 1 to 10, and Embodiment 11 relates to the imaging element etc. of the present disclosure including a transfer control electrode (charge transfer electrode). Figure 47 A schematic partial cross-sectional view of a part of the imaging element and the stacked imaging element of Embodiment 11 is shown. Figure 48 and 49 An equivalent circuit diagram of the imaging element and the stacked imaging element of Embodiment 11 is shown. Figure 50 A schematic layout of the first electrode, the transfer control electrode, the charge storage electrode, and the transistor of the control unit included in the imaging element of Embodiment 11 is shown. Figure 51 and 52 A potential state in each section during the operation of the imaging element of Embodiment 11 is schematically illustrated. Further, Figure 53 A schematic layout of the first electrode, the transfer control electrode, and the charge storage electrode included in the imaging element of Embodiment 11 is shown. Figure 9B An equivalent circuit diagram of the imaging element and the stacked imaging element of Embodiment 11 for describing Figure 51 and 52

[0467] The imaging element and the stacked imaging element of Embodiment 11 further include a transfer control electrode (charge transfer electrode) 15 arranged between the first electrode 11 and the charge storage electrode 14, separately from the first electrode 11 and the charge storage electrode 14, and arranged to face the photoelectric conversion layer 13 via the insulating layer 82. The transfer control electrode 15 is connected to the first electrode 11 and the charge storage electrode 14 by the connection hole 68B and the pad portion 68A provided in the interlayer insulating layer 81 and by the wiring V 0T connected to a pixel driving circuit included in a driving circuit.

[0468] Hereinafter, reference will be made to Figure 51 and 52 ​The operation of the imaging device of Embodiment 11 (first imaging device) is described. Note that, in particular, the value of the potential applied to the charge storage electrode 14 and the potential at the point P D vary between Figure 51 and 52 .

[0469] During the charge storage period, the drive circuit applies the potential V 11 to the first electrode 11, applies the potential V 12 to the charge storage electrode 14, and applies the potential V 14 to the transfer control electrode 15. Light incident on the photoelectric conversion layer 13 causes photoelectric conversion in the photoelectric conversion layer 13. Electron holes generated by the photoelectric conversion are sent from the second electrode 12 to the drive circuit through the wiring V 0U . On the other hand, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, a positive potential is applied to the first electrode 11, and a negative potential is applied to the second electrode 12. Thus, the potentials are set so that V 12 > V 14 (For example, V 12 > V 11 > V 14 or V 11 > V 12 > V 14 ) is maintained. Thus, the electrons generated by the photoelectric conversion are attracted to the charge storage electrode 14, and the electrons stop in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14. That is, charge is stored in the photoelectric conversion layer 13. V 12 is greater than V 14 , which of course prevents the electrons generated within the photoelectric conversion layer 13 from moving to the first electrode 11. During the time course of the photoelectric conversion, the potential in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 becomes a more negative value.

[0470] Subsequently, a reset operation is performed during the charge storage period. This resets the potential of the first floating diffusion layer FD1, and the potential of the first floating diffusion layer FD1 becomes the potential V DD of the power supply.

[0471] After the reset operation is complete, the charge is read out. That is, during the charge transfer period, the drive circuit applies the potential V 21 to the first electrode 11, applies the potential V 22 to the charge storage electrode 14, and applies the potential V 24 to the transfer control electrode 15. Here, the potentials are set so that V 22 ≤ V 24 ≤ V 21Thus, the electron stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 is surely read out to the first electrode 11 and further to the first floating diffusion layer FD1. That is, the charge stored in the photoelectric conversion layer 13 is read out to the control unit.

[0472] This completes the series of operations including the charge storage, the reset operation, and the charge transfer.

[0473] Amplification transistor TR1 after reading out the electron to the first floating diffusion layer FD1 amp and the selection transistor TR1 sel The operation of the selection transistor TR1 is the same as that of the conventional transistor. Further, for example, the series of operations including the charge storage, the reset operation, and the charge transfer of the second imaging element and the third imaging element are similar to the conventional series of operations including the charge storage, the reset operation, and the charge transfer.

[0474] As Figure 53 shown in the schematic layout of the transistor of the first electrode, the charge storage electrode, and the control unit included in the imaging element of Embodiment 11, another source / drain region 51B of the reset transistor TR1 rst may be grounded instead of connecting another source / drain region 51B to the power source V DD .

[0475] Embodiment 12

[0476] Embodiment 12 is a modification of Embodiments 1 to 11, and Embodiment 12 relates to the imaging element of the present disclosure and the like including a plurality of charge storage electrode sections.

[0477] Figure 54 A schematic partial cross-sectional view showing a part of the imaging element of Embodiment 12 is shown.

[0478] Figure 55 and 56 Equivalent circuit diagrams of the imaging element of Embodiment 12 and the stacked imaging element are shown. Figure 57 A schematic layout of the transistor of the first electrode, the charge storage electrode, and the control unit included in the imaging element of Embodiment 12 is shown. Figure 58 and 59 The potential state in each part during the operation of the imaging element of Embodiment 12 is schematically illustrated. Further, Figure 9C Equivalent circuit diagrams of the imaging element of Embodiment 12 and the stacked imaging element for describing each part in Figure 58 are shown.

[0479] In Embodiment 12, the charge storage electrode 14 includes a plurality of charge storage electrode sections 14A, 14B, and 14C. The number of the charge storage electrode sections can be equal to or greater than 2, and in Embodiment 12, the number is "3". Further, a different electric potential is applied to each of the N charge storage electrode sections in the imaging element and the stacked imaging element of Embodiment 12. The electric potential of the first electrode 11 is higher than the electric potential of the second electrode 12. That is, for example, a positive electric potential is applied to the first electrode 11, and a negative electric potential is applied to the second electrode 12. Accordingly, during the charge transfer, the electric potential applied to the charge storage electrode section (the first photoelectric conversion unit section) 14A located closest to the first electrode 11 is higher than the electric potential applied to the charge storage electrode section (the Nth photoelectric conversion unit section) 14C located farthest from the first electrode 11. In this way, a potential gradient is provided to the charge storage electrode 14. Accordingly, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 are more certainly read out to the first electrode 11 and further read out to the first floating diffusion layer FD1. That is, the charges stored in the photoelectric conversion layer 13 are read out to the control unit.

[0480] In Figure 58 the example shown in FIG. 12A, during the charge transfer, the electric potential of the charge storage electrode section 14C < the electric potential of the charge storage electrode section 14B < the electric potential of the charge storage electrode section 14A is maintained. In this way, the electrons stopped in the region of the photoelectric conversion layer 13 are simultaneously read out to the first floating diffusion layer FD1. On the other hand, in Figure 59 the example shown in FIG. 12B, during the charge transfer, the electric potential of the charge storage electrode section 14C, the electric potential of the charge storage electrode section 14B, and the electric potential of the charge storage electrode section 14A are gradually changed (i.e., changed in a stepped manner or in a sloped shape). In this way, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode section 14C move to the region of the photoelectric conversion layer 13 facing the charge storage electrode section 14B. Next, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode section 14B move to the region of the photoelectric conversion layer 13 facing the charge storage electrode section 14A. Next, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode section 14A are necessarily read out to the first floating diffusion layer FD1.

[0481] As Figure 60 shown in FIG. 12C, in a modification example of the imaging element of Embodiment 12, the other source / drain region 51B of the reset transistor TR1 rst may be grounded, instead of connecting the other source / drain region 51B to the power supply V DD .

[0482] Embodiment 13

[0483] Embodiment 13 is a modification of Embodiments 1 to 12, and relates to a first configuration and a sixth configuration of an imaging device.

[0484] Figure 61 A schematic partial cross-sectional view of the imaging device and the stacked imaging device of Embodiment 13 is shown. Figure 62 An enlarged schematic partial cross-sectional view of a portion in which the charge storage electrode, the photoelectric conversion layer, and the second electrode are stacked is shown. The equivalent circuit diagram of the imaging device and the stacked imaging device of Embodiment 13 is similar to the equivalent circuit diagram of the imaging device of Embodiment 1 described in Figure 3 and 4 The schematic layout diagram of the transistor included in the first electrode, the charge storage electrode, and the control unit in the imaging device of Embodiment 13 is similar to the imaging device of Embodiment 1 described in Figure 5 In addition, the operation of the imaging device (first imaging device) of Embodiment 13 is substantially similar to the operation of the imaging device of Embodiment 1.

[0485] Here, in the imaging device of Embodiment 13 or the imaging devices of Embodiments 14 to 18 described later,

[0486] The photoelectric conversion unit includes N (where N ≥ 2) photoelectric conversion unit segments (specifically, three photoelectric conversion unit segments 101, 102, and 103)

[0487] The photoelectric conversion layer 13 includes N photoelectric conversion layer segments (specifically, three photoelectric conversion layer segments 131, 132, and 133), and

[0488] The insulating layer 82 includes N insulating layer segments (specifically, three insulating layer segments 821, 822, and 823).

[0489] In Embodiments 13 to 15, the charge storage electrode 14 includes N charge storage electrode segments (specifically, three charge storage electrode segments 141, 142, and 143 in each embodiment).

[0490] In Embodiments 16 and 17 and in Embodiment 15 (as appropriate), the charge storage electrode 14 includes N charge storage electrode segments (specifically, three charge storage electrode segments 141, 142, and 143) arranged apart from each other,

[0491] The nth (where n = 1, 2, 3, ··· N) photoelectric conversion unit segment 10 n includes the nth charge storage electrode segment 14 n , the nth insulating layer segment 82 n , and the nth photoelectric conversion layer segment 13n and

[0492] The larger the n value of the photoelectric conversion unit section, the farther the photoelectric conversion unit section is from the position of the first electrode 11.

[0493] Alternatively, the imaging element of Embodiment 13 or the imaging elements of Embodiments 14 and 17 described later includes

[0494] The photoelectric conversion unit includes a first electrode 11, a photoelectric conversion layer 13, and a second electrode 12 stacked, wherein

[0495] The photoelectric conversion unit further includes a charge storage electrode 14 arranged separately from the first electrode 11 and arranged to face the photoelectric conversion layer 13 via an insulating layer 82, and

[0496] The cross-sectional area of the stacked portion of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13 when cut in a YZ virtual plane changes according to the distance from the first electrode, wherein the Z direction is the stacking direction of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13, and the X direction is the direction away from the first electrode 11.

[0497] Further, in the imaging element of Embodiment 13, the thickness of the insulating layer section gradually changes from the first photoelectric conversion unit section 101 to the Nth photoelectric conversion unit section 10 N Specifically, the thickness of the insulating layer section gradually increases. Alternatively, in the imaging element of Embodiment 13, the width of the cross section of the stacked portion is constant, and the thickness of the cross section of the stacked portion, specifically, the thickness of the insulating layer section, gradually increases according to the distance from the first electrode 11. Note that the thickness of the insulating layer section increases in steps. The thickness of the insulating layer section 82 n in the nth photoelectric conversion unit section 10 n is constant. Assuming that the thickness of the nth insulating layer section 82 n in the nth photoelectric conversion unit section 10 n is “1”, the thickness of the insulating layer section 82 (n+1) in the (n+1)th photoelectric conversion unit section 10 (n+1) may be 2 to 10. However, the value is not limited to these. In Embodiment 13, the thickness of the charge storage electrode sections 141, 142, and 143 gradually decreases to make the thickness of the insulating layer sections 821, 822, and 823 gradually increase. The thickness of the photoelectric conversion layer sections 131, 132, and 133 is constant.

[0498] Hereinafter, the operation of the imaging element of Embodiment 13 will be described.

[0499] During the charge storage, the drive circuit applies a potential V 11applied to the first electrode 11, and the potential V 12 applied to the charge storage electrode 14. Light incident on the photoelectric conversion layer 13 causes photoelectric conversion in the photoelectric conversion layer 13. The electron holes generated by the photoelectric conversion are sent from the second electrode 12 to the driving circuit through the wiring V 0U On the other hand, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, a positive potential is applied to the first electrode 11, and a negative potential is applied to the second electrode 12. Thus, the potentials are set so that V 12 ≥ V 11 , preferably, V 12 > V 11 is maintained. Thus, the electrons generated by the photoelectric conversion are attracted to the charge storage electrode 14, and the electrons stop in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14. That is, the charges are stored in the photoelectric conversion layer 13. V 12 is greater than V 11 , thus, the electrons generated within the photoelectric conversion layer 13 do not move toward the first electrode 11. During the time course of the photoelectric conversion, the potential in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 becomes a more negative value.

[0500] In the configuration employed in the imaging element of Embodiment 13, the thickness of the insulating layer section gradually increases. Thus, when the state during the charge storage becomes V 12 ≥ V 11 , the nth photoelectric conversion unit section 10 n can store more charges than the (n+1)th photoelectric conversion unit section 10 (n+1) . A strong electric field is applied, and it is certain that the flow of charges from the first photoelectric conversion unit section 101 to the first electrode 11 is prevented.

[0501] Subsequently, a reset operation is performed during the charge storage period. This resets the potential of the first floating diffusion layer FD1, and the potential of the first floating diffusion layer FD1 becomes the potential V DD of the power supply.

[0502] After the reset operation is completed, the charges are read out. That is, during the charge transfer period, the driving circuit applies the potential V 21 to the first electrode 11, and the potential V 22 to the charge storage electrode 14. Here, the potentials are set so that V 21 > V 22 is maintained. Thus, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 are read out to the first electrode 11 and further to the first floating diffusion layer FD1. That is, the charges stored in the photoelectric conversion layer 13 are read out to the control unit.

[0503] More specifically, when the state changes to V during charge transport 21 >V 22 At that time, it is certain that the charge flow from the first photoelectric conversion unit segment 101 to the first electrode 11 and from the (n+1)th photoelectric conversion unit segment 10 can be guaranteed. (n+1) up to the nth photoelectric conversion unit segment 10 n The flow of charge.

[0504] This completes a series of operations including charge storage, reset, and charge transfer.

[0505] In the imaging element of Embodiment 13, the thickness of the insulating layer segment gradually varies from the first photoelectric conversion unit segment to the Nth photoelectric conversion unit segment. Alternatively, the cross-sectional area of ​​the stacked portion of the charge storage electrode, insulating layer, and photoelectric conversion layer when the stacked portion is cut in the YZ virtual plane varies according to the distance from the first electrode. Thus, a charge transport gradient is formed, and the charge generated by photoelectric conversion can be transported more easily and definitively.

[0506] The imaging element and the stacked imaging element of Embodiment 13 can be produced by a method substantially similar to that of the imaging element of Embodiment 1, and details will not be described further.

[0507] Note that, in forming the first electrode 11, the charge storage electrode 14, and the insulating layer 82 in the imaging device of Embodiment 13, a conductive material layer for forming the charge storage electrode 143 is first deposited on the interlayer insulating layer 81. The conductive material layer is patterned, and the conductive material layer is left in a region where the photoelectric conversion unit sections 101, 102, and 103 and the first electrode 11 are to be formed. In this way, a part of the first electrode 11 and the charge storage electrode 143 can be obtained. Next, an insulating layer for forming the insulating layer section 823 is deposited on the entire surface. The insulating layer is patterned, and a planarization process is performed. In this way, the insulating layer section 823 can be obtained. Then, a conductive material layer for forming the charge storage electrode 142 is deposited on the entire surface, and the conductive material layer is patterned. The conductive material layer is left in a region where the photoelectric conversion unit sections 101 and 102 and the first electrode 11 are to be formed. In this way, a part of the first electrode 11 and the charge storage electrode 142 can be obtained. Then, an insulating layer for forming the insulating layer section 822 is deposited on the entire surface. The insulating layer is patterned, and a planarization process is performed. In this way, the insulating layer section 822 can be obtained. Then, a conductive material layer for forming the charge storage electrode 141 is deposited on the entire surface. The conductive material layer is patterned, and the conductive material layer is left in a region where the photoelectric conversion unit section 101 and the first electrode 11 are to be formed. In this way, the first electrode 11 and the charge storage electrode 141 can be obtained. Then, an insulating layer is deposited on the entire surface, and a planarization process is performed. In this way, the insulating layer section 821 (the insulating layer 82) can be obtained. Furthermore, the photoelectric conversion layer 13 is formed on the insulating layer 82. In this way, the photoelectric conversion unit sections 101, 102, and 103 can be obtained.

[0508] As Figure 63 illustrated, a schematic layout diagram of a first electrode, a charge storage electrode, and a transistor of a control unit included in a modification example of the imaging device of Embodiment 13 is shown. Another source / drain region 51B of the reset transistor TR1 rst may be grounded instead of being connected to a power supply V DD .

[0509] Embodiment 14

[0510] The imaging device of Embodiment 14 relates to the imaging device of the second configuration and the sixth configuration of the present disclosure. As shown in an enlarged schematic partial cross-sectional view of a portion in which a charge storage electrode, a photoelectric conversion layer, and a second electrode are stacked, Figure 64 in the imaging device of Embodiment 14, the thickness of the photoelectric conversion layer section is different from the first photoelectric conversion unit section 101 to the Nth photoelectric conversion unit section 10 Ngradually changes. Alternatively, in the imaging device of Embodiment 14, the width of the cross section of the stacked part is constant, and the thickness of the cross section of the stacked part, particularly the thickness of the photoelectric conversion layer section, gradually increases according to the distance from the first electrode 11. Specifically, the thickness of the photoelectric conversion layer section gradually increases. Note that the thickness of the photoelectric conversion layer section increases in steps. The thickness of the photoelectric conversion layer section 13 in the nth photoelectric conversion unit section 10 n n is constant. Assuming that the thickness of the photoelectric conversion layer section 13 in the nth photoelectric conversion unit section 10 n n is "1", the thickness of the photoelectric conversion layer section 13 in the (n+1)th photoelectric conversion unit section 10 (n+1) (n+1) may be 2 to 10. However, the value is not limited to these. In Embodiment 14, the thicknesses of the charge storage electrode sections 141, 142, and 143 gradually decrease to make the thicknesses of the photoelectric conversion layer sections 131, 132, and 133 gradually increase. The thicknesses of the insulating layer sections 821, 822, and 823 are constant.

[0511] In the imaging device of Embodiment 14, the thickness of the photoelectric conversion layer section gradually increases. Therefore, when the state during the charge storage period becomes V 12 ≥ V 11 , the electric field applied to the nth photoelectric conversion unit section 10 n is stronger than the electric field applied to the (n+1)th photoelectric conversion unit section 10 (n+1) . This surely prevents the flow of the charge from the first photoelectric conversion unit section 101 to the first electrode 11. Further, when the state during the charge transport period becomes V 22 < V 21 , the flow of the charge from the first photoelectric conversion unit section 101 to the first electrode 11 and the flow of the charge from the (n+1)th photoelectric conversion unit section 10 (n+1) to the nth photoelectric conversion unit section 10 n are surely ensured.

[0512] In this way, in the imaging device of Embodiment 14, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. Alternatively, the cross-sectional area of the stacked part of the charge storage electrode, the insulating layer, and the photoelectric conversion layer when the stacked part is cut in the YZ virtual plane changes according to the distance from the first electrode. Thus, a charge transport gradient is formed, and the charge generated by photoelectric conversion can be more easily and more surely transported.

[0513] ​​​In forming the first electrode 11, the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13 in the imaging device of Embodiment 14, first, a layer of conductive material for forming the charge storage electrode 143 is deposited on the interlayer insulating layer 81. The layer of conductive material is patterned, leaving the layer of conductive material in the regions where the photoelectric conversion cell segments 101, 102, and 103 and the first electrode 11 are to be formed. In this way, a portion of the first electrode 11 and the charge storage electrode 143 can be obtained. Next, a layer of conductive material for forming the charge storage electrode 142 is deposited over the entire surface, and the layer of conductive material is patterned. The layer of conductive material is left in the regions where the photoelectric conversion cell segments 101 and 102 and the first electrode 11 are to be formed. In this way, a portion of the first electrode 11 and the charge storage electrode 142 can be obtained. Next, a layer of conductive material for forming the charge storage electrode 141 is deposited over the entire surface, and the layer of conductive material is patterned. The layer of conductive material is left in the regions where the photoelectric conversion cell segment 101 and the first electrode 11 are to be formed. In this way, the first electrode 11 and the charge storage electrode 141 can be obtained. Next, the insulating layer 82 is deposited conformally over the entire surface. Further, the photoelectric conversion layer 13 is formed on the insulating layer 82, and a planarization process is applied to the photoelectric conversion layer 13. In this way, the photoelectric conversion cell segments 101, 102, and 103 can be obtained.

[0514] Embodiment 15

[0515] Embodiment 15 relates to an imaging device of a third configuration. Figure 65 A schematic partial cross-sectional view of the imaging device and the stacked imaging device of Embodiment 15 is shown. In the imaging device of Embodiment 15, the material included in the insulating layer segment varies between adjacent photoelectric conversion cell segments. Here, the dielectric constant value of the material included in the insulating layer segment gradually decreases from the first photoelectric conversion cell segment 101 to the nth photoelectric conversion cell segment 101 n In the imaging device of Embodiment 15, the same potential can be applied to all N charge storage electrode segments, or different potentials can be applied to each of the N charge storage electrode segments. In the latter case, as described in Embodiment 16, the charge storage electrode segments 141, 142, and 143 arranged apart from each other can be connected to the vertical drive circuit 112 included in the drive circuit through the pad portions 641, 642, and 643.

[0516] Further, by employing this configuration, a charge transport gradient is formed. When the state becomes V 12 ≥ V 11 during the charge storage period, the nth photoelectric conversion cell segment is able to store more charge than the (n+1)th photoelectric conversion cell segment. Further, when the state becomes V 22<V 21 flow of charges from the first photoelectric conversion unit section to the first electrode and the flow of charges from the (n+1)th photoelectric conversion unit section to the nth photoelectric conversion unit section can be ensured.

[0517] Embodiment 16

[0518] Embodiment 16 relates to an imaging device of a fourth configuration, Figure 66 A schematic partial sectional view of the imaging device and the stacked imaging device of Embodiment 16 is shown. In the imaging device of Embodiment 16, the material included in the charge storage electrode section varies between adjacent photoelectric conversion unit sections. Here, the value of the work function of the material included in the insulating layer section gradually increases from the first photoelectric conversion unit section 101 to the Nth photoelectric conversion unit section 1010 N In the imaging device of Embodiment 16, the same potential can be applied to all of the N charge storage electrode sections, or different potentials can be applied to each of the N charge storage electrode sections. In the latter case, the charge storage electrode sections 141, 142, and 143 are connected to the vertical drive circuit 112 included in the drive circuit through the pad portions 641, 642, and 643.

[0519] Embodiment 17

[0520] The imaging device of Embodiment 17 relates to an imaging device of a fifth configuration. Figure 67A 、 67B A schematic plan view of the charge storage electrode sections in Embodiment 17 is shown in FIGS. 68A and 68B. Figure 69 A schematic layout view of the first electrode, the charge storage electrode, and the transistor of the control unit included in the imaging device of Embodiment 17 is shown. The schematic partial sectional view of the imaging device and the stacked imaging device of Embodiment 17 is similar to the schematic partial sectional view shown in FIGS. 67A and 67B. Figure 66 or 71. In the imaging device of Embodiment 17, the area of the charge storage electrode section gradually decreases from the first photoelectric conversion unit section 101 to the Nth photoelectric conversion unit section 1010 N In the imaging device of Embodiment 17, the same potential can be applied to all of the N charge storage electrode sections, or different potentials can be applied to each of the N charge storage electrode sections. Specifically, as described in Embodiment 16, the charge storage electrode sections 141, 142, and 143 arranged apart from each other can be connected to the vertical drive circuit 112 included in the drive circuit through the pad portions 641, 642, and 643.

[0521] In Embodiment 17, the charge storage electrode 14 includes a plurality of charge storage electrode sections 141, 142, and 143. The number of the charge storage electrode sections can be equal to or greater than 2, and in Embodiment 17, the number is "3". Further, in the imaging device and the stacked imaging device of Embodiment 17, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, a positive potential is applied to the first electrode 11, and a negative potential is applied to the second electrode 12. Accordingly, during the charge transfer, the potential applied to the charge storage electrode section 141 located closest to the first electrode 11 is higher than the potential applied to the charge storage electrode section 143 located farthest from the first electrode 11. In this way, a potential gradient is provided to the charge storage electrode 14. Thus, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 are more certainly read out to the first electrode 11 and further read out to the first floating diffusion layer FD1. That is, the charges stored in the photoelectric conversion layer 13 are read out to the control unit.

[0522] Further, during the charge transfer, the potential of the charge storage electrode section 143 < the potential of the charge storage electrode section 142 < the potential of the charge storage electrode section 141 is maintained. In this way, the electrons stopped in the region of the photoelectric conversion layer 13 can be simultaneously read out to the first floating diffusion layer FD1. Alternatively, during the charge transfer, the potential of the charge storage electrode section 143, the potential of the charge storage electrode section 142, and the potential of the charge storage electrode section 141 are gradually changed (i.e., changed in a stepped manner or in a sloped shape). In this way, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode section 143 move to the region of the photoelectric conversion layer 13 facing the charge storage electrode section 142. Next, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode section 142 move to the region of the photoelectric conversion layer 13 facing the charge storage electrode section 141. Next, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode section 141 can be certainly read out to the first floating diffusion layer FD1.

[0523] As Figure 70 shown in the schematic layout of the transistors of the first electrode, the charge storage electrode, and the control unit included in a modification example of the imaging device of Embodiment 17, the other source / drain region 51B of the reset transistor TR3 rst may be grounded, instead of connecting the other source / drain region 51B to the power source V DD .

[0524] In the imaging device of Embodiment 17, a charge transfer gradient is also formed by adopting this configuration. That is, the area of the charge storage electrode section is larger from the first photoelectric conversion cell section 101 to the Nth photoelectric conversion cell section 10N decreases gradually. Therefore, when the state becomes V 12 ≥ V 11 during the charge storage period, the n-th photoelectric conversion unit section can store more charges than the (n+1)-th photoelectric conversion unit section. Further, when the state becomes V 22 < V 21 during the charge transport period, the charge flow from the first photoelectric conversion unit section to the first electrode and the charge flow from the (n+1)-th photoelectric conversion unit section to the n-th photoelectric conversion unit section are always ensured.

[0525] Embodiment 18

[0526] Embodiment 18 relates to an imaging element of a sixth configuration. Figure 71 A schematic partial cross-sectional view of an imaging element and a stacked imaging element of Embodiment 18 is shown. Figure 72A and 72B A schematic plan view of a charge storage electrode section in Embodiment 18 is shown. The imaging element of Embodiment 18 includes a photoelectric conversion unit including a stack of a first electrode 11, a photoelectric conversion layer 13, and a second electrode 12. The photoelectric conversion unit further includes a charge storage electrode 14 arranged separately from the first electrode 11 and arranged to face the photoelectric conversion layer 13 via an insulating layer 82. Further, a cross-sectional area of a stacked portion of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13 when the stacked portion is cut in a YZ virtual plane, where the Z direction is a stacking direction of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13, and the X direction is a direction away from the first electrode 11, varies according to a distance from the first electrode 11.

[0527] Specifically, in the imaging element of Embodiment 18, a thickness of the cross-section of the stacked portion is constant, and a width of the cross-section of the stacked portion decreases as the distance from the first electrode 11 increases. Note that the width can decrease continuously (see Figure 72A ) or can decrease in steps (see Figure 72B ).

[0528] Thus, in the imaging element of Embodiment 18, the cross-sectional area of the stacked portion of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13 when the stacked portion is cut in the YZ virtual plane varies according to the distance from the first electrode. Therefore, a charge transport gradient is formed, and the charge generated by photoelectric conversion can be transported more easily and more certainly.

[0529] Embodiment 19

[0530] Embodiment 19 relates to a solid-state imaging device of a first configuration and a second configuration.

[0531] The solid-state imaging device embodiment 19 includes

[0532] The photoelectric conversion unit includes a first electrode 11, a photoelectric conversion layer 13, and a second electrode 12 stacked in this order, wherein

[0533] The photoelectric conversion unit further includes a plurality of imaging elements each including a charge storage electrode 14 arranged separately from the first electrode 11 and arranged to face the photoelectric conversion layer 13 via an insulating layer 82,

[0534] The plurality of imaging elements are included in an imaging element block, and

[0535] The first electrode 11 is shared by the plurality of imaging elements included in the imaging element block.

[0536] Alternatively, the solid-state imaging device of embodiment 19 includes the plurality of imaging elements described in embodiments 1 to 18.

[0537] In embodiment 19, one floating diffusion layer is provided for the plurality of imaging elements. In addition, the timing of the charge transfer period can be appropriately controlled to allow the plurality of imaging elements to share one floating diffusion layer. Furthermore, in this case, the plurality of imaging elements can share one contact hole portion.

[0538] Note that the solid-state imaging device of embodiment 19 has a substantially similar configuration and construction to the solid-state imaging devices described in embodiments 1 to 18, except that the plurality of solid-state imaging devices included in the imaging element block share the first electrode 11.

[0539] Figure 73 (Embodiment 19), Figure 74 (A first modification of embodiment 19), Figure 75 (A second modification of embodiment 19), a modification 76 (a third modification of embodiment 19), and an embodiment 77 (a fourth modification of embodiment 19) schematically illustrate the arrangement state of the first electrode 11 and the charge storage electrode 14 in the solid-state imaging device of embodiment 19. Figure 73 , 74 , 77, and 78 show 16 imaging elements, Figure 75 and 76 show 12 imaging elements. Furthermore, two imaging elements are included in an imaging element block. The imaging element block is surrounded by a broken line and shown. The subscripts attached to the first electrode 11 and the charge storage electrode 14 are used to distinguish the first electrode 11 and the charge storage electrode 14. This is equally applicable to the following description. Furthermore, one on-chip microlens (not shown in Figure 73 to 82 ) is arranged on the upper side of one imaging element. Furthermore, in one imaging element block, two charge storage electrodes 14 are provided on both sides of the first electrode 11 (see Figure 73 and 74). Alternatively, one first electrode 11 is arranged to face two charge storage electrodes 14 arranged side by side (see Figure 77 and 78 ). That is, the first electrode is arranged adjacent to the charge storage electrodes of each imaging element. Alternatively, the first electrode is arranged adjacent to the charge storage electrodes of a part of the plurality of imaging elements, and is not arranged adjacent to the charge storage electrodes of the remaining part of the plurality of imaging elements (see Figure 75 and 76 ). In this case, the movement of the charge from the remaining part of the plurality of imaging elements to the first electrode is through the part of the plurality of imaging elements. It is preferable that the distance A between the charge storage electrode included in the imaging element and the charge storage electrode included in the imaging element be longer than the distance B between the first electrode and the charge storage electrode in the imaging element adjacent to the first electrode, to positively move the charge from each imaging element to the first electrode. Furthermore, it is preferable that the farther the position of the imaging element from the first electrode, the greater the value of the distance A. Furthermore, in the example shown in Figs. Figure 74 , 76 and 78, the charge movement control electrode 21 is arranged between the plurality of imaging elements included in the imaging element block. Arranging the charge movement control electrode 21 is able to positively suppress the movement of the charge in the imaging element block located on both sides of the charge movement control electrode 21. Note that the potential can be set so that V 12 > V 13 ( for example, V 12-2 > V 13 ) is maintained, where V 13 is the potential applied to the charge movement control electrode 21.

[0540] The charge movement control electrode 21 can be formed at the same level as the first electrode 11 or the charge storage electrode 14, or can be formed at a different level on the first electrode side (specifically, at a level located on the lower side of the first electrode 11 or the charge storage electrode 14). In the former case, the distance between the charge movement control electrode 21 and the photoelectric conversion layer can be reduced, and the potential can be easily controlled. On the other hand, in the latter case, the distance between the charge movement control electrode 21 and the charge storage electrode 14 can be reduced, which is advantageous for miniaturization.

[0541] Hereinafter, the operation of the imaging element block including the first electrode 112 and the two charge storage electrodes 14 21 and 14 22 will be described.

[0542] During charge storage, the drive circuit applies the potential V a to the first electrode 112, and applies the potential V A to the charge storage electrodes 1421 and 14 22 The light incident on the photoelectric conversion layer 13 causes photoelectric conversion in the photoelectric conversion layer 13. The electron hole generated by the photoelectric conversion is drawn to the charge storage electrode 14 0U from the second electrode 22 to the drive circuit. On the other hand, the potential of the first electrode 112 is higher than the potential of the second electrode 12. That is, for example, a positive potential is applied to the first electrode 112, and a negative potential is applied to the second electrode 12. Thus, the potentials are set so that V A ≥ V a is maintained. Thus, the electron generated by the photoelectric conversion is drawn to the charge storage electrode 14 21 and 14 22 , and the electron stops in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 and 14 22 . That is, the charge is stored in the photoelectric conversion layer 13. V A is equal to or greater than V a , and thus the electron generated within the photoelectric conversion layer 13 does not move to the first electrode 112. During the time course of the photoelectric conversion, the potential in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 and 14 22 becomes a more negative value.

[0543] Subsequently, a reset operation is performed during the charge storage. This resets the potential of the first floating diffusion layer, and the potential of the first floating diffusion layer becomes the potential V DD of the power supply.

[0544] After the reset operation is completed, the charge is read out. That is, during the charge transfer, the drive circuit applies the potential V b to the first electrode 112, applies the potential V 21-B to the charge storage electrode 14 21 , and applies the potential V 22-B to the charge storage electrode 14 22 . Here, the potentials are set so that V 21-B < V b < V 22-B is maintained. Thus, the electron stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 is read out to the first electrode 112 and further to the first floating diffusion layer FD1. That is, the charge stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 is read out to the control unit. Once the reading is completed, the potentials are set so that V 22-B ≤ V 21-B < V b is maintained. Note that, in Figure 77 andFigure 78 In the example shown in the diagram, the potential can be set such that V 22-B <V b <V 21-B This is maintained. Therefore, the charge storage electrode 14 facing the photoelectric conversion layer 13 is stopped. 22 Electrons in the region are read out to the first electrode 112 and further read out to the first floating diffusion layer FD1. Furthermore, in Figure 75 and 76 In the example shown, the charge storage electrode 14 is stopped at the photoelectric conversion layer 13. 22 Electrons in the region can interact with charge storage electrode 14 22 The adjacent first electrode 113 is read out to the first floating diffusion layer FD1. In this way, the charge storage electrode 14, which is oriented towards the photoelectric conversion layer 13, is stored. 22 The charge in the region is read out to the control unit. Note that this is done when the charge storage electrode 14 facing the photoelectric conversion layer 13 is fully charged. 21 When the charge in the region is read out to the control unit, the potential of the first floating diffusion layer can be reset.

[0545] Figure 83A An example of reading and driving in the imaging element block of Embodiment 19 is shown.

[0546] [Step A]

[0547] The auto zero signal is sent to the comparator input.

[0548] [Step B]

[0549] Reset operation of a shared floating diffusion layer

[0550] [Step C]

[0551] The imaging element corresponds to the charge storage electrode 14 21 The reading of the P phase and the movement of charge to the first electrode 112

[0552] [Step D]

[0553] The imaging element corresponds to the charge storage electrode 14 21 The reading of phase D and the movement of charge to the first electrode 112

[0554] [Step E]

[0555] Reset operation of a shared floating diffusion layer

[0556] [Step F]

[0557] Automatic zeroing signal to comparator input

[0558] [Step G]

[0559] The imaging element corresponds to the charge storage electrode 14 22 The reading of the P phase and the movement of charge to the first electrode 112

[0560] [Step H]

[0561] The imaging element corresponds to the charge storage electrode 14 22 The reading of phase D and the movement of charge to the first electrode 112

[0562] In this process, data is read from the charge storage electrode 14. 21 and charge storage electrode 14 22 The signals from the two imaging elements. Based on correlated double sampling (CDS) processing, the difference between the P-phase readout in [step C] and the D-phase readout in [step D] is the signal from the charge storage electrode 14. 21 The signal from the imaging element. The difference between the P-phase readout in [Step G] and the D-phase readout in [Step H] comes from the signal corresponding to the charge storage electrode 14. 22 The signal from the imaging element.

[0563] Note that step [E] can be skipped (see [Step E]). Figure 83B Furthermore, step F can be skipped, in which case step G can be further skipped (see [Step F]). Figure 83C The difference between the reading of phase P in [Step C] and the reading of phase D in [Step D] comes from the charge storage electrode 14. 21 The signal from the imaging element. The difference between the D-phase readout in [Step D] and the D-phase readout in [Step H] comes from the signal corresponding to the charge storage electrode 14. 22 The signal from the imaging element.

[0564] The arrangement of the first electrode 11 and the charge storage electrode 14 is schematically shown. Figure 79 The variant example (the sixth variant example of Example 19) and Figure 80 In the seventh variation of Example 19, four imaging elements are included in the imaging element block. The operation of the solid-state imaging device can be substantially similar to... Figure 73 to 78 The operation of the solid-state imaging device is shown in the figure.

[0565] The arrangement of the first electrode 11 and the charge storage electrode 14 is schematically illustrated. Figure 81 and 82 In the eighth and ninth variations, the imaging element block includes 16 imaging elements. For example... Figure 81 and 82As shown, charge movement control electrodes 21A1, 21A2, and 21A3 are arranged on charge storage electrode 14. 11 and charge storage electrode 14 12 Between, charge storage electrode 14 12 and charge storage electrode 14 13 Between and charge storage electrodes 14 13 and charge storage electrode 14 14 Between. Furthermore, such as Figure 82 As shown, charge motion control electrodes 21B1, 21B2, and 21B3 are arranged on charge storage electrode 14. 21 14 31 and 14 41 With charge storage electrode 14 22 14 32 and 14 42 Between, charge storage electrode 14 22 14 32 and 14 42 With charge storage electrode 14 23 14 33 and 14 43 Between years and charge storage electrodes 14 23 14 33 and 14 43 With charge storage electrode 14 24 14 34 and 14 44 Between. Furthermore, a charge movement control electrode 21C is disposed between the imaging element block and the imaging element block. Additionally, in each solid-state imaging device, sixteen charge storage electrodes 14 can be controlled to read the charge stored in the photoelectric conversion layer 13 from the first electrode 11.

[0566] [Step 10]

[0567] Specifically, firstly, the charge storage electrode 14 stored in the photoelectric conversion layer 13 is read from the first electrode 11. 11 The charge in the region. Then, through the charge storage electrode 14 facing the photoelectric conversion layer 13. 11 The region reads the charge storage electrode 14 stored in the photoelectric conversion layer 13 from the first electrode 11. 12 The charge in the region. Then, through the charge storage electrode 14 facing the photoelectric conversion layer 13. 12 and charge storage electrode 14 11 The region reads the charge storage electrode 14 stored in the photoelectric conversion layer 13 from the first electrode 11. 13 The charge in the region.

[0568] [Step 20]

[0569] Subsequently, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 11 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 12 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 23 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 13 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 24 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 14 .

[0570] [Step 21]

[0571] The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 31 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 32 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 33 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 23 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 34 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 24 .

[0572] [Step 22]

[0573] The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 41 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 31 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 42 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 32 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 43to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 33 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 44 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 34 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14

[0574] [Step 30]

[0575] Furthermore, step 10 can be performed again to read the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 , the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 , the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 23 , the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 24 , and the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14

[0576] [Step 40]

[0577] Subsequently, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 11 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 12 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 23 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 13 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 24 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 14 .

[0578] [Step 41]

[0579] The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 31 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 . The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 32 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22In the region. This allows the charge storage electrode 14, which is oriented towards the photoelectric conversion layer 13, to be stored. 33 Charge in the region moves to the charge storage electrode 14 facing the photoelectric conversion layer 13. 23 In the region. The charge storage electrode 14, which is stored in the photoelectric conversion layer 13, is oriented towards the charge storage electrode 14. 34 Charge in the region moves to the charge storage electrode 14 facing the photoelectric conversion layer 13. 24 In the region.

[0580] [Step 50]

[0581] Furthermore, step 10 can be performed again to read the charge storage electrode 14 stored in the photoelectric conversion layer 13 via the first electrode 11. 31 The charge in the region, stored in the photoelectric conversion layer 13 facing the charge storage electrode 14 32 The charge in the region, stored in the photoelectric conversion layer 13 facing the charge storage electrode 14 33 The charge in the region and the charge storage electrode 14 stored in the photoelectric conversion layer 13. 34 The charge in the region.

[0582] [Step 60]

[0583] Subsequently, the charge storage electrode 14 stored in the photoelectric conversion layer 13 is oriented towards the charge storage electrode 14. 21 Charge in the region moves to the charge storage electrode 14 facing the photoelectric conversion layer 13. 11 In the region. This allows the charge storage electrode 14, which is oriented towards the photoelectric conversion layer 13, to be stored. 22 Charge in the region moves to the charge storage electrode 14 facing the photoelectric conversion layer 13. 12 In the region. This allows the charge storage electrode 14, which is oriented towards the photoelectric conversion layer 13, to be stored. 23 Charge in the region moves to the charge storage electrode 14 facing the photoelectric conversion layer 13. 13 In the region. This allows the charge storage electrode 14, which is oriented towards the photoelectric conversion layer 13, to be stored. 24 Charge in the region moves to the charge storage electrode 14 facing the photoelectric conversion layer 13. 14 In the region.

[0584] [Step 70]

[0585] Furthermore, step 10 can be performed again to read the charge storage electrode 14 stored in the photoelectric conversion layer 13 via the first electrode 11. 41 The charge in the region, stored in the photoelectric conversion layer 13 facing the charge storage electrode 14 42 The charge in the region, stored in the photoelectric conversion layer 13 facing the charge storage electrode 1443 The charge in the region and the charge storage electrode 14 stored in the photoelectric conversion layer 13. 44 The charge in the region.

[0586] In embodiment 19 of the solid-state imaging device, the first electrode is shared by a plurality of imaging elements included in the imaging element block. This simplifies and miniaturizes the construction and configuration in the pixel region where a plurality of imaging elements are arranged. Note that the plurality of imaging elements provided for a floating diffusion layer may include a plurality of first-type imaging elements, or may include at least one first-type imaging element or one or two or more second-type imaging elements.

[0587] Example 20

[0588] Example 20 is a modification of Example 19. The arrangement of the first electrode 11 and the charge storage electrode 14 is schematically illustrated. Figure 84 , 85 In the solid-state imaging apparatus of Embodiment 20 in 86 and 87, two imaging elements are included in an imaging element block. Furthermore, an on-chip microlens 90 is disposed on the upper side of the imaging element block. Note that in Figure 85 and Figure 87 In the example shown, charge motion control electrode 21 is arranged between multiple imaging elements contained in the imaging element block.

[0589] For example, with charge storage electrode 14 included in the imaging element block. 11 14 21 14 31 and 14 41 The corresponding photoelectric conversion layer is highly sensitive to incident light from the upper right of the attached figure. Furthermore, it is compatible with the charge storage electrode 14 included in the imaging element block. 12 14 22 14 32 and 14 42 The corresponding photoelectric conversion layer is highly sensitive to incident light from the upper left of the attached figure. Therefore, for example, it can be combined with charge storage electrode 14. 11 Imaging element and including charge storage electrode 14 12 The imaging element is used to acquire the phase difference signal of the image plane. Additionally, the signal originates from the charge storage electrode 14. 11 Signals from the imaging element and from the charge storage electrode 14 12 The signals from the imaging elements can be added together, and a combination of imaging elements can provide an imaging element. Although in Figure 84 In the example shown, the first electrode 111 is arranged on the charge storage electrode 14. 11 and charge storage electrode 14 12However, a first electrode 111 can be arranged to face two charge storage electrodes 14 arranged side by side. 11 and 14 12 ,like Figure 86 The example shown further enhances sensitivity.

[0590] Although this disclosure has been described based on preferred embodiments, it is not limited to these embodiments. The structures, configurations, manufacturing conditions, manufacturing methods, and materials used for the imaging elements, stacked imaging elements, and solid-state imaging devices described in the embodiments are illustrative and may be suitably modified. The imaging elements of the embodiments may be suitably combined. For example, the imaging elements of Embodiment 13, Embodiment 14, Embodiment 15, Embodiment 16, and Embodiment 17 may be arbitrarily combined, as may the imaging elements of Embodiment 13, Embodiment 14, Embodiment 15, Embodiment 16, and Embodiment 18.

[0591] Floating diffusion layers FD1, FD 21 FD3, 51C, 45C and 46C can also be shared depending on the situation.

[0592] For example, in Figure 88 In the variant of the imaging element and the stacked imaging element described in Embodiment 1 shown, the first electrode 11 may extend in the opening 84A provided in the insulating layer 82, and the first electrode 11 may be connected to the stacked photoelectric conversion layer 13.

[0593] Or, for example, in Figure 89 In the examples of the imaging element and the variant of the stacked imaging element described in Embodiment 1 shown, and as in Figure 90A In the enlarged schematic partial cross-sectional view of a portion of the first electrode shown, the edge portion of the top surface of the first electrode 11 is covered by the insulating layer 82, and the first electrode 11 is exposed on the bottom surface of the opening 84B. The side surface of the opening 84B has a slope extending from the first surface 82a to the second surface 82b, where the first surface 82a is the surface of the insulating layer 82 that contacts the top surface of the first electrode 11, and the second surface 82b is the surface of the insulating layer 82 that contacts the portion of the photoelectric conversion layer 13 facing the charge storage electrode 14. Thus, the side surface of the opening 84B is sloped, allowing charge to move more smoothly from the photoelectric conversion layer 13 to the first electrode 11. Note that although in Figure 90A In the example shown, the side surface of the opening 84B has rotational symmetry with respect to the axis of the opening 84B, but as... Figure 90BAs shown, the side surface of the opening portion 84C that extends obliquely from the first surface 82a toward the second surface 82b can be disposed closer to the charge storage electrode 14. This makes it difficult for the electric charges to move from the portion of the photoelectric conversion layer 13 that is located on the opposite side of the charge storage electrode 14 with respect to the opening portion 84C. Further, although the side surface of the opening portion 84B extends obliquely from the first surface 82a toward the second surface 82b, the edge portion of the side surface of the opening portion 84B in the second surface 82b can be disposed outside the edge portion of the first electrode 11 as shown in Figure 90A , or can be disposed inside the edge portion of the first electrode 11 as shown in Figure 90C . The former configuration can be employed to more easily transport the electric charges, and the latter configuration can be employed to reduce shape changes during the formation of the opening portion.

[0594] Reflow including an etching mask of a resist material formed for forming an opening portion in the insulating layer based on an etching method can cause the opening side surface of the etching mask to form a slope, and the etching mask can be used to etch the insulating layer 82 to form the opening portions 84B and 84C.

[0595] Further, as in the imaging element and the variant of the stacked imaging element described in Embodiment 1 shown in, for example, Figure 91 , light can be incident from the second electrode 12 side, and a light shielding layer 92 can be formed on the light incident side closer to the second electrode 12. Note that various wiring provided on the light incident side with respect to the photoelectric conversion layer can also function as a light shielding layer.

[0596] Note that although the light shielding layer 92 is formed on the upper side of the second electrode 12 in the example shown in Figure 91 , that is, although the light shielding layer 92 is formed on the light incident side closer to the second electrode 12 and the upper side of the first electrode 11, the light shielding layer 92 can be disposed on the surface of the light incident side of the second electrode 12 as shown in Figure 92 . Further, as shown in Figure 93 , the light shielding layer 92 can be formed on the second electrode 12 as appropriate.

[0597] Alternatively, light can be incident from the second electrode 12 side, and light can not be incident on the first electrode 11. Specifically, as shown in Figure 91 , the light shielding layer 92 is formed on the light incident side closer to the second electrode 12 and the upper side of the first electrode 11. Alternatively, as shown in Figure 95As shown in FIG. 11, on-chip microlenses 90 can be provided on the upper side of the charge storage electrodes 14 and the second electrodes 12. Light incident on the on-chip microlenses 90 can be collected by the charge storage electrodes 14, and the light can not reach the first electrodes 11. Note that, in the case where the transfer control electrodes 15 are provided as described in Embodiment 11, light can not be incident on the first electrodes 11 and the transfer control electrodes 15. Specifically, as Figure 94 As shown in FIG. 11, light-shielding layers 92 can be formed on the upper side of the first electrodes 11 and the transfer control electrodes 15. Alternatively, light incident on the on-chip microlenses 90 can not reach the first electrodes 11, or can not reach the first electrodes 11 and the transfer control electrodes 15.

[0598] These configurations and structures can be employed. Alternatively, the light-shielding layers 92 can be provided so that light is incident only on the portion of the photoelectric conversion layer 13 located on the upper side of the charge storage electrodes 14. Alternatively, the on-chip microlenses 90 can be designed. In this way, the portion of the photoelectric conversion layer 13 located on the upper side of the first electrodes 11 (or the upper side of the first electrodes 11 and the transfer control electrodes 15) does not contribute to photoelectric conversion. Thus, all the pixels can be more certainly reset at the same time, and a global shutter function can be more easily achieved. That is, in a driving method of a solid-state imaging device including a plurality of imaging elements having the configurations and structures, the following steps are repeated:

[0599] In all the imaging elements, the charges in the first electrodes 11 are simultaneously all released to the outside of the system, and the charges are stored in the photoelectric conversion layers 13; subsequently,

[0600] In all the imaging elements, the charges stored in the photoelectric conversion layers 13 are simultaneously all transferred to the first electrodes 11, and after the transfer is completed, the imaging elements sequentially read the charges transferred to the first electrodes 11.

[0601] In the driving method of the solid-state imaging device, in each of the imaging elements, light from the second electrode side does not incident on the first electrode. In all the imaging elements, the charges in the first electrodes are simultaneously all released to the outside of the system, and the charges are stored in the photoelectric conversion layers. Thus, the first electrodes can be certainly reset at the same time in all the imaging elements. Further, subsequently, in all the imaging elements, the charges stored in the photoelectric conversion layers are simultaneously all transferred to the first electrodes. After the transfer is completed, the imaging elements sequentially read the charges transferred to the first electrodes. Thus, a so-called global shutter function can be easily achieved.

[0602] Further, in the modification of Embodiment 11, as shown in FIG. 12, a plurality of transfer control electrodes can be provided from the position closest to the first electrodes 11 toward the charge storage electrodes 14. Note that, Figure 95 Figure 96 ​An example of two transmission control electrodes 15A and 15B is shown. Furthermore, an on-chip microlens 90 can be disposed above the charge storage electrode 14 and the second electrode 12. Light incident on the on-chip microlens 90 can be collected by the charge storage electrode 14, and the light may not reach the first electrode 11 and the transmission control electrodes 15A and 15B.

[0603] exist Figure 61 and 62 In the illustrated embodiment 13, the thickness of the charge storage electrode segments 141, 142, and 143 gradually decreases, so that the thickness of the insulating layer segments 821, 822, and 823 gradually increases. On the other hand, as in... Figure 97 The diagram shows an enlarged schematic partial cross-sectional view of the stacked portion of the charge storage electrode, photoelectric conversion layer, and second electrode in a variant of Embodiment 13. The thicknesses of the charge storage electrode sections 141, 142, and 143 can be constant, while the thicknesses of the insulating layer sections 821, 822, and 823 can gradually increase. Note that the thicknesses of the photoelectric conversion layer sections 131, 132, and 133 are constant.

[0604] In addition, Figure 64 In the illustrated embodiment 14, the thickness of the charge storage electrode segments 141, 142, and 143 gradually decreases, thereby gradually increasing the thickness of the photoelectric conversion layer segments 131, 132, and 133. On the other hand, as in... Figure 98 The diagram shows an enlarged schematic partial cross-sectional view of the stacked portion of the charge storage electrode, photoelectric conversion layer, and second electrode in a variant of Embodiment 14. The thickness of the charge storage electrode segments 141, 142, and 143 can be constant, and the thickness of the insulating layer segments 821, 822, and 823 can be gradually reduced so that the thickness of the photoelectric conversion layer segments 131, 132, and 133 gradually increases.

[0605] It is obvious that the above-described variations can also be applied to embodiments other than Embodiment 1.

[0606] Although electrons are signal charges, and the conductivity type of the photoelectric conversion layer formed on the semiconductor substrate in the embodiment is n-type, the embodiment can also be applied to solid-state imaging devices in which holes are signal charges. In this case, the semiconductor regions can be semiconductor regions of opposite conductivity types, and the conductivity type of the photoelectric conversion layer formed on the semiconductor substrate can be p-type.

[0607] Further, in the above-described example, the embodiment is applied to a CMOS solid-state imaging device in which unit pixels that detect signal charges as physical quantities according to the amount of incident light are arranged in a matrix. However, the embodiment is not limited to application to a CMOS solid-state imaging device, and the embodiment can also be applied to a CCD solid-state imaging device. In the latter case, a vertical transfer register of the CCD structure transfers signal charges in the vertical direction, and a horizontal transfer register transfers signal charges in the horizontal direction. The charges are amplified, and a pixel signal (image signal) is output. Further, the embodiment is not limited to a general column-type solid-state imaging device in which pixels are formed in a two-dimensional matrix and a column signal processing circuit is provided for each pixel column. Further, depending on the circumstances, a selection transistor can not be included.

[0608] Further, the imaging element and the stacked imaging element of the present disclosure are not limited to application to a solid-state imaging device that detects a distribution of the amount of incident light of visible light to obtain an image of the distribution. The imaging element and the stacked imaging element can also be applied to a solid-state imaging device that captures an image of a distribution of the amount of incident light of infrared rays, X-rays, particles, and the like. Further, in a broad sense, the imaging element and the stacked imaging element can generally be applied to a solid-state imaging device (physical quantity distribution detection device) such as a fingerprint detection sensor that detects a distribution of another physical quantity such as pressure and capacitance to obtain an image of the distribution.

[0609] Further, the imaging element and the stacked imaging element are not limited to a solid-state imaging device that sequentially scans unit pixels of an imaging region line by line to read pixel signals from the unit pixels. The imaging element and the stacked imaging element can also be applied to an X-Y address type solid-state imaging device that selects an arbitrary pixel one by one and reads pixel signals from the selected pixels one by one. The solid-state imaging device can be formed as one chip, or can be in the form of a module having an imaging function in which an imaging region and a drive circuit or an optical system are packaged together.

[0610] Further, the imaging element and the stacked imaging element are not limited to application to a solid-state imaging device, and the imaging element and the stacked imaging element can also be applied to an imaging apparatus. Here, the imaging apparatus denotes a camera system such as a digital camera and a video camera, or an electronic device having an imaging function such as a mobile phone. In some cases, the imaging apparatus is in the form of a module mounted on an electronic device, i.e., a camera module.

[0611] Figure 99A and 99B An equivalent circuit diagram illustrating a modification example of a transistor that drives a charge storage electrode is shown. Figure 100A and 100B An equivalent circuit diagram illustrating a modification example of a transistor that drives a charge storage electrode is shown. Figure 99A and 99B Pulse waveforms for driving transistors in the equivalent circuits shown inFigure 100A and Figure 100B The horizontal axis represents time, and the vertical axis represents the potential of the charge storage electrode 14. A transistor typically applies a potential to the charge storage electrode 14. Note that the operation of a transistor applying a potential to the charge storage electrode 14 is expressed as "charge storage electrode 14 is driven by a transistor". On the other hand, in Figure 99A and 100A In the example shown, two transistors (FET-1, FET-2) drive the charge storage electrode 14. Furthermore, during the initial stage of charge transfer, the charge storage electrode 14 is driven by one transistor (FET-1), and during the later stage of charge transfer, the charge storage electrode 14 is driven simultaneously by both transistors (FET-1, FET-2). Note that the reference numeral "FET-0" indicates the transistor used for control. Figure 99B and Figure 100B In the example shown, charge storage electrode 14 is driven by a transistor with high drive capability (FET-5) and a transistor with low drive capability (FET-3). Specifically, in the early stages of charge transfer, charge storage electrode 14 is driven by the transistor with low drive capability (FET-3), and in the later stages of charge transfer, charge storage electrode 14 is driven by the transistor with high drive capability (FET-5). Note that reference numeral "FET-4" indicates a MOS diode. The drive capability of a transistor is defined by, for example, the channel width of the transistor. Based on the configuration, when a large amount of charge needs to be transferred, charge storage electrode 14 can be driven by a single transistor or by a transistor with low drive capability. This suppresses blooming. When blooming is no longer a concern, charge storage electrode 14 can be driven by two transistors or by a transistor with high drive capability (or by a transistor with high drive capability and a transistor with low drive capability). This increases the charge transfer speed (reduces the charge transfer time).

[0612] Figure 101A conceptual diagram showing an example of using a solid-state imaging device 201 including the imaging element and the stacked imaging element of the present disclosure in an electronic device (a camera) 200 is shown. The electronic device 200 includes the solid-state imaging device 201, an optical lens 210, a shutter device 211, a drive circuit 212, and a signal processing circuit 213. The optical lens 210 images image light (incident light) from an object to form an image on an imaging surface of the solid-state imaging device 201. Thus, signal charges are stored in the solid-state imaging device 201 for a certain time. The shutter device 211 controls a light-exposed period and a light-shielded period of the solid-state imaging device 201. The drive circuit 212 provides a drive signal for controlling a transfer operation and the like of the solid-state imaging device 201 and a shutter operation of the shutter device 211. Signals of the solid-state imaging device 201 are transferred based on a drive signal (a timing signal) provided from the drive circuit 212. The signal processing circuit 213 performs various types of signal processing. A video signal after the signal processing is stored in a storage medium such as a memory or the like or is output to a monitor. In the electronic device 200, the pixel size in the solid-state imaging device 201 can be miniaturized, and the transfer efficiency can be improved. Thus, the pixel characteristics in the electronic device 200 can be improved. The electronic device 200 to which the solid-state imaging device 201 can be applied is not limited to a camera. The solid-state imaging device 201 can be applied to a digital camera, a camera module for a mobile device (for example, a cell phone), and other imaging devices.

[0613] Note that the present disclosure can also be configured as follows.

[0614] [A01] <<Imaging Element: First Aspect>>

[0615] An imaging element includes:

[0616] a photoelectric conversion unit including a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein

[0617] the photoelectric conversion unit further includes a charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and

[0618] When photoelectric conversion occurs in the photoelectric conversion layer after light enters the photoelectric conversion layer, an absolute value of a potential applied to a portion of the photoelectric conversion layer facing the charge storage electrode is greater than an absolute value of a potential applied to an area of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0619] [A02] <<Imaging Element: Second Aspect>>

[0620] An imaging element includes:

[0621] a photoelectric conversion unit including a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein

[0622] The photoelectric conversion unit further includes a charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via the insulating layer, and

[0623] The width of the region of the photoelectric conversion layer between the first electrode and the charge storage electrode is narrower than the width of the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element.

[0624] [A03]<<Imaging element: third aspect>>

[0625] An imaging element includes:

[0626] A photoelectric conversion unit includes a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein

[0627] The photoelectric conversion unit further includes a charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via the insulating layer, and

[0628] The charge movement control electrode is formed in a region facing a region of the photoelectric conversion layer between the imaging element and the adjacent imaging element via the insulating layer.

[0629] [A04]<<Imaging element: fourth aspect>>

[0630] An imaging element includes:

[0631] A photoelectric conversion unit includes a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein

[0632] The photoelectric conversion unit further includes a charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via the insulating layer, and

[0633] In place of the second electrode, a charge movement control electrode is formed in a range of a region of the photoelectric conversion layer between the imaging element and the adjacent imaging element.

[0634] [A05]<<Imaging element: fifth aspect>>

[0635] An imaging element includes:

[0636] A photoelectric conversion unit includes a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein

[0637] The photoelectric conversion unit further includes a charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via the insulating layer, and

[0638] A value of a dielectric constant of an insulating material contained in a region between the first electrode and the charge storage electrode is higher than a value of a dielectric constant of an insulating material contained in a region between the imaging element and an adjacent imaging element.

[0639] [A06] <<Imaging element: Sixth aspect>>

[0640] An imaging element includes:

[0641] A photoelectric conversion unit includes a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein

[0642] The photoelectric conversion unit further includes a charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and

[0643] A thickness of a region of the insulating layer between the first electrode and the charge storage electrode is thinner than a thickness of a region of the insulating layer between the imaging element and an adjacent imaging element.

[0644] [A07] <<Imaging element: Seventh aspect>>

[0645] An imaging element includes:

[0646] A photoelectric conversion unit includes a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein

[0647] The photoelectric conversion unit further includes a charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and

[0648] A thickness of a region of the photoelectric conversion layer between the first electrode and the charge storage electrode is thicker than a thickness of a region of the photoelectric conversion layer between the imaging element and an adjacent imaging element.

[0649] [A08] <<Imaging element: Eighth aspect>>

[0650] An imaging element includes:

[0651] A photoelectric conversion unit includes a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein

[0652] The photoelectric conversion unit further includes a charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and

[0653] An amount of fixed charge in a region of an interface between the photoelectric conversion layer and the insulating layer between the first electrode and the charge storage electrode is smaller than an amount of fixed charge in a region of an interface between the photoelectric conversion layer and the insulating layer between the imaging element and an adjacent imaging element.

[0654] [A09]<<Imaging element: ninth aspect>>

[0655] An imaging element includes:

[0656] a photoelectric conversion unit including a first electrode, a photoelectric conversion layer, and a second electrode stacked, wherein

[0657] the photoelectric conversion unit further includes a charge storage electrode arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and

[0658] a value of a charge mobility of the photoelectric conversion layer in a region between the first electrode and the charge storage electrode is greater than a value of a charge mobility of the photoelectric conversion layer in a region between the imaging element and an adjacent imaging element.

[0659] [A10]

[0660] The imaging element according to [A03], further including:

[0661] a control unit provided on the semiconductor substrate and including a drive circuit, wherein

[0662] the first electrode, the second electrode, the charge storage electrode, and the charge movement control electrode are connected to the drive circuit,

[0663] during charge storage, the drive circuit applies a potential V 11 to the first electrode, applies a potential V 12 to the charge storage electrode, and applies a potential V 13 to the charge movement control electrode, and charges are stored in the photoelectric conversion layer, and

[0664] during charge transfer, the drive circuit applies a potential V 21 to the first electrode, applies a potential V 22 to the charge storage electrode, and applies a potential V 23 to the charge movement control electrode, and charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, wherein

[0665] in a case where a potential of the first electrode is higher than a potential of the second electrode

[0666] V 12 ≥ V 11 , V 12 > V 13 , and V 21 > V 22 > V 23 , and

[0667] in a case where a potential of the first electrode is lower than a potential of the sec...

Claims

1. An imaging element comprising: a photoelectric conversion unit including a first electrode, a photoelectric conversion layer, and a second electrode which are laminated, wherein the photoelectric conversion unit further includes a charge storage electrode which is arranged separately from the first electrode and is arranged to face the photoelectric conversion layer via an insulating layer, and a thickness of a region of the insulating layer between the first electrode and the charge storage electrode is thinner than a thickness of a region of the insulating layer between the imaging element and an adjacent imaging element.

2. The imaging element according to claim 1, further comprising: a semiconductor substrate, wherein the photoelectric conversion unit is provided on an upper side of the semiconductor substrate.

3. The imaging element according to claim 1, further comprising: a transfer control electrode which is arranged between the first electrode and the charge storage electrode, is arranged separately from the first electrode and the charge storage electrode, and is arranged to face the photoelectric conversion layer via the insulating layer.

4. The imaging element according to claim 1, wherein the charge storage electrode includes a plurality of charge storage electrode sections.

5. The imaging element according to claim 1, wherein a size of the charge storage electrode is larger than that of the first electrode.

6. A laminated imaging element including at least one imaging element according to any one of claims 1 to 5.

7. A solid-state imaging device including a plurality of imaging elements according to any one of claims 1 to 5.

8. A solid-state imaging device including a plurality of laminated imaging elements according to claim 6.

Images