Light detection substrate and method of manufacturing the same, display device

Abstract

The present disclosure provides a light detection substrate and a manufacturing method thereof, and a display device. The light detection substrate comprises a substrate and a photoelectric conversion unit; the substrate comprises a first surface and a second surface opposite to each other, the first surface is provided with a concave-convex part, the concave-convex part has a predetermined concave-convex depth in a direction perpendicular to the first surface of the substrate; the photoelectric conversion unit comprises: a stack structure at least partially conformally covering a side of the concave-convex part away from the second surface, the stack structure at least comprises a first electrode, a photosensitive layer and a second electrode stacked in order from a side close to the substrate to a side away from the substrate; a first signal line electrically connected with the first electrode; and a second signal line electrically connected with the second electrode. The light detection substrate provided by the present disclosure can reduce the occupied space of the photoelectric conversion unit while meeting the optical detection effect.

Description

Technical Field

[0001] This invention relates to the field of electronic equipment technology, and in particular to a photodetector substrate, its manufacturing method, and a display device. Background Technology

[0002] In related technologies, photoelectric conversion devices are integrated on the photodetector substrate. For example, in-display optical fingerprint technology, space is reserved between pixels to house the photoelectric conversion devices. However, with the continuous development of display technology, high pixel density (PPI) and narrow bezels have become hot topics. To achieve high pixel density, the space reserved for photoelectric conversion devices is compressed due to pixel arrangement requirements. This results in an insufficient photosensitive area of ​​the photosensitive layer in the photoelectric conversion device, which cannot meet its detection needs, leading to photodetection failure. This is detrimental to achieving higher PPI. Summary of the Invention

[0003] This disclosure provides a photodetector substrate and its manufacturing method, as well as a display device, which can at least solve the problems in the prior art.

[0004] The technical solutions provided in this disclosure are as follows:

[0005] A photodetector substrate includes a substrate and a photoelectric conversion unit; the substrate includes a first surface and a second surface facing away from each other, the first surface is provided with a concave-convex portion, and the concave-convex portion has a predetermined concave-convex depth in a direction perpendicular to the first surface of the substrate;

[0006] The photoelectric conversion unit includes:

[0007] A stacked structure that at least partially conformally covers the side of the protrusion away from the second surface, the stacked structure comprising at least a first electrode, a photosensitive layer and a second electrode sequentially stacked from the side closer to the substrate to the side away from the substrate;

[0008] The first signal line electrically connected to the first electrode; and

[0009] The second signal line is electrically connected to the second electrode.

[0010] For example, the uneven portion includes at least one ramp extending from the first surface in the uneven direction of the uneven portion, and the photosensitive layer at least partially conformally covers the area where at least one of the ramp portions is located.

[0011] For example, the protrusion or recess includes a groove or a hole.

[0012] For example, the substrate includes multiple layers of films stacked sequentially in a direction from the second surface to the first surface, wherein the predetermined unevenness depth is at least greater than the thickness of at least two layers of films located in the direction from the second surface to the first surface that are closest to the first surface.

[0013] For example, the light detection unit further includes intersecting gate lines and data lines, the gate lines and data lines intersecting to define a pixel area, the orthographic projection of the photoelectric conversion unit on the substrate not at least partially coinciding with the pixel area, the light detection unit further includes a display unit and a switching transistor unit at least partially disposed within the pixel area, the display unit includes a third electrode, the switching transistor unit includes at least one switching transistor, the switching transistor includes a gate connected to the gate line, an active layer, a source and a drain connected to the data line, the gate is electrically connected to the gate line, the source is electrically connected to the third electrode, the drain is electrically connected to the data line, and the active layer of at least one of the switching transistors is disposed on the same layer and of the same material as the first electrode.

[0014] For example, the switching transistor unit includes at least two switching transistors, and the at least two switching transistors are stacked sequentially on the first surface in at least two layers in the direction from the second surface to the first surface.

[0015] For example, the at least two switching transistors are at least divided into a first layer of switching transistors and a second layer of switching transistors, wherein the first layer of switching transistors includes at least a first thin-film transistor, and the second layer of switching transistors includes at least a second thin-film transistor and a third thin-film transistor;

[0016] The film structure of the optical detection unit includes:

[0017] A first gate layer, a second gate layer, and a third gate layer are sequentially stacked along a direction from the second surface to the first surface;

[0018] A first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer are sequentially stacked along a direction from the second surface to the first surface; and

[0019] A first active layer and a second active layer are sequentially stacked along a direction from the second surface to the first surface; wherein

[0020] The active layer of the first thin-film transistor is formed by a first active layer pattern on the first active layer, the gate of the first thin-film transistor is formed by a first gate pattern on the first gate layer, the source of the first thin-film transistor is formed by a first source pattern formed by the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer, and the first source pattern is connected to the third electrode and the first active layer pattern respectively, and the drain of the first thin-film transistor is formed by a first drain pattern on the first source-drain metal layer;

[0021] The active layer of the second thin film transistor is formed by a second active layer pattern on the second active layer, and the first drain pattern is connected to the second source pattern. The gate of the second thin film transistor is formed by a second gate pattern on the third gate layer. The drain of the second thin film transistor is formed by a second drain pattern on the second source-drain metal layer, and the second drain pattern is connected to the first gate line pattern on the first gate layer through a first overlap pattern on the first source-drain metal layer.

[0022] The active layer of the third thin-film transistor is formed by a third active layer pattern on the second active layer. The gate of the third thin-film transistor is formed by a third gate pattern on the third gate layer. The source of the third thin-film transistor is formed by a third source pattern on the second source-drain metal layer, and the third source pattern is connected to the first overlap pattern. The drain of the third thin-film transistor is formed by a third drain pattern on the second source-drain metal layer, and the third drain pattern is connected to the second gate line pattern on the second gate layer through a second overlap pattern on the first source-drain metal layer.

[0023] For example, the first signal line is formed by connecting a first trace pattern on the first source / drain metal layer and a second trace pattern on the second source / drain metal layer to each other; the second signal line is formed by connecting a third overlap pattern on the second active layer and a third trace pattern on the second source / drain metal layer to each other, wherein the third overlap pattern overlaps with the second electrode through a via.

[0024] For example, the second active layer is an IGZO active layer.

[0025] This disclosure also provides a display device, including the light detection substrate described above.

[0026] This disclosure also provides a method for manufacturing a photodetector substrate, used to manufacture the photodetector substrate as described above, the method comprising:

[0027] A substrate is formed, wherein the substrate includes a first surface and a second surface facing away from each other, the first surface is provided with a rough portion, and the rough portion has a predetermined rough depth in a direction perpendicular to the first surface of the substrate;

[0028] The photoelectric conversion unit is formed on a first surface of the substrate, wherein the photoelectric conversion unit includes: a stacked structure that at least partially conformally covers the side of the uneven portion away from the second surface, the stacked structure including at least a first electrode, a photosensitive layer and a second electrode sequentially stacked from the side near the substrate to the side away from the substrate; a first signal line electrically connected to the first electrode; and a second signal line electrically connected to the second electrode.

[0029] For example, the method further includes:

[0030] A display unit and a switching transistor unit are formed on the first surface of the substrate. The light detection unit further includes intersecting gate lines and data lines, which intersect to define a pixel area. The orthogonal projection of the photoelectric conversion unit on the substrate does not at least partially coincide with the pixel area. The display unit and the switching transistor unit are at least partially disposed within the pixel area. The display unit includes a third electrode. The switching transistor unit includes at least one switching transistor. The switching transistor includes a gate connected to the gate line, an active layer, a source connected to the data line, and a drain. The gate is electrically connected to the gate line, the source is electrically connected to the third electrode, and the drain is electrically connected to the data line. The active layer of at least one switching transistor is disposed on the same layer and of the same material as the first electrode.

[0031] For example, forming a display unit and a switching transistor unit on the first surface of the substrate specifically includes:

[0032] A first gate layer, a second gate layer, a first source / drain metal layer, a second source / drain metal layer, a third source / drain metal layer, a first active layer, and a second active layer are formed on a first surface of the substrate, wherein...

[0033] The first gate layer is stacked sequentially along the direction from the second surface to the first surface; the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer are stacked sequentially along the direction from the second surface to the first surface; and the first active layer and the second active layer are stacked sequentially along the direction from the second surface to the first surface.

[0034] The active layer of the first thin-film transistor is formed by a first active layer pattern on the first active layer, the gate of the first thin-film transistor is formed by a first gate pattern on the first gate layer, the source of the first thin-film transistor is formed by a first source pattern formed by the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer, and the first source pattern is connected to the third electrode and the first active layer pattern respectively, and the drain of the first thin-film transistor is formed by a first drain pattern on the first source-drain metal layer;

[0035] The active layer of the second thin film transistor is formed by a second active layer pattern on the second active layer, and the first drain pattern is connected to the second source pattern. The gate of the second thin film transistor is formed by a second gate pattern on the third gate layer. The drain of the second thin film transistor is formed by a second drain pattern on the second source-drain metal layer, and the second drain pattern is connected to the first gate line pattern on the first gate layer through a first overlap pattern on the first source-drain metal layer.

[0036] The active layer of the third thin-film transistor is formed by a third active layer pattern on the second active layer. The gate of the third thin-film transistor is formed by a third gate pattern on the third gate layer. The source of the third thin-film transistor is formed by a third source pattern on the second source-drain metal layer, and the third source pattern is connected to the first overlap pattern. The drain of the third thin-film transistor is formed by a third drain pattern on the second source-drain metal layer, and the third drain pattern is connected to the second gate line pattern on the second gate layer through a second overlap pattern on the first source-drain metal layer. The first signal line is formed by connecting the first trace pattern on the first source-drain metal layer and the second trace pattern on the second source-drain metal layer. The second signal line is formed by connecting the third overlap pattern on the second active layer and the third trace pattern on the second source-drain metal layer, wherein the third overlap pattern overlaps with the second electrode through a via.

[0037] The beneficial effects of the embodiments disclosed herein are as follows:

[0038] In the above scheme, by providing a recessed portion with a predetermined recessed depth on the first surface of the substrate of the photodetector substrate, and at least partially conformally covering the recessed portion with a stacked structure of the photoelectric conversion unit including a first electrode, a photosensitive layer, and a second electrode, the projected area of ​​the stacked structure on the substrate is smaller than the actual photosensitive area of ​​the photosensitive layer in the stacked structure. That is, since the photosensitive layer conformally covers the recessed portion, the photosensitive layer can be arranged at least partially in a direction perpendicular to the substrate (i.e., longitudinally). Compared with the flat design of the photosensitive layer in related technologies, the photosensitive area of ​​the photosensitive layer of the photodetector in the photodetector substrate provided in this disclosure is larger while occupying the same space on the substrate. In other words, the photodetector substrate provided in this disclosure can reduce the space occupied by the photoelectric conversion unit while satisfying its optical detection effect. Attached Figure Description

[0039] Figure 1 This is a partial structural cross-sectional view of a photodetector substrate provided in this disclosure. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0042] Before providing a detailed description of the photodetector substrate, its manufacturing method, and the display device provided in the embodiments of this disclosure, it is necessary to explain the related technologies as follows:

[0043] In related technologies, photoelectric conversion devices are integrated on the photodetector substrate. For example, in-display optical fingerprint technology, space is reserved between pixels to house the photoelectric conversion devices. However, with the continuous development of display technology, high pixel density (PPI) and narrow bezels have become hot topics. To achieve high pixel density, the space reserved for photoelectric conversion devices is compressed due to pixel arrangement requirements. This results in an insufficient photosensitive area of ​​the photosensitive layer in the photoelectric conversion device, which cannot meet its detection needs, leading to photodetection failure. This is detrimental to achieving higher PPI.

[0044] To address the aforementioned issues, this disclosure provides a photodetector substrate, a method for manufacturing the same, and a display device. Figure 1 The diagram shown is a structural schematic of one embodiment of a photodetector substrate provided in this disclosure.

[0045] like Figure 1 As shown, the photodetector substrate provided in this embodiment includes: a substrate 100 and a photoelectric conversion unit 200; the substrate 100 includes a first surface and a second surface facing away from each other, the first surface is provided with a concave-convex portion 110, the concave-convex portion 110 having a predetermined concave-convex depth in a direction perpendicular to the first surface of the substrate 100; the photoelectric conversion unit 200 includes: a stacked structure that at least partially conformally covers the side of the concave-convex portion 110 away from the second surface, the stacked structure including at least a first electrode 210, a photosensitive layer 220 and a second electrode 230 sequentially stacked from the side near the substrate 100 to the side away from the substrate 100; a first signal line 240 electrically connected to the first electrode 210; and a second signal line 250 electrically connected to the second electrode 230.

[0046] By adopting the above solution, by providing a concave-convex portion 110 with a predetermined concave-convex depth on the first surface of the substrate 100, and at least partially covering the concave-convex portion 110 with the stacked structure of the photoelectric conversion unit 200 including the first electrode 210, the photosensitive layer 220 and the second electrode 230, the stacked structure can have a projected area on the substrate 100 that is smaller than the actual photosensitive area of ​​the photosensitive layer 220 in the stacked structure. In other words, since the photosensitive layer 220 is covered with the concave-convex portion 110, the photosensitive layer 220 can be arranged at least partially in a direction perpendicular to the substrate 100 (i.e., longitudinally arranged). Compared with the flat design of the photosensitive layer 220 in related technologies, the photosensitive area of ​​the photosensitive layer 220 of the photoelectric conversion unit in the photodetector substrate provided by the present disclosure is larger while occupying the same space of the substrate 100. That is, the photodetector substrate provided by the present disclosure can reduce the space occupied by the photoelectric conversion unit 200 while satisfying its optical detection effect.

[0047] The application scenario of the light detection substrate can be an in-screen fingerprint recognition display substrate. Since the photosensitive layer 220 of the photoelectric conversion unit 200 is arranged vertically, the space occupied by the photoelectric conversion unit 200 is compressed, which is conducive to higher pixel and narrower bezel design.

[0048] In some embodiments, such as Figure 1 As shown, the uneven portion 110 includes at least one ramp portion 111 extending from the first surface in the uneven direction of the uneven portion 110, and the photosensitive layer 220 at least partially conformally covers the area where at least one of the ramp portions 111 is located.

[0049] With the above solution, the concave and convex portion 110 has at least one sloping portion 111. On the one hand, the setting of the sloping portion 111 is more conducive to further increasing the photosensitive area of ​​the photosensitive layer 220 under the same space occupation compared with other methods such as straight sidewalls. On the other hand, it is also more in line with the process precision requirements and easier to form.

[0050] by Figure 1 As shown in the example, the concave-convex portion 110 can be any suitable concave-convex structure such as a groove or a recess. The groove or recess can be any suitable shape such as a V-shape or a trapezoid. Of course, it is understood that in practical applications, the specific structure of the concave-convex portion 110 is not limited to this. For example, the concave-convex portion 110 can be a boss or other structure that protrudes from the first surface.

[0051] Furthermore, in some exemplary embodiments, the photoelectric conversion unit 200 may be, but is not limited to, a PIN photodiode. The first electrode 210 may be an output electrode, and correspondingly, the first signal line 240 may be an output signal line; the second electrode 230 may be a power supply electrode, and correspondingly, the second signal line 250 may be a power supply signal line; the structure of the photosensitive layer 220 may be an intrinsic semiconductor sandwiched between a P-type semiconductor and an N-type semiconductor.

[0052] Furthermore, in some exemplary embodiments, such as Figure 1 As shown, the substrate 100 includes multiple layers of films stacked sequentially in the direction from the second surface to the first surface, and the predetermined unevenness depth is at least greater than the thickness of at least two layers of films located in the direction from the second surface to the first surface that are closest to the first surface.

[0053] For example, with Figure 1 As shown in the example, the substrate 100 may include a PI (polyimide) substrate 100, a buffer layer, a planarization layer, etc., stacked sequentially. Figure 1 As shown in the example, the substrate includes n film layers, and the film layers are sequentially arranged as first film layer, second film layer...nth film layer in the direction from the second surface to the first surface. At least the (n-1)th film layer has grooves or recesses, and the nth film layer conformally covers the (n-1)th film layer to form the uneven portion at the corresponding position of the groove or recess. The predetermined uneven depth is the depth of the groove or recess.

[0054] In addition, in some embodiments, the light detection unit may be used as a display substrate, which may also include multiple gate lines and multiple data lines arranged in a cross pattern. The multiple gate lines and multiple data lines cross to define multiple pixel areas S distributed in an array. The light detection unit may also include a display unit and a switching transistor unit, which are at least partially located within the pixel areas S.

[0055] The orthographic projection of the photoelectric conversion unit 200 on the substrate 100 is at least partially non-coincident with the pixel region S. For example, the orthographic projection of the photosensitive layer 220 in the photoelectric conversion unit 200 on the substrate 100 is completely non-coincident with the pixel region S. In one embodiment, when the light detection substrate is a full-screen fingerprint recognition display substrate, the light detection substrate includes a plurality of units arranged in an array, each unit may include at least one pixel region S and at least one photoelectric conversion unit 200 (e.g., ...). Figure 1 The diagram shown is a structural schematic of one of the units in one embodiment.

[0056] In one exemplary embodiment, the display unit includes a third electrode 300, and the switching transistor unit 400 includes at least one switching transistor. The switching transistor includes a gate connected to the gate line, an active layer, a source connected to the data line, and a drain. The gate is electrically connected to the gate line, the source is electrically connected to the third electrode 300, and the drain is electrically connected to the data line. The active layer of at least one of the switching transistors is co-layered and made of the same material as the first electrode 210. This configuration allows the active layer of the switching transistor and the first electrode 210 to be formed in the same patterning process, simplifying the manufacturing process.

[0057] Furthermore, the inventors of this disclosure have discovered through research that in the related technologies, the switching transistors in the display substrate are single-layer designs, and the active layers of all switching transistors are arranged on the same layer. The switching transistors occupy a large space, that is, the pixel area S is large, which makes it impossible to arrange higher PPI. Moreover, because the pixel area S is large, the arrangement space of the photoelectric conversion unit 200 is compressed, and it is difficult to compress the bezel, which is not conducive to realizing a narrow bezel design.

[0058] To address the aforementioned problems, in some embodiments of this disclosure, such as... Figure 1 As shown, exemplarily, the switching transistor unit 400 includes at least two switching transistors, and the at least two switching transistors are stacked sequentially on the first surface in at least two layers from the second surface toward the first surface. This solution, by stacking the switching transistors, can compress the space occupied by the display area, allowing for a larger area of ​​the photoelectric sensing unit within the same space, thereby improving the optical detection effect. Simultaneously, due to the stacked switching transistor design, the space occupied by the switching transistors can be compressed, thus significantly reducing the area of ​​the pixel area S, which is beneficial for achieving higher PPI and narrower bezel designs.

[0059] There can be many specific implementations for the stacked design of switching transistors. As one exemplary embodiment, such as... Figure 1 As shown, the at least two switching transistors are at least divided into a first layer of switching transistors and a second layer of switching transistors. The first layer of switching transistors includes at least a first thin-film transistor 410, and the second layer of switching transistors includes at least a second thin-film transistor 420 and a third thin-film transistor 430. The film structure of the photodetector unit includes: a first gate layer, a second gate layer, and a third gate layer sequentially stacked along the direction from the second surface to the first surface; a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer sequentially stacked along the direction from the second surface to the first surface; and a first active layer and a second active layer sequentially stacked along the direction from the second surface to the first surface.

[0060] The active layer of the first thin-film transistor 410 is formed by a first active layer pattern 411 on the first active layer, the gate of the first thin-film transistor 410 is formed by a first gate pattern 412 on the first gate layer, the source of the first thin-film transistor 410 is formed by a first source pattern 413 formed by the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer, and the first source pattern 413 is connected to the third electrode 300 and the first active layer pattern 411 respectively, and the drain of the first thin-film transistor 410 is formed by a first drain pattern 414 on the first source-drain metal layer;

[0061] The active layer of the second thin-film transistor 420 is formed by a second active layer pattern 421 on the second active layer, the source of the second thin-film transistor 420 is formed by a second source pattern 422 on the second source-drain metal layer, and the first drain pattern 414 is connected to the second source pattern 422. The gate of the second thin-film transistor 420 is formed by a second gate pattern 423 on the third gate layer, and the drain of the second thin-film transistor 420 is formed by a second drain pattern 424 on the second source-drain metal layer, and the second drain pattern 424 is connected to the first gate line pattern 415 on the first gate layer through a first overlap pattern 425 on the first source-drain metal layer.

[0062] The active layer of the third thin-film transistor 430 is formed by a third active layer pattern 431 on the second active layer. The gate of the third thin-film transistor 430 is formed by a third gate pattern 432 on the third gate layer. The source of the third thin-film transistor 430 is formed by a third source pattern 433 on the second source-drain metal layer, and the third source pattern 433 is connected to the first overlap pattern 425. The drain of the third thin-film transistor 430 is formed by a third drain pattern 434 on the second source-drain metal layer, and the third drain pattern 434 is connected to the second gate line pattern 436 on the second gate layer through a second overlap pattern 435 on the first source-drain metal layer.

[0063] For example, the first signal line 240 is formed by connecting a first trace pattern 241 on the first source / drain metal layer and a second trace pattern 242 on the second source / drain metal layer; the second signal line 250 is formed by connecting a third overlap pattern 251 on the second active layer and a third trace pattern 252 on the second source / drain metal layer, wherein the third overlap pattern 251 overlaps with the second electrode 230 through a via.

[0064] Using the above scheme, at least three thin-film transistor stacks can be designed to achieve the performance of the switching transistor unit 400 while further compressing the space of the pixel area S. Furthermore, by rationally designing and arranging the patterns of each film layer, the patterns on each active layer, each gate layer, and each source / drain metal layer can be formed in a single patterning process, which can save space and simplify the process steps.

[0065] As an exemplary embodiment, such as Figure 1 As shown, the first signal line 240 is formed by connecting the first trace pattern 241 on the first source / drain metal layer and the second trace pattern 242 on the second source / drain metal layer; the second signal line 250 is formed by connecting the third overlap pattern 251 on the second active layer and the third trace pattern 252 on the second source / drain metal layer, wherein the third overlap pattern 251 overlaps with the second electrode 230 through a via. Using the above scheme, the process can be further simplified.

[0066] In addition, in one embodiment, the second active layer is an IGZO active layer, which can realize low-power LTPO (Low Temperature Polycrystalline Oxide) technology.

[0067] It should be noted that the above is only one possible implementation of a stacked switching transistor, and the specific implementation of a stacked switching transistor is not limited to this.

[0068] It should also be noted that in the above embodiments, the light detection substrate can be used as an in-screen fingerprint recognition display substrate, especially as a full-screen fingerprint recognition display substrate. However, the light detection substrate is not limited to this application and can also be other devices that can be used to realize the light detection function.

[0069] Furthermore, this disclosure also provides a display device, including the light detection substrate provided in this disclosure. Obviously, the display device provided in this disclosure can also achieve the beneficial effects of the light detection substrate provided in this disclosure, which will not be elaborated further here.

[0070] Furthermore, this disclosure also provides a method for manufacturing a photodetector substrate, used to manufacture the photodetector substrate provided in this disclosure, the method comprising:

[0071] Step S01: Forming a substrate 100, wherein the substrate 100 includes a first surface and a second surface facing away from each other, the first surface is provided with a concave-convex portion 110, and the concave-convex portion 110 has a predetermined concave-convex depth in a direction perpendicular to the first surface of the substrate 100.

[0072] Step S02: The photoelectric conversion unit 200 is formed on the first surface of the substrate 100, wherein the photoelectric conversion unit 200 includes: a stacked structure that at least partially conformally covers the side of the uneven portion 110 away from the second surface, the stacked structure including at least a first electrode 210, a photosensitive layer 220 and a second electrode 230 sequentially stacked from the side near the substrate 100 to the side away from the substrate 100; a first signal line 240 electrically connected to the first electrode 210; and a second signal line 250 electrically connected to the second electrode 230.

[0073] By adopting the above solution, by providing a concave-convex portion 110 with a predetermined concave-convex depth on the first surface of the substrate 100, and at least partially covering the concave-convex portion 110 with the stacked structure of the photoelectric conversion unit 200 including the first electrode 210, the photosensitive layer 220 and the second electrode 230, the stacked structure can have a projected area on the substrate 100 that is smaller than the actual photosensitive area of ​​the photosensitive layer 220 in the stacked structure. In other words, since the photosensitive layer 220 is covered with the concave-convex portion 110, the photosensitive layer 220 can be arranged at least partially in a direction perpendicular to the substrate 100 (i.e., longitudinally arranged). Compared with the flat design of the photosensitive layer 220 in related technologies, the photosensitive area of ​​the photosensitive layer 220 of the photoelectric conversion unit in the photodetector substrate provided by the present disclosure is larger while occupying the same space of the substrate 100. That is, the photodetector substrate provided by the present disclosure can reduce the space occupied by the photoelectric conversion unit 200 while satisfying its optical detection effect.

[0074] The application scenario of the light detection substrate can be an in-screen fingerprint recognition display substrate. Since the photosensitive layer 220 of the photoelectric conversion unit 200 is arranged vertically, the space occupied by the photoelectric conversion unit 200 is compressed, which is conducive to higher pixel and narrower bezel design.

[0075] In some embodiments, such as Figure 1 As shown, the uneven portion 110 includes at least one ramp portion 111 extending from the first surface in the uneven direction of the uneven portion 110, and the photosensitive layer 220 at least partially conformally covers the area where at least one of the ramp portions 111 is located.

[0076] With the above solution, the concave and convex portion 110 has at least one sloping portion 111. On the one hand, the setting of the sloping portion 111 is more conducive to further increasing the photosensitive area of ​​the photosensitive layer 220 under the same space occupation compared with other methods such as straight sidewalls. On the other hand, it is also more in line with the process precision requirements and easier to form.

[0077] by Figure 1As shown in the example, the concave-convex portion 110 can be any suitable concave-convex structure such as a groove or a recess. The groove or recess can be any suitable shape such as a V-shape or a trapezoid. Of course, it is understood that in practical applications, the specific structure of the concave-convex portion 110 is not limited to this. For example, the concave-convex portion 110 can be a boss or other structure that protrudes from the first surface.

[0078] Furthermore, in some exemplary embodiments, in step S01, the substrate 100 includes multiple layers of films stacked sequentially in the direction from the second surface to the first surface, and the predetermined unevenness depth is at least greater than the thickness of at least two layers of films located in the direction from the second surface to the first surface that are closest to the first surface.

[0079] For example, with Figure 1 As shown in the example, the substrate 100 may include a PI (polyimide) substrate 100, a buffer layer, a planarization layer, etc., stacked sequentially. Figure 1 As shown in the example, the substrate includes n film layers, and the film layers are sequentially arranged as first film layer, second film layer...nth film layer in the direction from the second surface to the first surface. At least the (n-1)th film layer has grooves or recesses, and the nth film layer conformally covers the (n-1)th film layer to form the uneven portion at the corresponding position of the groove or recess. The predetermined uneven depth is the depth of the groove or recess.

[0080] The uneven portion 110 may include grooves or recesses, which can be formed by patterning processes such as etching. It is understood that the specific film structure of the substrate 100 and the specific forming method of the uneven portion 110 are not limited thereto.

[0081] Furthermore, in some exemplary embodiments, the photoelectric conversion unit 200 may be, but is not limited to, a PIN photodiode. The first electrode 210 may be an output electrode, and correspondingly, the first signal line 240 may be an output signal line; the second electrode 230 may be a power supply electrode, and correspondingly, the second signal line 250 may be a power supply signal line; the structure of the photosensitive layer 220 may be an intrinsic semiconductor sandwiched between a P-type semiconductor and an N-type semiconductor.

[0082] For example, the method further includes:

[0083] Step S03: A display unit and a switching transistor unit 400 are formed on the first surface of the substrate 100. The light detection unit further includes intersecting gate lines and data lines, which intersect to define a pixel area S. The orthographic projection of the photoelectric conversion unit 200 on the substrate 100 does not coincide with the pixel area S at least partially. The display unit and the switching transistor unit 400 are at least partially disposed within the pixel area S. The display unit includes a third electrode 300. The switching transistor unit 400 includes at least one switching transistor. The switching transistor includes a gate connected to the gate line, an active layer, a source connected to the data line, and a drain. The gate is electrically connected to the gate line, the source is electrically connected to the third electrode 300, and the drain is electrically connected to the data line. The active layer of at least one switching transistor is disposed on the same layer and with the same material as the first electrode 210.

[0084] In this configuration, at least one of the active layers of the switching transistor is disposed on the same layer and made of the same material as the first electrode 210. With this configuration, the active layer of the switching transistor and the first electrode 210 can be formed in the same patterning process, simplifying the process.

[0085] For example, step S03 above specifically includes:

[0086] A first gate layer, a second gate layer, a first source / drain metal layer, a second source / drain metal layer, a third source / drain metal layer, a first active layer, and a second active layer are formed on the first surface of the substrate 100, wherein...

[0087] The first gate layer is stacked sequentially along the direction from the second surface to the first surface; the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer are stacked sequentially along the direction from the second surface to the first surface; and the first active layer and the second active layer are stacked sequentially along the direction from the second surface to the first surface.

[0088] The active layer of the first thin-film transistor 410 is formed by a first active layer pattern 411 on the first active layer, the gate of the first thin-film transistor 410 is formed by a first gate pattern 412 on the first gate layer, the source of the first thin-film transistor 410 is formed by a first source pattern 413 formed by the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer, and the first source pattern 413 is connected to the third electrode 300 and the first active layer pattern 411 respectively, and the drain of the first thin-film transistor 410 is formed by a first drain pattern 414 on the first source-drain metal layer;

[0089] The active layer of the second thin-film transistor 420 is formed by the second active layer pattern 421 on the second active layer, and the first drain pattern 414 is connected to the second source pattern 422. The gate of the second thin-film transistor 420 is formed by the second gate pattern 423 on the third gate layer. The drain of the second thin-film transistor 420 is formed by the second drain pattern 424 on the second source-drain metal layer, and the second drain pattern 424 is connected to the first gate line pattern 415 on the first gate layer through the first overlap pattern 425 on the first source-drain metal layer.

[0090] The active layer of the third thin-film transistor 430 is formed by a third active layer pattern 431 on the second active layer; the gate of the third thin-film transistor 430 is formed by a third gate pattern 432 on the third gate layer; the source of the third thin-film transistor 430 is formed by a third source pattern 433 on the second source-drain metal layer, and the third source pattern 433 is connected to the first overlap pattern 425; the drain of the third thin-film transistor 430 is formed by a third drain pattern 434 on the second source-drain metal layer, and the third drain pattern 434... 34 is connected to the second gate line pattern 436 on the second gate layer through the second overlap pattern 435 on the first source-drain metal layer, and the first signal line 240 is formed by connecting the first trace pattern 241 on the first source-drain metal layer and the second trace pattern 242 on the second source-drain metal layer to each other; the second signal line 250 is formed by connecting the third overlap pattern 251 on the second active layer and the third trace pattern 252 on the second source-drain metal layer to each other, wherein the third overlap pattern 251 overlaps with the second electrode 230 through a via.

[0091] The above scheme uses a stacked design for the switching transistors, which reduces the space occupied by the display area and allows for a larger area of ​​the photoelectric sensing unit within the same space, thereby improving the optical detection effect. At the same time, the stacked design of the switching transistors reduces the space occupied by the switching transistors, which in turn greatly reduces the area of ​​the pixel area S, making it easier to achieve a higher PPI and a narrow bezel design. Furthermore, by rationally designing and arranging the patterns of each film layer, the patterns on each active layer, each gate layer, and each source / drain metal layer can be formed in a single patterning process, saving space and simplifying the process steps.

[0092] In addition, in one embodiment, the second active layer is an IGZO active layer, which can realize low-power LTPO (Low Temperature Polycrystalline Oxide) technology.

[0093] It should be noted that in the above steps, the formation steps of the active layer, source / drain metal layer, gate layer, first electrode 210 layer, second electrode 230 layer and photosensitive layer 220 can adopt the film formation process and patterning process of the corresponding film layers in conventional display substrates, and will not be described in detail here.

[0094] The following points need to be explained:

[0095] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0096] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0097] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0098] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A photodetector substrate, comprising a substrate and a photoelectric conversion unit; characterized in that, The substrate includes a first surface and a second surface facing away from each other. The first surface is provided with a concave-convex portion. The concave-convex portion has a predetermined concave-convex depth in a direction perpendicular to the first surface of the substrate. The concave-convex portion includes a groove or a hole. The substrate includes n film layers stacked sequentially in a direction from the second surface to the first surface. The film layers are arranged sequentially in a direction from the second surface to the first surface. At least the (n-1)th film layer has a groove or a hole. The nth film layer covers the (n-1)th film layer in a conformal manner to form the concave-convex portion with continuous recesses at the corresponding positions of the groove or hole. The predetermined concave-convex depth is at least greater than the thickness of at least two film layers that are closest to the first surface in the direction from the second surface to the first surface among the n film layers. The photoelectric conversion unit includes: A stacked structure that at least partially conformally covers the side of the protrusion away from the second surface, the stacked structure comprising at least a first electrode, a photosensitive layer and a second electrode sequentially stacked from the side closer to the substrate to the side away from the substrate; The first signal line electrically connected to the first electrode; and The second signal line is electrically connected to the second electrode; wherein, The photosensitive layer is at least partially arranged longitudinally along a direction perpendicular to the substrate, and the projected area of ​​the stacked structure on the substrate is smaller than the actual photosensitive area of ​​the photosensitive layer in the stacked structure.

2. The photodetector substrate according to claim 1, characterized in that, The uneven portion includes at least one ramp extending from the first surface in the uneven direction of the uneven portion, and the photosensitive layer at least partially conformally covers the area where at least one of the ramp portions is located.

3. The photodetector substrate according to claim 1, characterized in that, The photodetector substrate further includes intersecting gate lines and data lines, which intersect to define a pixel area. The orthogonal projection of the photoelectric conversion unit on the substrate does not at least partially coincide with the pixel area. The photodetector substrate also includes a display unit and a switching transistor unit at least partially disposed within the pixel area. The display unit includes a third electrode, and the switching transistor unit includes at least one switching transistor. The switching transistor includes a gate connected to the gate line, an active layer, a source connected to the data line, and a drain. The gate is electrically connected to the gate line, the source is electrically connected to the third electrode, and the drain is electrically connected to the data line. The active layer of at least one switching transistor is disposed on the same layer and of the same material as the first electrode.

4. The photodetector substrate according to claim 3, characterized in that, The switching transistor unit includes at least two switching transistors, and the at least two switching transistors are stacked sequentially on the first surface in at least two layers in the direction from the second surface to the first surface.

5. The photodetector substrate according to claim 4, characterized in that, The at least two switching transistors are at least divided into a first layer of switching transistors and a second layer of switching transistors, wherein the first layer of switching transistors includes at least a first thin-film transistor, and the second layer of switching transistors includes at least a second thin-film transistor and a third thin-film transistor; The film structure of the optical detection substrate includes: A first gate layer, a second gate layer, and a third gate layer are sequentially stacked along a direction from the second surface to the first surface; A first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer are sequentially stacked along a direction from the second surface to the first surface; and A first active layer and a second active layer are sequentially stacked along a direction from the second surface to the first surface; wherein The active layer of the first thin-film transistor is formed by a first active layer pattern on the first active layer, the gate of the first thin-film transistor is formed by a first gate pattern on the first gate layer, the source of the first thin-film transistor is formed by a first source pattern formed by the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer, and the first source pattern is connected to the third electrode and the first active layer pattern respectively, and the drain of the first thin-film transistor is formed by a first drain pattern on the first source-drain metal layer; The active layer of the second thin-film transistor is formed by a second active layer pattern on the second active layer, the source of the second thin-film transistor is formed by a second source pattern on the second source-drain metal layer, and the first drain pattern is connected to the second source pattern. The gate of the second thin-film transistor is formed by a second gate pattern on the third gate layer, and the drain of the second thin-film transistor is formed by a second drain pattern on the second source-drain metal layer, and the second drain pattern is connected to the first gate line pattern on the first gate layer through a first overlap pattern on the first source-drain metal layer. The active layer of the third thin-film transistor is formed by a third active layer pattern on the second active layer. The gate of the third thin-film transistor is formed by a third gate pattern on the third gate layer. The source of the third thin-film transistor is formed by a third source pattern on the second source-drain metal layer, and the third source pattern is connected to the first overlap pattern. The drain of the third thin-film transistor is formed by a third drain pattern on the second source-drain metal layer, and the third drain pattern is connected to the second gate line pattern on the second gate layer through a second overlap pattern on the first source-drain metal layer.

6. The photodetector substrate according to claim 5, characterized in that, The first signal line is formed by connecting a first trace pattern on the first source / drain metal layer and a second trace pattern on the second source / drain metal layer to each other; the second signal line is formed by connecting a third overlap pattern on the second active layer and a third trace pattern on the second source / drain metal layer to each other, wherein the third overlap pattern overlaps with the second electrode through a via.

7. The photodetector substrate according to claim 6, characterized in that, The second active layer is an IGZO active layer.

8. A display device, characterized in that, Includes the photodetector substrate as described in any one of claims 1 to 7.

9. A method for manufacturing a photodetector substrate, characterized in that, The method for manufacturing a photodetector substrate as described in any one of claims 1 to 7 comprises: A substrate is formed, wherein the substrate includes a first surface and a second surface facing away from each other, the first surface is provided with a rough portion, and the rough portion has a predetermined rough depth in a direction perpendicular to the first surface of the substrate; The photoelectric conversion unit is formed on a first surface of the substrate, wherein the photoelectric conversion unit includes: a stacked structure that at least partially conformally covers the side of the uneven portion away from the second surface, the stacked structure including at least a first electrode, a photosensitive layer and a second electrode sequentially stacked from the side near the substrate to the side away from the substrate; a first signal line electrically connected to the first electrode; and a second signal line electrically connected to the second electrode.

10. The method for manufacturing a photodetector substrate according to claim 9, characterized in that, The method further includes: A display unit and a switching transistor unit are formed on the first surface of the substrate. The photodetector substrate further includes intersecting gate lines and data lines, which intersect to define a pixel area. The orthogonal projection of the photoelectric conversion unit on the substrate does not at least partially coincide with the pixel area. The display unit and the switching transistor unit are at least partially disposed within the pixel area. The display unit includes a third electrode. The switching transistor unit includes at least one switching transistor. The switching transistor includes a gate connected to the gate line, an active layer, a source connected to the data line, and a drain. The gate is electrically connected to the gate line, the source is electrically connected to the third electrode, and the drain is electrically connected to the data line. The active layer of at least one switching transistor is disposed on the same layer and of the same material as the first electrode.

11. The method for manufacturing the photodetector substrate according to claim 10, characterized in that, Applied to the photodetector substrate as described in claim 7, wherein forming a display unit and a switching transistor unit on the first surface of the substrate specifically includes: A first gate layer, a second gate layer, a first source / drain metal layer, a second source / drain metal layer, a third source / drain metal layer, a first active layer, and a second active layer are formed on a first surface of the substrate, wherein... The first gate layer is stacked sequentially along the direction from the second surface to the first surface; the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer are stacked sequentially along the direction from the second surface to the first surface; and the first active layer and the second active layer are stacked sequentially along the direction from the second surface to the first surface. The active layer of the first thin-film transistor is formed by a first active layer pattern on the first active layer, the gate of the first thin-film transistor is formed by a first gate pattern on the first gate layer, the source of the first thin-film transistor is formed by a first source pattern formed by the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer, and the first source pattern is connected to the third electrode and the first active layer pattern respectively, and the drain of the first thin-film transistor is formed by a first drain pattern on the first source-drain metal layer; The active layer of the second thin film transistor is formed by a second active layer pattern on the second active layer, and the first drain pattern is connected to the second source pattern. The gate of the second thin film transistor is formed by a second gate pattern on the third gate layer. The drain of the second thin film transistor is formed by a second drain pattern on the second source-drain metal layer, and the second drain pattern is connected to the first gate line pattern on the first gate layer through a first overlap pattern on the first source-drain metal layer. The active layer of the third thin-film transistor is formed by a third active layer pattern on the second active layer. The gate of the third thin-film transistor is formed by a third gate pattern on the third gate layer. The source of the third thin-film transistor is formed by a third source pattern on the second source-drain metal layer, and the third source pattern is connected to the first overlap pattern. The drain of the third thin-film transistor is formed by a third drain pattern on the second source-drain metal layer, and the third drain pattern is connected to the second gate line pattern on the second gate layer through a second overlap pattern on the first source-drain metal layer. The first signal line is formed by connecting the first trace pattern on the first source-drain metal layer and the second trace pattern on the second source-drain metal layer. The second signal line is formed by connecting the third overlap pattern on the second active layer and the third trace pattern on the second source-drain metal layer, wherein the third overlap pattern overlaps with the second electrode through a via.

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