A superjunction VDMOS device for adjusting dynamic characteristics and a preparation method thereof

Abstract

The present invention provides a superjunction VDMOS device for adjusting dynamic characteristics and a manufacturing method thereof. A trench is formed on the top of a column of a first conduction type, and a first gate structure including a first gate dielectric layer and a first sub-gate conductive layer and a second sub-gate conductive layer which are stacked and spaced apart from bottom to top within the first gate dielectric layer is formed in combination with the trench. Then, a source region of the first conduction type, a body region of the second conduction type and a second gate structure are formed. The second sub-gate conductive layer is electrically connected to the source region of the first conduction type, and the first sub-gate conductive layer is electrically connected to the second gate structure, so that Cgd and Cgs can be adjusted; by adjusting the thickness of the gate dielectric layer around the first sub-gate conductive layer and the second sub-gate conductive layer, the magnitudes and ratios of Ciss and Crss can be flexibly adjusted, thereby adjusting the dynamic characteristics of the superjunction VDMOS device, reducing switching current oscillation and alleviating EMI noise while maintaining high switching speed and low switching power consumption.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device manufacturing, and relates to a superjunction VDMOS device for adjusting dynamic characteristics and a preparation method thereof. Background Technique

[0002] In the field of semiconductor power devices, VDMOSFET (Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor) is widely used due to its advantages such as high operating frequency, good thermal stability, and simple drive circuit. Among them, the source-drain breakdown voltage (BVdss) and the on-resistance (Rdson) are two important performance parameters in power devices. For these two performance parameters, the general design requirement is that the power device should not only have a high BVdss, but also have a low Rdson to reduce power consumption.

[0003] In the drift region of a traditional VDMOS device, a superjunction structure is introduced, and a doping region composed of a series of alternately arranged P-type and N-type semiconductor thin layers is used to replace the single lightly doped drift region in the traditional VDMOS device to form a superjunction VDMOS device. In the cut-off state, due to the mutual compensation effect of the depletion region electric fields in the p-type and n-type layers, the doping concentrations of the p-type and n-type layers can be made very high without causing a decrease in the breakdown voltage of the device; when conducting, this high-concentration doping can significantly reduce its on-resistance. Because of this special structure, it can effectively optimize the trade-off relationship between BVdss and Rdson, and has attracted wide attention in the industry due to its advantages such as small on-resistance, fast conduction speed, and low switching loss.

[0004] In a MOSFET device, the gate is insulated by a thin gate dielectric layer, so that the power MOSFET has capacitances between the gate-drain, gate-source, and drain-source, as Figure 1As shown in the figure, the input capacitance (Ciss) is the sum of the gate-source parasitic capacitance (Cgs) and the gate-drain parasitic capacitance (Cgd), that is, Ciss = Cgs + Cgd; the output capacitance (Coss) is the sum of the drain-source parasitic capacitance (Cds) and the gate-drain parasitic capacitance (Cgd), that is, Coss = Cds + Cgd; the feedback capacitance (Crss) is also called the Miller capacitance, and Crss = Cgd. The power MOSFET is a voltage-driven device. The process of its gate drive voltage rising from 0V to the specified voltage can be understood as the process of charging the internal parasitic capacitance. The larger the parasitic capacitance, the more charging charge Qg is required, and the slower the corresponding turn-on speed. At the same time, it will also bring the adverse effect of increased turn-on loss. Similarly, the turn-off speed and turn-off loss during turn-off are also determined by the discharge process of the parasitic capacitance. During the entire switching process, the Miller capacitance Crss and the corresponding gate-drain charge (Qgd) will play a dominant role. Therefore, reducing Cgd can effectively improve the switching speed and reduce the switching loss.

[0005] With the development of semiconductor technology, semiconductor devices are moving towards miniaturization and low cost. By reducing the pitch of the superjunction structure unit, the superjunction VDMOS device can have a smaller chip area and lower cost under the same Rdson. However, the reduction of the device chip area reduces the parasitic capacitance and increases the switching speed. However, since the superjunction VDMOS device uses a lateral electric field, at high voltages, the middle N region is completely depleted and the stored charge is very small. Both Coss and Crss are very small, and Vds (drain-source voltage) starts to drop very fast. When Vds drops to 50V or lower, the depletion layer widths of the N and P regions decrease until they disappear and gradually return to the original highly doped state, which is equivalent to a sudden increase in the stored charge. Therefore, the capacitance will suddenly increase. Especially during the switching process, when the drain voltage is relatively low, the capacitance of the superjunction VDMOS device changes sharply (dV / dt has a mutation), which easily leads to problems such as device oscillation and EMI (Electro Magnetic Interference), and may even cause device failure in severe cases. Therefore, some application solutions with long verification cycles and difficult modification, such as charging piles, will abandon the cost-effective miniaturized superjunction VDMOS devices and choose traditional superjunction VDMOS devices.

[0006] Therefore, it is necessary to provide a superjunction VDMOS device and a preparation method for adjusting dynamic characteristics. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a superjunction VDMOS device and a preparation method for adjusting dynamic characteristics, which are used to solve the problem that the superjunction VDMOS device in the prior art is prone to device oscillation and electromagnetic interference due to sharp capacitance changes.

[0008] To achieve the above and other related objectives, the present invention provides a superjunction VDMOS device for adjusting dynamic characteristics. The superjunction VDMOS device includes:

[0009] A substrate of a first conductivity type;

[0010] An epitaxial layer of a first conductivity type, which is located on the surface of the substrate of the first conductivity type;

[0011] Columns of a second conductivity type, which are distributed at intervals in the epitaxial layer of the first conductivity type to form a superjunction structure by spacing out columns of the first conductivity type between the columns of the second conductivity type, and the tops of the columns of the first conductivity type have grooves;

[0012] A body region of a second conductivity type, which is located in the epitaxial layer of the first conductivity type and on the columns of the second conductivity type;

[0013] A source region of a first conductivity type, which is located in the body region of the second conductivity type;

[0014] A first gate structure, which is located in the groove. The first gate structure includes a first gate dielectric layer covering the bottom and side walls of the groove and a first sub-gate conductive layer and a second sub-gate conductive layer stacked on top of each other in the first gate dielectric layer. The first sub-gate conductive layer and the second sub-gate conductive layer are separated by the first gate dielectric layer, and the second sub-gate conductive layer is electrically connected to the source region of the first conductivity type;

[0015] A second gate structure, which is located on the source region of the first conductivity type, the body region of the second conductivity type, and the first gate structure. The second gate structure includes a second gate dielectric layer and a second gate conductive layer located on the surface of the second gate dielectric layer, and the first sub-gate conductive layer is electrically connected to the second gate structure;

[0016] An interlayer dielectric layer, which coats the second gate structure;

[0017] A front metal layer, which is located on the surfaces of the source region of the first conductivity type and the body region of the second conductivity type;

[0018] A back metal layer, which is located on the surface of the substrate of the first conductivity type away from the epitaxial layer of the first conductivity type.

[0019] Optionally, the cross-sectional morphology of the groove includes a rectangle, a trapezoid, a triangle, or an arc shape.

[0020] Optionally, it further includes a second-conductivity-type contact region located in the second-conductivity-type body region and adjacent to the first-conductivity-type source region.

[0021] Optionally, it further includes a first-conductivity-type buffer layer located between the first-conductivity-type substrate and the first-conductivity-type epitaxial layer, and the doping concentration of the first-conductivity-type buffer layer is between the doping concentrations of the first-conductivity-type substrate and the first-conductivity-type epitaxial layer.

[0022] Optionally, the first conductivity type is n-type and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.

[0023] The present invention also provides a method for manufacturing a superjunction VDMOS device for adjusting dynamic characteristics, including the following steps:

[0024] Provide a first-conductivity-type substrate;

[0025] Form a first-conductivity-type epitaxial layer on the surface of the first-conductivity-type substrate;

[0026] Form second-conductivity-type columns distributed at intervals in the first-conductivity-type epitaxial layer, and space out first-conductivity-type columns between the second-conductivity-type columns to form a superjunction structure;

[0027] Perform ion implantation to form a second-conductivity-type body region located on the second-conductivity-type columns in the first-conductivity-type epitaxial layer;

[0028] Form a trench at the top of the first-conductivity-type column;

[0029] Form a first gate structure located in the trench, the first gate structure includes a first gate dielectric layer covering the bottom and side walls of the trench and a first sub-gate conductive layer and a second sub-gate conductive layer stacked from bottom to top in the first gate dielectric layer, and the first sub-gate conductive layer and the second sub-gate conductive layer are separated by the first gate dielectric layer;

[0030] Form a second gate structure located on the second-conductivity-type body region and the first gate structure, the second gate structure includes a second gate dielectric layer and a second gate conductive layer on the surface of the second gate dielectric layer, and the first sub-gate conductive layer is electrically connected to the second gate structure;

[0031] Form an interlayer dielectric layer covering the second gate structure;

[0032] Ion implantation is performed to form a source region of the first conductivity type in the body region of the second conductivity type. The source region of the first conductivity type extends to the lower surface of the second gate structure, and the second sub-gate conductive layer is electrically connected to the source region of the first conductivity type.

[0033] A front metal layer and a back metal layer are formed. The front metal layer is located on the surfaces of the source region of the first conductivity type and the body region of the second conductivity type, and the back metal layer is located on the surface of the first conductivity type substrate away from the first conductivity type epitaxial layer.

[0034] Optionally, the cross-sectional morphology of the formed trench includes a rectangle, a trapezoid, a triangle, or an arc.

[0035] Optionally, it further includes the step of forming a contact region of the second conductivity type adjacent to the source region of the first conductivity type in the body region of the second conductivity type.

[0036] Optionally, it further includes the step of forming a buffer layer of the first conductivity type between the first conductivity type substrate and the first conductivity type epitaxial layer. The doping concentration of the buffer layer of the first conductivity type is between the doping concentrations of the first conductivity type substrate and the first conductivity type epitaxial layer.

[0037] Optionally, the first conductivity type is n-type and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.

[0038] As described above, in the superjunction VDMOS device and the manufacturing method for adjusting the dynamic characteristics of the present invention, a trench is formed at the top of the column of the first conductivity type in the superjunction VDMOS device. Combining with this trench, a first gate structure is formed in the trench. The first gate structure includes a first gate dielectric layer covering the bottom and sidewalls of the trench and a first sub-gate conductive layer and a second sub-gate conductive layer stacked from bottom to top in the first gate dielectric layer. The first sub-gate conductive layer and the second sub-gate conductive layer are separated by the first gate dielectric layer. Then, a body region of the second conductivity type, a source region of the first conductivity type, and a second gate structure are formed. The second sub-gate conductive layer in the first gate structure is electrically connected to the source region of the first conductivity type, and the first sub-gate conductive layer is electrically connected to the second gate structure, so that Cgd and Cgs can be adjusted; by adjusting the thickness of the gate dielectric layer around the first sub-gate conductive layer and the second sub-gate conductive layer, the magnitudes and ratios of Ciss and Crss can be flexibly adjusted, thereby adjusting the dynamic characteristics of the superjunction VDMOS device. While maintaining a high switching speed and low switching power consumption, the switching current oscillation is reduced and the EMI noise is alleviated. Description of the Drawings

[0039] Figure 1Shown is a capacitance schematic diagram of a MOSFET device in the prior art.

[0040] Figure 2 Shown is a process flow chart for fabricating a superjunction VDMOS device for adjusting dynamic characteristics in an embodiment of the present invention.

[0041] Figures 3 to 8 Shown is a schematic structural diagram presented by each step in the method for fabricating a superjunction VDMOS device in an embodiment of the present invention.

[0042] Figure 9 Shown is a capacitance simulation comparison diagram between the superjunction VDMOS device in an embodiment of the present invention and the existing superjunction VDMOS device.

[0043] Description of Component Labels

[0044] 110 Substrate of the first conductivity type

[0045] 120 Epitaxial layer of the first conductivity type

[0046] 130 Column of the second conductivity type

[0047] 140 Column of the first conductivity type

[0048] 141 Trench

[0049] 150 Body region of the second conductivity type

[0050] 161 First gate structure

[0051] 1611 First gate dielectric layer

[0052] 1612 First sub - gate conductive layer

[0053] 1613 Second sub - gate conductive layer

[0054] 162 Second gate structure

[0055] 1621 Second gate dielectric layer

[0056] 1622 Second gate conductive layer

[0057] 170 Interlayer dielectric layer

[0058] 180 Source region of the first conductivity type

[0059] 190 Contact region of the second conductivity type

[0060] 210 Front - side metal layer

[0061] 220 Back - side metal layer

[0062] Steps S1 to S10 Detailed Implementation Modes

[0063] The following describes the implementation modes of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0065] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. Among them, when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0066] Terms such as "between... and..." may be used herein, which means including the endpoint values, and terms such as "a plurality of" may be used, which means two or more, unless otherwise specifically defined. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0067] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0068] As Figure 8 shown, this embodiment provides a superjunction VDMOS device, and the superjunction VDMOS device includes:

[0069] A substrate 110 of a first conduction type;

[0070] An epitaxial layer 120 of a first conduction type, the epitaxial layer 120 of the first conduction type being located on the surface of the substrate 110 of the first conduction type;

[0071] Columns 130 of a second conduction type, the columns 130 of the second conduction type being distributed at intervals within the epitaxial layer 120 of the first conduction type, so as to form a superjunction structure with columns 140 of the first conduction type spaced between the columns 130 of the second conduction type and formed by alternating arrangement of the columns 140 of the first conduction type and the columns 130 of the second conduction type, and a trench 141 being provided at the top of the columns 140 of the first conduction type;

[0072] A body region 150 of a second conduction type, the body region 150 of the second conduction type being located within the epitaxial layer 120 of the first conduction type and on the columns 130 of the second conduction type;

[0073] A source region 180 of a first conduction type, the source region 180 of the first conduction type being located within the body region 150 of the second conduction type;

[0074] A first gate structure 161, the first gate structure 161 being located within the trench 141, the first gate structure 161 including a first gate dielectric layer 161 which covers the bottom and side walls of the trench 141 and a first sub-gate conductive layer 1612 and a second sub-gate conductive layer 1613 which are stacked from bottom to top within the first gate dielectric layer 1611, the first sub-gate conductive layer 1612 and the second sub-gate conductive layer 1613 being separated by the first gate dielectric layer 1611, and the second sub-gate conductive layer 1613 being electrically connected to the source region 180 of the first conduction type;

[0075] A second gate structure 162, the second gate structure 162 being located on the source region 180 of the first conduction type, the body region 150 of the second conduction type and the first gate structure 161, the second gate structure 162 including a second gate dielectric layer 1621 and a second gate conductive layer 1622 located on the surface of the second gate dielectric layer 1621, and the first sub-gate conductive layer 1612 being electrically connected to the second gate structure 162;

[0076] An interlayer dielectric layer 170, the interlayer dielectric layer 170 covering the second gate structure 162;

[0077] A front metal layer 210, the front metal layer 210 being located on the surfaces of the source region 180 of the first conduction type and the body region 150 of the second conduction type;

[0078] The back metal layer 220 is located on the surface of the first conductivity type substrate 110 away from the first conductivity type epitaxial layer 120.

[0079] In this embodiment, the trench 141 is formed on top of the first conductivity type pillar 140 in the superjunction VDMOS device, and in combination with the trench 141, the first gate structure 161 is formed in the trench 141. The first gate structure 161 includes the first gate dielectric layer 1611 covering the bottom and side walls of the trench 141, and the first sub-gate conductive layer 1612 and the second sub-gate conductive layer 1613 stacked from bottom to top in the first gate dielectric layer 1611. The first sub-gate conductive layer 1612 and the second sub-gate conductive layer 1613 are separated by the first gate dielectric layer 1611, and then the second gate structure 162 is formed on the first conductivity type source region 180, the second conductivity type body region 150, and the first gate structure 161, which can adjust Cgd and Cgs; by adjusting the thickness of the gate dielectric layer around the first sub-gate conductive layer 1612 and the second sub-gate conductive layer 1613, the magnitudes and ratios of Ciss and Crss can be flexibly adjusted, thereby adjusting the dynamic characteristics of the superjunction VDMOS device. While maintaining high switching speed and low switching power consumption, the switching current oscillation is reduced and the EMI noise is alleviated.

[0080] It should be noted that the first conductivity type epitaxial layer 120 in this embodiment is separated into a plurality of first conductivity type pillars 140 by a plurality of the second conductivity type pillars 130. The first conductivity type pillars 140 and the second conductivity type pillars 130 are alternately arranged to form a superjunction structure. Therefore, the first conductivity type pillar 140 is essentially a part of the first conductivity type epitaxial layer 120.

[0081] As an example, the first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is n-type.

[0082] Specifically, an n-type conductivity type (majority carriers are electrons) can be formed by doping group V elements such as nitrogen, phosphorus, and arsenic in a semiconductor substrate such as germanium or silicon, and a p-type conductivity type (majority carriers are holes) can be formed when group III elements such as boron and aluminum are doped. In this embodiment, the first conductivity type is preferably n-type, and the corresponding second conductivity type is p-type, but it is not limited thereto. According to requirements, the first conductivity type can also be p-type, and the corresponding second conductivity type is n-type.

[0083] As an example, the cross-sectional morphology of the trench 141 can include a rectangle, a trapezoid, a triangle, or an arc.

[0084] Specifically, referring to Figure 4 , in this embodiment, the trench 141 with a rectangular cross-sectional morphology is illustrated, but the morphology of the trench 141 is not limited thereto. For example, it may also include trapezoidal, triangular, or arc-shaped, etc., and no excessive limitation is made here.

[0085] As an example, it further includes a second-conductivity-type contact region 190 located in the second-conductivity-type body region 150 and adjacent to the first-conductivity-type source region 180.

[0086] Specifically, in this embodiment, the second-conductivity-type contact region 190 has a second conductivity type, and the doping concentration of the second-conductivity-type contact region 190 is greater than that of the second-conductivity-type body region 150. The contact between the second-conductivity-type contact region 190 and the subsequent front metal electrode 210 can improve the contact characteristics.

[0087] As an example, the superjunction VDMOS device may further include a first-conductivity-type buffer layer (not shown). The first-conductivity-type buffer layer is located between the first-conductivity-type substrate 110 and the first-conductivity-type epitaxial layer 120, and the doping concentration of the first-conductivity-type buffer layer is between the doping concentrations of the first-conductivity-type substrate 110 and the first-conductivity-type epitaxial layer 120. Thereby, it can prevent the impurity atoms of the first-conductivity-type substrate 110 from diffusing into the first-conductivity-type epitaxial layer 120 during the high-temperature process, and avoid the reduction of the breakdown voltage of the device caused by the increase of the doping concentration of the first-conductivity-type epitaxial layer 120.

[0088] As an example, the gate conductive layer is preferably a polysilicon layer. In addition, its work function can be changed by doping to reduce the critical voltage of the device; the gate dielectric layer is preferably silicon dioxide; however, the types of the gate dielectric layer and the gate conductive layer are not limited thereto.

[0089] Specifically, the first gate dielectric layer 1611 in the trench 141 can be silicon dioxide, but it is not limited thereto. Among them, the gate dielectric layers at the bottom and sidewalls of the first sub-gate conductive layer 1612 in the trench 141, the gate dielectric layers at the bottom and sidewalls of the second gate dielectric layer 1613, and the second gate dielectric layer 1621 can adopt the same material. Of course, they can also be different according to needs; the first sub-gate conductive layer 1612, the second gate dielectric layer 1613, and the second gate conductive layer 1622 in the trench 141 can adopt the same material such as a polysilicon layer. Of course, they can also be different according to needs.

[0090] Among them, the interlayer dielectric layer 170 can be, but is not limited to, a silicon nitride layer. The front metal layer 210 and the back metal layer 220 can include an aluminum metal layer, a copper metal layer, etc. The selection of the materials of the respective structural layers of the superjunction VDMOS device can be adaptively changed according to needs, and no excessive limitation is made here.

[0091] As Figure 2 shown, the present invention also provides a method for manufacturing a superjunction VDMOS device for adjusting dynamic characteristics, which can be used to manufacture the above-mentioned superjunction VDMOS device. However, the manufacturing method of the above-mentioned superjunction VDMOS device is not limited thereto. In this embodiment, the above-mentioned superjunction VDMOS device is manufactured by the following manufacturing method. Therefore, the above description of the superjunction VDMOS device will not be repeated here.

[0092] Specifically, the manufacturing method may include the following steps:

[0093] Refer to Figure 3 , first perform step S1 to provide a first-conductivity-type substrate 110.

[0094] Specifically, in this embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. However, it is not limited thereto. In another embodiment, the first conductivity type can also be p-type, and the corresponding second conductivity type is n-type.

[0095] The material, thickness, and doping concentration of the first-conductivity-type substrate 110 can be selected according to needs, and no excessive limitation is made here.

[0096] Next, perform step S2 to form a first-conductivity-type epitaxial layer 120 on the surface of the first-conductivity-type substrate 110.

[0097] The specific material, thickness, and doping concentration of the first-conductivity-type epitaxial layer 120 can be selected according to needs, and no excessive limitation is made here.

[0098] Furthermore, between the first-conductivity-type substrate 110 and the first-conductivity-type epitaxial layer 120, there may also be a step of forming a first-conductivity-type buffer layer (not shown). The doping concentration of the first-conductivity-type buffer layer is between the doping concentrations of the first-conductivity-type substrate 110 and the first-conductivity-type epitaxial layer 120. Thus, it can prevent the impurity atoms of the first-conductivity-type substrate 110 from diffusing into the first-conductivity-type epitaxial layer 120 during the high-temperature process, and avoid the reduction of the breakdown voltage of the device caused by the increase in the doping concentration of the first-conductivity-type epitaxial layer 120.

[0099] Next, step S3 is executed to form second-conductivity-type columns 130 distributed at intervals within the first-conductivity-type epitaxial layer 120, and first-conductivity-type columns 140 are spaced between the second-conductivity-type columns 130 to form a superjunction structure.

[0100] Specifically, the process steps for forming the first-conductivity-type epitaxial layer 120 and the second-conductivity-type columns 130 can refer to the preparation process of existing superjunction VDMOS devices, and no excessive restrictions are imposed here.

[0101] Next, referring to Figure 4 , step S4 is executed for ion implantation to form a second-conductivity-type body region 150 on the second-conductivity-type columns 130 within the first-conductivity-type epitaxial layer 120.

[0102] Next, referring to Figure 5 , step S5 is executed to form a trench 141 on the top of the first-conductivity-type column 140.

[0103] Specifically, the trench 141 with a certain distance from the side of the second-conductivity-type column 130 can be formed on the top of the first-conductivity-type column 140 by means of coating, exposure, and development, so as to provide space for the subsequent preparation of the first gate structure 161 through the trench 141. Among them, the morphology of the trench 141 can be selected as needed, such as including rectangular, trapezoidal, triangular, or arc-shaped, etc.

[0104] Next, referring to Figure 6 , step S6 is executed to form a first gate structure 161. The first gate structure 161 is located within the trench 141 and includes a first gate dielectric layer 1611 covering the bottom and side walls of the trench 141 and a first sub-gate conductive layer 1612 and a second sub-gate conductive layer 1613 stacked from bottom to top within the first gate dielectric layer 1611. The first sub-gate conductive layer 1612 and the second sub-gate conductive layer 1613 are separated by the first gate dielectric layer 1611.

[0105] Next, step S7 is executed to form a second gate structure 162. The second gate structure 162 is located on the second-conductivity-type body region 150 and the first gate structure 161. The second gate structure 162 includes a second gate dielectric layer 1621 and a second gate conductive layer 1622 on the surface of the second gate dielectric layer 1621, and the first sub-gate conductive layer 1612 is electrically connected to the second gate structure 162.

[0106] Specifically, a thermal oxidation growth process can be adopted to grow an oxide layer on the surface of the trench 141 as the first gate dielectric layer 1611. Then, polysilicon can be deposited in the trench 141 to prepare the first sub-gate conductive layer 1612. Subsequently, the oxide layer on the upper surface of the trench 141 can be etched away, and only the oxide layer at the bottom and sidewalls of the first sub-gate conductive layer 1612 is retained to form the first gate structure in the lower part of the trench 141. Then, an oxide layer is formed on the bottom gate structure, and polysilicon is deposited again to prepare the second sub-gate conductive layer 1613. The bottom and sidewalls of the second sub-gate conductive layer 1613 have the oxide layer to form the first gate structure in the upper part of the trench 141. However, the materials and preparation of the first gate dielectric layer 1611 and the first sub-gate conductive layer 1612 are not limited thereto. Then, the second gate dielectric layer 1621 and the second gate conductive layer 1622 on the second gate dielectric layer 1621 are formed.

[0107] Among them, the first gate dielectric layer 1611 in the trench 141 can be silicon dioxide, but it is not limited thereto. The gate dielectric layers at the bottom and sidewalls of the first sub-gate conductive layer 1612 in the trench 141, the gate dielectric layers at the bottom and sidewalls of the second gate dielectric layer 1613, and the second gate dielectric layer 1621 can adopt the same material, and of course, they can also be different according to needs. The first sub-gate conductive layer 1612, the second gate dielectric layer 1613, and the second gate conductive layer 1622 in the trench 141 can adopt the same material such as a polysilicon layer, and of course, they can also be different according to needs. The formed first sub-gate conductive layer 1612 and the second sub-gate conductive layer 1623 are separated by the first gate dielectric layer 1611, and the first gate structure 161 and the second gate structure 162 are separated by the second gate dielectric layer 1621.

[0108] Then, step S8 is executed to form an interlayer dielectric layer 170, and the interlayer dielectric layer 170 covers the second gate structure 162. The material of the interlayer dielectric layer 170 can adopt a silicon nitride layer, etc., and the specific material is not overly restricted here.

[0109] Then, refer to Figure 7 , and execute step S9 to form a first-conductivity-type source region 180 in the second-conductivity-type body region 150, and the first-conductivity-type source region 180 extends to the lower surface of the second gate structure 162.

[0110] Further, it may further include a step of forming a second-conduction-type contact region 190 adjacent to the first-conduction-type source region 180 in the second-conduction-type body region 150, and the doping concentration of the second-conduction-type contact region 190 is greater than that of the second-conduction-type body region 150, so that the second-conduction-type contact region 190 can improve the contact characteristics when contacting with the subsequent front metal electrode 210.

[0111] Next, referring to Figure 8 , step S10 is performed to form a front metal layer 210 and a back metal layer 220. The front metal layer 210 is located on the surfaces of the first-conduction-type source region 180 and the second-conduction-type body region 150. In this embodiment, the front metal layer 210 is located on the surfaces of the first-conduction-type source region 180 and the second-conduction-type contact region 190, and the back metal layer 220 is located on the surface of the first-conduction-type substrate 110 away from the first-conduction-type epitaxial layer 120.

[0112] Referring to Figure 9 schematically shows a capacitance simulation comparison diagram between the superjunction VDMOS device in this embodiment and the existing superjunction VDMOS device. Among them, the A curve represents the existing superjunction VDMOS device, and the B curve represents the superjunction VDMOS device in this embodiment. Since the first sub-gate conductive layer 1612 is electrically connected to the second gate conductive layer 1622, Cgd increases, and the second sub-gate conductive layer 1613 is electrically connected to the first-conduction-type source region 180, Cgs increases. Thus, from Figure 9 it can be known that for the Cgs, Cgd, and Csd simulation comparison: the Cgd and Cgs of the superjunction VDMOS device in this embodiment can be adjusted and increased simultaneously, and Csd decreases slightly; for the BVdss simulation comparison: it basically remains unchanged.

[0113] In summary, for the superjunction VDMOS device and its manufacturing method for adjusting dynamic characteristics according to the present invention, a trench is formed at the top of the first-conductivity-type columns in the superjunction VDMOS device, and in combination with this trench, a first gate structure is formed in the trench. The first gate structure includes a first gate dielectric layer covering the bottom and sidewalls of the trench, and a first sub-gate conductive layer and a second sub-gate conductive layer stacked from bottom to top within the first gate dielectric layer. The first sub-gate conductive layer and the second sub-gate conductive layer are separated by the first gate dielectric layer. Then, a second-conductivity-type body region, a first-conductivity-type source region, and a second gate structure are formed. The second sub-gate conductive layer in the first gate structure is electrically connected to the first-conductivity-type source region, and the first sub-gate conductive layer is electrically connected to the second gate structure, enabling adjustment of Cgd and Cgs. By adjusting the thickness of the gate dielectric layer around the first sub-gate conductive layer and the second sub-gate conductive layer, the magnitudes and ratios of Ciss and Crss can be flexibly adjusted, thereby adjusting the dynamic characteristics of the superjunction VDMOS device. While maintaining a high switching speed and low switching power consumption, the switching current oscillation is reduced and the EMI noise is alleviated.

[0114] The above embodiments merely illustrate the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A super junction VDMOS device for adjusting dynamic characteristics, characterized in that, The superjunction VDMOS device includes: A first conductive type substrate; A first conductive type epitaxial layer, which is located on the surface of the first conductive type substrate; Second conductive type columns, which are distributed at intervals in the first conductive type epitaxial layer to form a first conductive type column between each of the second conductive type columns to form a superjunction structure, and the top of the first conductive type column has a trench; A second conductive type body region, which is located in the first conductive type epitaxial layer and on the second conductive type column; A first conductive type source region, which is located in the second conductive type body region; A first gate structure, which is located in the trench. The first gate structure includes a first gate dielectric layer covering the bottom and side walls of the trench and a first sub-gate conductive layer and a second sub-gate conductive layer stacked from bottom to top in the first gate dielectric layer. The first sub-gate conductive layer and the second sub-gate conductive layer are separated by the first gate dielectric layer, and the second sub-gate conductive layer is electrically connected to the first conductive type source region; A second gate structure, which is located on the first conductive type source region, the second conductive type body region and the first gate structure. The second gate structure includes a second gate dielectric layer and a second gate conductive layer located on the surface of the second gate dielectric layer, and the first sub-gate conductive layer is electrically connected to the second gate structure; An interlayer dielectric layer, which covers the second gate structure; A front metal layer, which is located on the surfaces of the first conductive type source region and the second conductive type body region; A back metal layer, which is located on the surface of the first conductive type substrate away from the first conductive type epitaxial layer.

2. The super junction VDMOS device according to claim 1, characterized in that: The cross-sectional morphology of the trench includes a rectangle, a trapezoid, a triangle or an arc.

3. The superjunction VDMOS device according to claim 1, wherein: It further includes a second conductive type contact region located in the second conductive type body region and adjacent to the first conductive type source region.

4. The super junction VDMOS device according to claim 1, wherein: It further includes a first conductive type buffer layer, which is located between the first conductive type substrate and the first conductive type epitaxial layer, and the doping concentration of the first conductive type buffer layer is between the doping concentrations of the first conductive type substrate and the first conductive type epitaxial layer.

5. The superjunction VDMOS device according to claim 1, characterized in that: The first conductive type is n-type and the second conductive type is p-type; or the first conductive type is p-type and the second conductive type is n-type.

6. A method for fabricating a super junction VDMOS device for adjusting dynamic characteristics, characterized in that It includes the following steps: Providing a first conductive type substrate; Forming a first conductive type epitaxial layer on the surface of the first conductive type substrate; Forming second conductive type columns distributed at intervals in the first conductive type epitaxial layer, and forming a first conductive type column between each of the second conductive type columns to form a superjunction structure; Performing ion implantation to form a second conductive type body region located on the second conductive type column in the first conductive type epitaxial layer; Forming a trench at the top of the first conductive type column; Form a first gate structure, which is located in the trench. The first gate structure includes a first gate dielectric layer covering the bottom and sidewalls of the trench, and a first sub-gate conductive layer and a second sub-gate conductive layer stacked from bottom to top within the first gate dielectric layer. The first sub-gate conductive layer and the second sub-gate conductive layer are separated by the first gate dielectric layer; Form a second gate structure, which is located on the second-conductive-type body region and the first gate structure. The second gate structure includes a second gate dielectric layer and a second gate conductive layer on the surface of the second gate dielectric layer, and the first sub-gate conductive layer is electrically connected to the second gate structure; Form an interlayer dielectric layer, which coats the second gate structure; Perform ion implantation to form a first-conductive-type source region in the second-conductive-type body region. The first-conductive-type source region extends to the lower surface of the second gate structure, and the second sub-gate conductive layer is electrically connected to the first-conductive-type source region; Form a front metal layer and a back metal layer. The front metal layer is located on the surfaces of the first-conductive-type source region and the second-conductive-type body region, and the back metal layer is located on the surface of the first-conductive-type substrate away from the first-conductive-type epitaxial layer.

7. The manufacturing method of the super junction VDMOS device according to claim 6, characterized in that: The cross-sectional morphology of the formed trench includes a rectangle, a trapezoid, a triangle, or an arc.

8. The manufacturing method of the super junction VDMOS device according to claim 6, characterized in that: It further includes the step of forming a second-conductive-type contact region adjacent to the first-conductive-type source region in the second-conductive-type body region.

9. The manufacturing method of the superjunction VDMOS device according to claim 6, characterized in that: It further includes the step of forming a first-conductive-type buffer layer between the first-conductive-type substrate and the first-conductive-type epitaxial layer. The doping concentration of the first-conductive-type buffer layer is between the doping concentrations of the first-conductive-type substrate and the first-conductive-type epitaxial layer.

10. The manufacturing method of the superjunction VDMOS device according to claim 6, characterized in that: The first conductive type is n-type and the second conductive type is p-type; or the first conductive type is p-type and the second conductive type is n-type.

Images