Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes providing a substrate having a first region and a second region, forming a first fin structure on the first region and a second fin structure on the second region, forming a shallow trench isolation around the first fin structure and the second fin structure, forming a mask layer on the first fin structure, and performing a first annealing fabrication process to make a radius of curvature of the first fin structure different from a radius of curvature of the second fin structure.

Description

[0001] The present application is a divisional application of Chinese Patent Application No. 201810010463.4, filed on January 5, 2018, entitled "Semiconductor Device and Fabrication Method Thereof". TECHNICAL FIELD

[0002] The present application relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a fin structure with different radii of curvature using an annealing fabrication process. BACKGROUND

[0003] As the size of field effect transistors (FETs) continues to shrink, the development of existing planar FETs has reached the limit of fabrication processes. In order to overcome the fabrication process limitations, non-planar FETs, such as fin field effect transistors (Fin FETs), have become the mainstream development trend to replace planar transistors. Because the three-dimensional structure of a Fin FET can increase the contact area between the gate and the fin structure, the control of the gate over the carrier channel region can be further increased, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-size devices and suppressing the short channel effect (SCE). Furthermore, because a Fin FET has a wider channel width under the same gate length, it can double the drain drive current. Even the threshold voltage of the transistor can be adjusted by adjusting the work function of the gate.

[0004] However, in the current fabrication process of a Fin FET, there are still many bottlenecks in the formation of the fin structure, which affects the leakage current and overall electrical performance of the device. Therefore, how to improve the existing Fin FET fabrication process is an important issue today. SUMMARY

[0005] To solve the above problems, the present application discloses a method for fabricating a semiconductor device. First, a substrate is provided, which has a first region and a second region. Then, a first fin structure is formed on the first region and a second fin structure is formed on the second region. A shallow trench isolation is formed around the first fin structure and the second fin structure. A mask layer is formed on the first fin structure. A first annealing fabrication process is performed to make the radius of curvature of the first fin structure different from that of the second fin structure.

[0006] The present invention also discloses a semiconductor device, which mainly comprises: a substrate having a first region and a second region; and a first fin structure disposed on the first region and a second fin structure disposed on the second region, wherein the first fin structure and the second fin structure have different radii of curvature. Attached Figure Description

[0007] Figures 1 to 7 This is a schematic diagram of a method for fabricating a semiconductor device according to the present invention.

[0008] Explanation of main component symbols

[0009] 12 Basement 14 Fin-like structure

[0010] 16 First Zone 18 Second Zone

[0011] 20 Insulation layer 22 Shallow trench isolation

[0012] 24 Mask layer 26 First surface

[0013] 28 First annealing process 30 Second annealing process

[0014] 32 Second surface 34 Third surface

[0015] 36 Gate dielectric layer 38 Gate material layer

[0016] R1 First radius of curvature R2 Second radius of curvature

[0017] R3 Third radius of curvature Detailed Implementation

[0018] Please refer to Figures 1 to 7 , Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to the present invention. Figure 1 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. In this embodiment, a first region 16 and a second region 18 are preferably defined on the substrate 12, wherein the first region 16 and the second region 18 are preferably used in subsequent fabrication processes to fabricate components with different electric fields, and then a plurality of fin structures 14 are formed on the substrate 12. In this embodiment, although four fin structures 14 are respectively provided on the first region 16 and the second region 18, the number of fin structures can be arbitrarily adjusted according to product requirements and is not limited thereto.

[0019] According to a preferred embodiment of the present invention, the fin structure 14 is preferably fabricated using techniques such as sidewall image transfer (SIT). The process generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0020] In addition, the formation of the fin structure 14 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure 14. Alternatively, the fin structure 14 may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure 14. These embodiments of forming the fin structure 14 are all within the scope of this invention.

[0021] Then, a shallow trench isolation (STI) is formed around the fin structure 14. In this embodiment, the shallow trench isolation is formed by first using a flowable chemical vapor deposition (FCVD) process to form an insulating layer 20 made of silicon oxide on the substrate 12, completely covering the fin structure 14. Next, a planarization step is performed, for example, by using a chemical mechanical polishing (CMP) process to remove part of the insulating layer 20, so that the remaining insulating layer 20 is flush with the surface of the fin structure 14.

[0022] Subsequently, as Figure 2 As shown, an etching process is then used to remove part of the insulating layer 20, so that the remaining insulating layer 20 is slightly lower than the upper surface of the fin structure 14 of the first region 16 and the second region 18 to form a shallow trench isolation 22.

[0023] Then as Figure 3As shown, a mask layer 24 is first formed over the fin-like structure 14 of the first region 16 and the second region 18. Then, a photolithography and etching process or a pattern transfer process is performed to remove the mask layer 24 of the second region 18. For example, a patterned mask (not shown) can be formed first, such as a patterned photoresist covering the mask layer 24 of the first region 16. Then, using the patterned photoresist as a mask, etching is used to remove the mask layer 24 of the second region 18 that is not covered by the patterned photoresist, thereby forming a patterned mask layer 24 and simultaneously exposing the fin-like structure 14 of the second region 18. The patterned photoresist is then removed. In this embodiment, the mask layer 24 preferably comprises silicon nitride, and the etching process used to remove part of the mask layer 24 can use an etchant such as phosphoric acid, but is not limited to this. It should also be noted that when removing the mask layer 24 of the second region 18 by the aforementioned etching in this embodiment, it is preferable to remove the mask layer 24 without damaging any fin structure 14. Therefore, at this stage, the upper surface of the fin structure 14 of the second region 18 remains a flat surface after the mask layer 24 is removed.

[0024] Then as Figure 4 As shown, a first annealing process 28 is performed to induce silicon migration on the top of the fin structure 14 not covered by the mask layer 24, thereby changing the top profile of the fin structure 14 and simultaneously adjusting the electric field surface of the fin structure. More specifically, since the fin structure 14 in the first region 16 is covered by the mask layer 24 before the annealing process, in this embodiment, during the first annealing process 28, it is preferable to convert the flat surface of the top of the fin structure 14 in the second region 18 into a first curved surface 26 without any flat surface, but the fin structure 14 in the first region 16 remains unchanged. In other words, the top of the fin structure 14 in the second region 18, due to the absence of any mask layer 24 for shielding or protection, preferably changes from a flat surface to a curved top after silicon migration occurs via the first annealing process 28, while the top of the fin structure 14 in the first region 16 remains flat after the first annealing process 28, without any impact or silicon migration. In this embodiment, the temperature of the first annealing process 28 is preferably between 700 degrees Celsius and 850 degrees Celsius, and the pressure is preferably between 5 Torr and 300 Torr, but is not limited thereto.

[0025] Then as Figure 5 As shown, an etching process is performed, or more specifically, the mask layer 24 of the first region 16 is directly removed by etching without forming an additional patterned mask, exposing the underlying fin structure 14. In this embodiment, the etching process used to remove the mask layer 24 may use an etchant such as phosphoric acid, but is not limited thereto.

[0026] It is worth noting that the tops of each fin structure 14 in the first region 16 and the tops of each fin structure 14 in the second region 18 both have a radius of curvature (Rc) at this stage. Preferably, the radius of curvature defined in this embodiment is the distance from any point on the top or top surface of each fin structure 14 to a center of curvature (Cc). Figure 5 Taking the structure as an example, since the top surface of each fin structure 14 in the first region 16 is a flat surface, the radius of curvature of each fin structure 14 in the first region 16 is preferably infinitely large. After being heated by the aforementioned first annealing process 28, each fin structure 14 in the second region 16 is transformed from a flat surface into a first curved surface 26. Therefore, the distance from the top surface of each fin structure 14 to a center of curvature (Cc) can obtain a first radius of curvature R1. At this stage, since the radius of curvature of each fin structure 14 in the first region 16 is infinitely large, the first radius of curvature R1 of each fin structure 14 in the second region 18 is preferably smaller than the radius of curvature of each fin structure 14 in the first region 16.

[0027] Subsequently, as Figure 6 As shown, an optional second annealing process 30 can be performed to change the top contour of the fin structure 14 and adjust the electric field behavior of the fin structure again using high temperature without forming an additional mask. More specifically, since the fin structure 14 of the first region 16 is no longer covered by the mask layer 24 at this stage, it is preferable to change the top contour of the fin structure 14 of both the first region 16 and the second region 18 simultaneously when performing the second annealing process 30. For example, the flat surface of the top of each fin structure 14 in the first region 16 can be converted into a second curved surface 32, and the first curved surface 26 of each fin structure 14 in the second region 18 can be converted into a third curved surface 34, wherein the second curved surface 32 and the third curved surface 34 are both completely curved surfaces and do not contain any flat surfaces.

[0028] From the perspective of the change in radius of curvature, the top surface of each fin structure 14 in the first region 16 is preferably transformed from a flat surface to a second curved surface 32 after the aforementioned second annealing process 30. Therefore, the distance from any point on the top surface or the second curved surface 32 of each fin structure 14 to a center of curvature (Cc) can obtain a second radius of curvature R2. The top surface of each fin structure 14 or the first curved surface 26 in the second region 18 is transformed from the original first radius of curvature R1 to the third radius of curvature R3 of the third curved surface 34 after the aforementioned second annealing process 30. In detail, the third radius of curvature R3 of the third curved surface 34 is preferably smaller than the second radius of curvature R2 and the first radius of curvature R1. The second radius of curvature R2 is not significantly different from the first radius of curvature R1. For example, the second radius of curvature R2 can be slightly smaller or slightly larger than the first radius of curvature R1. These variations are all within the scope of this invention. It should also be noted that this embodiment is based on Figures 5 to 6 The first radius of curvature R1, the second radius of curvature R2, and the third radius of curvature R3 shown are only approximate representations of the size relationship between the radii of curvature, and do not represent the actual lengths of the radii of curvature. Furthermore, as with the aforementioned first annealing process 28, the temperature of the second annealing process 30 can also be between 700 and 850 degrees Celsius, and the pressure is preferably between 5 Torr and 300 Torr, but neither is limited to these limits.

[0029] like Figure 7 As shown, subsequent transistor fabrication processes can be performed according to the manufacturing process requirements. For example, a gate dielectric layer 36 and a gate material layer 38 made of polysilicon can be formed sequentially on the fin structure 14 of the first region 16 and the second region 18. Then, according to the manufacturing process requirements, photolithography and etching processes can be performed on the gate material layer 38 to form the gate structure, and then transistor elements such as spacers and source / drain regions can be formed on both sides of the gate structure. It should be noted that although in this embodiment the gate dielectric layer 36 and the gate material layer 38 are formed on the fin structure 14 after the second annealing process 30, it is not limited to this. The present invention can also be selected to... Figure 5 After removing the mask layer 24, the gate dielectric layer 36 and the gate material layer 38 are directly formed on the fin structure 14 for subsequent transistor fabrication processes. This embodiment is also within the scope of the present invention.

[0030] In summary, this invention primarily involves first forming multiple fin-like structures in a first region and a second region on a substrate, then forming shallow trenches to isolate and surround the fin-like structures, and finally forming a mask layer to cover the fin-like structures in the first region. Next, an annealing process is performed, using high temperatures to induce silicon migration on the top of the fin-like structures not covered by the mask layer. This alters the top contour of the fin-like structures, giving the top surfaces of the fin-like structures in the first and second regions different radii of curvature. Simultaneously, the electric field surface of the fin-like structures is adjusted, allowing the fin-like structures in each region to be suitable for different products.

[0031] The above description is only the preferred embodiment of the present application, and any equivalent changes and modifications made according to the claims of the present application shall be within the scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: providing a substrate having a first region and a second region; forming a first fin structure on the first region and a second fin structure on the second region, wherein the first fin structure and the second fin structure comprise different radii of curvature; and forming a shallow trench isolation around the first fin structure and the second fin structure, wherein a center of curvature of the first fin structure is below an upper surface of the shallow trench isolation, and a center of curvature of the second fin structure is above the upper surface of the shallow trench isolation.

2. The method of claim 1, further comprising: forming an insulating layer around the first fin structure and the second fin structure; and removing portions of the insulating layer to form the shallow trench isolation.

3. The method of claim 1, wherein, The first fin structure and the second fin structure are formed from third and fourth fin structures, respectively, the third and fourth fin structures having upper surfaces comprising a planar surface, the method further comprising, after forming the shallow trench isolation and before forming the first and second fin structures, forming a mask layer on the third fin structure, wherein the mask layer comprises silicon nitride.

4. The method of claim 3, further comprising performing a first anneal process to convert the upper surface of the fourth fin structure to a first curved surface.

5. The method of claim 4, further comprising removing the mask layer after performing the first anneal process.

6. The method of claim 5, further comprising, after removing the mask layer, performing a second anneal process to convert the upper surface of the third fin structure to a second curved surface and to convert the first curved surface to a third curved surface such that the third fin structure is formed as the first fin structure and the fourth fin structure is formed as the second fin structure.

7. The method of claim 6, wherein the third curved surface has a smaller radius of curvature than the second curved surface.

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