A dummy load, a control circuit, and a high-voltage switching power supply

Abstract

This application relates to the field of power supply technology, and specifically discloses a dummy load and a control circuit. The output end of the power supply output feedback circuit and the output end of the dummy load feedback circuit are connected to the regulated output end of the voltage regulation circuit through a second voltage dividing resistor, so that the voltage value obtained by dividing the regulated value through the second voltage dividing resistor is input to the inverting input end of the first operational amplifier, generating a control signal to adjust the state of the power MOS transistor in the dummy load circuit, such that the power of the dummy load circuit is negatively correlated with the output voltage of the switching power supply. Therefore, it is possible to increase the power of the dummy load circuit when the switching power supply is no-load or lightly loaded to solve the problem of unstable power supply output, and reduce the power of the dummy load circuit when the switching power supply is no-load and at high voltage to avoid overheating of the dummy load circuit, that is, without the need for an additional control chip, it not only meets the requirements of high stability of the switching power supply, but also reduces the power consumption of the dummy load. This application also discloses a high-voltage switching power supply with the above beneficial effects.

Description

Technical Field

[0001] The present application relates to the technical field of power supply, and in particular to a dummy load and control circuit, and a high-voltage switching power supply. Background Art

[0002] A dummy load is a component, part or device that replaces a terminal in a circuit (such as an amplifier) ​​or an electrical output port to receive electrical power. It is usually used as an informal load when debugging or testing machine performance.

[0003] Switch Mode Power Supply (SMPS), also known as switching power supply or switching converter, is a high-frequency power conversion device and a type of power supply. Its function is to convert a voltage level into the voltage or current required by the user through different forms of architecture. The input of the switching power supply is mostly AC power (such as mains) or DC power, and the output is mostly equipment that requires DC power, such as personal computers, and the switching power supply performs the voltage and current conversion between the two.

[0004] With the development of high-tech industries, the application occasions of high-voltage switching power supplies are gradually increasing. When the switching power supply is unloaded or lightly loaded, the controller duty cycle is extremely low, resulting in output oscillation of the switching power supply, and this problem is particularly serious in the application of high-voltage switching power supplies. If a control circuit is used to stabilize the power output, the design of the control circuit becomes complicated, so a dummy load needs to be added to the output end of the switching power supply.

[0005] At present, the dummy load circuit configured in the switching power supply mainly uses the output voltage feedback method to control the dummy load. However, when the switching power supply is in the no-load low voltage output mode, the dummy load power is too low and still cannot solve the problem of the switching power supply output oscillation; in the no-load high voltage mode, the dummy load power is too high and the heat is serious.

[0006] To solve this problem, existing solutions are either to use control chips such as digital signal processors (DSP) and ARM (Advanced RISC Machines) to regulate the power of the dummy load, or to increase the number of MOS tubes in the dummy load, but this undoubtedly increases excessive costs and has poor practicality.

[0007] Providing a solution that can solve the output oscillation problem of a switching power supply when it is unloaded or lightly loaded and can reduce the power consumption of a dummy load is a technical problem that needs to be solved by those skilled in the art. Summary of the invention

[0008] The objective of this application is to provide a dummy load, a control circuit, and a high-voltage switching power supply, which can meet the requirements of high stability of the switching power supply and reduce the power consumption of the dummy load.

[0009] To solve the above technical problems, this application provides a dummy load and a control circuit, including: a power output feedback circuit, a dummy load feedback circuit, a voltage stabilizing circuit, a control circuit, and a dummy load circuit;

[0010] Among them, the dummy load circuit includes multiple power MOS transistors. The drain of each power MOS transistor is connected to the output terminal of the switching power supply. The source of each power MOS transistor is grounded through a first voltage-dividing resistor. The switching state of the power MOS transistor is controlled by the output signal of the control circuit;

[0011] The input terminal of the power output feedback circuit is connected to the output sampling point of the switching power supply, and the input terminal of the dummy load feedback circuit is connected to the sampling point of the dummy load circuit;

[0012] The control circuit includes a first operational circuit and a switching circuit built based on a first operational amplifier. The inverting input terminal of the first operational amplifier is connected to the output terminal of the power output feedback circuit, the output terminal of the dummy load feedback circuit is connected to the first end of a second voltage-dividing resistor, the second end of the second voltage-dividing resistor is connected to the regulated output terminal of the voltage stabilizing circuit, the non-inverting input terminal of the first operational amplifier is grounded, the enable terminal of the switching circuit is connected to the output terminal of the first operational amplifier, and the output terminal of the switching circuit is connected to the switching control terminal of the power MOS transistor.

[0013] Optionally, the power output feedback circuit specifically includes a power current sampling circuit and a power voltage sampling circuit.

[0014] Optionally, the power current sampling circuit is specifically a second operational circuit built based on a second operational amplifier, the power voltage sampling circuit is specifically a third operational circuit built based on a third operational amplifier, and the dummy load feedback circuit is specifically a fourth operational circuit built based on a fourth operational amplifier;

[0015] Based on the second operational circuit, the third operational circuit, the fourth operational circuit, and the voltage stabilizing circuit, the output current sampling voltage of the switching power supply, the output voltage sampling voltage of the switching power supply, and the working current sampling voltage of the dummy load circuit satisfy the following formula:

[0016] K i ·U i +K v ·U v +K Fi ·U Fi =U w ;

[0017] Among them, K i is the operation proportional coefficient of the output current sampling voltage, U i is the output current sampling voltage, K v is the operation proportional coefficient of the output voltage sampling voltage, U v is the output voltage sampling voltage, K Fi is the operation proportional coefficient of the working current sampling voltage, U Fi is the working current sampling voltage, U w is the reference voltage signal provided by the voltage stabilizing circuit.

[0018] Optionally, the second operation circuit specifically includes: the second operational amplifier, the first resistor, the second resistor, the third resistor, the fourth resistor, the first capacitor, the second capacitor and the third capacitor;

[0019] Among them, the first end of the first resistor is connected to the current sampling point of the switching power supply, the second end of the first resistor, the first end of the second resistor, and the first end of the first capacitor are connected to the inverting input terminal of the second operational amplifier, the second end of the first capacitor and the first end of the third resistor are connected to the non-inverting input terminal of the second operational amplifier, the positive power supply terminal of the second operational amplifier and the first end of the second capacitor are connected to the positive pole of the DC power supply, the negative power supply terminal of the second operational amplifier and the first end of the third capacitor are connected to the negative pole of the DC power supply, the second end of the third resistor, the second end of the second capacitor, and the second end of the third capacitor are grounded, the second end of the second resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to the first end of the second voltage dividing resistor.

[0020] Optionally, the third operation circuit specifically includes: the third operational amplifier, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor and the fourth capacitor;

[0021] Among them, the first end of the fifth resistor is connected to the voltage sampling point of the switching power supply, the second end of the fifth resistor, the first end of the seventh resistor, and the first end of the fourth capacitor are connected to the inverting input terminal of the third operational amplifier, the second end of the fourth capacitor and the first end of the sixth resistor are connected to the non-inverting input terminal of the third operational amplifier, the second end of the sixth resistor is grounded, the second end of the seventh resistor and the first end of the eighth resistor are connected to the output terminal of the third operational amplifier, and the second end of the eighth resistor is connected to the first end of the second voltage dividing resistor.

[0022] Optionally, the fourth arithmetic circuit specifically includes: the fourth operational amplifier, the ninth resistor, the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, the fifth capacitor, the sixth capacitor, and the seventh capacitor;

[0023] Among them, the second end of the eleventh resistor is connected to the sampling point of the dummy load circuit. The first end of the tenth resistor, the second end of the ninth resistor, the second end of the fifth capacitor, and the first end of the sixth capacitor are connected to the non-inverting input terminal of the fourth operational amplifier. The second end of the sixth capacitor, the first end of the eleventh resistor, the second end of the twelfth resistor, and the second end of the seventh capacitor are connected to the inverting input terminal of the fourth operational amplifier. The second end of the tenth resistor, the first end of the fifth capacitor, and the first end of the ninth resistor are grounded. The first end of the twelfth resistor, the first end of the seventh capacitor, and the second end of the thirteenth resistor are connected to the output terminal of the fourth operational amplifier. The first end of the thirteenth resistor is connected to the first end of the second voltage-dividing resistor.

[0024] Optionally, the first arithmetic circuit specifically includes: the first operational amplifier, the fourteenth resistor, the fifteenth resistor, the sixteenth resistor, the eighth capacitor, the ninth capacitor, and the first diode;

[0025] Among them, the anode of the first diode, the first end of the fifteenth resistor, the first end of the ninth capacitor, and the inverting input terminal of the first operational amplifier are connected to the first end of the second voltage-dividing resistor. The second end of the ninth capacitor and the first end of the fourteenth resistor are connected to the non-inverting input terminal of the first operational amplifier. The second end of the fifteenth resistor is connected to the first end of the eighth capacitor. The cathode of the first diode, the second end of the eighth capacitor, and the first end of the sixteenth resistor are connected to the output terminal of the first operational amplifier. The second end of the fourteenth resistor is grounded.

[0026] Optionally, the switch circuit specifically includes: the seventeenth resistor, the eighteenth resistor, the nineteenth resistor, the second diode, and the first PNP transistor;

[0027] Among them, the first end of the seventeenth resistor and the first end of the eighteenth resistor are connected to the DC power supply. The second end of the eighteenth resistor and the base of the first PNP transistor are connected to the output terminal of the first arithmetic circuit. The second end of the seventeenth resistor is connected to the emitter of the first PNP transistor. The collector of the first PNP transistor, the cathode of the second diode, and the first end of the nineteenth resistor are connected to the switch control terminal of the power MOS transistor. The anode of the second diode and the second end of the nineteenth resistor are grounded.

[0028] Optionally, the dummy load circuit specifically includes: a first power MOS transistor, a second power MOS transistor, a third power MOS transistor, a fourth power MOS transistor, and a fifth power MOS transistor;

[0029] Wherein, the gate of the first power MOS transistor is connected to the output end of the switching circuit, and the source of the first power MOS transistor is connected to the switching control ends of the second power MOS transistor, the third power MOS transistor, the fourth power MOS transistor, and the fifth power MOS transistor.

[0030] Optionally, an operational amplifier circuit is provided between the gate of the second power MOS transistor, the gate of the third power MOS transistor, the gate of the fourth power MOS transistor, and the gate of the fifth power MOS transistor and the source of the first power MOS transistor respectively.

[0031] Optionally, a current sharing resistor is provided between the source of the first power MOS transistor, the source of the second power MOS transistor, the source of the third power MOS transistor, the source of the fourth power MOS transistor, the source of the fifth power MOS transistor and the voltage dividing resistor respectively.

[0032] To solve the above technical problems, the present application further provides a high-voltage switching power supply, including the dummy load and the control circuit described in any one of the above.

[0033] In the dummy load and the control circuit provided by the present application, a power output sampling signal of the power output feedback circuit and a dummy load circuit sampling signal of the dummy load feedback circuit are simultaneously introduced into the control circuit of the dummy load circuit. The output ends of the power output feedback circuit and the dummy load feedback circuit are connected to the regulated output end of the voltage regulating circuit through a second voltage dividing resistor, so that the voltage value obtained by dividing the regulated value through the second voltage dividing resistor is input to the inverting input end of the first operational amplifier, generating a control signal to adjust the state of the power MOS transistor in the dummy load circuit. Therefore, when the output voltage of the switching power supply increases, the power of the dummy load circuit is suppressed from rising; when the output voltage of the switching power supply decreases, the power of the dummy load circuit is increased, thus being able to increase the power of the dummy load circuit when the switching power supply is no-load or lightly loaded to solve the problem of unstable power output, and reducing the power of the dummy load circuit when the switching power supply is no-load and at high voltage to avoid overheating of the dummy load circuit. That is, without the need for an additional control chip, the requirements of high stability of the switching power supply are satisfied and the power consumption of the dummy load is reduced.

[0034] The present application further provides a high-voltage switching power supply, which has the above beneficial effects and will not be elaborated here. Description of the Drawings

[0035] To more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 The structural schematic diagram of a dummy load and a control circuit provided by an embodiment of the present application;

[0037] Figure 2 The circuit diagram of a dummy load and a control circuit provided by an embodiment of the present application. Detailed implementation manners

[0038] The core of the present application is to provide a dummy load, a control circuit, and a high-voltage switching power supply, which meet the requirements of high stability of the switching power supply and reduce the power consumption of the dummy load.

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0040] Embodiment 1

[0041] Figure 1 The structural schematic diagram of a dummy load and a control circuit provided by an embodiment of the present application.

[0042] The power of the dummy load circuit in the prior art is positively correlated with the output voltage of the switching power supply, and it can only act as a temporary load. At this time, the power of the dummy load circuit is relatively low when the switching power supply is no-load or lightly loaded, resulting in output oscillation of the switching power supply. In the no-load high-voltage mode of the switching power supply, the power of the dummy load circuit is too high, resulting in serious heating of the dummy load circuit, generating a large amount of power consumption and causing energy waste.

[0043] To address this issue, the embodiments of this application consider adding a sampling circuit and a control circuit 104, and design the control idea of the control circuit 104 such that the power of the dummy load circuit 105 is negatively correlated with the output voltage of the switching power supply. Based on this concept, and considering that using a control chip would result in too high costs, a first operational amplifier U1A is used to generate a control signal according to the output result of the sampling circuit, and the output of the switching circuit serves as the control signal for the power MOS transistor in the dummy load circuit 105 to automatically adjust the power of the dummy load circuit 105. In order to achieve the control effect that the power of the dummy load circuit 105 is negatively correlated with the output voltage of the switching power supply, it is designed that the connection point of each sampling circuit and the inverting input terminal of the first operational amplifier U1A in the control circuit 104 is connected to the regulated output terminal of the voltage regulation circuit 103. Combining the operational properties of the first operational amplifier U1A and the regulated value of the regulated output terminal, the control purpose that the power of the dummy load circuit 105 is negatively correlated with the output voltage of the switching power supply is achieved.

[0044] Then, as Figure 1 shown, the dummy load and control circuit 104 provided by the embodiments of this application may specifically include: a power output feedback circuit 101, a dummy load feedback circuit 102, a voltage regulation circuit 103, a control circuit 104, and a dummy load circuit 105;

[0045] Among them, the dummy load circuit 105 includes multiple power MOS transistors. The drain of each power MOS transistor is connected to the output terminal of the switching power supply, the source of each power MOS transistor is grounded through a first voltage-dividing resistor, and the power MOS transistor is controlled by the output signal of the control circuit 104 to switch states;

[0046] The input terminal of the power output feedback circuit 101 is connected to the output sampling point of the switching power supply, and the input terminal of the dummy load feedback circuit 102 is connected to the sampling point of the dummy load circuit 105;

[0047] The control circuit 104 includes a first operational circuit and a switching circuit built based on the first operational amplifier U1A. The inverting input terminal of the first operational amplifier U1A is connected to the output terminal of the power output feedback circuit 101, the output terminal of the dummy load feedback circuit 102 is connected to the first end of the second voltage-dividing resistor, the second end of the second voltage-dividing resistor is connected to the regulated output terminal of the voltage regulation circuit 103, the non-inverting input terminal of the first operational amplifier U1A is grounded, the enable terminal of the switching circuit is connected to the output terminal of the first operational amplifier U1A, and the output terminal of the switching circuit is connected to the switching control terminal of the power MOS transistor.

[0048] In a specific implementation, the dummy load circuit 105 includes multiple power MOS transistors, and the gates of these power MOS transistors can all be directly connected to the output terminal of the switching circuit. A hierarchical relationship can also be set among multiple power MOS transistors. The gate of the previous-stage power MOS transistor is connected to the output terminal of the switching circuit, and the gate of the subsequent-stage power MOS transistor is controlled by the previous-stage power MOS transistor.

[0049] The source electrode of each power MOS transistor is grounded through a first voltage-dividing resistor. Specifically, the source electrodes of all power MOS transistors can be connected and then grounded through the same first voltage-dividing resistor. The sampling point of the dummy load circuit 105 can be set at the first voltage-dividing resistor, that is, the voltages at both ends of the voltage-dividing resistor are collected to feedback the state of the dummy load circuit 105.

[0050] The power supply output feedback circuit 101 is used to collect the output signal of the switching power supply, specifically, it can be a voltage signal and / or a current signal.

[0051] The control circuit 104 includes a first operation circuit and a switching circuit. Among them, the first operation circuit is built based on the first operational amplifier U1A, and the inverting input terminal of the first operational amplifier U1A is connected to the output terminal of the power supply output feedback circuit 101, the output terminal of the dummy load feedback circuit 102, and the first end of the second voltage-dividing resistor. The second end of the second voltage-dividing resistor is connected to the regulated output terminal of the voltage regulation circuit 103. Based on this, an equation between the output signal of the switching power supply, the feedback signal of the dummy load circuit 105 after being combined, and the regulated value output by the voltage regulation circuit 103 can be obtained. The reference voltage signal output by the regulated output terminal of the voltage regulation circuit 103 is fixed and acts on the inverting input terminal of the first operational amplifier U1A, while the non-inverting input terminal of the first operational amplifier U1A is grounded. The first operational amplifier U1A outputs an enable signal to the switching circuit to obtain a control signal for the dummy load circuit 105, so that the output signal of the switching power supply and the feedback signal of the dummy load circuit 105 are negatively correlated.

[0052] It can be seen that in addition to the function of the dummy load circuit 105 as a temporary load, the dummy load and control circuit provided by the embodiment of the present application can also automatically adjust the power of the dummy load according to the output situation of the switching power supply, so that the power of the dummy load is negatively correlated with the output voltage of the switching power supply, and it solves the problems of unstable power supply output during light load and no load, and overheating of the dummy load during no load and high voltage output. Moreover, there is no need to additionally set a control chip for adjustment, nor to set a large number of power MOS transistors in the dummy load circuit 105, which saves costs.

[0053] Embodiment Two

[0054] Figure 2 It is a circuit diagram of a dummy load and control circuit provided by an embodiment of the present application.

[0055] Based on the above embodiments, the embodiments of the present application will be described by taking the power output feedback circuit 101 as an example, which specifically includes a power current sampling circuit and a power voltage sampling circuit.

[0056] Since the output voltage of a switching power supply, especially a high-voltage switching power supply, is large while the output current is small, in order to include the power current sampling signal, the power voltage sampling signal, and the dummy load feedback signal in the same control relationship for calculation, in the dummy load and control circuit 104 provided by the embodiments of the present application, the power current sampling circuit is specifically a second operational circuit built based on the second operational amplifier U1B, the power voltage sampling circuit is specifically a third operational circuit built based on the third operational amplifier U1C, and the dummy load feedback circuit 102 is specifically a fourth operational circuit built based on the fourth operational amplifier U1D;

[0057] Based on the second operational circuit, the third operational circuit, the fourth operational circuit, and the voltage stabilizing circuit 103, the output current sampling voltage of the switching power supply, the output voltage sampling voltage of the switching power supply, and the working current sampling voltage of the dummy load circuit 105 satisfy the following formula:

[0058] K i ·U i +K v ·U v +K Fi ·U Fi =U w ;

[0059] Wherein, K i is the operation proportional coefficient of the output current sampling voltage, U i is the output current sampling voltage, K v is the operation proportional coefficient of the output voltage sampling voltage, U v is the output voltage sampling voltage, K Fi is the operation proportional coefficient of the working current sampling voltage, U Fi is the working current sampling voltage, U w is the reference voltage signal provided by the voltage stabilizing circuit 103.

[0060] For example Figure 2As shown in the figure, the voltage stabilizing circuit 103 may include a voltage stabilizing diode Q1, a twenty-ninth resistor (i.e., the second voltage dividing resistor), and a thirtieth resistor. Among them, the anode of the voltage stabilizing diode Q1 is grounded, and the cathode of the voltage stabilizing diode Q1, the voltage stabilizing output terminal of the voltage stabilizing diode Q1, the second terminal of the twenty-ninth resistor, and the first terminal of the thirtieth resistor are connected. The second terminal of the thirtieth resistor is connected to the DC power supply (+12V), and the first terminal of the twenty-ninth resistor is connected to the output terminal of the power supply output feedback circuit 101, the output terminal of the dummy load feedback circuit 102, and the inverting input terminal of the first operational amplifier U1A. By setting the parameters of the voltage stabilizing diode Q1 and the thirtieth resistor, the reference voltage signal provided by the voltage stabilizing circuit 103 (i.e., the voltage at the cathode of the voltage stabilizing diode Q1) can be made 2.5V (i.e., U w = 2.5V). The voltage stabilizing diode Q1 can adopt TL431.

[0061] When the switching power supply outputs no load, that is, the output current sampling voltage U i = 0, the dummy load current decreases as the output voltage of the switching power supply increases, that is, the working current sampling voltage U Fi will decrease as the output current sampling voltage U v increases. Then, when the switching power supply outputs low voltage with no load, a relatively large current is maintained in the dummy load circuit 105, that is, the power of the dummy load circuit 105 is elevated to maintain the stable operation of the switching power supply. When the switching power supply outputs high voltage with no load, the current in the dummy load circuit 105 can be reduced, and the power consumption of the dummy load can be reduced, thereby avoiding the overheating of the dummy load circuit 105 in the no-load high-voltage state, and the number of required power MOS transistors can be reduced, saving costs.

[0062] When the switching power supply outputs with load, that is, the output current sampling voltage U i > 0, the dummy load current gradually decreases as the output voltage of the switching power supply increases until it decreases to 0.

[0063] Then, during the entire working process of the switching power supply, the dummy load current will change dynamically with the output voltage and output current of the switching power supply, ensuring that the power consumed on the dummy load is always maintained within a certain range, so that the dummy load can not only maintain the stable operation of the power supply but also minimize the overall loss to the greatest extent.

[0064] Furthermore, as Figure 2 shown in the figure, the second operation circuit may specifically include: a second operational amplifier U1B, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, and a third capacitor C3;

[0065] Among them, the first end of the first resistor R1 is connected to the current sampling point of the switching power supply, the second end of the first resistor R1, the first end of the second resistor R2, and the first end of the first capacitor C1 are connected to the inverting input terminal of the second operational amplifier U1B. The second end of the first capacitor C1 and the first end of the third resistor R3 are connected to the non-inverting input terminal of the second operational amplifier U1B. The positive power supply terminal of the second operational amplifier U1B and the first end of the second capacitor C2 are connected to the positive pole of the DC power supply (+12V). The negative power supply terminal of the second operational amplifier U1B and the first end of the third capacitor C3 are connected to the negative pole of the DC power supply (-12V). The second end of the third resistor R3, the second end of the second capacitor C2, and the second end of the third capacitor C3 are grounded. The second end of the second resistor R2 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the first end of the second voltage-dividing resistor.

[0066] The second operational circuit is used to feedback the output current of the switching power supply collected to the control circuit 104.

[0067] The third operational circuit may specifically include: a third operational amplifier U1C, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a fourth capacitor C4;

[0068] Among them, the first end of the fifth resistor R5 is connected to the voltage sampling point of the switching power supply, the second end of the fifth resistor R5, the first end of the seventh resistor R7, and the first end of the fourth capacitor C4 are connected to the inverting input terminal of the third operational amplifier U1C. The second end of the fourth capacitor C4 and the first end of the sixth resistor R6 are connected to the non-inverting input terminal of the third operational amplifier U1C. The second end of the sixth resistor R6 is grounded. The second end of the seventh resistor R7 and the first end of the eighth resistor R8 are connected to the output terminal of the third operational amplifier U1C. The second end of the eighth resistor R8 is connected to the first end of the second voltage-dividing resistor.

[0069] The third operational circuit is used to feedback the output voltage of the switching power supply collected to the control circuit 104.

[0070] The fourth operational circuit may specifically include: a fourth operational amplifier U1D, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor C7;

[0071] Among them, the second end of the eleventh resistor R11 is connected to the sampling point of the dummy load circuit 105. The first end of the tenth resistor R10, the second end of the ninth resistor R9, the second end of the fifth capacitor C5, and the first end of the sixth capacitor C6 are connected to the non-inverting input terminal of the fourth operational amplifier U1D. The second end of the sixth capacitor C6, the first end of the eleventh resistor R11, the second end of the twelfth resistor R12, and the second end of the seventh capacitor C7 are connected to the inverting input terminal of the fourth operational amplifier U1D. The second end of the tenth resistor R10, the first end of the fifth capacitor C5, and the first end of the ninth resistor R9 are grounded. The first end of the twelfth resistor R12, the first end of the seventh capacitor C7, and the second end of the thirteenth resistor R13 are connected to the output terminal of the fourth operational amplifier U1D. The first end of the thirteenth resistor R13 is connected to the first end of the second voltage-dividing resistor.

[0072] The fourth operational circuit is used to feedback the sampled working current voltage of the dummy load circuit 105 to the control circuit 104.

[0073] On this basis, as Figure 2 shown, in the control circuit 104 provided in the embodiment of the present application, the first operational circuit may specifically include: a first operational amplifier U1A, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, an eighth capacitor C8, a ninth capacitor C9, and a first diode D1;

[0074] Among them, the anode of the first diode D1, the first end of the fifteenth resistor R15, the first end of the ninth capacitor C9, and the inverting input terminal of the first operational amplifier U1A are connected to the first end of the second voltage-dividing resistor. The second end of the ninth capacitor C9 and the first end of the fourteenth resistor R14 are connected to the non-inverting input terminal of the first operational amplifier U1A. The second end of the fifteenth resistor R15 is connected to the first end of the eighth capacitor C8. The cathode of the first diode D1, the second end of the eighth capacitor C8, and the first end of the sixteenth resistor R16 are connected to the output terminal of the first operational amplifier U1A. The second end of the fourteenth resistor R14 is grounded.

[0075] The switch circuit may specifically include: a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a second diode D2, and a first PNP transistor Q2;

[0076] Among them, the first end of the seventeenth resistor R17 and the first end of the eighteenth resistor R18 are connected to a DC power supply (+12V). The second end of the eighteenth resistor R18, the base of the first PNP transistor Q2 are connected to the output end of the first operational circuit. The second end of the seventeenth resistor R17 is connected to the emitter of the first PNP transistor Q2. The collector of the first PNP transistor Q2, the cathode of the second diode D2, and the first end of the nineteenth resistor R19 are connected to the switching control end of the power MOS transistor. The anode of the second diode D2 and the second end of the nineteenth resistor R19 are grounded.

[0077] During operation, the sampled voltage of the output current of the switching power supply, the sampled voltage of the output voltage of the switching power supply, and the sampled voltage of the operating current of the dummy load circuit 105 are input to the input end of the control circuit 104. They are processed by operation together with the reference voltage signal provided by the voltage stabilizing circuit 103 through the first operational amplifier U1A. The signal output by the first operational amplifier U1A controls the conduction state of the first PNP transistor Q2, and adjusts the control signal voltage of the dummy load circuit 105. This control signal voltage determines the current of the power MOS transistor in the dummy load circuit 105, thereby controlling the overall output power of the dummy load circuit 105.

[0078] Embodiment 3

[0079] As mentioned in the above embodiment, in the dummy load circuit 105, the gates of the power MOS transistors can all be directly connected to the output end of the switching circuit, or a hierarchical relationship can be set among multiple power MOS transistors. The gate of the front-stage power MOS transistor is connected to the output end of the switching circuit, and the gate of the rear-stage power MOS transistor is controlled by the front-stage power MOS transistor.

[0080] In the dummy load and control circuit provided by the embodiment of the present application, the first power MOS transistor Q3 is used as the front-stage power MOS transistor in the dummy load circuit 105, and the remaining power MOS transistors are controlled by the first power MOS transistor Q3. Then, as Figure 2 shown, the dummy load circuit 105 may specifically include: a first power MOS transistor Q3, a second power MOS transistor Q4, a third power MOS transistor Q5, a fourth power MOS transistor Q6, and a fifth power MOS transistor Q7;

[0081] Among them, the gate of the first power MOS transistor Q3 is connected to the output end of the switching circuit. The source of the first power MOS transistor Q3 is connected to the switching control ends of the second power MOS transistor Q4, the third power MOS transistor Q5, the fourth power MOS transistor Q6, and the fifth power MOS transistor Q7.

[0082] In addition, the dummy load circuit 105 may further include a third diode D3. The anode of the third diode D3 is connected to the output terminal of the switching power supply, and the cathode of the third diode D3 is connected to the drain of the first power MOS transistor Q3, for preventing current backflow.

[0083] Furthermore, an operational amplifier circuit is provided between the gate of the second power MOS transistor Q4, the gate of the third power MOS transistor Q5, the gate of the fourth power MOS transistor Q6, and the gate of the fifth power MOS transistor Q7 respectively and the source of the first power MOS transistor Q3.

[0084] As Figure 2 shown, the first voltage-dividing resistor may specifically include a resistor R31 and a resistor R32. That is, the sampling point of the dummy load circuit 105 may be set to collect the voltage across the first voltage-dividing resistor. The working current sampling voltage U of the dummy load circuit 105 is collected at the first end of the resistor R31 Fi .

[0085] As Figure 2 shown, a fifth operational amplifier circuit is provided at the front end of the gate of the second power MOS transistor Q4, specifically including a fifth operational amplifier U2B and a twentieth resistor R20; a sixth operational amplifier circuit is provided at the front end of the gate of the third power MOS transistor Q5, specifically including a sixth operational amplifier U3B and a twenty-first resistor R21; a seventh operational amplifier circuit is provided at the front end of the gate of the fourth power MOS transistor Q6, specifically including a seventh operational amplifier U2A and a twenty-second resistor R22; an eighth operational amplifier circuit is provided at the front end of the gate of the fifth power MOS transistor Q7, specifically including an eighth operational amplifier U3A and a twenty-third resistor R23;

[0086] Among them, the drains of the first power MOS transistor Q3, the second power MOS transistor Q4, the third power MOS transistor Q5, the fourth power MOS transistor Q6, and the fifth power MOS transistor are all connected to the cathode of the third diode. The non-inverting input terminals of the fifth operational amplifier U2B, the sixth operational amplifier U3B, the seventh operational amplifier U2A, and the eighth operational amplifier U3A are all connected to the source of the first power MOS transistor Q3. The inverting input terminal of the fifth operational amplifier U2B is connected to the source of the second power MOS transistor Q4. The inverting input terminal of the sixth operational amplifier U3B is connected to the source of the third power MOS transistor Q5. The inverting input terminal of the seventh operational amplifier U2A is connected to the source of the fourth power MOS transistor Q6. The inverting input terminal of the eighth operational amplifier U3A is connected to the source of the fifth power MOS transistor Q7. The output terminal of the fifth operational amplifier U2B is connected to the first end of the twentieth resistor R20. The second end of the twentieth resistor R20 is connected to the gate of the second power MOS transistor Q4. The output terminal of the sixth operational amplifier U3B is connected to the first end of the twenty-first resistor R21. The second end of the twenty-first resistor R21 is connected to the gate of the third power MOS transistor Q5. The positive power supply terminal of the seventh operational amplifier U2A is connected to the first end of the tenth capacitor C10 to a DC power supply (+12V). The negative power supply terminal of the seventh operational amplifier U2A is grounded at the second end of the tenth capacitor C10. The output terminal of the seventh operational amplifier U2A is connected to the first end of the twenty-second resistor R22. The second end of the twenty-second resistor R22 is connected to the gate of the fourth power MOS transistor Q6. The positive power supply terminal of the eighth operational amplifier U3A is connected to the first end of the eleventh capacitor C11 to a DC power supply (+12V). The negative power supply terminal of the eighth operational amplifier U3A is grounded at the second end of the eleventh capacitor C11. The output terminal of the eighth operational amplifier U3A is connected to the first end of the twenty-third resistor R23. The second end of the twenty-third resistor R23 is connected to the gate of the fifth power MOS transistor Q7.

[0087] Based on the dummy load circuit 105 provided by the embodiment of the present application, the first power MOS transistor Q3 receives the regulation of the control voltage signal output by the pre-stage control circuit 104, and then controls the working states of the second power MOS transistor Q4, the third power MOS transistor Q5, the fourth power MOS transistor Q6, and the fifth power MOS transistor Q7, regulates the current in the dummy load circuit 105, and further regulates the parameters in the dummy load circuit 105, providing a dummy load power consumption negatively correlated with the output voltage of the switching power supply.

[0088] Embodiment 4

[0089] Based on the above embodiments, to ensure that the power consumption of each power MOS transistor is basically the same, in the dummy load and control circuit provided in the embodiments of the present application, the dummy load circuit 105 further includes current sharing resistors respectively provided between the source electrodes of the first power MOS transistor Q3, the second power MOS transistor Q4, the third power MOS transistor Q5, the fourth power MOS transistor Q6, and the fifth power MOS transistor Q7 and the voltage dividing resistors.

[0090] As Figure 2 shown, between the source electrode of the first power MOS transistor Q3 and the first voltage dividing resistor, a first current sharing resistor R24 is provided; between the second power MOS transistor Q4 and the first voltage dividing resistor, a second current sharing resistor R25 is provided; between the third power MOS transistor Q5 and the first voltage dividing resistor, a third current sharing resistor R26 is provided; between the fourth power MOS transistor Q6 and the first voltage dividing resistor, a fifth current sharing resistor R27 is provided; between the fifth power MOS transistor Q7 and the first voltage dividing resistor, a sixth current sharing resistor R28 is provided.

[0091] Through each current sharing resistor, good current sharing performance of each power MOS transistor on the dummy load circuit 105 can be ensured.

[0092] It can be seen that in the dummy load and control circuit provided in the embodiments of the present application, the dummy load circuit 105 has a simple structure, accurate feedback signals, and can ensure good current sharing performance of each power MOS transistor on the dummy load circuit 105.

[0093] Embodiment Five

[0094] The above details each embodiment corresponding to the dummy load and control circuit method. On this basis, the present application also discloses a high-voltage switching power supply corresponding to the above dummy load and control circuit.

[0095] It should be noted that the dummy load and control circuit provided in the above embodiments of the present application can be applied to different types of switching power supplies, and can achieve the effects of solving the problems of unstable power supply output under light load and no load and overheating of the dummy load under no load high-voltage output without the need to additionally set a control chip for adjustment and without the need to set a large number of power MOS transistors in the dummy load circuit. However, the regulation effect on the high-voltage switching power supply is significantly better than that of the dummy load circuit in the prior art.

[0096] Then, the high-voltage switching power supply provided in the embodiments of the present application may include the dummy load and control circuit provided in any one of the above embodiments.

[0097] Since the embodiments of the high-voltage switching power supply part correspond to the embodiments of the dummy load and control circuit part, for the embodiments of the high-voltage switching power supply part, please refer to the description of the embodiments of the dummy load and control circuit part, and will not be elaborated here for the time being.

[0098] The above has provided a detailed introduction to a dummy load, a control circuit, and a high-voltage switching power supply according to the present application. Each embodiment in the specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the high-voltage switching power supply disclosed in the embodiments, since it corresponds to the dummy load and the control circuit disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description of the dummy load and the control circuit part. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0099] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

Claims

1. A dummy load and a control circuit, characterized in that, Comprising: A power output feedback circuit, a dummy load feedback circuit, a voltage stabilizing circuit, a control circuit, and a dummy load circuit; Wherein, the dummy load circuit includes a plurality of power MOS transistors, the drain of each power MOS transistor is connected to the output terminal of the switching power supply, the source of each power MOS transistor is grounded through a first voltage dividing resistor, and the switching state of the power MOS transistor is controlled by the output signal of the control circuit; The input terminal of the power output feedback circuit is connected to the output sampling point of the switching power supply, and the input terminal of the dummy load feedback circuit is connected to the sampling point of the dummy load circuit; The control circuit includes a first operational circuit and a switching circuit built based on a first operational amplifier. The inverting input terminal of the first operational amplifier is connected to the output terminal of the power output feedback circuit, the output terminal of the dummy load feedback circuit is connected to the first end of a second voltage dividing resistor, the second end of the second voltage dividing resistor is connected to the voltage stabilizing output terminal of the voltage stabilizing circuit, the non-inverting input terminal of the first operational amplifier is grounded, the enabling terminal of the switching circuit is connected to the output terminal of the first operational amplifier, and the output terminal of the switching circuit is connected to the switching control terminal of the power MOS transistor.

2. The dummy load and control circuit according to claim 1, characterized in that, The power output feedback circuit specifically includes a power current sampling circuit and a power voltage sampling circuit.

3. The dummy load and control circuit according to claim 2, wherein The power current sampling circuit is specifically a second operational circuit built based on a second operational amplifier, the power voltage sampling circuit is specifically a third operational circuit built based on a third operational amplifier, and the dummy load feedback circuit is specifically a fourth operational circuit built based on a fourth operational amplifier; Based on the second operational circuit, the third operational circuit, the fourth operational circuit, and the voltage stabilizing circuit, the output current sampling voltage of the switching power supply, the output voltage sampling voltage of the switching power supply, and the working current sampling voltage of the dummy load circuit satisfy the following formula: K i ·U i +K v ·U v +K Fi ·U Fi =U w ; Among them, K i is the operational proportionality coefficient of the output current sampling voltage, U i is the output current sampling voltage, K v is the operational proportionality coefficient of the output voltage sampling voltage, U v is the output voltage sampling voltage, K Fi is the operational proportionality coefficient of the working current sampling voltage, U Fi is the working current sampling voltage, U w is the reference voltage signal provided by the voltage stabilizing circuit.

4. The dummy load and control circuit according to claim 3, wherein The second operational circuit specifically includes: the second operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, and a third capacitor; Wherein, the first end of the first resistor is connected to the current sampling point of the switching power supply, the second end of the first resistor, the first end of the second resistor, and the first end of the first capacitor are connected to the inverting input terminal of the second operational amplifier, the second end of the first capacitor and the first end of the third resistor are connected to the non-inverting input terminal of the second operational amplifier, the positive power supply terminal of the second operational amplifier and the first end of the second capacitor are connected to the positive pole of the DC power supply, the negative power supply terminal of the second operational amplifier and the first end of the third capacitor are connected to the negative pole of the DC power supply, the second end of the third resistor, the second end of the second capacitor, and the second end of the third capacitor are grounded, the second end of the second resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to the first end of the second voltage dividing resistor.

5. The dummy load and control circuit according to claim 3, characterized in that, The third operational circuit specifically includes: the third operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a fourth capacitor; Among them, the first end of the fifth resistor is connected to the voltage sampling point of the switching power supply. The second end of the fifth resistor, the first end of the seventh resistor, and the first end of the fourth capacitor are connected to the inverting input terminal of the third operational amplifier. The second end of the fourth capacitor and the first end of the sixth resistor are connected to the non-inverting input terminal of the third operational amplifier. The second end of the sixth resistor is grounded. The second end of the seventh resistor and the first end of the eighth resistor are connected to the output terminal of the third operational amplifier. The second end of the eighth resistor is connected to the first end of the second voltage-dividing resistor.

6. The dummy load and control circuit according to claim 3, characterized in that, The fourth operational circuit specifically includes: the fourth operational amplifier, the ninth resistor, the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, the fifth capacitor, the sixth capacitor, and the seventh capacitor; Among them, the second end of the eleventh resistor is connected to the sampling point of the dummy load circuit. The first end of the tenth resistor, the second end of the ninth resistor, the second end of the fifth capacitor, and the first end of the sixth capacitor are connected to the non-inverting input terminal of the fourth operational amplifier. The second end of the sixth capacitor, the first end of the eleventh resistor, the second end of the twelfth resistor, and the second end of the seventh capacitor are connected to the inverting input terminal of the fourth operational amplifier. The second end of the tenth resistor, the first end of the fifth capacitor, and the first end of the ninth resistor are grounded. The first end of the twelfth resistor, the first end of the seventh capacitor, and the second end of the thirteenth resistor are connected to the output terminal of the fourth operational amplifier. The first end of the thirteenth resistor is connected to the first end of the second voltage-dividing resistor.

7. The dummy load and control circuit according to claim 1, characterized in that, The first operational circuit specifically includes: the first operational amplifier, the fourteenth resistor, the fifteenth resistor, the sixteenth resistor, the eighth capacitor, the ninth capacitor, and the first diode; Among them, the anode of the first diode, the first end of the fifteenth resistor, the first end of the ninth capacitor, and the inverting input terminal of the first operational amplifier are connected to the first end of the second voltage-dividing resistor. The second end of the ninth capacitor and the first end of the fourteenth resistor are connected to the non-inverting input terminal of the first operational amplifier. The second end of the fifteenth resistor is connected to the first end of the eighth capacitor. The cathode of the first diode, the second end of the eighth capacitor, and the first end of the sixteenth resistor are connected to the output terminal of the first operational amplifier. The second end of the fourteenth resistor is grounded.

8. The dummy load and control circuit according to claim 1, characterized in that, The switching circuit specifically includes: the seventeenth resistor, the eighteenth resistor, the nineteenth resistor, the second diode, and the first PNP transistor; Among them, the first end of the seventeenth resistor and the first end of the eighteenth resistor are connected to a DC power supply. The second end of the eighteenth resistor, the base of the first PNP transistor are connected to the output end of the first operational circuit. The second end of the seventeenth resistor is connected to the emitter of the first PNP transistor. The collector of the first PNP transistor, the cathode of the second diode, and the first end of the nineteenth resistor are connected to the switch control end of the power MOS transistor. The anode of the second diode and the second end of the nineteenth resistor are grounded.

9. The dummy load and control circuit according to claim 1, wherein, The dummy load circuit specifically includes: a first power MOS transistor, a second power MOS transistor, a third power MOS transistor, a fourth power MOS transistor, and a fifth power MOS transistor. Among them, the gate of the first power MOS transistor is connected to the output end of the switch circuit. The source of the first power MOS transistor is connected to the switch control ends of the second power MOS transistor, the third power MOS transistor, the fourth power MOS transistor, and the fifth power MOS transistor.

10. The dummy load and control circuit according to claim 9, wherein An operational amplifier circuit is provided between the gate of the second power MOS transistor, the gate of the third power MOS transistor, the gate of the fourth power MOS transistor, the gate of the fifth power MOS transistor and the source of the first power MOS transistor respectively.

11. The dummy load and control circuit according to claim 9, characterized in that, A current sharing resistor is provided between the source of the first power MOS transistor, the source of the second power MOS transistor, the source of the third power MOS transistor, the source of the fourth power MOS transistor, the source of the fifth power MOS transistor and the voltage dividing resistor respectively.

12. A high-voltage switching power supply, characterized in that, It includes the dummy load and control circuit according to any one of claims 1 to 11.

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