Hybrid package device and manufacturing method

Abstract

Some features relate to a hybrid package, including a bare die, a first substrate structure, and a first metallization structure at least partially coplanar with the substrate. The bare die is electrically coupled to the first metallization structure and the first substrate via a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

Description

[0001] Claiming priority under 35 U.S.C. § 119

[0002] This patent application claims priority to U.S. Provisional Application No. 63 / 002,750, filed on March 31, 2020, entitled “HYBRID PACKAGE APPARATUS AND METHOD OF FABRICATING,” and priority to U.S. Non-Provisional Application No. 17 / 211,164, filed on March 24, 2021, entitled “HYBRID PACKAGE APPARATUS AND METHOD OF FABRICATING,” each of which is assigned to its assignee and expressly incorporated herein by reference. Technical Field

[0003] Various features are directed to a hybrid package including a package substrate and at least partially coplanar metallization structures. Background Art

[0004] Integrated circuits, integrated circuit packages, and electronic devices are continually driven to smaller form factors. Correspondingly, connections between such devices are driven to have smaller widths and finer pitches to increase input / output while still maintaining a smaller form factor.

[0005] Additionally, the integrated circuit package supports various types of signaling, including power signaling, data signaling, and ground signaling. Summary of the invention

[0006] Various features are directed to a hybrid package including a package substrate and at least partially coplanar metallization structures.

[0007] A first example provides a package including a die, a first substrate structure, and a first metallization structure at least partially coplanar with the first substrate structure. The die is electrically coupled to the first metallization structure and the first substrate structure.

[0008] A second example provides a method of forming a package, comprising: forming a first metallization structure; forming a first substrate structure, the first substrate structure being at least partially coplanar with the first substrate structure on a horizontal plane; and forming a die, the die being electrically coupled to the first metallization structure and the first substrate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various features, properties and advantages will become apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, wherein like reference numerals are correspondingly identified throughout.

[0010] Figure 1A A cross-sectional view of a hybrid package is shown.

[0011] Figure 1B A simplified top view of a hybrid package is shown.

[0012] Figures 1C to 1F The various electrical paths through the hybrid package are illustrated.

[0013] Figure 2 The diagram shows a surface mounted device Figure 1A and 1B of mixed packages.

[0014] Figure 3 A cross-sectional view of another hybrid package is shown.

[0015] Figure 4 The diagram shows a surface mounted device Figure 3 of mixed packages.

[0016] Figures 5A to 5K Illustration of manufacturing Figure 1A and Figure 1B Sequence of process steps for the fabrication of a hybrid package.

[0017] Figures 6A to 6I Illustration of manufacturing Figure 3 Sequence of process steps for the fabrication of a hybrid package.

[0018] Figure 7 An exemplary flow chart of a method for making a hybrid package is illustrated.

[0019] Figure 8 Various electronic devices are illustrated that may be integrated with any of the above hybrid packages. DETAILED DESCRIPTION

[0020] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, one of ordinary skill in the art will appreciate that various aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obfuscating various aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail in order not to obfuscate various aspects of the present disclosure.

[0021] Overview

[0022] Some features relate to a hybrid package. The hybrid package includes a first portion, the first portion including a first metallization structure and a plurality of interconnects, such as copper pillars or through-mold vias, for electrically coupling to a fourth portion of the hybrid package. The first metallization structure also includes a plurality of interconnects, including metal for electrical coupling (i.e., electrical connection) within the first metallization structure. The first portion also includes a first substrate structure, the first substrate structure including a plurality of substrate interconnects, such as copper pillars or through-mold vias, for electrically connecting to the fourth portion of the hybrid package.

[0023] The first metallization structure is at least partially coplanar with the first substrate structure in a horizontal plane and is adjacent to the first substrate. In the first example, the uppermost substrate dielectric layer is higher than the uppermost dielectric layer of the first metallization structure. Other portions of the first metallization structure are coplanar with the first substrate structure.

[0024] The first molding at least partially surrounds and covers the first metallization structure and the first substrate structure. The first molding at least partially separates the first metallization structure and the first substrate structure.

[0025] The fourth portion of the hybrid package is above the first portion. The fourth portion of the hybrid package is configured to electrically couple the hybrid package to a printed circuit board (PCB). The fourth portion of the hybrid package includes a plurality of interconnects and solder balls for coupling the hybrid package to the PCB.

[0026] The second portion of the hybrid package is below the first portion and adjacent to the first portion. The second portion of the hybrid package includes a second metallization structure including a plurality of interconnects for electrically coupling to the second portion. Optionally, the second metallization may have an additional plurality of interconnects for electrically coupling to a third portion of the hybrid package.

[0027] The third portion of the hybrid package is below the second portion and adjacent to the second portion. The third portion includes a bare die having multiple interconnections for coupling to the second portion. The bare die and the multiple interconnections of the bare die are at least partially surrounded by the second molding. The hybrid package can optionally be coupled to the second package in a package-on-package (POP) configuration. If the POP configuration is selected, the third portion can optionally include a through-mold via configured to be electrically coupled to an optional fifth portion.

[0028] The optional fifth portion of the hybrid package includes a third metallization structure for coupling the hybrid package to the second package.

[0029] The second metallization structure can be coupled to a ground signal so that the second metallization is grounded or configured to operate as a ground plane. The first metallization structure can be configured to provide an electrical path for data signaling. The first substrate structure can be configured to provide an electrical path for power (e.g., for a power distribution network or for power signaling).

[0030] In one example, the hybrid package may include a surface mount device (SMD), such as a resistor, a capacitor, or an inductor. The SMD may be located in the fourth portion of the hybrid package instead of the solder balls. The SMD may be located in the second molding of the third portion of the hybrid package.

[0031] The first metallization structure includes a plurality of first interconnects including pads having a first thickness, and the first substrate structure includes a plurality of substrate interconnects including pads having a second thickness, wherein the second thickness is greater than the first thickness. In addition, the first metallization structure includes a plurality of first vias having a first via width, and the first substrate includes a plurality of substrate vias having a substrate via width, wherein the substrate via width is greater than the first via width.

[0032] Advantageously, because the first metallization structure has a first thickness associated with its plurality of interconnects and a first width associated with its plurality of vias, the first thickness being less than a second thickness associated with the plurality of substrate interconnects, and the first width being less than a second width associated with the plurality of substrate vias, the first metallization structure has improved signal integrity due to lower impedance in the plurality of interconnects and the plurality of vias. These first thickness and first width characteristics of the first metallization structure allow it to be particularly suitable for providing an electrical path for data signaling, as it is advantageous for the data signaling path to have low impedance to obtain high-speed data signaling.

[0033] Advantageously, because the first substrate structure has a second thickness associated with its plurality of substrate interconnects and a second width associated with its plurality of substrate vias that are thicker and wider, respectively, than the first thickness and first width associated with the plurality of interconnects and the plurality of vias of the first metallization structure, the first substrate structure is able to better distribute power over a larger surface area of ​​the plurality of substrate interconnects and the substrate vias. Additionally, the above-described second thickness and second width features of the first substrate structure allow for improved thermal heat distribution.

[0034] The hybrid package includes a first metallization structure having a first thickness and a first width characteristic and a first substrate structure having a second thickness and a second width characteristic. The area of ​​the hybrid package is reduced compared to a conventional package in which all interconnects (e.g., pads and traces) are configured to accommodate power signals. This is because the area is reduced by using the first metallization structure having the first thickness and the first width characteristic (i.e., the reduced thickness and the reduced width) for data signaling.

[0035] Terms and Definitions

[0036] In some embodiments, interconnection is an element or component that allows or promotes the electrical connection between two points, elements and / or components.In some embodiments, interconnection may include traces, pads, posts, redistributed metal layers, under bump metallization (UBM) layers, solder (e.g., solder balls).In some embodiments, interconnection is a conductive material (e.g., metal) that can be configured to provide an electrical path for a signal (e.g., data signal, ground signal, power signal).Interconnection may be a part of equipment, electronic components, substrates, interposers, printed circuit boards (PCBs), bare chips, bare chip interconnections or circuits.In some embodiments, interconnection may include more than one element or component.

[0037] A trace is a form of interconnect that provides an electrical path in a device along a horizontal or nearly horizontal direction. In some implementations, the trace may be formed in a substrate or may be formed on a substrate.

[0038] A pad is a form of interconnection that provides an electrical path in an integrated device. In some embodiments, a pad is an element or component that provides a coupling interface for an interconnection made of different materials. For example, a pad can be configured to provide an interface for solder (e.g., a solder ball).

[0039] A via provides an electrical path along a vertical or nearly vertical direction in an integrated device. In some embodiments, a via may be formed in a substrate (e.g., a through-substrate via). In some embodiments, a via may be formed in a molding layer (e.g., a through-substrate via). In some embodiments, a via may have vertical walls, or may have tapered or angled walls or other orientations.

[0040] The term "thickness" may be defined as the vertical measurement of an object. In other words, thickness may be defined as the measurement from the bottom to the top of an object.

[0041] The term "width" may be defined as a lateral or horizontal measurement of an object when the object is viewed in a cross-sectional view. For example, the width of a via (e.g., 114) is a lateral or horizontal measurement of the via from a first sidewall (or first side) to a second sidewall (or second side) thereof.

[0042] Unless otherwise specified, the term coupled refers to an electrical (eg, conductive) coupling. Additionally, an object or component or device A may be coupled to a device C even if there are one or more intervening components therebetween.

[0043] As used herein, the term "ground" is a conductive point or plane where the potential of the ground or grounded conductive point or plane is used as a reference potential from which other voltages in the circuit are measured. In addition, the grounded conductive point or plane provides a low impedance path for return current. Such a grounded conductive point or grounded conductive plane (such as a metal layer) should be understood to provide a ground signal. Although the grounded conductive point or plane provides a low impedance path, the potential of the grounded conductive point or plane (e.g., a ground signal) is not necessarily zero voltage.

[0044] Hybrid Package Device

[0045] Figure 1A A cross-sectional view of a hybrid package 100 including a first metallization structure and a first substrate structure is illustrated. Figure 1B Picture shows Figure 1A 1 is a simplified top view of a hybrid package 100 .

[0046] Figure 1A A first portion 101 of a hybrid package 100 is illustrated, including a first metallization structure 110, a first substrate structure 130, and a first molding 180. A second portion 102 of the hybrid package 100 includes a second metallization structure 140. The second portion 102 of the hybrid package 100 is below the first portion 101 and adjacent to the first portion 101. A third portion 103 of the hybrid package 100 includes a die 160 and a second molding 182. A fourth portion 104 of the hybrid package 100 includes a metallization structure including solder balls 152 configured to couple the hybrid package 100 to a printed circuit board (PCB) (not shown). An optional fifth portion 105 of the hybrid package 100 includes an optional third metallization structure 170 configured to couple the hybrid package 100 to an optional second package 199 in a package-on-package configuration.

[0047] The fourth portion 104 is above the first portion 101, the second portion 102, the third portion 103, and the optional fifth portion 105. The first portion 101 of the hybrid package 100 is above the second 102 portion, the third portion 103, and the optional fifth portion 105 of the hybrid package 100. The first portion 101 is directly below the fourth portion 104. The second portion 102 of the hybrid package 100 is above the third portion and the optional fifth portion of the hybrid package 100. The second portion 102 is directly below the first portion 101 and directly below the fourth portion 104. The third portion 103 of the hybrid package 100 is above the optional fifth portion of the hybrid package 100. The third portion 103 is directly below the second portion 102 and directly below the fourth portion 104 and the first portion 101.

[0048] The optional fifth portion 105 of the hybrid package 100 is located at the bottom of the package, below the fourth, first, second and third portions (ie, 104, 101, 102, 103, respectively).

[0049] It should be understood that the terms "above" and "below" include partially above and partially below, respectively. In other words, the terms "above" and "below" do not require that an object is completely above or below. In addition, the term "above" is a relative term, and if the Hybrid 100 package is rotated or turned over, what is described as "above" may be "below". Likewise, the term "below" is a relative term, and if the Hybrid 100 package is rotated or turned over, what is described as "below" may be "above".

[0050] The first portion 101 includes a first metallization structure 110. The first metallization structure 110 includes a plurality of first interconnects 112 (e.g., pads and traces such as 112a, 112b, 112c), a plurality of first vias 114 (e.g., 114a, 114b), a plurality of first dielectric layers 116 (including an uppermost dielectric layer 116f), and a plurality of sixth interconnects 150. The plurality of first interconnects 112 are electrically coupled together through the plurality of first vias 114. The plurality of first dielectric layers 116 are insulator layers configured to at least partially surround and electrically insulate each first interconnect 112 of the plurality of first interconnects 112 and each first via 114 of the plurality of first vias 114.

[0051] The first metallization structure 110 is electrically coupled to the second metallization structure 140 by a first interconnect 112 a of the plurality of first interconnects 112 being directly coupled to second vias 144 a and 144 b of the plurality of second vias 144 of the second metallization structure 140 .

[0052] Each sixth interconnect 150 of the plurality of sixth interconnects 150 is directly coupled to one of the uppermost first interconnects 112c of the plurality of first interconnects 112. The first metallization structure 110 is directly coupled to the fourth portion 104 by each sixth interconnect 150 of the plurality of sixth interconnects 150 being directly coupled to the plurality of fourth vias 158a. Each sixth interconnect 150 of the plurality of sixth interconnects 150 may be a copper pillar or a column or a cylindrical bump.

[0053] The plurality of first interconnects 112 each have a first thickness, wherein the first thickness is Figure 1A In one example, the first thickness of at least some of the plurality of first interconnects 112 may be between 2 μm and 10 μm, but is not limited thereto. Additionally, the plurality of first vias 114 each have a first via width, wherein the first via width is Figure 1A In one example, the first via width of at least some of the plurality of first vias 114 may be between 10 μm and 50 μm, but is not limited thereto. The plurality of first dielectric layers 116 each have a first dielectric thickness, which is Figure 1A The thickness of the first dielectric is measured in the vertical direction of the cross section of the first dielectric. The thickness of the first dielectric is between 5 μm and 10 μm. In another example, the thickness of the first dielectric is between 5 μm and 15 μm.

[0054] The first metallization structure 110 is configured to provide an electrical path for data signaling. The first metallization structure is configured to receive data signaling from the die 160. Alternatively, the first metallization structure 110 is configured to receive data signaling from a PCB (not shown) or an optional second package 199. The electrical path for data signaling will be discussed in further detail. The first metallization structure 110 is configured as a redistribution layer (RDL).

[0055] As will be discussed further below, the first thickness of the first interconnect 112 and the first via width of the plurality of first vias 114 are smaller than corresponding elements of the first substrate structure 130. Advantageously, the first metallization structure enables a higher density of data signaling paths due to the finer lines and spaces of the plurality of first interconnects 112 and the plurality of first vias 114.

[0056] The first metallization structure 110 is at least partially coplanar with the first substrate structure 130 in a horizontal plane and is adjacent to the first substrate structure 130. In one aspect, because the first substrate structure 130 is longer or taller than the first metallization structure 110, the uppermost portion 110a of the first metallization structure 110 is not coplanar with the uppermost portion 130a of the first substrate structure 130. However, the first metallization structure 110 is coplanar with the first substrate structure 130 in other horizontal planes (i.e., the first metallization structure 110 and the first substrate structure 130 are adjacent).

[0057] In one aspect, the uppermost portion 110a of the first metallization structure 110 is the uppermost dielectric layer 116f of the plurality of first dielectric layers 116, and the uppermost portion 130a of the first substrate structure 130 is the uppermost substrate dielectric layer 136e of the plurality of substrate dielectric layers 136. As used herein, the term uppermost does not include uppermost interconnects, such as the plurality of sixth interconnects 150 of the first metallization structure 110 or the plurality of seventh interconnects 154 of the first substrate structure 130, as these top interconnects may be planar with respect to each other.

[0058] The first substrate structure 130 may be a metallization build-up, a laminate substrate, or an organic material, such as bismaleimide triazine (BT), FR-4 (or also referred to as FR4, a NEMA grade designation for glass-reinforced epoxy laminates), or a liquid crystal polymer, or a polyimide, or an epoxy molding compound. The first substrate structure 130 includes the following: a plurality of substrate interconnects 132 (e.g., pads and traces, such as 132a, 132b, and 132c), a plurality of substrate vias 134 (e.g., 134a and 134b), a plurality of substrate dielectric layers 136 (including an uppermost dielectric layer 136e), and a plurality of seventh interconnects 154. The plurality of substrate interconnects 132 are electrically coupled together through the plurality of substrate vias 134. The plurality of substrate dielectric layers 136 are insulator layers configured to at least partially surround and electrically insulate each of the plurality of substrate interconnects 132 and each of the plurality of substrate vias 134. The first substrate structure 130 is coupled to the second metallization structure 140 by the substrate interconnects 132 a of the first substrate structure 130 being directly coupled to the plurality of solder interconnects 148 of the second metallization structure 140 .

[0059] The plurality of seventh interconnects 154 are electrically coupled to the uppermost substrate interconnect 132c of the plurality of substrate interconnects 132. The plurality of seventh interconnects 154 are configured to be directly coupled to some of the plurality of fourth vias 158b through the uppermost substrate interconnect 132c, respectively, to couple the first substrate structure 130 to the fourth portion 104 of the hybrid package 100. Each of the plurality of seventh interconnects 154 may be a copper pillar or a column or a cylindrical bump.

[0060] The plurality of substrate interconnects 132 each have a second thickness, wherein the second thickness is Figure 1A The second thickness of at least some of the plurality of substrate interconnects 132 may be between 10 μm and 30 μm. The second thickness of the plurality of substrate interconnects 132 may be greater than the first thickness of the plurality of first interconnects 112 of the first metallization structure 110 .

[0061] Additionally, the plurality of substrate vias 134 each have a substrate via width, wherein the substrate via width is Figure 1A The substrate via width of at least some of the plurality of substrate vias 134 may be between 50 μm and 100 μm. The substrate via width of the plurality of substrate vias 134 may be greater than the first via width of the plurality of first vias 114 of the first metallization structure 110 .

[0062] The first substrate structure 130 is configured to provide an electrical path for power (ie, the first substrate structure 130 may operate as a power distribution network), as will be discussed further later.

[0063] Advantageously, because the first metallization structure 110 has a first thickness (measured in the vertical direction) associated with each of the plurality of interconnects 112 that is less than a second thickness (measured in the vertical direction) associated with the plurality of substrate interconnects 132, and a first via width (measured in the horizontal direction) associated with each of the plurality of first vias 114 that is less than a substrate via width associated with each of the plurality of substrate vias 134, the first metallization structure 110 has improved signal integrity due to lower impedance in the plurality of interconnects 112 and the plurality of vias 114. These first thickness and first via width characteristics of the first metallization 110 structure make it particularly suitable for providing an electrical path for data signaling, as it is advantageous to have a data signaling path with low impedance to achieve high-speed data signaling.

[0064] Advantageously, because the first substrate structure 130 has a second thickness associated with its plurality of substrate interconnects 132 and a substrate via width associated with its plurality of substrate vias 134 that is thicker and wider, respectively, than the first thickness and first via width associated with the plurality of interconnects 112 and the plurality of vias 114 of the first metallization structure 110, the first substrate structure 130 is able to better distribute power (e.g., because it operates as a power distribution network) through the larger surface area of ​​the plurality of substrate interconnects 132 and the plurality of substrate vias 134. Additionally, the above-described second thickness and substrate via width features of the first substrate structure 130 allow for improved thermal heat distribution.

[0065] The hybrid package includes both a first metallization structure 110 having a first thickness and a first via width characteristic and a first substrate structure 130 having a second thickness and a second via width characteristic. The area of ​​the hybrid package 100 is reduced compared to a conventional package in which all interconnects (e.g., pads and traces) are configured to accommodate power signals. This is because the area is reduced by using the first metallization structure 110 having the first thickness and the first via width characteristics (i.e., reduced thickness and reduced width) for data signaling.

[0066] Furthermore, because the first substrate structure 130 is configured as a power distribution network, the first substrate structure 130 may experience higher temperatures than if it were configured as a ground plane.Thus, the thicker plurality of substrate interconnects 132 and the wider plurality of substrate vias 134 provide increased surface area for greater heat dissipation.

[0067] The first substrate structure 130 is at least partially coplanar with the first metallization structure 110, and the first substrate structure 130 is adjacent to the first metallization structure 110. The first substrate structure 130 is surrounded by the first metallization structure 110 (as shown in FIG. Figure 1B The first molding 180 at least partially surrounds the first metallization structure 110 and the first substrate structure 130. The first molding 180 at least partially physically separates and electrically insulates the first metallization structure 110 and the first substrate structure 130 from each other. The first molding 180 provides structural support for the first metallization structure 110 and the first substrate structure 130.

[0068] The uppermost portion 130a of the first substrate structure 130 may be higher than or longer than the uppermost portion 110a of the first metallization structure 110. As used herein, the term "higher than" may or may not take into account the actual height of the first substrate structure 130 compared to (or relative to) the actual height of the first metallization structure 110. However, the term "higher than" as used herein means Figure 1A The uppermost portion 130a of the first substrate structure 130 is illustrated above (but not necessarily overlapping) the uppermost portion 110a of the first metallization structure 110, regardless of where each of the bottom sides of the first substrate structure 130 and the first metallization structure 110 are located.

[0069] Go to Figure 1B , Figure 1B Picture shows Figure 1A A simplified top view of a hybrid package 100 (where Figure 1A yes Figure 1B Cross-section taken at "A"). For simplicity, Figure 1B Not pictured Figure 1A all components. Figure 1B The first substrate structure 130 is shown to be completely surrounded by the first metallization structure 110. In other words, Figure 1B The illustrated first metallization structure 110 is a single structure surrounding the first substrate structure 130. The first molding 180 physically separates the first substrate structure 130 from the first metallization structure 110. Furthermore, the first molding 180 electrically insulates the first substrate structure 130 from the first metallization structure.

[0070] although Figure 1B The first metallization structure is illustrated as surrounding the first substrate structure 130, but is not limited thereto. In another aspect, the first metallization structure 110 may include multiple portions (e.g., a first portion, a second portion, etc.) that partially or completely surround the first substrate structure 130 but are physically separated by a molding, such as the first molding 180. In yet another aspect, the first metallization structure 110 may only partially surround the first substrate 130 structure.

[0071] Return to Figure 1A , Figure 1A The second portion 102 is further illustrated as including a second metallization structure 140. The second metallization structure 140 is located between the die 160 and the first metallization structure 110, and between the die 160 and the first substrate structure 130. The second metallization structure 140 includes a plurality of second interconnects 142 (e.g., pads or traces, such as 142a and 142b), a plurality of second vias 144 (e.g., 144a and 144b), a plurality of solder interconnects 148, and a plurality of second dielectric layers 146.

[0072] The first subset 144 a of the plurality of second vias 144 is configured to couple the die 160 (in the third portion 103 ) to the first metallization structure 110 (or the first portion of the hybrid package 100 ) through the plurality of second interconnects 142 a .

[0073] The second subset 144b of the plurality of second vias 144 is optional and is configured to couple the plurality of first interconnects (e.g., 112a) to the plurality of second interconnects 142 (e.g., 142b). That is, the second subset 144b is configured to couple the optional fifth portion of the hybrid package 100 to the first metallization structure 110 (or the first portion of the hybrid package 100). If the optional fifth portion of the hybrid package 100 is omitted, the first subset 144b of the plurality of second vias 144 may also be omitted.

[0074] The plurality of solder interconnects 148 are electrically coupled to the plurality of second interconnects 142 (eg, 142a). The plurality of solder interconnects 148 are configured to electrically couple the die 160 to the first substrate structure 130 through the plurality of second interconnects 142a.

[0075] The second metallization structure 140 is configured as a ground plane, ie, the second metallization structure 140 is coupled to a ground signal and serves as a return path for currents from different components on the board.

[0076] The third portion 103 of the hybrid package 100 includes a third metallization structure 170. The third metallization structure 170 includes a die 160, a plurality of third interconnects 162 (e.g., flip chip bumps), a second molding 182, and an optional plurality of through-mold vias 164. The illustrated die 160 is a flip chip, but is not limited thereto. The die 160 may also be any die including copper plating on its pads. The die 160 includes an active side (the active side is the side of the die that includes active circuit components such as transistors). The active side of the die 160 is the side of the die 160 that is closest to the second metallization structure 140. The die 160 includes a back side (not including transistors). The back side of the die 160 is the side of the die 160 that is farthest from the second metallization structure 140.

[0077] The second molding 182 at least partially surrounds and covers the die and the plurality of third interconnects 162. A first side (i.e., top side) of the second molding 182 is directly connected to the second metallization structure 140. A second side (i.e., bottom side) of the second molding 182 is directly connected to the third metallization structure 170. The second molding 182 also at least partially surrounds an optional plurality of through-mold vias 164.

[0078] The plurality of through-mold vias 164 are configured to be coupled to the plurality of second interconnects 142 b in the second metallization structure 140 .

[0079] A subset or portion of the plurality of third interconnects 162 is configured to couple the die 160 to the plurality of second interconnects 142 (e.g., 142a) of the second metallization structure 140. That is, the third metallization structure 170 is electrically coupled to the second metallization structure 140, and the second metallization structure 140 is electrically coupled to both the first metallization structure 110 and the first substrate structure 130.

[0080] The fourth portion 104 of the hybrid package 100 includes at least one dielectric layer 156, a plurality of fourth vias (e.g., 158a, 158b), a plurality of fourth interconnects (e.g., 159a, 159b), and a plurality of solder balls 152. The fourth portion 104 of the hybrid package 100 is configured to be electrically coupled to a printed circuit board (not shown) through the plurality of solder balls 152.

[0081] The plurality of fourth vias 158b are coupled to the plurality of seventh interconnects 154 of the first substrate structure 130. Thus, the fourth portion 104 of the hybrid package 100 is electrically coupled to the first substrate structure 130. In addition, the plurality of fourth vias 158a are electrically coupled to the plurality of sixth interconnects 150 of the first metallization structure 110. Thus, the fourth portion 104 of the hybrid package 100 is electrically coupled to the first metallization structure 110.

[0082] The plurality of fourth vias 158a and 158b are coupled to the plurality of fourth interconnections 159a and 159b, respectively. The plurality of fourth interconnections 159a and 159b are coupled to the plurality of solder balls 152, respectively.

[0083] The optional fifth portion 105 of the hybrid package 100 includes an optional third metallization structure 170. The optional third metallization structure 170 includes a plurality of fifth interconnects 172 (eg, 172a, 172b) (eg, pads and traces), a plurality of fifth vias 174, and a plurality of fifth dielectric layers 176.

[0084] The plurality of fifth interconnects 172 (e.g., 172b) are coupled to the optional plurality of through-mold vias 164. That is, the plurality of fifth interconnects 172 electrically couple the third metallization structure 170 to the second metallization structure 140 through the through-mold vias 164. In addition, the plurality of fifth interconnects 172 (e.g., 172a) electrically couple the third metallization structure 170 to the optional second package 199 in a package-on-package (POP) configuration.

[0085] Figures 1C to 1F Illustrated are various electrical paths through the hybrid package 100. These various electrical paths are exemplary and are not limiting.

[0086] Figure 1C A first electrical path 181 from the die 160 through the first metallization structure 110 and through the plurality of solder balls 152 is illustrated. The first electrical path 181 can be configured to transmit a data signal. It should be understood that the first electrical path 181 is operable in the opposite direction. The die 160 located in the third portion 103 of the hybrid package 100 is configured to send a data signal (or multiple data signals) along the following first electrical path 181: the die 160 transmits the data signal through the plurality of third interconnects 162 (e.g., flip chip bumps), through the plurality of second interconnects 142a, and through the plurality of second vias 144a of the second metallization structure 140.

[0087] The data signal continues from the plurality of second vias 144a through the plurality of first interconnects 112 (e.g., 112a, 112b, and 112c), through the plurality of first vias 114 (e.g., 114a and 114b), and through the plurality of sixth interconnects 150 of the first metallization structure 110. The data signal continues from the plurality of sixth interconnects 150 through the plurality of fourth vias 158a to the plurality of fourth interconnects 159a to the plurality of solder balls 152. The plurality of solder balls 152 are configured to be coupled to a PCB (not shown). Therefore, the data signal transmitted from the die 160 can be electrically transmitted from the die 160 to the coupled PCB (not shown) through the solder balls 152.

[0088] It should be understood that the first electrical path 181 also operates in the reverse direction. In other words, another data signal can be transmitted from another electronic component (not shown) of the PCB (not shown) through the plurality of solder balls 152, the first metallization structure 110, and the second metallization structure 140 to the die 160, as described in detail above.

[0089] Figure 1D A second electrical path 183 from the plurality of solder balls 152 to the die 160 is illustrated. The second electrical path 183 may be configured to transmit power from a PCB (not shown) coupled to the plurality of solder balls 152, where the PCB may be coupled to a power source, to the die 160. The second electrical path 183 is as follows: power is transmitted through the plurality of solder balls 152, through the plurality of fourth interconnects 158b and 159b, through the plurality of seventh interconnects 154, through the plurality of substrate interconnects 132 (e.g., 132a, 132b, and 132c), through the plurality of substrate vias 134 (e.g., 134a and 134b) of the first substrate structure 130. The power then continues from the plurality of substrate interconnects 132 (e.g., 132a) through the plurality of solder interconnects 148, the plurality of second interconnects 142a, the third plurality of interconnects 162, and then to the die 160. The second electrical path 183 may operate in the opposite direction.

[0090] Figure 1E A third electrical path 185 and a fourth electrical path 187 are illustrated.

[0091] The third electrical path 185 can be used to distribute power (e.g., power signals) from a PCB (not shown) coupled to the plurality of solder balls 152 to an optional second package 199 (e.g., a POP package). The third electrical path 185 is as follows: power is transmitted from the plurality of solder balls 152 through the plurality of fourth interconnects 158b and 159, through the plurality of seventh interconnects 154, through the plurality of substrate interconnects 132 (e.g., 132a, 132b, and 132c), through the plurality of substrate vias 134 (e.g., 134a and 134b) of the first substrate structure 130. The power (e.g., power signals) then continue from the plurality of substrate interconnects 132 (e.g., 132a) through the plurality of solder interconnects 148, through the plurality of second interconnects 142a, through the plurality of second interconnects 142b, through the optional plurality of through-mold vias 164, through the plurality of fifth interconnects 172, and the plurality of fifth vias 174 to the optional second package 199. The electrical path 185 operates in the opposite direction.

[0092] A fourth electrical path 187 may be used to transmit data signals from the die 160 to an optional second package 199. The fourth electrical path 187 is as follows: the data signals are transmitted from the die to the second package 199 through the third plurality of interconnects 162, the plurality of second interconnects 142a, the plurality of second interconnects 142b, the optional plurality of through-mold vias 164, the optional third metallization structure 170 (as previously described). The fourth electrical path 187 may operate in the reverse direction.

[0093] Figure 1F A fifth electrical path 189 is illustrated from the optional second package 199 through the first metallization structure 110 and through the plurality of solder balls 152. The fifth electrical path 189 can be configured to transmit data signals. The fifth electrical path 189 is as follows: the data signal from the optional second package 199 can be transmitted through the plurality of fifth interconnects 172 (e.g., 172a and 172b), through the plurality of fifth vias 174 to the optional plurality of through-mold vias 164, through the plurality of second interconnects 142b to the plurality of second vias 144 of the second metallization structure 140, through the plurality of first interconnects 112 (e.g., 112a, 112b, and 112c) and through the plurality of first vias 114 (e.g., 114a and 114b) of the first metallization structure 110. The data signal will then continue to the plurality of fourth vias 158a, to the plurality of fourth interconnects 159a, and then to the plurality of solder balls 152. The plurality of solder balls 152 are configured to be coupled to a PCB (not shown), and thus signals transmitted from the optional second package 199 may be electrically transmitted to the coupled PCB (not shown) through the solder balls 152 .

[0094] As will be appreciated by those skilled in the art, other electrical paths are included. It should also be appreciated that various electrical paths may be used simultaneously. For example, die 160 may receive power from second electrical path 183 while data signaling is transmitted via first electrical path 181 or via fourth electrical path 187 or via fifth electrical path 189.

[0095] Figure 2 The diagram shows a surface mounted device Figure 1A and 1B Specifically, Figure 2 A hybrid package 200 is illustrated that is similar to the hybrid package 100, except that the hybrid package 200 includes surface mount devices 202a and 202b. The surface mount devices 202a and 202b can be any passive components, such as inductors, capacitors, or resistors. The surface mount devices 202a and 202b can be the same type of surface mount devices (e.g., both can be inductors), or they can be different (e.g., 202a can be an inductor and 202b can be a capacitor).

[0096] The surface mount device 202a may be located in the fourth portion 104 of the hybrid package 200 in place of the selected solder ball 152. The surface mount device 202a may be electrically coupled to the plurality of fourth interconnects 159a and 159b of the fourth portion 104, and thus electrically coupled to the die 160 through the first metallization structure 110 or through the first substrate structure 130. That is, one electrode of the surface mount device 202a may be located on one fourth interconnect 159a of the plurality of fourth interconnects, and another electrode of the surface mount device 202a may be located on another fourth interconnect 159b of the plurality of fourth interconnects.

[0097] The surface mount device 202b may be located in the third portion 103 of the hybrid package 200. Specifically, the surface mount device 202b may be embedded in the second molding 182 of the third portion 103. The surface mount device 202b may be electrically coupled to the plurality of second interconnects 142 (eg, 142a and 142b).

[0098] Although not shown, the hybrid package 200 may be coupled to the second package 199 (in Figure 1A (see figure in the figure).

[0099] An advantage of the surface mount devices 202 a and 202 b is that they do not require additional area in the hybrid package 200 .

[0100] Figure 3 A cross-sectional view of another hybrid package 300 including a metallization structure and a substrate is illustrated. Figure 3 Similar to 1A, except: Figure 3 A plurality of sixth interconnects 350 in the first metallization structure 110 and a plurality of seventh interconnects 354 in the first substrate structure 130 are illustrated. The plurality of sixth interconnects 350 are through-mold vias formed in the first molding 180, which are directly coupled to the plurality of fourth interconnects 159a (e.g., pads or traces). The plurality of seventh interconnects 354 are through-mold vias formed in the first molding 180 (rather than copper pillars), which are directly coupled to the plurality of interconnects 159b. Thus, Figure 1A The plurality of fourth vias 158a and 158b are omitted in this embodiment. Figure 1A The plurality of sixth interconnects 150 and the dielectric layer 156 are omitted in this embodiment.

[0101] In contrast, Figure 1A The plurality of seventh interconnects 154 are illustrated as being directly coupled to the plurality of fourth vias 158 b .

[0102] Figure 4 The diagram shows a surface mounted device Figure 3 Specifically, Figure 4A hybrid package 400 (similar to hybrid package 300) is illustrated that includes surface mount devices 402a and 402b. Surface mount devices 402a and 402b may be any passive components, such as inductors, capacitors, or resistors. Surface mount devices 402a and 402b may be the same type of surface mount devices (e.g., both may be inductors), or they may be different (e.g., 402a may be an inductor and 402b may be a capacitor).

[0103] The surface mount device 402a may be located in the fourth portion 104 of the hybrid package 100 in place of the selected solder balls 152. The surface mount device 402a may be electrically coupled to the plurality of fourth interconnects 159a and 159b of the fourth portion 104 and thus electrically coupled to the die 160 through the first metallization structure 110 or through the first substrate structure 130.

[0104] The surface mount device 402b may be located in the third portion 103 of the hybrid package 200. Specifically, the surface mount device 402b may be embedded in the second molding 182 of the third portion 103. The surface mount device 402b may be electrically coupled to the plurality of second interconnects 142 (eg, 142a and 142b).

[0105] Exemplary sequence for making a hybrid package

[0106] In some embodiments, manufacturing a hybrid package includes several processes. Figures 5A to 5K Illustration of manufacturing Figure 1A and 1B 1 is a sequence of process steps for manufacturing the hybrid package 100 . Figures 6A to 6I Illustration of manufacturing Figure 3 1. A sequence of process steps for manufacturing the hybrid package 300.

[0107] Figures 5A to 5K Now in the manufacturing process including Figure 1A It should be noted that Figures 5A to 5K The sequence of the process may be combined with one or more stages to simplify and / or clarify the sequence. In some embodiments, the order of the process may be changed or modified.

[0108] Figure 5AA detachable first carrier 543 is illustrated. The first carrier 543 may be provided or manufactured by a supplier. An adhesive layer 545 is formed on and above the first carrier 543 so that a passivation layer 549 may be attached to the first carrier 543 through the adhesive layer 545. The passivation layer 549 is formed on the adhesive layer 545. The passivation layer 549 is selected to provide electrical isolation and act as a physical barrier. The passivation layer 549 may include any of the following materials, but is not limited thereto: a temporary film detachable by UV or chemical action, or a double-layer film structure including UV and an adhesive layer.

[0109] The second metallization structure 540 is formed on the passivation layer 549, the adhesive layer 545 and the first carrier 543. The second metallization structure 540 includes a plurality of dielectric layers 546 and a plurality of metal interconnects 542. The plurality of dielectric layers 546 are formed on the passivation layer 549. A plurality of metal interconnects 542 are formed (e.g., patterned) in the plurality of dielectric layers 546. The plurality of metal interconnects 542 can be formed by any known method. The plurality of metal interconnects 542 can include pads or traces or both. A plurality of holes 547 are formed in the uppermost dielectric layer of the plurality of dielectric layers 546. The second metallization structure 540 is the second portion 502 of the hybrid package 500.

[0110] The material of the plurality of dielectric layers 546 is selected to provide electrical isolation. Unless otherwise specified, the material of the plurality of dielectric layers 546 and any other dielectric layers mentioned herein in this document (e.g., dielectric layer, a plurality of first dielectric layers, a plurality of second dielectric layers, etc.) may include, but is not limited to, a photosensitive dielectric that may be polyimide, PBO, or epoxy resin. Unless otherwise specified, the material of the plurality of interconnects 542 and any other interconnects mentioned herein in this document (e.g., a plurality of first interconnects, a plurality of second interconnects, etc.) may include, but is not limited to, copper.

[0111] Figure 5B The first metallization structure 510 is shown formed above and on the second metallization structure 540. The first metallization structure 510 may be formed such that it is circular or rectangular or any other shape that leaves an opening or space between or in the center of the first metallization structure 510 (e.g., see Figure 1B , Figure 1B An opening in the first metallization structure 110 filled with the first substrate structure 130 is illustrated.

[0112] The first metallization structure 510 includes a plurality of dielectric layers 516, a plurality of metal interconnects 512, and a plurality of vias 514 (e.g., a plurality of first vias 114). The plurality of metal interconnects 512 are formed in the plurality of dielectric layers 516. The plurality of metal interconnects 512 and the plurality of vias 514 may be formed by any known method (e.g., forming a dielectric layer, forming a cavity in a dielectric layer, plating the metallization structure 510).

[0113] The first metallization structure 510 is coupled to the second metallization structure 540 through a plurality of vias 544 in the second metallization structure 540 .

[0114] Figure 5C It is illustrated that a plurality of metal interconnects 550 are formed. The plurality of metal interconnects 550 are formed on and coupled to the uppermost first interconnects of the plurality of first interconnects 512. The plurality of metal interconnects 550 may be copper pillars, or columns, or cylindrical bumps.

[0115] Figure 5D The first substrate structure 530 is illustrated as being formed over and on the second metallization structure 540. The first substrate structure 530 is formed such that the first metallization structure 110 at least partially surrounds or completely surrounds the first substrate structure 530. The first substrate structure 530 is formed in an opening or space between or in the center of the first metallization structures 510. The first substrate structure 530 is coupled to the second metallization structure 540 via a plurality of solder connections 548 formed in a plurality of holes 647b.

[0116] A plurality of substrate dielectric layers 536 are formed. A plurality of substrate interconnects 532 (e.g., metal interconnects) are formed in the plurality of substrate dielectric layers 536. A plurality of substrate vias 534 couple the plurality of substrate interconnects 532 formed in separate layers in the plurality of substrate dielectric layers 536. A plurality of metal interconnects 554 are formed on the uppermost layer of the plurality of substrate interconnects 532.

[0117] The first substrate structure 530 is formed to be at least partially coplanar with the first metallization structure 510 in a horizontal plane and adjacent to the first metallization structure 510. In one aspect, the uppermost portion of the first metallization structure 510 is not coplanar with the uppermost portion of the first substrate structure 530, but other portions of the first metallization structure 510 are coplanar with the first substrate structure 530. In one aspect, the uppermost portion of the first metallization structure 510 is the uppermost dielectric layer of the plurality of first dielectric layers 516, and the uppermost portion of the first substrate structure 530 is the uppermost substrate dielectric layer of the plurality of substrate dielectric layers 536. As used herein, the term uppermost does not include top interconnects, such as the plurality of metal interconnects 550 of the first metallization structure 510 or the plurality of metal interconnects 554 of the first substrate structure 530, as these metal interconnects (e.g., 550 and 554) may be coplanar with respect to each other.

[0118] Figure 5E A first molding 580 (e.g., first molding 180) is illustrated. The first molding 580 can be any molding sealant (e.g., thermosetting resin), but is not limited thereto. The first molding 580 is formed so that it at least partially surrounds the first metallization structure 510 and the first substrate structure 530. The first molding 580 physically separates and electrically insulates the first metallization structure 510 and the first substrate structure 530 from each other. The first molding 580 provides structural support for the first metallization structure 510 and the first substrate 530.

[0119] The first metallization structure 510 , the first substrate structure 530 and the first molding 580 together form a first portion 501 of the hybrid package 500 .

[0120] Fig. 5F The formation of the fourth portion 504 of the hybrid package 500 is illustrated. At least one dielectric layer 556 is formed over the first portion 501. A plurality of metal interconnects 558 are formed, including a plurality of vias 558a formed in the at least one dielectric layer 556, and a plurality of metal interconnects 558b (e.g., pads) formed over the at least one dielectric layer 556. A plurality of solder balls 552 are formed on the plurality of metal interconnects 558b, such that some of the solder balls 552 are electrically coupled to the plurality of interconnects 550 of the first metallization structure 510, and some of the plurality of metal interconnects 558b are electrically coupled to the plurality of interconnects 554 of the first substrate structure 530.

[0121] Figure 5G A second carrier 551 formed over the fourth portion 504 is illustrated.

[0122] Figure 5HThe diagram shows the first carrier 543 after being flipped over and after the first carrier 543 is removed so that the second metallization layer 540 is exposed. Fig. 5F .

[0123] Fig.5I The formation of the third portion 503 of the hybrid package 500 is illustrated. The third portion includes a die 560. The die 560 is coupled to a plurality of interconnects 542a of the second metallization 540 via a plurality of metal interconnects 562. The plurality of metal interconnects 562 may be flip chip bumps, and the die 560 may be a flip chip die. If it is desired that the hybrid package 500 be coupled to the second package 599 in a package-on-package (PoP) configuration (see Figure 5K ), then an optional through-mold via 564 is formed and coupled to the plurality of metal interconnects 542b of the second metallization structure 540.

[0124] The second molding 582 is formed over and at least partially surrounds the die 560 , the plurality of metal interconnects 562 (eg, flip chip bumps), and the through-mold vias 564 .

[0125] Figure 5J An optional third metallization structure 570 is illustrated as being formed over the third portion 503 of the hybrid package 500. The optional third metallization structure 570 provides an additional metal layer for connecting the hybrid package 500 to the second package 599 in a PoP configuration.

[0126] The third metallization structure 570 includes forming a plurality of dielectric layers 576 (e.g., a plurality of fifth dielectric layers 176). A plurality of metal interconnects 572 are formed in the plurality of dielectric layers 576. A plurality of vias 574 couple the plurality of metal interconnects 572 formed in separate layers in the plurality of dielectric layers 576. A plurality of holes 575 are formed above the uppermost plurality of metal interconnects 572 (e.g., 527a) so that, if desired, an optional second package 599 (see FIG. K) can be coupled to the third metallization structure 570 in a PoP configuration by any known method (e.g., solder balls, metal interconnects).

[0127] Figure 5K The diagram shows the substrate after being turned over and the second carrier 551 has been removed. Figure 5J . Figure 5K A hybrid package 500 is illustrated that includes a first portion 501 , a second portion 502 , a third portion 503 , a fourth portion 504 , and an optional fifth portion 505 .

[0128] Figure 5K It is further illustrated that the hybrid package 500 may be coupled to a second package 599 .

[0129] Figures 6A to 6I Illustration of manufacturing Figure 3 1. A sequence of process steps for manufacturing the hybrid package 300. Figures 6A to 6I The present invention will now be described in the context of manufacturing a hybrid package 600, which includes a plurality of metal interconnects 650 and another plurality of metal interconnects 354, which are through-mold vias. It should be noted that Figures 6A to 6I The sequence of the process may be combined with one or more stages to simplify and / or clarify the sequence. In some embodiments, the order of the process may be changed or modified.

[0130] Fig. 6A Similar to Figure 5A , so for simplicity, Fig. 6A Details can be found in Figure 5A can be found in the description. Fig. 6A The first carrier 643 , an adhesive layer 645 , a passivation layer 649 , a second metallization structure 640 including a plurality of dielectric layers 646 , a plurality of holes 647 , and a plurality of metal interconnections 642 (eg, 642 a and 642 b ).

[0131] Figure 6B Similar to Figure 5B , so for simplicity, Figure 6B Details can be found in Figure 5A can be found in the description. Figure 6B It includes a plurality of vias 644 , a plurality of holes 647 , a first metallization structure 610 including a plurality of dielectric layers 616 , a plurality of metal interconnects 612 , and a plurality of vias 614 .

[0132] Figure 6C Similar to combination Figure 5D and 5E ,Apart from Figure 6C No Figure 5D and 5E The plurality of metal interconnects 550 are shown. Therefore, for the sake of simplicity, Figure 6C Details can be found in Figure 5D and Figure 5E , except for the above differences.

[0133] Figure 6C Included is a first substrate structure 630 formed over and on a second metallization structure 640 and between first metallization structures 610 . Figure 6CThe first substrate structure 630 includes a plurality of substrate dielectric layers 636, a plurality of substrate interconnects 632 (e.g., metal interconnects), a plurality of substrate vias 634, and a plurality of solder interconnects 648 for electrically coupling the first substrate structure 630 to the second metallization structure 640. After the first substrate structure 630 is formed, a first molding 680 is formed over the first substrate structure 630 and the first metallization structure 610, and at least partially surrounds the first substrate structure 630 and the first metallization structure 610.

[0134] The first metallization structure 610, the first substrate structure 630 and the first molding 680 together form a first portion 601 of the hybrid package 600. The second metallization structure 640 forms a second portion 602 of the hybrid package 600.

[0135] Fig.6D Illustrated is a hole 603 formed in the first molding 680. The hole 603 exposes the plurality of metal interconnects 612 in the first metallization structure 610 (specifically, the uppermost interconnect of the plurality of metal interconnects 612). Fig.6D Further illustrated is a hole 603 exposing a plurality of substrate interconnects 632 (specifically, an uppermost substrate interconnect) among the plurality of substrate interconnects 632 .

[0136] Fig. 6E The hole 603 is illustrated as being filled with a conductive material, such as a metal, thereby forming a plurality of through-mold vias 660. The plurality of through-mold vias 660 are in electrical and physical contact with the plurality of interconnect metals 612 of the first metallization structure 610. In addition, the hole 604 is filled with a conductive material, such as a metal, thereby forming a plurality of through-mold vias 654. The plurality of through-mold vias 654 are in electrical and physical contact with the plurality of interconnect metals 632 of the first substrate structure 630.

[0137] Fig. 6E Further illustrated are a plurality of metal interconnects 658 (e.g., pads or traces) formed on the first molding 680, on the through-mold vias 660, and on the through-mold vias 654. A plurality of solder balls 652 are formed on the plurality of metal interconnects 658 for electrical connection to a PCB (not shown). The plurality of metal interconnects 658 and the plurality of solder balls 652 together form a fourth portion of the hybrid package 600.

[0138] Fig. 6F The diagram shows the Fig. 6E A detachable second carrier 651 is shown on the structure.

[0139] Figure 6G The diagram shows the structure after the first carrier 643 has been removed and the structure has been flipped over so that the second metallization structure 640 faces upwards. Fig. 6F structure.

[0140] Figure 6H The third portion 603 is shown after being formed. Figure 6G The third portion 603 includes a die 660. The die 660 is coupled to a plurality of interconnects 642a of the second metallization 640 via a plurality of metal interconnects 662. The plurality of metal interconnects 662 may be flip chip bumps, and the die 660 may be a flip chip die. A second molding 682 is formed over the die 660 and over the second metallization structure 640.

[0141] If it is desired that the hybrid package 600 be coupled to a second package (not shown) in a package-on-package (PoP) configuration, an optional through-mold via 664 is formed and coupled to the plurality of metal interconnects 642 b of the second metallization structure 640. The through-mold via 664 is formed by making a hole or cavity in the second molding 682 and filling the hole with a conductive material such as a metal. The second molding 682 at least partially surrounds the die 660, the plurality of metal interconnects 662 (e.g., flip chip bumps), and the through-mold via 664.

[0142] Fig.6I The diagram shows the structure after it has been flipped over, after the second carrier 651 has been removed and the optional third metallization structure 670 has been formed. Figure 6H An optional third metallization structure 670 is formed below the third portion 603 of the hybrid package 600 (ie, below the Fig.6I The optional third metallization structure 670 provides an additional metal layer for connecting the hybrid package 600 to the second package 699 in a PoP configuration.

[0143] The third metallization structure 670 is formed by forming a plurality of dielectric layers 676. A plurality of metal interconnects 672 are formed in the plurality of dielectric layers 676. A plurality of vias 674 connect (e.g., electrically connect) the plurality of metal interconnects 672 formed in separate layers of the plurality of dielectric layers 676. A plurality of holes 675 are formed over the uppermost plurality of metal interconnects 672 (e.g., 672a) so that, if desired, the optional second package 699 can be coupled to the third metallization structure 670 by any known method (e.g., solder balls, metal interconnects) in a PoP configuration.

[0144] Optionally, the second package 699 may be coupled to the hybrid package 600. The hybrid package 600 may be coupled to the second package 699 through a third metallization structure.

[0145] Exemplary flow chart of a method for making a hybrid package

[0146] In some embodiments, making a hybrid package includes several processes. Figure 7 An exemplary flow chart of a method 700 for making a hybrid package is shown. In some embodiments, Figure 7 The method 700 may be used to make the Figure 1A , 1B , 2, 3, 4, mixed packages of 5A to 5K and 6A to 6I.

[0147] It should be noted that in order to simplify and / or clarify the method for providing or making a die, Figure 7 The sequence of one or more processes can be combined. In some embodiments, the order of the processes can be changed or modified.

[0148] At 702 , the method includes forming a first metallization structure.

[0149] At 704 , the method includes forming a first substrate structure that is at least partially coplanar with the first substrate structure in a horizontal plane.

[0150] At 706 , the method includes forming a die electrically coupled to the first metallization structure and the first substrate.

[0151] Exemplary Electronic Devices

[0152] Figure 8 Various electronic devices that can be integrated with any of the above hybrid packages are illustrated. For example, a mobile phone device 802, a laptop device 804, a fixed location terminal device 806, and a wearable device 808 can include an integrated device 800 described herein. The integrated device 800 can be, for example, any of the substrates, integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and stacked package devices described herein. Figure 8 The devices 802, 804, 806, 808 shown are merely exemplary. Other electronic devices may also feature the integrated device 800, including but not limited to a group of devices (e.g., electronic devices) including a mobile device, a handheld personal communication system (PCS) unit, a portable data unit such as a personal digital assistant, a global positioning system (GPS) enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading device, a communication device, a smart phone, a tablet computer, a computer, a wearable device (e.g., a watch, glasses), an Internet of Things (IoT) device, a server, a router, an electronic device implemented in a motor vehicle (e.g., an autonomous vehicle), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0153] One or more components, processes, features and / or functions illustrated in Figures 1 to 6 (wherein Figure 5 includes 5A to 5K, and where Figure 6 includes 6A to 6I) may be rearranged and / or combined into a single component, process, feature or function, or implemented in several components, processes or functions. Additional elements, components, processes and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1 to 6 and their corresponding descriptions in the present disclosure are not limited to hybrid packages. In some embodiments, Figures 1 to 6 and their corresponding descriptions may be used to manufacture, create, provide and / or produce integrated devices. In some embodiments, the device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device and / or an interposer.

[0154] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "various aspects" does not require that all aspects of the disclosure include the discussed features, advantages, or modes of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact with each other.

[0155] Moreover, it should be noted that the various disclosures contained herein can be described as processes, which are depicted as flow charts, job diagrams, structure diagrams or block diagrams. Although flow charts can describe operations as sequential processes, many operations can be performed in parallel or concurrently. In addition, the order of operations can be rearranged. The process terminates when its operation is completed.

[0156] Without departing from the present disclosure, the various features of the present disclosure described herein can be implemented in different systems. It should be noted that the foregoing aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative, rather than limiting the scope of the claims. Therefore, this teaching can be easily applied to other types of devices, and many alternatives, modifications and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: Bare chips; a first substrate structure; as well as a first metallization structure at least partially coplanar with the first substrate structure, wherein the die is electrically coupled to the first metallization structure and the first substrate structure, wherein the first substrate structure is at least partially surrounded by the first metallization structure, and The first metallization structure has at least one of the following: a first thickness associated with a first plurality of interconnects of the first metallization structure, the first thickness being less than a second thickness associated with a plurality of substrate interconnects of the first substrate structure; and A first width associated with the plurality of vias of the first metallization structure is less than a second width associated with the plurality of substrate vias of the first substrate structure.

2. The package according to claim 1, wherein: The first metallization structure is at least partially coplanar with the first substrate structure in a horizontal plane, and The first metallization structure is adjacent to the first substrate structure. 3 . The package of claim 2 , wherein the first metallization structure and the first substrate structure are at least partially separated by a first molding. The package of claim 3 , wherein the first molding at least partially surrounds the first metallization structure and the first substrate structure.

5. The package according to claim 1, further comprising: A second metallization structure is electrically coupled to the die, the first substrate structure, and the first metallization structure.

6. The package according to claim 5, wherein: The die is electrically coupled to the first metallization structure through the second metallization and to the first substrate structure through the second metallization structure.

7. The package according to claim 1, further comprising: A second metallization structure is between the die and the first metallization structure and between the die and the first substrate structure.

8. The package according to claim 7, further comprising: a second molding at least partially covering the die; and The first side of the second molding is directly connected to the second metallization structure.

9. The package according to claim 8, further comprising: The second side of the second molding is directly connected to a third metallization structure configured to be coupled to a second package in a package-on-package configuration.

10. The package of claim 6, wherein: The first metallization structure is configured to provide an electrical path for data signaling, The second metallization structure is coupled to a ground signal, and The first substrate structure is configured to provide an electrical path for power.

11. The package of claim 10, wherein: The plurality of first interconnects include pads having the first thickness, and The plurality of substrate interconnects include pads having the second thickness. 12 . The package of claim 1 , wherein a top side of the first substrate structure is higher than a top side of the first metallization structure.

13. A package according to claim 1, wherein the package is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

14. A method of forming a package, comprising: forming a first metallization structure; forming a first substrate structure, the first substrate structure being at least partially coplanar with the first metallization structure in a horizontal plane and the first substrate structure being at least partially surrounded by the first metallization structure; as well as forming a die electrically coupled to the first metallization structure and the first substrate structure, The first metallization structure is formed to have at least one of the following: a first thickness associated with a first plurality of interconnects of the first metallization structure, the first thickness being less than a second thickness associated with a plurality of substrate interconnects of the first substrate structure; and A first width associated with the plurality of vias of the first metallization structure is less than a second width associated with the plurality of substrate vias of the first substrate structure.

15. The method according to claim 14, further comprising: A second metallization structure is formed and electrically coupled to the die, the first substrate structure, and the first metallization structure.

16. The method of claim 15, wherein: The die is electrically coupled to the first metallization structure through the second metallization and to the first substrate structure through the second metallization structure.

17. The method according to claim 16, further comprising: electrically coupling the second metallization structure to a ground signal; and Wherein the first metallization structure is an electrical path for signaling, and wherein the first substrate structure is an electrical path for power.

18. The method of claim 14, wherein: Forming the first metallization structure includes: forming the plurality of first interconnects, the plurality of first interconnects including pads having the first thickness, and Forming the first substrate structure includes forming the plurality of substrate interconnects, the plurality of substrate interconnects including pads having the second thickness.

19. The method of claim 18, wherein: Forming the first metallization structure includes: forming the plurality of vias having the first width, and Forming the first substrate structure includes forming the plurality of substrate vias having the second width.

20. The method of claim 14, wherein a top side of the first substrate structure is higher than a top side of the first metallization structure.

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