Method for manufacturing semiconductor light-emitting device

Abstract

The present disclosure relates to a method for manufacturing a semiconductor light-emitting device (METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE), which is a method for manufacturing a semiconductor light-emitting device by non-wire bonding. The method includes the following steps: preparing a semiconductor light-emitting diode and a supporting substrate; attaching the semiconductor light-emitting diode to the supporting substrate with a second electrical path exposed, so that a conductive bonding member covering the entire second semiconductor region is seamlessly bonded to a bonding layer; removing the substrate; and electrically connecting the remaining one of the first semiconductor region and the second semiconductor region to the second electrical path through deposition.

Description

Technical Field

[0001] The present disclosure generally relates to a method of manufacturing a semiconductor light emitting device, and more particularly, to a method of manufacturing a semiconductor light emitting device having an electrical path configured on a supporting substrate. A semiconductor light emitting device is a semiconductor light emitting device that generates light through the recombination of electrons and holes, such as a Group III compound (nitride, phosphide, arsenide) semiconductor light emitting device. Typically, a Group III nitride semiconductor is composed of a compound of Al(x)Ga(y)In(1-xy)N (0=x=1, 0=y=1, 0=x+y=1).

[0002] Furthermore, the present disclosure generally relates to a method for manufacturing an aluminum nitride template, and in particular, to a method for manufacturing an aluminum nitride template that is crack-free and has a low density of crystal defects. The aluminum nitride (AlN) template manufactured by the above method can be used to grow a semiconductor layer containing aluminum (Al), typically, it can be used to manufacture light-emitting diodes (LEDs), laser diodes (LDs), high electron mobility transistors (HEMTs), piezoelectric films, etc. In particular, it can be used for ultraviolet light-emitting devices (UV LEDs), semiconductor devices that emit short-wave ultraviolet (UVC) or deep ultraviolet (Deep UV). UVC or deep ultraviolet generally refers to light with a wavelength of 200nm to 340nm, and depending on the circumstances, it also refers to light with a wavelength of 200nm to 400nm. Among them, a semiconductor light-emitting device refers to a semiconductor optical device that generates light by the recombination of electrons and holes, for example, a group III nitride semiconductor light-emitting device. Group III nitride semiconductors are composed of Al x Ga y In 1-x-y The compound composition of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) does not exclude the possibility of containing other elements. The semiconductor light emitting device can have the form of a wafer or a chip. Background Art

[0003] This section provides background information related to the present disclosure which is not necessarily prior art.

[0004] Figure 1The figure shows an example of an ultraviolet light-emitting semiconductor device disclosed in U.S. Patent Gazette No. US9627580. The semiconductor light-emitting device includes: a growth substrate 10 (e.g., a sapphire substrate); an AlN layer 20 (e.g., AlN grown at high temperature (HT); a first semiconductor region 30 (e.g., an n-type AlGaN layer); an active region 40 (e.g., AlGaN / AlGaN MQWs) that generates light through recombination of electrons and holes; an electron blocking layer 50 (e.g., p-type AlGaN); a second semiconductor region 60 (e.g., p-type (Al)GaN); a first ohmic electrode 70 (e.g., Cr / Ni); a first pad electrode 75 (e.g., Au); a current spreading electrode 80 (e.g., a transparent electrode (indium tin oxide (ITO)) or a reflective electrode (Al / Ni)); and a second pad electrode 85 (e.g., Cr / Ni / Au or Au). Figure 1 The semiconductor light-emitting device shown in the embodiment uses a light-transmitting material as the current spreading electrode 80, and when the first pad electrode 75 and the second pad electrode 85 serve as wire bonding pads, it is called a lateral chip. When a reflective metal is used as the current spreading electrode 80, and when the first pad electrode 75 and the second pad electrode 85 serve as flip-chip pads, it is called a flip chip. Furthermore, when the growth substrate 10 is removed and the first pad electrode 75 is formed on the first semiconductor region 60 from which the growth substrate 10 is removed, it is called a vertical chip (e.g., U.S. Patent No. 10,263,140).

[0005] When manufacturing semiconductor devices that emit ultraviolet light, the aluminum content of the semiconductor regions 30, 40, 50, and 60 increases as the wavelength of the ultraviolet light decreases. Therefore, considering the thermal expansion coefficient and lattice constant, it is ideal to use an aluminum nitride substrate as the growth substrate 10. However, aluminum nitride substrates are too expensive and lack the light transmittance required for light-emitting devices. Therefore, a sapphire growth substrate 10, which is a single crystal of aluminum oxide (Al2O3) and has excellent light transmittance in the ultraviolet band, is used as an aluminum nitride template by forming an AlN layer 20 thicker than 2 microns on top of the growth substrate 10. However, in manufacturing this aluminum nitride template, if the tensile stress caused by the difference in lattice constant and thermal expansion coefficient between the sapphire growth substrate 10 and the HT-AlN layer 20 is not properly relaxed, fine microcracks will form within the 2-micron-thick AlN layer 20. Typically, at temperatures exceeding 1100°C, a 2D growth mode HT-AlN layer 20 is formed on top of a sapphire growth substrate 10. During this process, in addition to various frequently observed crystal defects (vacancies, dislocations, stacking faults, nanotubes, and inversion domains), cracks may also occur. To address this issue, a 3D growth mode HT-AlN layer 20 formation process is appropriately combined with a tensile stress-releasing mechanism by introducing multiple air voids into the interior of the HT-AlN layer 20 or at the interface between the sapphire growth substrates 10. This resolves the problem of minute microcracks. However, the HT-AlN layer 20 formed by this film formation process has both aluminum polarity (Al Polarity) and nitrogen polarity (N Polarity) crystallinity. In particular, the HT-AlN layer 20 has a rough surface. Therefore, it not only has an adverse effect on the crystal quality of the active layer of the subsequently formed light-emitting device, but also has an adverse effect on the quality (Quality) of the light-emitting device, such as the reliability (Reliability) and lifespan (Lifetime).

[0006] The paper (High-quality AlN epilayers grown on nitrided sapphire by metalorganic chemical vapor deposition, www.nature.com / scientificreports, published: 21 February 2017) discloses the following technique for forming a crack-free HT-AlN template: Before growing the HT-AlN layer 20 on the sapphire growth substrate 10, the growth substrate 10 is nitrided. This suppresses the nitrogen-polar AlN species in the HT-AlN layer 20 and overcomes the difference in lattice constant and thermal expansion coefficient between the sapphire growth substrate 10 and the HT-AlN layer 20. The nitridation treatment can be performed by flowing 2400 sccm of NH3 for 7 seconds at 950°C using metalorganic chemical vapor deposition (MOCVD). The HT-AlN layer 20 can be grown at a temperature above 850°C (e.g., 1200°C).

[0007] By applying this method, a crack-free AlN template with a thickness of 2 μm to 3 μm can be obtained. However, the threading dislocation density (TDD) of the HT-AlN layer 20 is currently as low as 10 9 cm -2 ~-10 10 cm -2 This means that the matrix of the aluminum-polar HT-AlN layer 20 still contains regions of nitrogen-polar AlN material with irregular distribution and size (i.e., inversion domains (ID)). The interface between the two polar AlN forms an inversion domain boundary (IDB). As mentioned above, this has a significant impact not only on the crystal quality of the active layer of the subsequently formed light-emitting device, but also on the reliability and lifespan of the light-emitting device. Therefore, technology is needed to minimize the presence of nitrogen-polar AlN in the HT-AlN layer 20.

[0008] Figure 21 This figure shows an example of a semiconductor light emitting device disclosed in U.S. Patent Publication No. 6329667. The semiconductor light emitting device includes: a first semiconductor region 5; active regions 61 and 62 (MQWs) that generate light by recombination of electrons and holes; an electron blocking layer 7; and a second semiconductor region 8. Figure 1Similarly, it may include a growth substrate, a first electrode, and a second electrode. A V-shaped pit generating layer 5a is disposed between the first semiconductor region 5 and the active regions 61 and 62. In the V-shaped pit generating layer 5a, V-shaped pits 49 are generated from threading dislocations 15 connected to the first semiconductor region 5 and formed in the active regions 61 and 62. This prevents carrier trapping by preventing the threading dislocations 15 from extending to the upper side of the semiconductor light-emitting device. Furthermore, holes 17 injected from the second semiconductor region 8 can pass through the V-shaped pits 49 and recombine with electrons 16 in the well layer 61 located near the first semiconductor region 5, thereby achieving a high-efficiency semiconductor light-emitting device. The electron blocking layer 7 also fills the V-shaped pits 49. The V-shaped pit generating layer 5a can be formed by growing a semiconductor layer at a low temperature (e.g., 600°C to 850°C).

[0009] Figure 22 This figure shows an example of a semiconductor light-emitting device disclosed in U.S. Patent Publication No. 9,184,344, which discloses an example of applying a V-shaped pit generating layer to an ultraviolet light-emitting semiconductor device. The semiconductor light-emitting device includes: a growth substrate 10; an n-type or unintentionally doped (UID; Un-Intentionally Doped) GaN layer 21', which serves as a buffer layer; a V-shaped pit generating layer 1000; + AlGaN layer 22', which serves as a first semiconductor region; n - AlGaN layer 23'; active region 30'; p-AlGaN layer 42', which serves as an electron blocking layer; p-layer (p-layer) 43', which serves as a second semiconductor region; first electrode 81; and second electrode 82. - The AlGaN layer 23' has a doping concentration relatively lower than n + The AlGaN layer 22', the V-shaped pit generating layer 1000 can also be arranged on the n - The V-pit generating layer 1000 may be made of AlN and may be undoped or doped with silicon (Si), with a doping concentration of 1*10 17 / cm 3 ~5*10 18 / cm 3 The V-pit density can be 2*10 8 / cm 2 ~2*10 9 / cm 2The V-shaped pit generating layer 1000 may have a thickness of 50 nm to 1000 nm and may be composed of a single layer or a multilayer film.

[0010] In order to Figure 21 and Figure 22 The semiconductor light emitting device shown in FIG. 1 forms a V-shaped pit, using the V-shaped pit generating layer 5 a, 1000. The basic principle of generating the V-shaped pit in the V-shaped pit generating layer 5 a, 1000 is to reduce the growth temperature of the V-shaped pit generating layer 5 a, 1000 ( Figure 14 The medium temperature is 600℃~850℃, Figure 15 However, in order to manufacture deep UV (C, B) LED chips composed of Al-rich AlGaN (AlGaN with an Al content of 30% or more) and AlN with a peak wavelength of less than 320nm, the crystallinity of AlN at the lower end adjacent to the growth substrate must be significantly improved, and AlN growth must be carried out at a high temperature of more than 1000℃. However, if Figure 15 The semiconductor light emitting device shown in FIG. 17 / cm 3 ~5*10 18 / cm 3 AlN doped with silicon at a doping concentration of 100 nm and grown at a growth temperature of 650°C to 950°C not only fails to obtain the required level of V-pit density, but also fails to obtain the high-quality aluminum-rich AlGaN and AlN films required for high-performance deep ultraviolet light-emitting semiconductor devices.

[0011] Therefore, in order to obtain high-quality thin films required for ultraviolet light-emitting semiconductor devices, a V-shaped pit generating layer is formed at a temperature above 1000°C. In order to form V-shaped pits at such a growth temperature, a 6*10 18 / cm 3 Silicon is doped at the above doping concentration.

[0012] Figure 25The figure shows an example of a semiconductor light-emitting chip in a lateral chip form, which includes: a substrate 100 (e.g., a sapphire substrate); a buffer region 200 (e.g., undoped GaN); a first semiconductor region 300 (e.g., Si-doped GaN) having a first conductivity; an active region 400 (e.g., InGaN / (In)GaN MQWs) that generates light through recombination of electrons and holes; a second semiconductor region 500 (e.g., Mg-doped GaN) having a second conductivity different from the first conductivity; a transparent conductive film 600 (e.g., ITO) for current diffusion; an electrode 700 (e.g., Cr / Ni / Au) that performs a pad function; and an electrode 800 (e.g., Cr / Ni / Au) that performs a pad function on the first semiconductor region 300 exposed by etching. The electrodes 700 and 800 receive electricity from an external power source through wire bonding.

[0013] Figure 26 This figure shows an example of a semiconductor light-emitting chip in the form of a flip-chip chip, the semiconductor light-emitting chip includes: a substrate 100; a first semiconductor region 300 having a first conductivity; an active region 400 that generates light by recombination of electrons and holes; a second semiconductor region 500 having a second conductivity different from the first conductivity; an electrode film 901 (e.g., Au), an electrode film 902 (e.g., Ni), and an electrode film 903 (e.g., Au) consisting of three layers, which is used to reflect light toward the substrate 100 side; and an electrode 800 that performs a pad function on the first semiconductor region 300 exposed by etching. The electrode films 901, 902, and 903 composed of three layers are connected to the electrode 800 through conductive paste, metal bonding, etc. to an external power supply substrate (e.g., a printed circuit board (PCB)) without wire bonding. The reflection function of the electrode films 901, 902, and 903 composed of three layers can be replaced by a dielectric material such as a distributed Bragg reflector (DBR) (e.g., U.S. Patent Gazette No. 9236524).

[0014] Figure 27 This figure shows an example of a semiconductor light-emitting chip in a vertical chip form. The semiconductor light-emitting chip includes: a first semiconductor region 300 having a first conductivity; an active region 400 generating light by recombination of electrons and holes; a second semiconductor region 500 having a second conductivity different from the first conductivity; a metal reflective film 910 for reflecting light toward the first semiconductor region 300; a bonding layer 920; a supporting substrate 930; an electrode 940 performing a pad function; and an electrode 800 performing a pad function on the first semiconductor region 300. Figure 26As shown in FIG, the electrode film 901, 902, and 903 composed of three layers is connected to the external power supply without wire bonding. Figure 25 The electrode 800 is connected to the external power supply by wire bonding. Of course, the electrode 800 can also be connected to the external power supply by metal deposition without using wire bonding (e.g., U.S. Patent Publication No. 10263140).

[0015] Horizontal chips and vertical chips are classified according to the way the current flows, and wire bonding and flip-chip bonding are classified according to the bonding method with the external power supply. A horizontal chip is a wire-bonded chip using two wires, and a vertical chip is a wire-bonded chip using one wire. If flip-chip chips are classified according to the way the current flows, they can be regarded as a type of horizontal chip. In the present disclosure, regardless of horizontal chips and vertical chips, chips that use wire bonding are referred to as wire bonding, and flip-chip chips and vertical chips that do not use wires are defined as non-wire-bonding chips. When wire-bonded chips are used to implement packaging, interposers, displays, etc., space for bonding wires is required, and therefore, it is difficult to implement a semiconductor light-emitting device with a small form factor. Therefore, when implementing a semiconductor light-emitting device with a small form factor, a non-wire-bonded chip is required.

[0016] Figure 28 and Figure 29 This is a diagram showing an example of a method for manufacturing a semiconductor light emitting device equipped with a non-wire bonding chip. First, as shown in FIG. Figure 28 As shown, it will be Figure 26 The semiconductor light emitting chip shown in FIG is mounted on a wiring substrate 1000. Specifically, after aligning the electrode films 901, 902, and 903 composed of three layers with the electrode pattern 1010 and aligning the electrode 800 with the electrode pattern 1020, the semiconductor light emitting chip is bonded to the wiring substrate 100 using stud bumps, paste, or eutectic metal 950 and 960. Figure 29 As shown, the substrate 100 is removed by laser, thereby completing a semiconductor light emitting device with a non-wire bonding chip.

[0017] Figure 30 and Figure 31 FIG. 1 is a diagram showing an example of a method for manufacturing a semiconductor light emitting device disclosed in U.S. Patent Publication No. 2006-0202223. First, as shown in FIG. Figure 30 As shown, in the manufacturing Figure 29In the process of the semiconductor light-emitting device shown in (Laser Lift-Off (LLO) process and the process thereafter), in order to prevent the semiconductor light-emitting chip A from breaking, before performing the LLO process, the semiconductor light-emitting chip A is attached to the supporting substrate S and an underfill material U is poured into the semiconductor light-emitting chip A and the supporting substrate S. Filling the space between the semiconductor light-emitting chip A and the supporting substrate S by pouring the underfill material U is a necessary factor in the process of performing the LLO process. Afterwards, as Figure 31 As shown in FIG, the semiconductor light emitting device is completed by removing the substrate 100. The electrode structure 900 is shown in FIG. Figure 26 and Figure 29 The electrodes 901, 902, and 903 shown in FIG. 1 are composed of three layers. As mentioned above, the electrode structure 900 can be formed by a metal reflective film structure, a dielectric reflective film structure, or a combination thereof.

[0018] Figures 32 to 40 The figure is a diagram illustrating a method for manufacturing a semiconductor light emitting device disclosed in U.S. Patent Gazette No. 10263140. Figure 31 and Figure 32 In order to solve the problem of the manufacturing method of the semiconductor light-emitting device shown in the (the process is performed at the chip level, so the process is long and complicated, and it is difficult to align the electrode structure 900 and the electrode 800 with the electrode patterns 1010 and 1020.), the following manufacturing method of the semiconductor light-emitting device is disclosed: a substrate removal process is performed at the wafer level, and after dividing into a plurality of semiconductor light-emitting chips, a semiconductor light-emitting device is manufactured.

[0019] Figures 32 to 36 An example of a method for manufacturing a semiconductor light emitting device disclosed in US Patent No. 10263140 is shown in FIG.

[0020] First, if Figure 32As shown, a semiconductor light-emitting device is prepared, which includes: a substrate 10 (e.g., sapphire, Si, AlN, AlGaN, SiC); a plurality of semiconductor regions, including a first semiconductor region 30 having a first conductivity (e.g., n-type GaN), a second semiconductor region 50 having a second conductivity different from the first conductivity (p-type GaN), and an active region 40 (e.g., InGaN / (In)GaN multiple quantum well structure (MQWs)) arranged between the first semiconductor region 30 and the second semiconductor region 50 and generating light by recombination of electrons and holes; a bonding layer 90; and a supporting substrate 101, which includes a first electrical path 91 and a second electrical path 92. A plurality of semiconductor regions 30, 40, 50 are bonded or joined to a supporting substrate 101 (e.g., SiC, AlSiC, AlN, AlGaN, GaN, sapphire, low temperature co-fired ceramic (LTCC), high temperature co-fired ceramic (HTCC)) via a bonding layer 90. The conductivity of the first semiconductor region 30 and the conductivity of the second semiconductor region 50 are interchangeable. When the active region 40 emits ultraviolet light, the first semiconductor region 30 and the second semiconductor region 50 are composed of AlGaN, and the active region 40 can be composed of AlGaN / AlGaN MQWs. As the peak wavelength reaches medium-wave ultraviolet (UVB) and UVC, the Al content increases. The bonding layer 90 can be manufactured by Figure 27 The semiconductor light-emitting chip shown in FIG is formed using a conventional wafer bonding method.

[0021] Afterwards, if Figure 33 As shown, the substrate 10 is separated and removed from the plurality of semiconductor regions 30, 40, and 50. When removing the substrate 10, known methods such as laser lift-off, wet etching using a sacrificial layer, grinding, and chemical-mechanical polishing (CMP) can be used.

[0022] Then, if Figure 34 As shown, in order to manufacture individual dies or chips at the wafer level (wafer level should be understood as a relative concept relative to chip level. Generally, wafer level refers to a state in which multiple semiconductor regions 30, 40, 50 are stacked on a substrate 10. Before the chip level, that is, before becoming a chip cut into a form for actual use, it should be understood as a state in which multiple semiconductor regions 30, 40, 50 on a substrate 10 are cut into blocks larger than the chip level.), isolation is achieved by removing a portion of the multiple semiconductor regions 30, 40, 50 to expose the bonding layer 90.

[0023] Afterwards, if Figure 35 As shown, the bonding layer 90 is removed to form a bonding layer-removed surface 102, exposing the second electrical path 92. When removing the bonding layer 90, known dry etching or wet etching methods can be used. The order of separating the plurality of semiconductor regions 30, 40, 50 into individual dies or chips and removing the bonding layer 90 does not necessarily follow this sequence. It is also possible to first remove the plurality of semiconductor regions 30, 40, 50 and the bonding layer 90 to form the bonding layer-removed surface 102, and then separate the plurality of semiconductor layers 30, 40, 50 into individual dies or chips.

[0024] Finally, if Figure 36 As shown, as needed, an insulating layer 110 (e.g., SiO2) is formed, and an electrical connection 93 is formed. The electrical connection 93 can be formed by depositing a metal that is widely used in semiconductor processes. The bonding layer 90 can be formed by configuring a bonding material on multiple semiconductor regions 30, 40, 50 and the supporting substrate 101, or by configuring a bonding material on only one side. The first electrical path 91 and the second electrical path 92 can be formed by inserting a conductive material after forming a hole in the supporting substrate 101, for example, by using electroplating. The first electrical path 91 and the second electrical path 92 can pass through the supporting substrate 101 from the beginning, or they can be exposed by grinding the supporting substrate 101. An example of the supporting substrate 101 is disclosed in U.S. Patent Gazette No. 2017-0317230.

[0025] Figure 37 Show Figure 36In an example of an electrical connection forming method shown in FIG, a first electrical connection 91 is electrically connected to the first semiconductor region 30 via a bonding layer 90, thereby supplying electrons to the active region 40 via the first semiconductor region 30. A second electrical connection 92 is electrically connected to the second semiconductor region 40 via an electrical connection 93 and a first conductive layer 94, thereby supplying holes to the active region 40 via the second semiconductor region 50. The first conductive layer 94 is exposed by removing the plurality of semiconductor regions 30, 40, and 50, thereby being electrically connected to the electrical connection 93. Preferably, the first conductive layer 94 is composed of a material that diffuses current toward the second semiconductor region 50 and reflects light generated in the active region 40 toward the first semiconductor region 30. The first conductive layer 94 can be formed of Au, Pt, Ag, Al, Rh, Cr, Cu, Ta, Ni, Pd, Mg, Ru, Ir, Ti, V, Mo, W, TiW, CuW, ITO, ZnO, SnO2, In2O3, or alloys thereof, or a multilayer structure of two or more layers of these or their alloys. The electrical connection 93 can be formed of Au, Pt, Ag, Al, Rh, Cr, Cu, Ta, Ni, Pd, Mg, Ru, Ir, Ti, V, Mo, W, TiW, CuW, or alloys thereof, or a multilayer structure of two or more layers of these or their alloys. The bonding layer 90 includes a conductive bonding layer 96 disposed on the supporting substrate 101 and a second conductive layer 95 disposed on the plurality of semiconductor regions 30, 40, and 50 and connected to the first semiconductor region 30 by penetrating the second semiconductor region 50 and the active region 40. The second conductive layer 95 may be composed of a single substance, or the side in contact with the conductive bonding layer 96 may be composed of a separate substance suitable for bonding. The second conductive layer 95 is composed of a GaN material, a substance that forms an ohmic contact, and a substance that plays a bonding role. It can be formed by Au, Pt, Ag, Al, Rh, Cu, Ta, Ni, Pd, Ti, V, Mo, W, TiW, CuW, Sn, In, Bi, or their alloys, or a multilayer structure of more than two layers formed by them or their alloys. The conductive bonding layer 96 is composed of a material with excellent adhesion to the supporting substrate 101 and a substance that plays a bonding role. It can be formed by Ti, Ni, W, Cu, Ta, V, TiW, CuW, Au, Pd, Sn, In, Bi, or their alloys, or a multilayer structure of more than two layers formed by them or their alloys. Reference numerals 110 and 111 are insulating layers, and reference numerals 120 and 121 are conductive sheets.

[0026] Figure 38 Shows the formation Figure 36In another example of the electrical connection method shown in , the first conductive layer 94 is bonded to the conductive bonding layer 96 to form the bonding layer 90 , and the second conductive layer 95 is connected to the electrical connection 93 , thereby supplying current from the second electrical path 92 to the first semiconductor region 30 .

[0027] Figure 39 Shown to form Figure 36 In another example of an electrical connection method shown in , a conductive bonding layer 96 is bonded to a second conductive layer 94 to form a bonding layer 90. However, the second conductive layer 94 only participates in bonding and does not supply current to the first semiconductor region 30. A first electrical path 91 is electrically connected to the second semiconductor region 50 via the bonding layer 90 and the first conductive layer 95. In this case, the first conductive layer 95 can function as a reflective film and / or a current diffusion layer. Current supply to the first semiconductor region 30 can be achieved through an electrical connection 93 connecting the second electrical path 92 to the substrate removal surface 31.

[0028] Figure 40 Shown to form Figure 36 In another example of the electrical connection method shown in , before bonding, the second semiconductor region 50 and the active region 40 are removed from the plurality of semiconductor regions 30, 40, and 50, thereby forming a mesa surface 32 in the first semiconductor region 30. Furthermore, after forming the mesa surface 32, the plurality of semiconductor regions 30, 40, and 50 may be separated in advance. With this structure, after forming the mesa surface 32, the active region 40 can be provided with a protective layer (e.g., SiO2, which becomes part of the insulating layer 110), thereby improving device reliability in subsequent processes.

[0029] about Figure 30 and Figure 31 In the method shown in FIG, when performing the LLO process, the space between the semiconductor light emitting chip A and the supporting substrate S must be filled by pouring the bottom filling material U. As described above, Figures 32 to 40 In the method shown in , the entire surface of the plurality of semiconductor regions 30 , 40 , 50 is seamlessly bonded to the entire surface of the support substrate 101 , which is a very necessary factor for preventing the plurality of semiconductor regions 30 , 40 , 50 from being broken during the LLO process.

[0030] And, according to Figures 32 to 40 In the method shown in FIG, the alignment between the first electrical via 91 and the second electrical via 92 and the plurality of semiconductor regions 30, 40, 50 is also performed at the wafer level and can therefore be accomplished without difficulty.

[0031] However, after removing the substrate 10, it is necessary to electrically connect the second electrical path 92 to the plurality of semiconductor regions 30, 40, and 50. To this end, the bonded bonding layer 90 is removed to form a bonding layer removal surface 102, and the second electrical path 92 is electrically connected to the second semiconductor region 50 using an electrical connection 93. However, it is difficult to remove the sticky bonding layer 90. This is further complicated by the need to precisely expose the second electrical path 92 when manufacturing semiconductor light-emitting devices with small form factors (e.g., UVB and UVC CSPs). Summary of the Invention

[0032] Problems to be solved by the invention

[0033] This will be described later in the "Detailed Description of Implementation Methods".

[0034] Solutions for solving problems

[0035] This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features.

[0036] According to one aspect of the present disclosure, an ultraviolet light-emitting semiconductor device is provided, comprising: a plurality of semiconductor regions grown on a growth substrate, comprising a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting ultraviolet light through recombination of electrons and holes; an Al2O3-grown substrate; x Ga 1-x N (0.5≤x≤1) layer, which is configured below the first semiconductor region; and ID and IDB inhibition layer, which are configured between the growth substrate and the high temperature grown Al x Ga 1-x Between N (0.5≤x≤1) layers.

[0037] According to another aspect of the present disclosure, an ultraviolet light-emitting semiconductor device is provided. The ultraviolet light-emitting semiconductor device comprises: a plurality of semiconductor regions grown on a growth substrate, including a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting ultraviolet light through recombination of electrons and holes; an unintentionally doped Al x Ga 1-x An N (0.5≤x≤1) layer is configured on the first semiconductor region on the opposite side of the active region; a supporting substrate is configured on the second semiconductor region side and is used to support multiple semiconductor regions with the growth substrate removed; and a bonding layer is used to bond the multiple semiconductor regions to the supporting substrate.

[0038] According to another aspect of the present disclosure, a UV light emitting semiconductor device is provided. The UV light emitting semiconductor device includes: a plurality of semiconductor regions grown using a growth substrate, including a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting UV light through recombination of electrons and holes; a first AlN layer grown on the growth substrate; a stress adjustment layer; a second AlN layer disposed below the first semiconductor region; a first AlGaN region disposed in multiple layers on the first AlN region; and a plurality of AlGaN regions disposed on the first AlN region. Between the N layer and the stress adjustment layer, on the side contacting the first AlN layer, the N layer has an aluminum composition difference of within 20% with the first AlN layer, on the side contacting the stress adjustment layer, the N layer has an aluminum composition difference of within 20% with the stress adjustment layer, and on the side contacting the stress adjustment layer, the N layer has an aluminum composition difference of within 20% with the stress adjustment layer, and the multiple layers have an aluminum composition difference of within 20%; and a second AlGaN region, which is arranged between the stress adjustment layer and the second AlN layer in multiple layers, has an aluminum composition difference of within 20% with the stress adjustment layer on the side contacting the stress adjustment layer, has an aluminum composition difference of within 20% with the second AlN layer on the side contacting the second AlN layer, and the multiple layers have an aluminum composition difference of within 20%.

[0039] According to another aspect of the present disclosure, there is provided an ultraviolet light-emitting semiconductor device, comprising: a plurality of semiconductor regions grown on a growth substrate, comprising a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting ultraviolet light through recombination of electrons and holes; a first AlN layer grown on the growth substrate; a stress adjustment layer; an AlN layer; and a plurality of semiconductor regions. x Ga1-x N (0.5≤x≤1) layer, which is configured below the first semiconductor region; a first AlGaN region, which is configured in multiple layers between the first AlN layer and the stress adjustment layer, has an aluminum composition difference of less than 20% with the first AlN layer on the side adjacent to the first AlN layer, and has an aluminum composition difference of less than 20% with the stress adjustment layer on the side adjacent to the stress adjustment layer, and the multiple layers have an aluminum composition difference of less than 20%; and a second AlGaN region, which is configured in multiple layers between the stress adjustment layer and the AlN layer. x Ga 1-x Between the N (0.5≤x≤1) layers, on the side in contact with the stress adjustment layer, there is an aluminum composition difference of less than 20% with the stress adjustment layer, and on the side in contact with the Al x Ga 1-x The side connected to the N (0.5≤x≤1) layer and Al x Ga 1-x The N (0.5≤x≤1) layers have an aluminum composition difference within 20%, and the multiple layers each have an aluminum composition difference within 20%.

[0040] According to another aspect of the present disclosure, a method for manufacturing an aluminum nitride template is provided, the method comprising the following steps: preparing a growth substrate; growing Al on the growth substrate; 1-v-w Ga v In w N (0≤v<1, 0≤w<1, v+w<1) layer; 1-v-w Ga v In w Gallium (Ga) and indium (In) in the N (0≤v<1, 0≤w<1, v+w<1) layer decompose and evaporate to form a porous Al with multiple voids. 1-v-w Ga v In w N (0≤v<1, 0≤w<1, v+w<1) layer is etched; and in porous Al 1-v-w Ga v In w An AlN layer is grown on the N (0≤v<1, 0≤w<1, v+w<1) layer.

[0041] According to another aspect of the present disclosure, a method for manufacturing an ultraviolet light-emitting semiconductor device is provided. The ultraviolet light-emitting semiconductor device includes a plurality of semiconductor regions, the plurality of semiconductor regions including a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting ultraviolet light having a peak wavelength of 320 nm or less through recombination of electrons and holes. The method for manufacturing the ultraviolet light-emitting semiconductor device includes the following steps: growing the first semiconductor region; 18 / cm 3 ~5*10 19 / cm 3 A V-shaped pit generating layer having a V-shaped pit is grown at a doping concentration within a range of 1:1; the active region is grown while maintaining the V-shaped pit; and the second semiconductor region is grown on the active region.

[0042] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor light-emitting device is provided, which is a method for manufacturing a semiconductor light-emitting device without wire bonding. The method for manufacturing the semiconductor light-emitting device includes the following steps: preparing a semiconductor light-emitting diode and a supporting substrate, wherein the semiconductor light-emitting diode is individualized from a wafer state and is configured with a substrate, multiple semiconductor regions (the multiple semiconductor regions include a first semiconductor region having a first conductivity, an active region that generates light by recombination of electrons and holes, and a second semiconductor region having a second conductivity different from the first conductivity), and a conductive bonding member electrically connected to one of the first semiconductor region and the second semiconductor region and formed throughout the second semiconductor region; the supporting substrate is configured with an upper surface and a lower surface, a first electrical path and a second electrical path connected from the upper surface to the lower surface side, and a bonding layer on the upper surface that is electrically connected by covering the first electrical path; attaching the semiconductor light-emitting diode to the supporting substrate with the second electrical path exposed so that the conductive bonding member covering the entire second semiconductor region is seamlessly bonded to the bonding layer; removing the substrate; and electrically connecting the remaining one of the first semiconductor region and the second semiconductor region to the second electrical path by deposition.

[0043] Effects of the Invention

[0044] This will be described later in the "Detailed Description of Implementation Methods". BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a diagram showing an example of an ultraviolet light emitting semiconductor device disclosed in U.S. Patent No. 9,627,580.

[0046] Figure 2 This is a diagram showing an example of the ultraviolet light emitting semiconductor device disclosed in the present invention.

[0047] Figure 3 This is a diagram showing still another example of the ultraviolet light emitting semiconductor device disclosed herein.

[0048] Figure 4 This is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed in the present invention.

[0049] Figure 5 This is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed herein.

[0050] Figure 6 This is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed in the present invention.

[0051] Figure 7 This is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed in the present invention.

[0052] Figure 8 This is a diagram showing an example of a semiconductor light-emitting device disclosed in U.S. Patent No. 10263140.

[0053] Figure 9 This is a diagram showing an example of a semiconductor light-emitting device in the form of a semiconductor chip according to the present disclosure.

[0054] Figure 10 To show Figure 9 A diagram showing a specific example of a semiconductor light emitting device shown in .

[0055] Figure 11 To show Figure 9 FIG. 2 is a diagram showing another specific example of the semiconductor light emitting device shown in FIG.

[0056] Figure 12 To show Figure 9 FIG. 2 is a diagram showing another specific example of the semiconductor light emitting device shown in FIG.

[0057] Figure 13 To show Figure 9 There is another specific example of the semiconductor light emitting device shown in FIG.

[0058] Figure 14 This is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed in the present invention.

[0059] Figure 15 For illustration purposes Figure 14 Graph showing the curvature variation during growth of the ultraviolet light-emitting semiconductor device shown in FIG.

[0060] Figure 16 and Figure 17 FIG. 1 is a diagram illustrating an example of a method for manufacturing an aluminum nitride template according to the present disclosure.

[0061] Figure 18 To show Figure 17 FIG. 1 is a diagram showing an example of a method for producing an aluminum nitride template.

[0062] Figure 19 To show Figure 17 FIG. 2 is a diagram showing another example of a method for manufacturing an aluminum nitride template.

[0063] Figure 20 To show Figure 17 FIG. 2 is a diagram showing another example of a method for producing an aluminum nitride template.

[0064] Figure 21 This is a diagram showing an example of a semiconductor light emitting device disclosed in U.S. Patent No. 6,329,667.

[0065] Figure 22 This is a diagram showing an example of a semiconductor light emitting device disclosed in U.S. Patent No. 9,184,344.

[0066] Figure 23 This is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed in the present invention.

[0067] Figure 24 A graph showing the extent of V-shaped pit formation according to doping concentration.

[0068] Figure 25 A diagram showing an example of a semiconductor light-emitting chip in a lateral chip form.

[0069] Figure 26 A diagram showing an example of a flip-chip semiconductor light-emitting chip.

[0070] Figure 27 A diagram showing an example of a vertical chip-type semiconductor light-emitting chip.

[0071] Figure 28 and Figure 29 A diagram illustrating an example of a method for manufacturing a semiconductor light-emitting device in which a non-wire-bonded chip is provided.

[0072] Figure 30 and Figure 31 This is a diagram showing an example of a method for manufacturing a semiconductor light-emitting device disclosed in U.S. Patent Publication No. 2006-0202223.

[0073] Figures 32 to 40 The diagram exemplifies a method for manufacturing a semiconductor light-emitting device disclosed in U.S. Patent No. 10263140.

[0074] Figure 41 and Figure 42 This is a diagram illustrating an example of a method for manufacturing a semiconductor light-emitting device according to the present disclosure.

[0075] Figure 43 and Figure 44 A diagram illustrating a specific example of the semiconductor light-emitting device disclosed herein.

[0076] Figure 45 This is a diagram showing another specific example of the semiconductor light emitting device disclosed herein. DETAILED DESCRIPTION

[0077] Hereinafter, the present disclosure will now be described in detail with reference to the accompanying drawing(s).

[0078] Figure 2 FIG is a diagram showing an example of the ultraviolet light emitting semiconductor device disclosed in the present invention, and Figure 1 Similarly, the ultraviolet light-emitting semiconductor device includes: a growth substrate 10 (e.g., sapphire), a high-temperature grown AlN layer 20, a first semiconductor region 30 (e.g., an n-type AlGaN layer), an active region 40 (e.g., AlGaN / AlGaN MQWs) that generates light through the recombination of electrons and holes, and a second semiconductor region 60 (e.g., p-type (Al)GaN). Preferably, an electron blocking layer 50 (e.g., p-type AlGaN) is included. Furthermore, between the high-temperature grown AlN layer 20 and the first semiconductor region 30, an ID and IDB suppression layer 21, a low-temperature grown AlN layer 22, and a high-temperature grown AlGaN layer are included. x Ga 1-x N (0.5≤x≤1) layer 23.

[0079] The ID and IDB suppression layer 21 can be formed by sputtering AlN material in an oxygen (O2) atmosphere. a N b O c The AlN layer 20 grown at high temperature is formed by oxygen surface treatment (plasma, annealing). Usually, the AlN layer 20 grown at high temperature is formed in a MOCVD device. In order to perform oxygen surface treatment on the AlN / sapphire template, it is taken out of the MOCVD device for oxygen surface treatment, or Al is directly deposited. a N b O cAfter that, other layers are grown again inside the MOCVD device. (1) In the oxygen surface treatment (Oxygen Surface Treatment) as an example of the process for the ID and IDB suppression layer 21, basically, in a small amount of oxygen (Oxygen) atmosphere, it is exposed to a high temperature of 500°C or more for more than 10 minutes. Preferably, when the AlN layer on the surface is promoted by activating oxygen molecules, the AlN layer is exposed to a high temperature of 500°C or more for more than 10 minutes. a N b O c Radio frequency (RF) plasma is used for the formation. (2) In the Al process as another example of the ID and IDB suppression layer 21 a N b O c During deposition, Al is deposited by a physical vapor deposition (PVD) process including sputtering. a N b O c Directly form a film of material, or deposit AlN material in an oxygen atmosphere to form Al a N b O c .

[0080] Compared to the high-temperature grown AlN layer 20, the relatively low-temperature grown AlN layer 22 (below 850°C) promotes the formation of an AlN layer with aluminum polarity without damaging the surface of the ID / IDB suppression layer 21. For example, the low-temperature grown AlN layer 22 is grown at a temperature of 550°C to 850°C, with a V / III ratio of 3000, using a 7.5 μmol / min TMAl MO source, and at a growth rate of 10 nm / min to a thickness of less than 50 nm. Film formation in an atmosphere containing a relatively high concentration of aluminum relative to nitrogen (N) is particularly advantageous for achieving an aluminum-polar surface. The low-temperature grown AlN layer 22 may be removed as needed.

[0081] High temperature grown Al x Ga 1-x The N (0.5≤x≤1) layer 23 provides a foundation for the growth of the first semiconductor region 30 and also minimizes stress by adjusting the difference in lattice constant between the underlying AlN templates 10, 20, 21, 22, 23 and the first semiconductor region 30. For example, film formation is performed at a growth temperature of 1100°C or higher and a low pressure (below 200 mbar) using a TMAl MO source at a flow rate of 2 to 60 μmol / min and a TMGa MO source at a flow rate of 10 to 40 μmol / min, with a V / III ratio of 200 to 40,000.

[0082] When Al is grown at high temperaturex Ga 1-x When the N (0.5≤x≤1) layer 23 grows to a predetermined thickness or more, the V / III ratio can be controlled by changing the ammonia flow rate at a fixed TMAl and TMGa MO source flow rate (μmol / min), and multiple pores (Air Void) are formed by repeating three-dimensional (3D) growth (the growth rate along the out-plane (z-axis direction) of the growth surface is greater than the growth rate along the in-plane (xy-axis direction) of the growth surface) and two-dimensional (2D) growth (the growth rate along the in-plane (xy-axis direction) of the growth surface is greater than the growth rate along the out-plane (z-axis direction)). For example, when the V / III ratio is 400-800, three-dimensional growth can be performed, and when the V / III ratio is 50-200, two-dimensional growth can be performed. By repeating growth and changing the V / III ratio, multiple pores can be formed while controlling their size and density. As a result, the Al growth including high temperature growth is alleviated. x Ga 1-x The thermomechanical stress of the N (0.5≤x≤1) layer 23 and the entire growth substrate 10 template is used to suppress micro cracks and the like.

[0083] The high-temperature grown AlN layer 20 can be formed as follows: after a basic nitridation or aluminum pre-flow (Alumination) process is performed on the upper part of the sapphire growth substrate 10 at a high temperature of above 1000°C, for example, under the conditions of a growth temperature above 1100°C, low pressure (below 200 mbar), and a V / III ratio of 1000 to 2000, the AlN layer 20 can be formed at a growth rate of 1 μm / h by adjusting the TMAl MO source at 10 μmol / min to 50 μmol / min and the ammonia flow rate at 900 sccm to 1200 sccm.

[0084] Figure 2 The ultraviolet light emitting semiconductor device of the present disclosure is shown in the epitaxial wafer form. Figure 1 Similarly, a lateral chip or flip-chip chip form can be formed by forming a first ohmic electrode 70 (e.g., Cr / Ni), a first pad electrode 75 (e.g., Au), a current diffusion electrode 80 (e.g., a transparent electrode (ITO) or a reflective electrode (Al / Ni)) and a second pad electrode 85 (e.g., Cr / Ni / Au or Au).

[0085] Figure 3 FIG. 1 is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed in the present invention. Figure 2Based on the ultraviolet light-emitting semiconductor device shown, the ultraviolet light-emitting semiconductor device includes an AlN layer 24 grown at a high temperature between the AlN layer 22 grown at a low temperature and the Al x Ga 1-x N(0.5 ≤ x ≤ 1) layer 23. As an example, under the conditions of a growth temperature above 1100 °C, a low pressure (below 200 mbar), and a V / III ratio of 1000 to 2000, a film is formed at a growth rate of 1 μm / h by adjusting the TMAl MO source from 10 μmol / min to 50 μmol / min and the ammonia flow rate from 900 sccm to 1200 sccm. In a fixed TMAl MO source flow rate (μmol / min), the V / III ratio can be controlled according to the change in the ammonia flow rate, and multiple pores can be formed by repeating three-dimensional growth and two-dimensional growth. As an example, when the V / III ratio is 400 to 800, three-dimensional growth can be performed, and when the V / III ratio is 50 to 200, two-dimensional growth can be performed. By repeating growth and V / III ratio change, the size and density of multiple pores can be controlled while forming them.

[0086] Figure 4 A diagram showing another example of the ultraviolet light-emitting semiconductor device of the present disclosure. Based on the ultraviolet light-emitting semiconductor device shown in Figure 3 the ultraviolet light-emitting semiconductor device includes a sacrificial layer 25 between the AlN layer 20 grown at a high temperature and the ID and IDB suppression layer 21. By disposing the sacrificial layer 25, the ultraviolet light-emitting semiconductor device (epitaxial wafer) can be used in the form of manufacturing a vertical chip structure. Preferably, the sacrificial layer 25 is removed by laser lift-off (LLO; Laser Liff-Off). Thus, the growth substrate 10 can be separated from multiple semiconductor layers (25 to 60). Of course, the sacrificial layer 25 can be removed by wet etching. The growth of the sacrificial layer 25 can be a single layer and an alternately stacked layer of AlN / Al y Ga 1-y N(0 < y ≤ 0.5), with a thickness of 1 μm or less, preferably 100 nm to 600 nm. The growth temperature is 1100 °C to 1200 °C, and the sacrificial layer 25 is grown while maintaining a V / III ratio of 2000 to 3000, a TMAl MO source of 60 μmol / min to 80 μmol / min, NH3 of 6000 sccm to 8000 sccm, and a growth rate of 1 μm / h. Al z Ga 1-z N(0.5 < z < 1) can also be used to replace the AlN constituting the sacrificial layer 25.

[0087] Figure 5 A diagram showing still another example of the ultraviolet light-emitting semiconductor device of the present disclosure. And Figure 4Unlike the ultraviolet light-emitting semiconductor device shown in FIG, a sacrificial layer 25 is configured between the low-temperature grown AlN layer 22 and the high-temperature grown AlN layer 24. In this case, the sacrificial layer 25, having an aluminum composition of less than 50%, is formed as a single layer or multiple layers on top of the low-temperature grown AlN layer 22 having an aluminum composition of 100%. This results in a significant difference in lattice constant values, generating thermomechanical stress and acting as a catalyst for the formation of various crystal defects (Crystalline Defects), including inversion domains and inversion domain boundaries, in the epitaxial structure of the ultraviolet light-emitting semiconductor device having an aluminum composition of more than 50% subsequently grown on top of the sacrificial layer 25. This problem can be addressed by configuring the ID and IDB suppression layer 21 and the low-temperature grown AlN layer 21 below the sacrificial layer 25.

[0088] Figure 6 FIG. 1 is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed in the present invention, and FIG. Figure 2 Unlike the ultraviolet light emitting semiconductor device shown in FIG, the ultraviolet light emitting semiconductor device includes a sacrificial layer 25 at the position of the high temperature grown AlN layer 20. Therefore, the sacrificial layer 25 not only performs the function of removing the growth substrate 10, but also performs the function of a seed for growing the semiconductor layer. Figure 3 Unlike the ultraviolet light-emitting semiconductor device shown in FIG, the ultraviolet light-emitting semiconductor device includes a high-temperature grown AlN layer 20 in place of a high-temperature grown AlN layer 24. The ID and IDB suppression layer 21 and the low-temperature grown AlN layer 22 serve to suppress crystal defects present in the sacrificial layer 25. Before forming the sacrificial layer 25, a nitridation treatment (Nitridation) or an aluminum pre-flow (Al Pre-flow; Alumination) process is preferably performed.

[0089] Figure 7 FIG. 1 is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed in the present invention, and FIG. Figure 6 Unlike the ultraviolet light-emitting semiconductor device shown in , the ultraviolet light-emitting semiconductor device includes a sacrificial layer 25 between the low-temperature grown AlN layer 22 and the high-temperature grown AlN layer 20. Preferably, before forming the ID and IDB suppression layers 21, a nitridation process or an Al pre-flow (Alumination) process is performed.

[0090] Figure 8This figure shows an example of a semiconductor light-emitting device disclosed in U.S. Patent Gazette No. 10263140. The semiconductor light-emitting device (in the form of a semiconductor chip; in the form of a growth substrate removed) includes a first semiconductor region 30, an active region 40, a second semiconductor region 50, a bonding layer 90, a first electrical connection 93, and a support substrate 101 provided with a first electrical path 91 and a second electrical path 92. The plurality of semiconductor regions 30, 40, 50 are electrically connected to the first electrical path 91 and the second electrical path 92 via the bonding layer 90 and the first electrical connection 93. While the support substrate 101 is bonded to the plurality of semiconductor regions 30, 40, 50 via the bonding layer 90, a growth substrate removal process (e.g., LLO) is performed on the sacrificial layer 25, thereby separating it from the plurality of semiconductor regions 30, 40, 50 and the support substrate 101. Figures 4 to 7 The growth substrate 10 is shown in FIG.

[0091] Figure 9 This is a diagram showing an example of a semiconductor light emitting device in the form of a semiconductor chip of the present disclosure. Figure 8 The process for manufacturing a semiconductor light emitting device shown in Figures 4 to 7 The product of the semiconductor light emitting device of the semiconductor epitaxial form shown in FIG. That is, the first semiconductor region 30 is configured with a high temperature grown Al x Ga 1-x N (0.5≤x≤1) layer 23. After removing the sacrificial layer 25, the high-temperature grown AlN layer 24, the low-temperature grown AlN layer 22, the ID and IDB inhibition layer 21, and the high-temperature grown AlN layer 20 are removed. For example, after removing the sacrificial layer 25 and the growth substrate 10 made of sapphire by the LLO process, the high-temperature grown AlN layer 24, the low-temperature grown AlN layer 22, the IDB inhibition layer 21, and the high-temperature grown AlN layer 20 are completely removed by the dry etching process until the high-temperature grown AlN layer is exposed. x Ga 1-x N (0.5≤x≤1) layer 23. At room temperature (25°C), argon (Ar), chlorine (Cl2), and boron chloride (BCl3) gases are flowed into the chamber of an inductively coupled plasma reactive ion etching (ICP-RIE) dry etching apparatus to maintain a total flow rate of 45 sccm. Furthermore, while adjusting the Ar flow rate to 10 sccm or less, the flow rates of Cl2 and BCl3 are adjusted in an appropriate ratio to perform etching to obtain a flat surface.

[0092] Preferably, in order to minimize the crystal defects (vacancies, dislocations, stacking faults, nanotubes) included in ID or IDB, the Al x Ga 1-xThe N (0.5≤x≤1) layer 23 is formed of a high resistance insulator that does not contain intentionally introduced impurities or dopants (Si, Mg). x Ga 1-x The N (0.5≤x≤1) layer 23 forms a rough surface 23S for improving the light extraction efficiency. According to the requirements, a low refractive index material (23P; SiO2, Al2O3, AlON, MgF, CaF, etc.) can be formed on the high temperature grown Al2O3 by PVD or CVD method. x Ga 1-x N (0.5≤x≤1) layer 23. High temperature grown Al with minimized crystal defects such as ID or IDB. x Ga 1-x The N (0.5≤x≤1) layer 23 not only plays a supporting role, so that the first semiconductor region 30, the active region 40, and the second semiconductor region 50, which are the core areas of the semiconductor light-emitting device (semiconductor chip form; the form without the growth substrate), can be protected from mechanical impacts that may occur during the LLO process and maintain structural stability, but also minimizes crystal defects such as ID or IDB in the growth process, which helps prevent the epitaxy of the semiconductor light-emitting device from being damaged when high current is applied.

[0093] The low refractive index material 23P helps to easily output the ultraviolet light (photon) generated by the semiconductor light emitting device (semiconductor chip form; form without the growth substrate) composed of a high refractive index of 2.0 or more to the air (refractive index 1.1). In particular, it is preferable to use a material having a refractive index less than that of Al grown at high temperature. x Ga 1-x A material having a refractive index of N (0.5≤x≤1) is formed into a film.

[0094] Figure 10 To show Figure 9 In the diagram of a specific example of a semiconductor light-emitting device shown in FIG, a first electrical path 91 is electrically connected to the first semiconductor region 30 via a bonding layer 90, and a second electrical path 92 is electrically connected to the second semiconductor region 50 via a first electrical connection 93. Reference numerals 110 and 111 denote insulating layers, and reference numeral 94 denotes a first conductive layer. A roughened surface 23S and a low-refractive-index material 23P may also be provided.

[0095] Figure 11 To show Figure 9 In the specific example of the semiconductor light emitting device shown in FIG, the first electrical path 91 is electrically connected to the second semiconductor region 50 through the bonding layer 90, and the second electrical path 92 is electrically connected to the first semiconductor region 30 through the first electrical connection 93. x Ga 1-xThe first semiconductor region 30 exposed by a portion of the N (0.5≤x≤1) layer 23 forms a first electrical connection 93. Reference numeral 110 is an insulating layer, and reference numeral 95 is a second conductive layer. Of course, a rough surface 23S and a low refractive index material 23P may be provided.

[0096] Figure 12 To show Figure 9 FIG. 1 shows another specific example of a semiconductor light emitting device, and FIG. Figure 10 The semiconductor light emitting device shown in FIG. 1 is different in that, instead of providing first and second electrical paths 91 and 92 on support substrate 101, an opening is formed in insulating layer 111 to form second electrical connection 96. First electrical connection 93 is electrically connected to second semiconductor region 50 via first conductive layer 94, and second electrical connection 96 is electrically connected to first semiconductor region 30 via bonding layer 90. First and second electrical connections 93 and 96 function as pads for wire bonding.

[0097] Figure 13 To show Figure 9 There is another specific example of a semiconductor light emitting device shown in FIG. Figure 12 Different from the semiconductor light emitting device shown in FIG, the first electrical connection 93 is electrically connected to the second semiconductor region 50 through the second conductive layer 95, and the second electrical connection 96 is electrically connected to the second semiconductor region 50 through the Al layer grown at high temperature. x Ga 1-x The N (0.5≤x≤1) layer 23 is electrically connected to the first semiconductor region 30. Preferably, the second electrical connection 96 is connected to the region with the highest doping concentration in the first semiconductor region 30. The first electrical connection 93 and the second electrical connection 96 function as pads for wire bonding.

[0098] Figure 14 This is a diagram showing another example of the ultraviolet light emitting semiconductor device disclosed in the present invention. The ultraviolet light emitting semiconductor device has Figure 5 The structure is similar to that of the ultraviolet light-emitting semiconductor device shown in , and the first AlGaN region A is configured to replace the low-temperature grown AlN layer 22, and the second AlGaN region B is configured between the sacrificial layer 25 and the high-temperature grown AlN layer 24. In this example, the high-temperature grown AlN layer 20 is referred to as the first AlN layer 20, the high-temperature grown AlN layer 24 is referred to as the second AlN layer 24, and the high-temperature grown Al x Ga 1-x The N (0.5≤x≤1) layer 23 is simply referred to as Al x Ga 1-x N (0.5≤x≤1) layer 23. When the sacrificial layer 25 is removed by laser lift-off process, for example, a laser light source with a wavelength of 248 nm is used. y Ga1- y When the multilayer structure is made of AlN, the y component of the sacrificial layer 25 is designed to have a value of 0.55 or less. In this case, there is an overall aluminum composition difference of more than 20% between the first AlN layer 20 and the second AlN layer 24 and the sacrificial layer 25, which will result in the upper part of the sacrificial layer 25, that is, the second AlN layer 24, AlN and AlN. x Ga 1-x The quality of the N (0.5≤x≤1) layer 23 and the first semiconductor region 30 is rapidly degraded, i.e., a large number of crystal defects (misfit dislocations (MDs)) (Defect reduced AlN and AlGaN as basic layers for UV LEDs; Viola Kuller; https: / / depositonce.tu-berlin.de / handle / 11303 / 4320).

[0099] While the aforementioned examples considered device improvement by suppressing the formation and generation of inversion domains or inversion domain boundaries, this example aims to improve device performance by considering the thermal expansion coefficient and thermomechanical stress. Specifically, the first AlGaN region A serves to prevent rapid aluminum composition changes exceeding 20% ​​by forming a multilayer structure between the first AlN layer 20 and the sacrificial layer 25, while the second AlGaN region B serves to prevent rapid aluminum composition changes exceeding 20% ​​by forming a multilayer structure between the sacrificial layer 25 and the second AlN layer 24. For example, if the first AlGaN region A consists of three layers, the first layer A1, which is in contact with the first AlN layer 20, has an aluminum composition of at least 80%, the third layer A3, which is in contact with the sacrificial layer 25, has an aluminum composition difference of less than 20% with the sacrificial layer 25, and the second layer A2, which is positioned between the first layer A1 and the third layer A3, has an aluminum composition difference of less than 20% with each of the first layer A1 and the third layer A3. If three layers are insufficient, four or more layers can be used. If two layers meet the requirements, two layers are sufficient. To summarize, the first AlGaN region A is composed of multiple layers, wherein the side contacting the first AlN layer 20 has an aluminum composition difference of within 20% with the first AlN layer 20, and the side contacting the sacrificial layer 25 has an aluminum composition difference of within 20% with the sacrificial layer 25. Furthermore, the first AlGaN region A is composed of multiple layers each having an aluminum composition difference of within 20%. If the second AlGaN region B is composed of three layers, the first layer B1 contacting the sacrificial layer 25 has an aluminum composition difference of within 20% with the sacrificial layer 25, the third layer B3 contacting the second AlN layer 24 has an aluminum composition difference of within 20% with the second AlN layer 24, and the second layer B2 disposed between the first layer B1 and the third layer B3 has an aluminum composition difference of within 20% with each of the first layer B1 and the third layer B3. To summarize, the second AlGaN region B is composed of multiple layers, wherein the side contacting the sacrificial layer 25 has an aluminum composition difference of less than 20% with the sacrificial layer 25, and the side contacting the second AlN layer 24 has an aluminum composition difference of less than 20% with the second AlN layer 24. Furthermore, the second AlGaN region B is composed of multiple layers each having an aluminum composition difference of less than 20%. Each layer A1, A2, A3, B1, B2, and B3, composed of a ternary AlGaN compound obtained using binary AlN and GaN compounds having substantially opposite gas-phase chemical properties, can be formed using MOCVD at a high temperature of 900°C or higher, a low pressure of 50 Torr to 200 Torr, and a high V / III ratio atmosphere containing a large amount of ammonia. The thickness of each layer A1, A2, A3, B1, B2, and B3 can be considered the thickness of the interface where crystal defects are introduced, that is, the critical thickness (T). c) is designed. In the case of omitting the second AlN layer 24, the second AlGaN region B is formed between the sacrificial layer 25 and the Al x Ga 1-x The N (0.5≤x≤1) layers 23 are formed to meet the same conditions. Preferably, the first AlGaN region A is in a form in which the aluminum component decreases as it approaches the upper side, and the second AlGaN region B is in a form in which the aluminum component decreases as it approaches the lower side, thereby forming a symmetrical structure with each other to achieve a balance of thermomechanical stresses. It has a structure symmetrical with the sacrificial layer 25 as the center, thereby alleviating or adjusting the tensile and compressive stresses caused by the lattice constant and thermal expansion coefficient, thereby preventing cracks. As mentioned above, preferably, the Al x Ga 1-x The N (0.5≤x≤1) layer 23 is intentionally doped, and ID and IDB suppression layers 21 may be provided. The first semiconductor region 30, active region 40, electron blocking layer 50, and second semiconductor region 60 constitute the light-emitting portion. As previously described, the first AlN layer 20 includes nanoscale voids (or holes, pores, trenches) to relieve tensile stress, or undergoes a high-temperature heat treatment process before growth, thereby introducing nanoscale surface roughness into the sapphire surface. In contrast, the second AlN layer 24 preferably does not include nanoscale voids (or holes, pores, trenches). This is because, if the second AlN layer 24 is retained in the final device, the nanoscale voids (or holes, pores, trenches) present in the retained second AlN layer 24 can perform the opposite function of absorbing light.

[0100] Figure 15 For illustration purposes Figure 14 The curvature variation during the growth of the ultraviolet light emitting semiconductor device shown in FIG, the growth substrate 10 (refer to Figure 14 ) is close to the threshold value (50 / km) for crack generation during the growth of the first AlN layer 20, and has a concave shape with less bending during the growth of the first AlGaN region A, a convex shape during the growth of the sacrificial layer 25, and a convex shape with less bending during the growth of the second AlGaN region B, and becomes a morphology close to a flat surface during the growth of the second AlN layer 24. This curvature behavior well illustrates the role of the second AlN layer 24 in terms of thermomechanical stress. It can be seen from this that by configuring the second AlN layer 24, compared to the case of simply growing only the first AlN layer 24 and the sacrificial layer 25, the AlN layer 24 is more stable than the first AlN layer 24. x Ga 1-xThe layer above the N(0.5≤x≤1) layer 23 can grow in a flatter state. The growth substrate 10 - the first AlGaN region A - the sacrificial layer 25 - the second AlGaN region B - the second AlN layer 24 can be regarded as a template for the growth of AlN-based nitrides. At this time, the thickness of the second AlN layer 24 can be 3 μm or more. By growing the second AlN layer 24 to 3 μm or more, crystal defects including dislocations from the growth substrate 10 can be eliminated to form a template with low-density defects. In Al x Ga 1-x When the aluminum composition x value of the N(0.5≤x≤1) layer 23 is close to 1, the second AlN layer 24 can be omitted. However, considering Figure 15 the curvature performance shown in, preferably, the second AlN layer 24 is configured. Al x Ga 1-x The N(0.5≤x≤1) layer 23 also functions to reduce the aluminum composition difference between the first semiconductor region 30 grown thereon and the second AlN layer 24.

[0101] Considering the curvature performance, Figure 15 the ultraviolet light-emitting semiconductor device shown in can be applied not only to the vertical chip removing the growth substrate 10 but also directly to the flip-chip. At this time, the sacrificial layer 25 functions as a stress adjustment layer (relieving stress by reducing the aluminum composition), and can be named accordingly. Of course, in the vertical chip, the sacrificial layer 25 also functions as a stress adjustment layer. However, in the flip-chip, the stress adjustment layer 25 is not finally removed, thus having the risk of absorbing the ultraviolet light generated in the active region 40. Therefore, preferably, it is composed of a single layer or multiple layers to have a higher aluminum composition than the active region 40. In addition, when the stress adjustment layer 25 is composed of AlN / Al y Ga 1-y N(0<y≤0.5) (of course, it can be composed of a single layer of AlGaN and multiple layers of AlGaN / AlGaN). If the aluminum composition is increased compared to the case of the sacrificial layer 25 in the vertical chip, compared to Figure 15 the case where the sacrificial layer 25 grows, the convex bending degree of the growth substrate 10 can be alleviated, so it also helps to improve the quality of the upper layer.

[0102] Figure 16 And Figure 17 FIG. is an example showing a method of manufacturing an aluminum nitride template according to the present disclosure. And Figure 14Differently, no sacrificial layer 25 is provided under the second AlN layer 24. Therefore, the second AlGaN region B for overcoming the difference in lattice constant and thermal expansion coefficient between the second AlN layer 24 and the sacrificial layer 25 is not required, and the first AlGaN region A is also not required. In this case, there is no crack-free structure, and a template (a structure with low defect density (e.g., middle 10) is still required by eliminating crystal defects including dislocations from the growth substrate 10 (e.g., sapphire, SiC)) is still required. 8 cm -2 ~low(low)10 9 cm -2 The second AlN layer 24 of TDD) Figure 3 In the example shown in , considering the generation and suppression of inversion domains or inversion domain boundaries, a proposal is made to dispose an ID and IDB suppression layer 21 and a low-temperature grown AlN layer 22 between a first AlN layer 20 and a second AlN layer 24. In this example, considering the relaxation or adjustment of tensile and compressive stresses, a method for manufacturing an aluminum nitride template is proposed in which a second AlN layer 24 having a thickness of 3 μm or greater is disposed.

[0103] First, if Figure 16 As shown in FIG, a method for forming a second AlN layer 24 on the first AlN layer 20 is discussed. As previously mentioned, the following methods have been proposed: ① During the film formation process, a plurality of air voids are formed in the first AlN layer 20 by adjusting the growth conditions; ② Before film formation, a periodically nanoscale patterned sapphire substrate (NPSS) is fabricated on the surface of the growth substrate 10 by ex-situ photolithography, followed by formation of the first AlN layer 20; ③ After depositing a sputtered AlN material as a seeding layer on the growth substrate 10, a high-temperature heat treatment (HTA) at a temperature of 1600°C or higher is performed; ④ During the film formation process, a small amount of gallium (less than 3%; acting as a surface surfactant) is injected into the AlN to promote lateral growth to relieve tensile stress. However, by applying only this method or a combination thereof, it is difficult to prevent cracks and ensure low defect density when the second AlN layer 24 exceeds the critical thickness (about 1.5 μm) and becomes thicker than 3 μm, that is, the thickness required to provide an AlN template for stable film formation.

[0104] In the paper (Fabrication of crack-free AlN film on sapphire by hydride vapor phase epitaxy using an in situ etching method; Xue-Hua Liu et al., Applied Physics Express 9, 045501 (2016)), the following method was proposed: 1) After forming the first AlN layer 20 by hydride vapor phase epitaxy (HVPE) at a temperature of 1400 °C, 2) Multiple voids (Air Voids) were formed by etching (at a temperature of 1550 °C in a hydrogen (H2) gas atmosphere for 2 minutes), 3) The second AlN layer 24 was formed again at a temperature of 1400 °C, thereby manufacturing an AlN template with an overall thickness of 5 μm, and a method was proposed to prevent cracks in the second AlN layer 24 and reduce crystal defects in the AlN template by using this method.

[0105] However, the method applied in the paper uses the HVPE method and is difficult to apply to the MOCVD method. Also, in order to etch the AlN thin film material grown at a high temperature above 1200 °C, an etching temperature (Te; above 1300 °C) that is 100 °C or more higher than the film formation temperature (Tg; above 1200 °C) was used. In the case of the MOCVD method, in reality, it is difficult to apply an etching temperature (Te) that is 100 °C or more higher than the film formation temperature (Tg) of AlN grown at a high temperature above 1200 °C to a commercial MOCVD device.

[0106] In Figure 17 it, an Al 1-v Ga v N(0 < v < ½) layer 20a was configured to replace the first AlN layer 20. The Al 1-v Ga v N(0 < v < ½) layer 20a has a porous structure that performs the same function as multiple pores and can be named a porous Al 1-v Ga v N(0 < v < ½) layer 20a. Hereinafter, the second AlN layer 24 will be simply referred to as the AlN layer 24. According to requirements, a seed layer 20b (Nucleation Layer) that performs a seed function may also be included between the growth substrate 10 and the Al 1-v Ga v N(0 < v < ½) layer 20a. AlInN or AlGaInN can be used instead of AlGaN, and the Al 1-v Ga v N(0 < v < ½) layer 20a can be extended to Al1-v-w Ga v In w an AlGaN layer 20a where 0≤v<1, 0≤w<1, and v + w<1. As an example of a device that can be placed on the AlN templates 10, 20a, and 24, similar to Figure 14 a first semiconductor region 30, an active region 40, an electron blocking layer 50, and a second semiconductor region 60 that form an ultraviolet light-emitting semiconductor device are formed on the upper part of the AlN layer 24.

[0107] When directly growing AlGaN on the growth substrate 10 or growing AlGaN on the growth substrate / AlN (thin film) instead of the first AlN layer 20, the following effects can be achieved: 1) the effect of suppressing the tensile stress that induces cracks due to an increase in the in-plane (C-plane) lattice constant (Lattice Constant, a) (replacing a part of Al with Ga), that is, the primary effect of strengthening the compressive stress in the Al(Ga)N grown on the upper part of the growth substrate, 2) the secondary effect of relieving the tensile stress of the Al(Ga)N thin film or thick film grown subsequently after forming porous AlN or porous AlGaN (the total amount of gallium components is significantly less than the total amount of gallium components for AlGaN growth) through the gallium decomposition and evaporation process inside the grown AlGaN, and 3) if growing gallium that is more than the AlGaN material constituting the MQW, that is, a Ga-rich AlGaN thin film, it will cause an adverse effect of absorbing the generated deep ultraviolet light, but using the concept of the present disclosure, the tertiary effect of suppressing or minimizing the absorption of deep ultraviolet light can be achieved.

[0108] Figure 18 To show Figure 17 an example of the manufacturing method of the aluminum nitride template shown in Figure 18 as shown in (a) of 1-v Ga v an AlGaN layer 20c where 0<v<1 is formed on the growth substrate 10 (e.g., sapphire, SiC). As described above, a seed layer 20b can be disposed between the growth substrate 10 and the Al 1-v Ga v N layer 20c where 0<v<1.

[0109] In the case where the seed layer 20b is in-situ AlN, the growth temperature is preferably a high temperature of 900 °C or higher, but can be in the range of 500 °C to 1300 °C, and the growth pressure in the chamber is preferably a low pressure as low as possible, but can be in the range of 20 mbar to 200 mbar. Preferably, before forming the seed layer 20b on the growth substrate 10, three-dimensional AlN islands are directly formed on the upper part of the growth substrate, that is, a three-dimensional growth mode. For this purpose, film formation is carried out at a relatively large V / III ratio (for example, 200 or more), that is, inside the MOCVD chamber, compared to a large amount of aluminum gas atmosphere (Al-rich ambient), film formation is carried out in a large amount of ammonia gas atmosphere (NH3-rich ambient). After forming the three-dimensional AlN islands, in order to complete the AlN seed layer 20b with a specified thickness in the subsequent process, preferably, film formation is carried out at a relatively small V / III ratio (for example, less than 200). In other words, inside the MOCVD chamber, compared to a large amount of ammonia gas atmosphere (NH3-rich ambient), film formation is carried out in a large amount of aluminum gas atmosphere (Al-rich ambient). The thickness of the seed layer 20b composed of AlN is preferably 200 nm or less. In the case of non-in-situ AlN(O), in a sputter system, preferably, at a temperature of 200 °C to 700 °C, AlN or an AlNO substance containing a small amount of oxygen (O2) is formed into a seed layer 20b with a thickness of 50 nm or less.

[0110] Al 1-v Ga v The film formation of the N(0 < v < 1) layer 20c can be carried out on the upper part of the growth substrate 10 or the seed layer 20b, and key adjustment parameters (parameters) that determine the degree of wafer bow in the growth process, substrate nitridation, NH3 flow, and the TMGa flow injected and added to the aluminum flow can be appropriately adjusted. Also, if the seed layer 20b is formed by in-situ or non-in-situ film formation, the thickness of the seed layer 20b has a great influence on the wafer bow, so the thickness of the seed layer 20b needs to be appropriately adjusted to prevent excessive wafer bow. The basic growth conditions are a temperature of 1100 °C or lower and a pressure of 200 mbar or lower. For example, at a growth temperature of 1050 °C and a growth pressure of 100 mbar, Al 1-v Ga vThe N(0 < v < 1) layer 20c is formed. Compared with a specific Al 1-v Ga v Regarding the thickness of the N(0 < v < 1) layer 20c and the gallium component content, it is very important to form the film by applying the following principle: if the injected added gallium component content increases, a relatively thin thickness is formed; if the injected added gallium component content decreases, a relatively thick thickness is formed.

[0111] When using Al 1-v-w Ga v In w to form the N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer 20c, different from the film formation of the Al 1-v Ga v N layer 20c, when injecting and adding indium components with a smaller chemical bonding energy (eV) with nitrogen compared to aluminum and gallium, it is necessary to significantly reduce the growth temperature. The basic growth conditions are a temperature below 1000 °C and a low pressure below 200 mbar. For example, at a growth temperature of 900 °C and a growth pressure of 100 mbar, it is possible to form the Al 1-v-w Ga v In w N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer 20c at a growth rate of 0.5 μm / h to 2 μm / h. Compared with a specific Al 1-v- w Ga v In w Regarding the thickness of the N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer 20c and the gallium and indium component contents, it is very important to form the film by applying the following principle: if the injected added gallium and indium component contents increase, a relatively thin thickness is formed; if the injected added gallium and indium component contents decrease, a relatively thick thickness is formed.

[0112] After that, as shown in (b) of Figure 18 multiple voids V are formed in the Al 1-v Ga v N(0 < v < 1) layer 20c (refer to (a) of Figure 18 ), making the Al 1-v Ga v N(0 < v < 1) layer 20c become a porous Al 1-v Ga v N(0 < v < 1) layer 20a. The multiple voids V can be formed by heating above the Al 1-v Ga v N(0 < v < 1) layer 20c to the porous Al 1-v Ga vGrowth temperature Tg of the N(0 < v < 1) layer 20a is etched at the etching temperature Te for Al 1-v Ga v The N(0 < v < 1) layer 20c is formed by decomposition through etching. The etching can be carried out in a gas atmosphere containing hydrogen, and multiple voids V at the nanoscale can be formed through the gallium evaporation process. The multiple voids V formed by etching can have a depth spanning the entire porous Al 1-v Ga v N(0 < v < 1) layer 20a, and can also have a depth that only extends to a part, which can be changed according to the etching conditions. In the porous Al 1-v Ga v In the N(0 < v < 1) layer 20a, the component v of Ga depends on Al 1- v Ga v The component v of gallium in the N(0 < v < 1) layer 20c and the etching conditions, and can also be formed in a manner close to AlN. Most preferably, it is an AlN material layer that does not contain gallium and / or indium components at all and forms multiple voids V. In order to minimize light absorption, it is necessary to be less than the gallium and / or indium components contained in the MQW of light-emitting devices such as LEDs or LDs with continuous film formation. As an example, if the N(0 < v < 1) layer 20c is formed at a temperature of 1050 °C and a low pressure of 100 mbar for Al 1-v Ga v The etching can be carried out in a separate hydrogen atmosphere or a hydrogen atmosphere containing a specified amount of ammonia at a temperature of 1150 °C and a pressure of 50 mbar.

[0113] Finally, as shown in (c) of Figure 18 On the porous Al 1-v Ga v The AlN layer 24 is grown on the N(0 < v < 1) layer 20a. As described below, according to the purpose of use, the growth conditions of the AlN layer 24 can vary according to two cases.

[0114] First, in order to further strengthen the three-dimensional growth mode (rough surface) and control cracks by more tensile stress relief and increase the thickness of the continuous film-forming AlN template, preferably, ① set the growth temperature to 1100 °C or below and set the V / III ratio in a relatively low manner, or ② set the growth temperature to 1300 °C or above and set the V / III ratio in a relatively large manner. The thickness is preferably 100 nm to 3.5 μm.

[0115] Thereafter, in order to smooth the surface by further strengthening the two-dimensional growth mode (smooth surface), preferably, ① the growth temperature is set to be above 1300 °C, and the V / III ratio is set in a relatively low manner, or ② the growth temperature is set to be below 1100 °C, and the V / III ratio is set in a relatively large manner. The thickness is preferably 10 nm to 2 μm.

[0116] Figure 19 To show Figure 17 Another example of the manufacturing method of the aluminum nitride template shown in Figure 19 As shown in (a) of 1-v Ga v After forming the porous Al 1-v Ga v N(0 < v < 1) layer 20a-1, then form an Al Figure 19 As shown in (b) of 1-v Ga v After forming the porous Al Figure 19 After repeating this process the required number of times n, as shown in (c) of 1-v Ga v N(0 < v < 1) layer 20c is formed. The aluminum component of each of the layers 20c-1 and 20c-2 can also be increased as it approaches the AlN layer 24 by adjusting the gallium decomposition and evaporation of each of the layers 20c-1 and 20c-2. The number of repetitions is not particularly limited, but it is determined considering the crystallinity of the AlN thin film. In particular, it can be repeated until the full width at half maximum (FWHM) of the X-ray rocking curve (XRC) AlN(0002) and AlN(102) spectra peaks can ensure a value below 300 arcsec. The basic growth conditions are a temperature below 1100 °C and a low pressure below 200 mbar. As an example, at a growth temperature of 1050 °C and a growth pressure of 100 mbar, the Al 1-v Ga v N(0 < v < 1) layer 20c is formed at a growth rate of 0.5 μm / h to 2 μm / h. Compared with the thickness and gallium component amount of a specific Al 1-v Ga v N(0 < v < 1) layer 20c, if the amount of the injected and added gallium component increases, a relatively thin thickness is formed, and if the amount of the injected and added gallium component decreases, a relatively thick thickness is formed. As an example, at a temperature of 1050 °C and a low pressure of 100 mbar, if the Al 1-v Ga v N(0 < v < 1) layer 20c is formed, the etching can be performed at a temperature of 1150 °C and a pressure of 50 mbar in a separate hydrogen atmosphere or a hydrogen atmosphere containing a specified amount of ammonia.

[0117] Figure 20 To show Figure 17 Another example of a method for manufacturing an aluminum nitride template shown in, as Figure 20 (a) of shows, after forming a porous Al 1-v Ga v N (0 < v < 1) layer 20a-1 and an AlN layer 24-1, an Al 1-v Ga v N (0 < v < 1) layer 20c-2 is formed. Then, as Figure 20 (b) of shows, a porous Al 1-v Ga v N (0 < v < 1) layer 20a-2 is formed by etching. Next, as Figure 20 (c) of shows, an AlN layer 24-2 is formed again. This process is repeated the required number of times n. The thickness of the last-formed nth AlN layer 24-n is formed to be thicker than the thicknesses of the previous AlN layers 24-1 to 24-n-1, thereby constituting an AlN template. When forming the porous Al 1-v Ga v N (0 < v < 1) layer 20a-1 and the porous Al 1-v Ga v N (0 < v < 1) layer 20a-2, the film formation conditions and the number of repetitions shown in Figure 19 can be directly used, and the thicknesses of the AlN layer 24-1 and the nth AlN layer 24-n can be adjusted in consideration of the thickness of the entire AlN layer. The AlN layers 24-1 to 24-n-1 can be referred to as AlN intermediate layers, and the AlN intermediate layers 24-1 to 24-n-1 can each have a thickness of 100 nm or less.

[0118] Figure 23 To show another example of an ultraviolet light-emitting semiconductor device of the present disclosure, the ultraviolet light-emitting semiconductor device includes: a growth substrate 10 (example: sapphire), a buffer layer 20a (example: a high-temperature-grown AlN layer 20), a first semiconductor region 30 (example: a single-layer n-type Al n Ga 1-n N (x < n) or a single pair or multiple pairs (pair) of n-type Al n Ga 1-n N / Al u Ga 1-u N (x < n < u)), a V-pit generation layer 31 (example: a single-layer AlN or Al e Ga 1-e N (x < e, 0.5 ≤ e < 1), a single pair or multiple pairs of Al z Ga 1-z N / Al j Ga[[ID=*60]] 1-jN(x < z < j ≤ 1), the entire Al content of the V - pit generation layer 31 is 50% or more, having a dopant (e.g., Si) doping concentration in the range of 6*10 18 / cm 3 ~5*10 19 / cm 3 range, a thickness in the range of 50 nm to 500 nm; it is difficult to adjust the size of the V - pit V in high - quality Al - rich AlGaN and AlN thin films to be 200 nm or more. The position of the V - pit generation layer 31 is very important. Preferably, it is arranged up to 500 nm below the lower end of the active region MQW. ), an active region 40 that generates light through the recombination of electrons and holes (e.g., 2 to 6 pairs of Al x Ga 1-x N / Al[[ID=?]] y Ga 1-y N(x < y) MQWs; a well layer with a thickness of 1 nm to 5 nm and a barrier layer with a thickness of 1.5 nm to 10 nm) and a second semiconductor region 60. Preferably, it includes an electron blocking layer 50 (e.g., a single - layer of Al h Ga 1-h N(y < h) or one or more pairs of Al h Ga 1-h N / Al g Ga 1-g N(y < h < g)). According to requirements, the buffer layer 20a may further include an AlN 20b that performs a seed function and a dislocation filtering layer 20c (Dislocation Filtering Layer; e.g., one or more pairs of Al m Ga 1-m N / Al s Ga 1-s N(n < m < s ≤ 1)), of course, the buffer layer 20a can be composed of the high - temperature - grown AlN layer 20, ID and IDB suppression layer 21, low - temperature - grown AlN layer 22, high - temperature - grown Al Figures 2 to 7 shown in, AlGaN layer 23 (0 ≤ x ≤ 0.5), high - temperature - grown AlN layer 24 and sacrificial layer 25. And, a first spacer layer 32 (e.g., a non - doped Al x Ga 1-x N(0.5 < p)) with a thickness of 20 nm to 60 nm can be arranged between the V - pit generation layer 31 and the active region 40, and a second spacer layer 52 (e.g., a non - doped Al p Ga 1-p N(p < q)) with a thickness of 10 nm to 50 nm can be arranged between the active region 40 and the electron blocking layer 50. The second semiconductor region 60 can be composed of a first hole injection layer 60a (e.g., a single - layer of p - type Al q Ga 1-q N(p < q)) with a thickness of 10 nm to 50 nm can be arranged between the active region 40 and the electron blocking layer 50. The second semiconductor region can be composed of a first hole injection layer 60a (e.g., a single - layer of p - type Al i Ga It should be noted that there seems to be some inconsistent or unclear notations in the original text (such as the repeated " y " without clear indication in the context). This translation is done as accurately as possible based on the existing text.1-i N(x < i < h) or single or multiple pairs of p-type Al i Ga 1-i N / Al v Ga 1-v N(x < i < v << h)), the second hole injection layer 60b (e.g., a single layer of p-type Al k Ga 1-k N(x < k < i) or single or multiple pairs of p-type Al k Ga 1-k N / Al w Ga 1-w N(x < k < w < i)) and the second contact layer 60c are formed. The second contact layer 60c (e.g., a single layer of p-type Al o Ga 1-o N(x < o) or single or multiple pairs of p-type Al o Ga 1-o [[ID=二十九]]N / Al f Ga 1-f N(x < o < f)) is a layer that contacts the second electrode 82 (refer to Figure 22 ). Considering this, the first semiconductor region 30 contacts the first electrode 81 (refer to Figure 22 ), so it can be called the first contact layer. Figure 23 The ultraviolet semiconductor device shown in Figures 9 to 13 can have the form of a lateral chip, a flip-chip, or a vertical chip. Of course, it can also have the form shown in Figures 9 to 13 . The V-shaped pit V is generated from the V-shaped pit generation layer 31 and formed to the active region 40 and the current blocking layer 50. For example, it can be formed with a depth of 50 nm to 500 nm and is filled with the first hole injection layer 60a. Of course, the current blocking layer 50 can fill the V-shaped pit V. In the V-shaped pit generation layer 31 (e.g., a single layer of AlN or Al e Ga 1-e N(x < e, 0.5 ≤ e < 1), single or multiple pairs of Al z Ga 1-z N / Al j Ga 1-j N(x < z < j ≤ 1), the total Al content of the V-shaped pit generation layer 31 is 50% or more, and it has 6 * 10 18 / cm 3 ~5 * 10 19 / cm 3When the dopant (e.g., Si) doping concentration is within a certain range and the thickness is within the range of 50 nm to 500 nm for a single layer, it can be formed at a temperature of 1000 °C to 1300 °C, a pressure of 50 mbar to 100 mbar, an Al molar ratio of 50 umole to 300 umole, and a V / III ratio of 30 to 200 or 800 to 5000. In the case of single pairs or multiple pairs, under the same conditions, it can be formed at a V / III ratio of 800 to 3000. The dislocation filtering layer 20c (e.g., single pair or multiple pairs of Al m Ga 1-m N / Al s Ga 1-s N (n < m < s ≤ 1) performs the function of reducing the number of a large number of threading dislocations (generated due to the difference in lattice constant and thermal expansion coefficient between the growth substrate 10 and the AlN material). In particular, its main function is to suppress the open-core dislocations that propagate parallel to the growth direction. Preferably, the first spacer layer 32 (e.g., undoped Al p Ga 1-p N (0.5 < p)) and the second spacer layer 52 (e.g., undoped Al q Ga 1-q N (p < q)) are usually not doped with dopants (Si, Mg), suppressing the phenomenon of dopants (Si, Mg) in the first semiconductor region sides 30, 31 and the second semiconductor region sides 50, 60 diffusing into the active region 40 during growth or long-term operation, thereby playing a role in improving performance and reliability. The first hole injection layer 60a (e.g., single layer of p-type Al i Ga 1-i N (x < i < h) or single pair or multiple pairs of p-type Al i Ga 1-i N / Al v Ga 1-v N (x < i < v << h)) is a layer that fills the V-shaped pit V and also plays a role in smoothly supplying holes to the well layer located below the active region 40 through the V-shaped pit V. Generally, in MQWs, the bottommost well layer and barrier layer are called the first well and barrier, and the topmost well layer and barrier layer are called the last well and barrier. In the absence of the V-shaped pit V, the light emission of the semiconductor light-emitting device mainly occurs in the last well and its nearby well layers. However, when the V-shaped pit V is formed starting from below the active region 40, holes can also be smoothly supplied to the first well and its nearby well layers, thereby achieving light emission, which is a necessary factor for realizing a high-output deep ultraviolet light-emitting semiconductor device. The second hole injection layer 60b (e.g., single layer of p-type Al k Ga1-k N(x < k < i), either singly or in multiple pairs, of p-type Al k Ga 1-k N / Al w Ga 1-w N(x < k < w < i)) performs the function of facilitating current spreading throughout the second semiconductor region 60.

[0119] Figure 24 A graph showing the degree of formation of V-shaped pits according to the doping concentration, showing that V-shaped pits cannot be well formed when the doping concentration is 5 * 10 18 / cm 3 or less. (a) is a graph when the doping concentration is 2 * 10 17 / cm 3 , (b) is a graph when the doping concentration is 1 * 10 18 / cm 3 , (c) is a graph when the doping concentration is 6 * 10 18 / cm 3 , (d) is a graph when the doping concentration is 2 * 10 19 / cm 3 .

[0120] Figure 41 and Figure 42 A graph showing an example of the manufacturing method of the semiconductor light-emitting device of the present disclosure. As Figure 41 shown, a plurality of semiconductor light-emitting regions 30, 40, 50 are bonded to a single support substrate 101. Each semiconductor light-emitting region 30, 40, 50 is disposed on the substrate 10, a buffer region 20 and a sacrificial layer 21 are disposed between the substrate 10 and the semiconductor light-emitting regions 30, 40, 50, and a conductive bonding member 98 is disposed on the opposite side thereof, which supplies power to the semiconductor light-emitting regions 30, 40, 50 while providing bonding (bonding). Different from what is shown in Figure 32 , the substrate 10, the buffer region 20, the sacrificial layer 21, the semiconductor light-emitting regions 30, 40, 50, and the conductive bonding member 98 are not in a wafer state, but are individualized from the wafer through a cutting process such as scribing and / or breaking. They are respectively called semiconductor light-emitting diodes A, B (Semiconductor Light Emitting Die). As will be described later, in the present disclosure, the semiconductor light-emitting diodes A, B are different from the semiconductor light-emitting chip A shown in Figure 30 in that in the semiconductor light-emitting diodes A, B, both electrodes 800, 900 are not in an exposed form. That is, in the present disclosure, the semiconductor light-emitting diodes A, B are different from the semiconductor light-emitting chip (refer to Figure 30) and semiconductor light emitting chips (refer to Figure 32 ), forming two electrodes and being different from a semiconductor light emitting chip in which both electrodes are exposed to the outside, and also being different from a semiconductor light emitting wafer in which electrodes are not yet formed, or even if electrodes are formed, the substrate is not individualized by processes such as scribing and / or breaking. The semiconductor light emitting diodes A and B are in a state in which only one electrode is formed (refer to Figure 43 ), or even if two electrodes are formed, only one electrode may be exposed to the outside (see Figure 45 ).

[0121] The following description will be based on the semiconductor light emitting diode A.

[0122] The support substrate 101 is provided with a first electrical path 91 and a second electrical path 92, and a bonding layer 90 is provided on the first electrical path 91. The semiconductor light emitting diode A is bonded to the bonding layer 90 provided on the first electrical path 91. The bonding layer 90 is designed so that the entire bonding surface of the semiconductor light emitting diode A is placed on the bonding layer 90 without any gap. The bonding is performed using the bonding layer 90 and the conductive bonding member 98. With this structure, the semiconductor light emitting diode A is bonded to the bonding layer 90. Figure 30 and Figure 31 Unlike the semiconductor light emitting device shown in FIG, the gap between the semiconductor light emitting diode A and the support substrate 101 can be removed without the difficulty of aligning the electrodes and without a separate bottom filling material U. Figures 32 to 36 Unlike the semiconductor light emitting device shown in , the semiconductor light emitting device can be manufactured without difficulty in removing the adhesive bonding layer 90 on the second electrical path 92 .

[0123] Substrate 10 is typically a growth substrate, but this does not exclude a support substrate that is removed from the growth substrate and attached by wafer bonding. This support substrate differs from support substrate 101 in that first electrical paths 91 and second electrical paths 92 are not formed. Substrate 10 can be made of sapphire (single crystal Al2O3), sintered or polycrystalline Al2O3 (aluminum oxide), single crystal or polycrystalline AlN (aluminum nitride), single crystal silicon carbide (SiC), single crystal Si, and the like.

[0124] The semiconductor light-emitting regions 30, 40, and 50 are composed of a first conductive region 30, an active region 40, and a second conductive region 50. The composition of these regions can be varied depending on the wavelength of light emitted by the active region 40. The amounts of Al, In, and Ga in the Group III nitride semiconductor can be adjusted to suitably determine whether visible light (green, blue) or ultraviolet light (long-wave ultraviolet (UVA), UVB, and UVC) is emitted. Furthermore, they can be composed of Group III phosphide and / or arsenide semiconductors that emit red and infrared light.

[0125] In the buffer region 20 , the material forming the active region 40 is selected based on the wavelength of light. For example, when the active region 40 emits light with UVB or UVC peak wavelengths, it can be composed of a thick AlN layer (average thickness of about 3 μm) having a seed layer and air voids.

[0126] The sacrificial layer 21 is a layer that separates the substrate 10 from the semiconductor light emitting regions 30, 40, 50 during the LLO process. The sacrificial layer 21 can be made of Al x Ga 1-x N (0≤x≤1) is formed as a single layer or multiple layers. More preferably, when the substrate 10 is removed by laser separation in the subsequent process, a multilayer structure is better than a single layer that can effectively absorb the laser beam. For example, a multilayer structure is made of Al x Ga 1-x N (0≤x≤1) and Al y Ga 1-y At least two or more layers composed of N (0≤y≤1) are formed.

[0127] The conductive bonding member 98 will be described later together with a detailed example of the semiconductor light emitting diode A.

[0128] The bonding layer 90 can be made of any conductive material, but preferably one that can be soldered (joined at temperatures below 400°C) or brazed (joined at temperatures above 400°C). Representative materials include PdIn, AgIn, AuSn, NiSn, CuSn, AuSi, AuGe, porous noble metals, and Cu.

[0129] Preferably, as the support substrate 101, sapphire (single crystal Al2O3), sintered or polycrystalline Al2O3 (aluminum oxide), sintered or polycrystalline silicon nitride (SiN x), sintered or polycrystalline AlN (aluminum nitride), single crystal or polycrystalline electrically insulating silicon carbide (SiC), single crystal or polycrystalline electrically insulating diamond (Diamond), etc.

[0130] The first electrical path 91 and the second electrical path 92 can be formed by forming through-holes in an electrically insulating and thermally stable support substrate 101, then depositing an adhesion-strengthening layer material using a PVD process. Furthermore, as a continuous process, the through-holes are filled with copper (Cu) using an electroplating or electroless gold plating process. Preferably, the adhesion-strengthening layer material deposited by the PVD process is selected from two or more layers of Ti, Cr, Ni, Pd, Au, Cu, and the like.

[0131] Preferably, conductive sheets 120 and 121 are arranged on the lower surface 104 of the support substrate 101 so as to correspond to the first electrical path 91 and the second electrical path 92 , respectively.

[0132] Reference numeral 103 denotes the upper surface of the support substrate 101 .

[0133] Then, if Figure 42 As shown, the substrate 10 is removed and the residue removed by the LLO process, leaving only the semiconductor light-emitting regions 30, 40, and 50. An insulating layer 110 is formed by a passivation process, and the electrical connection 93 for electrically connecting the second electrical path 92 to the semiconductor light-emitting regions 30, 40, and 50 is formed by electrode deposition rather than wire bonding, thereby completing a semiconductor light-emitting device having a non-wire-bonded semiconductor light-emitting chip. Depending on the required specifications, the support substrate 101 can also be cut so that each semiconductor light-emitting diode A is configured, or the support substrate 101 is cut so that each semiconductor light-emitting diode A is configured. As needed, an etching process can be performed to remove a portion of the semiconductor light-emitting regions 30, 40, and 50, reduce their thickness, or form a roughened surface for light scattering. In order to ensure a stable bond between the insulating layer 110 and the bonding layer 90, as mentioned above, the top layer of the bonding layer 90 can be formed of a metal having good bonding strength with the insulating layer 110, such as Ti, Cr, Ni, V, or W. Before forming the insulating layer 110, it is preferably subjected to an oxygen plasma treatment or an annealing treatment in an oxygen atmosphere to strengthen the bonding strength with the insulating layer 110. As a material of high quality insulating layer 110 which is absolutely necessary for passivation and preventing electrical short circuits, SiN including SiO2 is preferred. x, Al2O3, Cr2O3, TiO2 and other metal oxides or nitrides with high voltage resistance, these substances can usually be formed by chemical vapor deposition methods such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or physical vapor deposition methods (PVD) such as sputtering and pulsed laser deposition (PLD). As a more preferred process, a liquid phase spin-on glass (SOG) or flowable oxide (FOx) material containing SiO2 material is spin-coated and formed by a curing process. This liquid phase spin coating process has great advantages in forming an insulating layer 110 that will not break and can fill gaps (Gap Filling). In the present disclosure, SOG and FOx substances are classified according to the carbon content. Generally, a liquid phase SiO2 insulating layer that does not contain carbon components is referred to as FOx.

[0134] The subsequent process and Figures 37 to 15 The process shown in the figure is no different and can be cut by Figures 37 to 39 The semiconductor light emitting wafer state shown in is used as the semiconductor light emitting diode of the present disclosure.

[0135] Figure 43 and Figure 44 This figure shows a specific example of the semiconductor light emitting device disclosed in the present invention. For the sake of convenience, the process of converting the semiconductor light emitting diode A into a chip form (the process of forming the electrical connection 93) is shown in the state of being bonded to the support substrate 101 (not shown). Figure 43As shown in (a), a semiconductor light emitting diode A is prepared. The semiconductor light emitting diode A includes a substrate 10, a buffer region 20, a sacrificial layer 21, semiconductor light emitting regions 30, 40, 50, an insulating layer 111, and a conductive bonding member 98. The conductive bonding member 98 is electrically connected to the semiconductor light emitting regions 30, 40, 50 through an opening formed in the insulating layer 111. In the example shown, the conductive bonding member 98 is electrically connected to the second semiconductor region 50. The conductive bonding member 98 includes a first conductive layer 94 and a second conductive layer 95. The first conductive layer 94 performs an electrode function for the second semiconductor region 50 and also performs a function as a reflective film. For UVB and UVC, the first conductive layer 94 can be made of a material such as Rh, Ni / Au, and for visible light and UVA, the first conductive layer 94 can have a structure such as Ag, Ni / Ag, ITO / Ag, ITO / DBR. Preferably, in order to prevent the diffusion of substances with the second conductive layer 95, the first conductive layer 94 further includes a diffusion barrier layer composed of Ti, Ni, Cr, V, Pt, W, TiW, TiN, CrN, VN, etc. The second conductive layer 95 provides a bonding function with the bonding layer 90 and can be composed of AuSn, NiSn, CuSn, PdIn, Au, Ag, Cu. Figure 43 As shown in (b), the substrate 10 is removed, and the residue is removed by etching to reduce the thickness of the first semiconductor region 30 and expose the insulating layer 111 (eg SiO2). Figure 43 As shown in (c), insulating layer 110 is formed. Importantly, insulating layer 110 is formed so as to be directly connected to exposed insulating layer 111. Since both insulating layers 110 and 111 are composed of insulating materials, their connection is structurally stable and reliably prevents electrical shorts. To distinguish between insulating layers 110 and 111, insulating layer 110 may be referred to as the first passivation layer.

[0136] Afterwards, if Figure 43 As shown in (c), an insulating layer 110 is formed. Figure 43 As shown in (d), a substrate-removed surface 31 having a rough surface for light scattering is formed in the first semiconductor region 30. Figure 43As shown in (e), an electrical connection 93 is formed. The electrical connection 93 is connected to the first semiconductor region 30. The electrical connection 93 formed through the upper portion of the first passivation layer or insulating layer 110 is performed by a photoresist photolithography and metal deposition process as a conventional semiconductor wafer fabrication process. The electrical connection 93 can be formed in a multilayer structure composed of Cr, Ti, Ni, V, Al, Pt, Au, Cu, etc. As required, Figure 43 As shown in FIG. 1 ( f ), a second passivation layer or insulating layer 112 is formed to passivate the electrical connection 93 .

[0137] Figure 45 To illustrate another specific example of the semiconductor light emitting device disclosed herein, first, as shown in FIG. Figure 45 As shown in (a), a semiconductor light emitting diode A is prepared. The semiconductor light emitting diode A includes a substrate 10, a buffer region 20, a sacrificial layer 21, semiconductor light emitting regions 30, 40, 50, an insulating layer 111, a first conductive layer 94, an insulating diaphragm or insulating layer 113, an insulating layer 114, and a conductive bonding member 98. If required, a conductive cap layer 114 may be added to prevent the electrical performance of the first conductive layer 94 from deteriorating. Figure 43 Different from (a), the conductive bonding member 98 is composed of a second conductive layer 95 and a third conductive layer 99. The second conductive layer 95 is electrically connected to the third conductive layer 99 through an opening V formed by penetrating the insulating layer 111 and the insulating diaphragm or the insulating layer 113. The third conductive layer 99 can be composed of a form such as Cr / Ti / Al / Ni / Au, and can be composed of a combination of a metal with good adhesion (Cr, Ti), a barrier metal (Ti, Ni, Pt), a metal with excellent reflectivity, and a metal with good bonding (Au). Afterwards, as Figure 45 As shown in (b), the substrate 10 is removed, and the residue is removed by etching to reduce the thickness of the first semiconductor region 30 and expose the insulating layer 111 (eg SiO2). Figure 45 As shown in (c), Figure 43 Similarly to (d), a substrate removal surface 31 having a rough surface for light scattering is formed on the first semiconductor region 30, and then the first passivation layer or insulating layer 110 is directly connected to the exposed insulating layer 111. Figure 45 As shown in (d), the first passivation layer or insulating layer 110, insulating layer 111, insulating membrane or insulating layer 113 are removed to form an electrical connection 93 connected to the exposed conductive cap layer 114 and / or the first conductive layer 94. Figure 45 In (d), the first conductive layer 94 is not connected to the electrical connection 93, but as shown in FIG. Figure 37As shown, they are electrically connected. Figure 43 As shown in FIG. 1 ( f ), an insulating layer 112 may be formed to passivate the electrical connection 93 .

[0138] Hereinafter, various embodiments of the present disclosure will be described.

[0139] (1) An ultraviolet light-emitting semiconductor device, comprising: a plurality of semiconductor regions grown on a growth substrate, including a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting ultraviolet light through recombination of electrons and holes; an Al2O3-based semiconductor layer grown at a high temperature; x Ga 1-x N (0.5≤x≤1) layer, which is configured below the first semiconductor region; and ID and IDB inhibition layer, which are configured between the growth substrate and the high temperature grown Al x Ga 1-x Between N (0.5≤x≤1) layers.

[0140] (2) The ultraviolet light emitting semiconductor device comprises: a first high temperature grown AlN layer, which is arranged between the growth substrate and the ID and IDB suppression layers; and a low temperature grown AlN layer, which is arranged between the ID and IDB suppression layers and the high temperature grown AlN layer. x Ga 1-x Between N (0.5≤x≤1) layers.

[0141] (3) The ultraviolet light emitting semiconductor device comprises: a first high temperature grown AlN layer, which is arranged between the growth substrate and the ID and IDB inhibition layers; a low temperature grown AlN layer, which is arranged between the ID and IDB inhibition layers and the high temperature grown AlN layer; x Ga 1-x N (0.5≤x≤1) layers; and a second high-temperature grown AlN layer.

[0142] (4) Ultraviolet light-emitting semiconductor devices on the growth substrate and high-temperature grown Al x Ga 1-x A sacrificial layer for removing the growth substrate is included between the N (0.5≤x≤1) layers.

[0143] (5) The ultraviolet light emitting semiconductor device comprises: a first high temperature grown AlN layer, which is arranged between the growth substrate and the ID and IDB inhibition layers; a sacrificial layer for removing the growth substrate; a low temperature grown AlN layer, which is arranged between the ID and IDB inhibition layers and the high temperature grown AlN layer; x Ga 1-x N (0.5≤x≤1) layers; and a second high-temperature grown AlN layer.

[0144] (6) The ultraviolet light emitting semiconductor device comprises: a first high temperature grown AlN layer, which is arranged between the growth substrate and the ID and IDB inhibition layers; a low temperature grown AlN layer, which is arranged between the ID and IDB inhibition layers and the high temperature grown AlN layer; x Ga 1-x N (0.5≤x≤1) layers; a sacrificial layer used to remove the growth substrate; and a second high-temperature grown AlN layer.

[0145] (7) The ultraviolet light-emitting semiconductor device includes: a sacrificial layer, which is arranged between the growth substrate and the ID and IDB inhibition layers, and is used to remove the growth substrate; an AlN layer grown at a low temperature, which is arranged between the ID and IDB inhibition layers and the AlN layer grown at a high temperature; x Ga 1-x N (0.5≤x≤1) layers; and a first high-temperature grown AlN layer.

[0146] (8) The ultraviolet light emitting semiconductor device includes: a low temperature grown AlN layer, which is arranged between the ID and IDB inhibition layers and the high temperature grown Al x Ga 1-x N (0.5≤x≤1) layers; a sacrificial layer used for removing the growth substrate; and a first high-temperature grown AlN layer.

[0147] (9) An ultraviolet light-emitting semiconductor device comprises: a plurality of semiconductor regions grown on a growth substrate, including a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting ultraviolet light through recombination of electrons and holes; an unintentionally doped Al x Ga 1-x An N (0.5≤x≤1) layer is configured on the first semiconductor region on the opposite side of the active region; a supporting substrate is configured on the second semiconductor region side and is used to support multiple semiconductor regions with the growth substrate removed; and a bonding layer is used to bond the multiple semiconductor regions to the supporting substrate.

[0148] (10) The ultraviolet light-emitting semiconductor device includes: a first electrical path that passes through a support substrate and is electrically connected to a first semiconductor region through a bonding layer; and a first electrical path that passes through the support substrate and is electrically connected to a second semiconductor region through a first electrical connection.

[0149] (11) The ultraviolet light-emitting semiconductor device includes: a first electrical path that passes through the supporting substrate and is electrically connected to the second semiconductor region through the bonding layer; and a first electrical path that passes through the supporting substrate and is electrically connected to the first semiconductor region through the first electrical connection.

[0150] (12) The ultraviolet light-emitting semiconductor device includes: a first electrical connection, which is configured as a wire bonding pad on the side facing the support substrate with the bonding layer as a reference, and is electrically connected to the second semiconductor region; and a second electrical connection, which is configured as a wire bonding pad on the side facing the support substrate with the bonding layer as a reference, and is electrically connected to the first semiconductor region through the bonding layer.

[0151] (13) The ultraviolet light emitting semiconductor device comprises: a first electrical connection, which is configured as a wire bonding pad on the side facing the support substrate with respect to the bonding layer and is electrically connected to the second semiconductor region; and a second electrical connection, which is configured as a wire bonding pad on the side facing the support substrate with respect to the bonding layer and is electrically connected to the second semiconductor region; xG a 1-x The N (0.5≤x≤1) layer is electrically connected to the first semiconductor region.

[0152] (14) A method for manufacturing the above-mentioned ultraviolet light-emitting semiconductor device.

[0153] (15) An ultraviolet light-emitting semiconductor device, comprising: a plurality of semiconductor regions grown on a growth substrate, including a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting ultraviolet light through recombination of electrons and holes; a first AlN layer grown on the growth substrate; a stress adjustment layer; a second AlN layer disposed below the first semiconductor region; a first AlGaN region disposed in multiple layers between the first AlN layer and the stress adjustment layer; Between the adjustment layers, on the side contacting the first AlN layer, the aluminum composition difference between the first AlN layer and the first AlN layer is within 20%, on the side contacting the stress adjustment layer, the aluminum composition difference between the stress adjustment layer and the stress adjustment layer is within 20%, and the multiple layers each have an aluminum composition difference within 20%; and a second AlGaN region, which is configured between the stress adjustment layer and the second AlN layer in multiple layers, has an aluminum composition difference between the stress adjustment layer and the stress adjustment layer on the side contacting the stress adjustment layer and the stress adjustment layer is within 20%, on the side contacting the second AlN layer, the aluminum composition difference between the second AlN layer and the second AlN layer is within 20%, and the multiple layers each have an aluminum composition difference within 20%.

[0154] (16) In the ultraviolet light-emitting semiconductor device, the stress adjustment layer is a sacrificial layer.

[0155] (17) Ultraviolet light-emitting semiconductor devices include Al x Ga 1-x The N (0.5≤x≤1) layer is disposed between the second AlN layer and the first semiconductor region.

[0156] (18) The ultraviolet light emitting semiconductor device includes an ID and IDB suppression layer, which is arranged between the first AlN layer and the first AlGaN region.

[0157] (19) In the ultraviolet light emitting semiconductor device, the decreased aluminum composition of the first AlGaN region and the increased aluminum composition of the second AlGaN region are symmetrical to each other.

[0158] (20) An ultraviolet light-emitting semiconductor device, comprising: a plurality of semiconductor regions grown on a growth substrate, including a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting ultraviolet light through recombination of electrons and holes; a first AlN layer grown on the growth substrate; a stress adjustment layer; an AlN layer; and a stress adjustment layer. x Ga 1-x N (0.5≤x≤1) layer, which is configured below the first semiconductor region; a first AlGaN region, which is configured in multiple layers between the first AlN layer and the stress adjustment layer, has an aluminum composition difference of less than 20% with the first AlN layer on the side adjacent to the first AlN layer, and has an aluminum composition difference of less than 20% with the stress adjustment layer on the side adjacent to the stress adjustment layer, and the multiple layers have an aluminum composition difference of less than 20%; and a second AlGaN region, which is configured in multiple layers between the stress adjustment layer and the AlN layer. x Ga 1-x Between the N (0.5≤x≤1) layers, on the side in contact with the stress adjustment layer, there is an aluminum composition difference of less than 20% with the stress adjustment layer, and on the side in contact with the Al x Ga 1-x The side connected to the N (0.5≤x≤1) layer and Al x Ga 1-x The N (0.5≤x≤1) layers have an aluminum composition difference within 20%, and the multiple layers each have an aluminum composition difference within 20%.

[0159] (21) The ultraviolet light emitting semiconductor device includes an ID and IDB suppression layer, which is arranged between the first AlN layer and the first AlGaN region.

[0160] (22) A method for manufacturing an aluminum nitride template, the method comprising the following steps: preparing a growth substrate; growing Al on the growth substrate; 1-v-w Ga v In w N (0≤v<1, 0≤w<1, v+w<1) layer; 1-v-w Ga v In wThe gallium and indium in the N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer decompose and evaporate to become porous Al with multiple voids 1-v- w Ga v In w etching is performed in the manner of the N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer; and on the porous Al 1-v-w Ga v In w an AlN layer is grown on the N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer.

[0161] (23) In the method for manufacturing an aluminum nitride template, before the step of growing the AlN layer, the steps of growing the Al 1-v-w Ga v In w N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer and the etching step are repeated multiple times. <l

[0162] (24) In the method for manufacturing an aluminum nitride template, the steps of growing the Al 1-v-w Ga v In w N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer, the etching step, and the step of growing the AlN layer are repeated multiple times.

[0163] (25) In the method for manufacturing an aluminum nitride template, before the step of growing the Al 1-v-w Ga v In w N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer, there is further included a step of forming a seed layer on the substrate.

[0164] (26) In the method for manufacturing an aluminum nitride template, the Al 1-v-w Ga v In w N(0 ≤ v < 1, 0 ≤ w < 1, v + w < 1) layer is an Al 1- vGa v N(0 < v < 1) layer.

[0165] (27) In the method for manufacturing an aluminum nitride template, before the nth grown AlN layer, the thickness of the AlN intermediate layers grown from the 1st to the n - 1st is 100 nm or less.

[0166] (28) A method for manufacturing an ultraviolet light-emitting semiconductor device, the ultraviolet light-emitting semiconductor device comprising a plurality of semiconductor regions, the plurality of semiconductor regions comprising a first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and an active region disposed between the first semiconductor region and the second semiconductor region and emitting ultraviolet light having a peak wavelength of less than 320 nm through recombination of electrons and holes, the method for manufacturing the ultraviolet light-emitting semiconductor device comprising the following steps: growing the first semiconductor region; growing the first semiconductor region at a growth temperature of more than 1000°C and a temperature of 6*10 18 / cm 3 ~5*10 19 / cm 3 A V-shaped pit generating layer having a V-shaped pit is grown at a doping concentration within a range of 1:1; the active region is grown while maintaining the V-shaped pit; and the second semiconductor region is grown on the active region.

[0167] (29) In the method for manufacturing an ultraviolet light-emitting semiconductor device, the V-pit generating layer has a thickness of 50 nm to 500 nm.

[0168] (30) In the method for manufacturing an ultraviolet light-emitting semiconductor device, the V-pit generating layer is composed of AlN.

[0169] (31) In the method for manufacturing an ultraviolet light-emitting semiconductor device, the entire Al content of the above-mentioned V-pit generating layer is greater than 50%.

[0170] (32) In the method for manufacturing an ultraviolet light-emitting semiconductor device, before the step of growing the active region, the method further includes the following steps: growing a first spacer layer, the first spacer layer being used to prevent the 6*10 18 / cm 3 ~5*10 19 / cm 3 The dopant of the V-shaped pit generating layer doped with a doping concentration in a range of 1:1 is diffused into the active region.

[0171] (33) A method for manufacturing a semiconductor light-emitting device, which is a method for manufacturing a semiconductor light-emitting device by non-wire bonding, the method for manufacturing the semiconductor light-emitting device comprising the following steps: preparing a semiconductor light-emitting diode and a supporting substrate, wherein the semiconductor light-emitting diode is individualized from a wafer state and is provided with a substrate, a plurality of semiconductor regions (the plurality of semiconductor regions include a first semiconductor region having a first conductivity, an active region that generates light by recombination of electrons and holes, and a second semiconductor region having a second conductivity different from the first conductivity), and a conductive bonding member electrically connected to one of the first semiconductor region and the second semiconductor region and formed throughout the entire second semiconductor region; the supporting substrate is provided with an upper surface and a lower surface, a first electrical path and a second electrical path connected from the upper surface to the lower surface side, and a bonding layer electrically connected on the upper surface by covering the first electrical path; in a state where the second electrical path is exposed, the semiconductor light-emitting diode is attached to the supporting substrate so that the conductive bonding member covering the entire second semiconductor region is bonded to the bonding layer without a gap; removing the substrate; and electrically connecting the remaining one of the first semiconductor region and the second semiconductor region to the second electrical path by deposition.

[0172] (34) In the method for manufacturing a semiconductor light emitting device, the conductive bonding member includes a first conductive layer in ohmic contact with the second semiconductor region and a second conductive layer bonded to the bonding layer.

[0173] (35) In the method for manufacturing a semiconductor light emitting device, the conductive bonding member includes a third conductive layer in ohmic contact with the first semiconductor region and a second conductive layer bonded to the bonding layer.

[0174] (36) In a method for manufacturing a semiconductor light-emitting device, in a semiconductor light-emitting diode, an insulating layer exposed after removing a substrate is arranged between the second semiconductor region and the second conductive layer.

[0175] (37) In the manufacturing method of a semiconductor light-emitting device, before the step of electrical connection, the following step is also included: forming a first passivation layer, and the above-mentioned first passivation layer is covered from above the multiple semiconductor regions through the insulating layer to the bonding layer.

[0176] (38) In the method for manufacturing a semiconductor light-emitting device, before the step of forming the first passivation layer, the method further includes the following step: performing an oxygen plasma treatment on the bonding layer or performing an annealing treatment on the bonding layer in an oxygen atmosphere.

[0177] (39) In the method for manufacturing a semiconductor light emitting device, the first passivation layer is formed by spin coating a flowable oxidizing material containing a SiO2 material.

[0178] According to the ultraviolet light emitting semiconductor device of the present disclosure, IDB can be suppressed.

[0179] Furthermore, according to the ultraviolet light emitting semiconductor device of the present disclosure, a semiconductor chip using an IDB suppression structure can be manufactured.

[0180] Furthermore, according to the ultraviolet light emitting semiconductor device of the present disclosure, an ultraviolet light emitting semiconductor device with reduced crystal defects of the device can be manufactured.

[0181] Furthermore, according to the method for manufacturing an aluminum nitride template disclosed herein, an aluminum nitride template having no cracks and a low density of crystal defects can be manufactured.

[0182] According to the ultraviolet light emitting semiconductor device disclosed herein, an ultraviolet light emitting semiconductor device provided with a V-shaped pit can be actually realized.

[0183] According to the manufacturing method of the semiconductor light emitting device disclosed in the present invention, the following semiconductor light emitting device can be manufactured: Figure 30 and Figure 31 Unlike the semiconductor light emitting device shown in FIG, the electrodes can be aligned without difficulty, and a separate bottom filling material U is not required. The gap between the semiconductor light emitting diode A and the supporting substrate 101 can also be removed. Figures 32 to 36 Unlike the semiconductor light emitting device shown in FIG, the adhesive bonding layer 90 on the second electrical path 92 can be removed without difficulty.

Claims

1. A method for manufacturing a semiconductor light-emitting device, which is a method for manufacturing a semiconductor light-emitting device by non-wire bonding, characterized in that: The steps include: A semiconductor light-emitting diode and a supporting substrate are prepared, wherein the semiconductor light-emitting diode is individualized from a wafer state and is provided with a substrate, a plurality of semiconductor regions, and a conductive bonding member electrically connected to one of a first semiconductor region and a second semiconductor region and formed throughout the second semiconductor region, the plurality of semiconductor regions including a first semiconductor region having a first conductivity, an active region that generates light by recombination of electrons and holes, and a second semiconductor region having a second conductivity different from the first conductivity; the supporting substrate is provided with an upper surface and a lower surface, a first electrical path and a second electrical path connected from the upper surface to the lower surface, and a bonding layer on the upper surface that is electrically connected by covering the first electrical path; Attaching the semiconductor light emitting diode to the supporting substrate in a manner such that the conductive bonding member covering the entire second semiconductor region is seamlessly bonded to the bonding layer, with the second electrical path exposed before the conductive bonding member is bonded to the bonding layer; removing the substrate; and The remaining one of the first semiconductor region and the second semiconductor region is electrically connected to the second electrical path through deposition.

2. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein: The conductive bonding member includes: a first conductive layer in ohmic contact with the second semiconductor region; and The second conductive layer is bonded to the bonding layer.

3. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein: The conductive bonding member includes: a third conductive layer in ohmic contact with the first semiconductor region; and The second conductive layer is bonded to the bonding layer.

4. The method for manufacturing a semiconductor light emitting device according to claim 2 or 3, characterized in that: In the semiconductor light emitting diode, the insulating layer exposed after removing the substrate is arranged between the second semiconductor region and the second conductive layer.

5. The method for manufacturing a semiconductor light emitting device according to claim 4, wherein: Before the step of electrical connection, the method for manufacturing the semiconductor light emitting device further includes the following step: forming a first passivation layer, wherein the first passivation layer covers the plurality of semiconductor regions through the insulating layer to the bonding layer.

6. The method for manufacturing a semiconductor light emitting device according to claim 5, wherein: Before the step of forming the first passivation layer, the method for manufacturing a semiconductor light emitting device further comprises the following steps: performing an oxygen plasma treatment on the bonding layer, or performing an annealing treatment on the bonding layer in an oxygen atmosphere.

7. The method for manufacturing a semiconductor light emitting device according to claim 5, wherein: The first passivation layer is formed by spin coating a flowable oxide material including SiO2 material.

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