MsgA PUSCH Verification

Abstract

An embodiment relates to providing MsgA PO verification. An embodiment of a user equipment (UE) includes a processor configured to: determine an initial uplink / downlink (UL / DL) time slot configuration for communicating with the UE; receive, from a base station, cell-specific uplink / downlink configured time slots for communicating with the UE; generate a MsgA physical uplink shared channel (PUSCH) occasion (PO); and perform a verification test to determine whether the MsgA PO is configured on an allowed time slot in a transmission frame structure.

Description

Technical Field

[0001] The present disclosure generally relates to the field of electronic communications, including aspects generally related to methods for performing MsgA PUSCH verification in a communication network. Background Art

[0002] In some radio network architectures (e.g., radio access technologies (RATs) operating according to fifth generation (5G) wireless network protocols), a user equipment (UE) initiates a radio connection with a radio base station (BS) (commonly also referred to as an evolved Node B (eNB) or a giga Node B (gNB)) using a random access channel (RACH) message.

[0003] Some instances of radio access protocols use a four-step RACH procedure, where the UE first transmits a physical random access channel (PRACH) preamble to the BS, commonly referred to as Msg1. The BS responds by transmitting a random access response (RAR) (commonly referred to as Msg2) to the UE, which includes an uplink grant for the physical uplink shared channel (PUSCH). The UE transmits a scheduled transmission (commonly referred to as Msg3) to the BS, which includes a contention resolution identifier. In response, the base station transmits a contention resolution message to the base station, commonly referred to as Msg4.

[0004] This four-step random access procedure requires two round-trip cycles between the UE and the BS, which results in latency and requires additional control signaling overhead. To address these and other issues, efforts are underway to replace the four-step random access procedure with a two-step random access procedure. Brief Description of the Drawings

[0005] A detailed description is provided with reference to the accompanying drawings. The same reference numerals are used in different drawings to denote similar or identical items.

[0006] Figure 1A is a schematic block diagram illustration of components in a 3GPP LTE (e.g., 4G) network according to various examples discussed herein, which can be used to implement MsgA PUSCH verification in a communication network.

[0007] Figure 1B is a schematic block diagram illustration of components in a 3GPP NR (e.g., 5G) network according to various examples discussed herein, which can be used to implement MsgA PUSCH verification in a communication network.

[0008] Figure 2 is a flowchart showing operations in a method for implementing MsgA PUSCH verification in a communication network according to various examples discussed herein.

[0009] Figure 3is a diagram illustrating MsgA PUSCH configurations according to various examples discussed herein.

[0010] Figure 4 is a diagram illustrating MsgA PUSCH configurations according to various examples discussed herein.

[0011] Figure 5 is a flow diagram illustrating operations in a method of implementing MsgA PUSCH verification in a communication system according to various examples discussed herein.

[0012] Figure 6 is a diagram illustrating MsgA PUSCH configurations according to various examples discussed herein.

[0013] Figure 7 is a flow diagram illustrating operations in a method of implementing MsgA PUSCH verification in a communication system according to various examples discussed herein.

[0014] Figure 8A 、 Figure 8B and Figure 8C is a diagram illustrating MsgA PUSCH configurations according to various examples discussed herein.

[0015] Figure 9 is a schematic block diagram illustration of an information processing system according to exemplary embodiments disclosed herein.

[0016] Figure 10 is a schematic block diagram illustration of components of a representative UE according to one or more example embodiments disclosed herein.

[0017] It should be understood that for simplicity and / or clarity of illustration, the elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Furthermore, where deemed appropriate, reference numerals have been repeated in the drawings to indicate corresponding and / or similar elements. DETAILED DESCRIPTION

[0018] Many specific details are shown in the following description to provide a thorough understanding of the various examples. However, the various examples may be practiced without these specific details. In other cases, well-known methods, processes, components, and circuits are not described in detail so as not to obscure the particular examples. In addition, various aspects of the examples may be performed using various means, such as integrated semiconductor circuits ("hardware"), computer-readable instructions organized into one or more programs ("software"), or some combination of hardware and software. For the purposes of this disclosure, reference to "logic" shall refer to hardware, software, or some combination thereof.

[0019] As used throughout the specification, the term "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing throughout the specification are not necessarily all referring to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Further, the term "exemplary" as used herein is meant to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or superior to other embodiments.

[0020] The various operations may be described sequentially in a manner that is most helpful in understanding the claimed subject matter. However, the order of the description should not be construed as implying that these operations necessarily depend on order. Specifically, these operations need not be performed in the order presented. The operations may be performed in an order different from that of the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0021] As described above, the four-step random access procedure implemented in some network protocols requires two round-trip cycles between the UE and the BS, which results in latency and requires additional control signaling overhead. To address these and other issues, efforts are underway to replace the four-step random access procedure with a two-step random access procedure that is designed to reduce latency and control signaling overhead, for example, by using one round-trip cycle between the UE and the base station. This is achieved by combining the preamble and the scheduled PUSCH transmission (e.g., Msg1 and Msg3) into a single message from the UE (referred to as MsgA), and combining the random access response and the contention resolution message (e.g., Msg2 and Msg4) into a single message from the BS to the UE (referred to as MsgB).

[0022] In some examples, MsgA includes MsgA PRACH and the associated MsgA-PUSCH. Before transmitting MsgA, the UE may identify whether the MsgA PUSCH timing opportunity (PO) and the MsgA PRACH timing opportunity (RO) are valid. The MsgA PUSCH configuration is independently configured for UEs in the RRC_CONNECTED state and the RRC_IDLE / INACTIVE state.

[0023] In some examples, the UE may verify the MsgA RO and PO before transmitting MsgA. In some existing embodiments, a rule may be applied according to which, if a Physical Uplink Shared Channel occasion (PO) does not overlap in time and frequency with any Physical Random Access Channel occasion associated with a Type 1 Random Access Procedure (RACH) or a Type 2 Random Access Procedure (RACH), the Physical Uplink Shared Channel occasion may be considered valid. Additionally, if the UE is provided with TDD-UL-DL-ConfigurationCommon, the Physical Uplink Shared Channel occasion (PO) may be considered valid if: (1) it is within an uplink (UL) symbol; or (2) it is not before the Subcarrier Spacing Physical Broadcast Channel block (SS / PBCH) in the PUSCH time slot, and starts at least a predetermined gap length (gap) symbol after the last downlink symbol and at least a predetermined gap length (gap) symbol after the last SS / PBCH block symbol.

[0024] In some examples, a verification rule may be applied according to which, if a Physical Uplink Shared Channel occasion does not overlap in time and frequency with any Physical Random Access Channel occasion associated with a Type 1 Random Access Procedure or a Type 2 Random Access Procedure, the Physical Uplink Shared Channel occasion is valid. Additionally, if the UE is provided with TDD-UL-DL-ConfigurationCommon, the Physical Uplink Shared Channel occasion is valid if: (1) it is within a UL symbol; or (2) it is not before the SS / PBCH block in the PUSCH time slot, and starts a gap symbol after the last downlink symbol and at least a gap symbol after the last SS / PBCH block symbol.

[0025] These verification rules allow the UE to transmit the PO on flexible symbols and / or UL time slots. Some New Radio (NR) Time Division Duplex (TDD) algorithms support dynamic TDD. More specifically, the flexible symbols indicated by a semi-static uplink / downlink (UL / DL) configuration can be configured as DL or UL through a Dynamic Slot Format Indication (SFI) or Downlink Control Information (DCI).

[0026] In some examples, MsgA transmitted by the UE includes a Physical Random Access Channel preamble (referred to as MsgA PRACH) and a Physical Uplink Shared Channel transmission (commonly referred to as MsgA PUSCH). The MsgA PRACH preamble may be transmitted in one or more Physical Random Access Channel occasions (RO). The Physical Uplink Shared Channel transmission is organized as a Physical Uplink Shared Channel occasion (PO), which may span multiple symbols and Physical Resource Blocks (PRB), with an optional guard period and guard band between consecutive POs.

[0027] If dynamic TDD is indicated, these verification rules for MsgA PUSCH are insufficient. The flexible symbols used by MsgA PUSCH can change the transmission direction via UE-specific RRC signaling or DCI. The MsgA PUSCH configuration can be configured separately for UEs in the RRC_CONNECTED state and the RRC_IDLE / INACTIVE state. For RRC_CONNECTED UEs, the UE will need further actions to determine whether the PO is still valid under dynamic TDD signaling. For RRC_IDLE UEs, MsgA PUSCH is still transmitted on flexible symbols, but the base station (e.g., eNB, gNB) will transmit DL signals at these symbols, which may cause interference between UEs and the base station may not receive MsgA-PUSCH.

[0028] To address these and other issues, various techniques for verifying MsgA PUSCH are described herein, which may be useful in a communication network, particularly in the case where dynamic TDD is indicated to the UE. In summary, in a first exemplary technique, the same PO verification rules can be applied to UEs in the RRC_IDLE / INACTIVE state and UEs in the RRC_CONNECTED state. For UEs in the RRC_IDLE / INACTIVE state, if the PO is not configured on a DL time slot via semi-static UL / DL configuration, the UE can assume that the configured PO is always valid. For UEs in the RRC_CONNECTED state, the transmission direction of the flexible symbols of MsgA PUSCH cannot be reversed to DL via dynamic signaling. Therefore, the UE assumes this is an error condition. The UE does not receive a DL channel / signal in the time slot that overlaps with the MsgA PUSCH symbol, and the symbol for MsgA PUSCH transmission cannot be set to DL via the slot format indication (SFI) DCI.

[0029] In a second exemplary technique, MsgA PUSCH is only allowed to be transmitted on UL time slots, rather than on flexible symbols configured by semi-static UL / DL configuration, e.g., via the parameter TDD-UL-DL-ConfigurationCommon. If the PO is configured to be transmitted on a flexible symbol and / or a DL time slot, the PO is considered invalid.

[0030] In a third exemplary technique, the PO verification rules are defined separately for UEs in the RRC_IDLE / INACTIVE state and UEs in the RRC_CONNECTED state. For UEs in the RRC_IDLE / INACTIVE state, the PUSCH occasion (PO) is only configured in UL time slots; otherwise, the PO is invalid. For UEs in the RRC_CONNECTED state, the PO can be configured on flexible symbols, and if the flexible symbol indicates a DL symbol, the relevant PO becomes invalid.

[0031] Further details of these techniques will be described with reference to the network architecture, devices, and methods described below with reference to Figures 1A to 10 description. Figure 1A is a schematic block diagram illustration of components in a 3GPP NR (or 5G) network 100A according to various examples discussed herein, which can be used to implement MsgA PUSCH verification in a communication network. Figure 1A Exemplary network elements and exemplary standardized interfaces are also generally shown. At a high level, network 100A includes a core network (CN) 101 (also referred to as an evolved packet system (EPC)) and an air interface access network (also referred to as E-UTRAN 102). CN 101 is responsible for the overall control of various user equipments (UEs) connected to the network and the establishment of bearers. CN 101 may include functional entities such as a home agent and / or an ANDSF server or entity, although not explicitly described. E-UTRAN 102 is responsible for all radio-related functions.

[0032] The main exemplary logical nodes of CN 101 include, but are not limited to, a serving GPRS support node 103, a mobility management entity 104, a home subscriber server (HSS) 105, a serving gateway (SGW) 106, a PDN gateway 107, and a policy and charging rules function (PCRF) manager 108. The functions of each network element of CN 101 are well known and will not be described herein. Each network element of CN 101 is interconnected through well-known exemplary standardized interfaces, some of which are shown, such as interfaces S3, S4, S5, etc., although not described herein. Figure 1A shown, such as interfaces S3, S4, S5, etc., although not described herein.

[0033] Although CN 101 includes many logical nodes, the E-UTRAN access network 102 is formed by at least one node (such as an evolved node B (base station (BS), evolved node B (eNB), or next-generation node B (gNB)) 110), which is connected to one or more user equipments (UEs) 111. Figure 1AOnly one user equipment is depicted therein. UE 111 may also be referred to herein as a wireless device (WD) and / or a subscriber station (SS), and may include M2M type devices. In one example, UE 111 may be coupled to an eNB via the LTE Uu interface. In an exemplary configuration, a single cell of the E UTRAN access network 102 provides a substantially localized geographical transmission point (with multiple antenna devices), which provides access to one or more UEs. In another exemplary configuration, a single cell of the E UTRAN access network 102 provides multiple geographically substantially isolated transmission points (each transmission point having one or more antenna devices), each transmission point simultaneously providing access to one or more UEs, and signaling bits are defined for a cell such that all UEs share the same spatial signaling dimension. For normal user traffic (as opposed to broadcast), there is no centralized controller in the E-UTRAN; thus, the E-UTRAN architecture is said to be flat. eNBs are typically interconnected with each other via an interface called "X2" and are connected to the EPC via the S1 interface. More specifically, an eNB is connected to the MME 104 via the S1 MME interface and to the SGW 106 via the S1 U interface. The protocol running between the eNB and the UE is typically referred to as the "AS protocol". The details of the various interfaces are well known and will not be described herein.

[0034] The eNB 110 hosts the physical layer (PHY), the media access control layer (MAC), the radio link control layer (RLC), and the packet data control protocol layer (PDCP), which include user plane header compression and encryption functions. The eNB 110 also provides radio resource control (RRC) functions corresponding to the control plane and performs many functions, including radio resource management, admission control, scheduling, negotiation of the execution of uplink (UL) QoS, cell information broadcast, encryption / decryption of user and control plane data, and compression / decompression of DL / UL user plane packet headers.

[0035] The RRC layer in eNB 110 covers all functions related to radio bearers, such as radio bearer control, radio access control, radio mobility control, resource scheduling and dynamic allocation for the UE in both the uplink and downlink, header compression for efficient use of the radio interface, security of all data transmitted over the radio interface, and connection to the EPC. The RRC layer makes handover decisions based on the neighboring cell measurements sent by the UE 111, generates paging for the UE 111 in the air, broadcasts system information, controls the periodicity of UE measurement reports such as channel quality information (CQI) reports, and assigns cell-level temporary identifiers to the active UE 111. The RRC layer also performs the transfer of the UE context from the source eNB to the target eNB during handover and provides integrity protection for RRC messages. Additionally, the RRC layer is responsible for the establishment and maintenance of radio bearers.

[0036] In some examples, communications on a network (such as network 100A) can be digitized and assigned to discrete frames, and each discrete frame can contain subframes. Each subframe of a frame can in turn contain multiple time slots. In some examples, the eNB can schedule uplink and downlink transmissions on various frequency bands. The resource allocation in a subframe used in one frequency band may be different from the resource allocation in another frequency band. Depending on the system used, each time slot of a subframe can contain a predetermined number of symbols. In some embodiments, a subframe can contain 12 or 24 subcarriers.

[0037] A resource grid can be used for downlink and uplink transmissions between the eNB and the UE. The resource grid can be a time-frequency grid, which is the physical resources in each time slot. The smallest time-frequency unit in the resource grid can be represented as a resource element (RE).

[0038] Each column and each row of the resource grid can correspond to an OFDM symbol and an OFDM subcarrier, respectively. The resource grid can contain resource blocks (RBs), which describe the mapping of physical channels to resource elements and physical RBs (PRBs). In some network protocols, the PRB may be the smallest resource unit that can be allocated to a UE. In some examples, the frequency of a resource block can be 180 kHz wide and the time can be 1 time slot long. In frequency, a resource block can be 12×15 kHz subcarriers or 12×30 kHz subchannels wide. For most channels and signals, depending on the system bandwidth, each resource block can use 12 subcarriers. In some examples, the duration of the resource grid in the time domain corresponds to one subframe or two resource blocks. For example, for the normal cyclic prefix (CP) case, each resource grid can include 12 (subcarriers)×14 (symbols) = 168 resource elements. Such resource blocks can be used to transmit several different physical channels. In 5G networks, the sizes of resource blocks, resource elements, and symbols, etc. may vary.

[0039] There may be several different physical downlink channels transmitted using such resource blocks, including the Physical Downlink Control Channel (PDCCH) and the Physical Downlink Shared Channel (PDSCH). Each subframe may contain a PDCCH and a PDSCH. The PDCCH typically may occupy the first three symbols of each subframe (four in the case of a 1.4 MHz narrow bandwidth), and among other things, carry the transmission format and resource allocation information related to the PDSCH channel, as well as the uplink scheduling grant for the Physical Uplink Shared Channel (PUSCH) transmission.

[0040] The PDSCH may carry user data and higher layer signaling to a specific UE and occupy the remainder of the downlink subframe to avoid the resources for transmitting the downlink control channel (PDCCH). Generally, downlink scheduling (allocating control and shared channel resource blocks for UEs in a cell) may be performed at the eNB based on the channel quality information provided by the UE, and then the downlink resource allocation information may be sent to the scheduled UE on the PDCCH used for (assigned to) the PDSCH reception of the UE.

[0041] The PDCCH may contain downlink control information (DCI) in one of several formats, which tell the UE where to find and how to decode the data transmitted on the PDSCH from the resource grid in the same subframe. The DCI may provide details such as the number of resource blocks, resource allocation type, modulation scheme, transport block, redundancy version, coding rate, etc. Each DCI format may have a cyclic redundancy check (CRC) and be scrambled using a Radio Network Temporary Identifier (RNTI), which identifies the target UE for the PDSCH. The use of the RNTI (which may be UE-specific) may limit the decoding of the DCI information (and thus the corresponding PDSCH) to the intended UE.

[0042] The PDCCH may be located in any one of many frequency / time regions, depending on whether the PDCCH is UE-specific or common, and the aggregation level. A set of possible candidate locations for the PDCCH is defined according to the search space. The search space is defined by a set of control channel elements (CCEs) candidates with multiple aggregation levels L ∈ {1, 2, 4, 8}, where the UE may monitor to find its PDCCH. The common search space may carry the DCI common to all UEs; for example, system information (using SI-RNTI), paging (P-RNTI), PRACH response (RA-RNTI) or UL TPC command (TPC-PUCCH / PUSCH-RNTI).

[0043] UE-specific search spaces may carry DCI for UE-specific allocations using the cell radio network temporary identifier (C-RNTI) assigned to the UE, semi-persistent scheduling (SPS C-RNTI), or initial allocation (temporary C-RNTI). When SPS (uplink or downlink) is configured, the SPS C-RNTI is provided by the eNB, and the UE is configured by a higher layer to decode PDCCHs with CRC scrambled by the SPS C-RNTI. The UE may monitor PDCCHs with CRC scrambled by the SPS C-RNTI in each subframe, since the eNB may activate / reactivate / release SPS at any time using DCI formats with CRC scrambled by the SPS C-RNTI. The received DCI format with CRC scrambled by the SPS C-RNTI may be a retransmission of SPS or an authorization / assignment for activation / reactivation / release of SPS.

[0044] In addition to PDCCH, the eNB and the UE may also use enhanced PDCCH (EPDCCH). Thus, the PDSCH may contain data in some resource blocks (RBs), and then the EPDCCH may contain downlink control signals in other RBs of the bandwidth supported by the UE. Different UEs may have different EPDCCH configurations. A set of RBs corresponding to the EPDCCH may be configured, for example, by higher layer signaling (such as radio resource control (RRC) signaling) for EPDCCH monitoring.

[0045] The UE may use the physical uplink control channel (PUCCH) to send uplink control information (UCI) to the eNB. The PUCCH may be mapped to UL control channel resources defined by one orthogonal cover code and two resource blocks (RBs), which are continuous in time and may jump at the boundary between adjacent time slots. The PUCCH may adopt several different formats, where the UCI contains format-dependent information. Specifically, the PUCCH may contain a scheduling request (SR), an acknowledgement / negative acknowledgement (ACK / NACK), or a channel quality indicator (CQI) / channel state information (CSI). The CQI / CSI may indicate to the eNB an estimate of the current downlink channel conditions seen by the UE to assist in channel-dependent scheduling, and if a MIMO transmission mode is configured for the UE, the CQI / CSI may include MIMO-related feedback (e.g., precoder matrix indicator, PMI).

[0046] Figure 1B is a schematic block diagram illustration of components in a 3GPP NR network (e.g., 5G network) according to various examples discussed herein, which may be used to implement MsgA PUSCH verification in a communication network. Refer to Figure 1B, in some examples, network 100B includes one or more access and mobility management function / user plane function (AMF / UMF) devices 150A, 150B, one or more gNBs 160A, 160B, and one or more ng-eNBs 160C, 160D. The AMF / UFP devices are communicatively coupled to the gNBs 160A, 160B and the gn-eNBs 160C, 160D via the NG interface. The gNBs 160A, 160B and the gn-eNBs 160C, 160D are communicatively coupled to each other via the Xn interface.

[0047] Figure 2 is a flowchart showing operations in a method of implementing MsgA PUSCH verification in a communication network according to various examples discussed herein. Figure 2 The operations depicted in may correspond to the first solution described above. In some examples, Figure 2 the operations depicted in may be implemented by processing resources on a UE (such as Figure 1A the UE 111 depicted in ).

[0048] Referring to Figure 2 , at operation 210, the UE first performs a semi-static UL / DL configuration check for a PUSCH occasion (PO). In some examples, valid POs are only configured on UL time slots and / or flexible symbols, as indicated by the semi-static UL / DL configuration, for example, by the parameter TDD-UL-DL-ConfigurationCommon. Thus, at operation 215, it is determined whether the PO is configured on a downlink time slot. If, at operation 215, the PO is configured on a downlink time slot, then control transfers to operation 220 and the PO is determined to be invalid. In contrast, if, at operation 215, the PO is not configured on a downlink time slot, then control transfers to operation 225.

[0049] If the PO is not invalid, the UE performs a dynamic TDD check for the PO. At operation 225, it is determined whether the UE is in the RRC_CONNECTED state. If, at operation 225, the UE is not in the RRC_CONNECTED state, which means the UE is in the RRC_IDLE state, then control transfers to operation 230 and the PO is considered valid. In contrast, if, at operation 225, the UE is in the RRC_CONNECTED state, then control transfers to operation 235.

[0050] At operation 235, it is determined whether the PO has been allocated to a flexible symbol in the radio frame time slot structure. If, at operation 235, the PO has not been allocated to a flexible symbol (e.g., it is allocated to a UL symbol), then control goes to operation 230 and the PO is considered valid. In contrast, if, at operation 235, the PO is allocated to a flexible symbol, then control goes to operation 240.

[0051] At operation 240, it is determined whether the flexible symbol to which the PO is allocated is indicated as a DL symbol in the radio frame time slot structure. If, at operation 240, the flexible symbol is not indicated as a DL symbol (e.g., it is a UL symbol), then control goes to operation 230 and the PO is considered valid. In contrast, if, at operation 240, the flexible symbol is indicated as a DL symbol, then control goes to operation 520 and the PO is considered an error condition.

[0052] Figures 3 to 4 FIG. is a diagram showing a MsgA PUSCH configuration according to various examples discussed herein. First, referring to Figure 3 , in some examples, a frame may be configured with one or more downlink time slots 310, one or more flexible time slots 315, and one or more uplink time slots 320. In one example, one or more POs 325A, 325B, 325C may be configured, for example, via a semi-static UL / DL configuration, on the flexible symbol 315 and / or the UL time slot 320. After a dynamic TDD check for the PO, the UE behavior is defined as follows: For a set of symbols of a time slot corresponding to a valid PO and the symbols before the valid PO, the resource grid may be configured such that if reception would overlap with any of the symbols in the set, the UE does not receive PDCCH, PDSCH, or CSI-RS in the time slot.

[0053] Referring to Figure 4 , the resource grid may be configured such that the UE does not expect the set of symbols of the time slot to be indicated as downlink by TDD-UL-DL-ConfigurationCommon or TDD UL-DL-ConfigurationDedicated.

[0054] For a set of symbols of a time slot corresponding to a valid PUSCH occasion and the Ngap symbols before the valid PUSCH occasion, the UE does not expect to detect DCI format 2_0 with an SFI-index field value that indicates the set of symbols of the time slot as downlink.

[0055] Figure 5 FIG. is a flowchart showing operations in a method for MsgA PUSCH verification in a communication system according to various examples discussed herein. In some specific implementations, Figure 5The operations depicted therein may correspond to the second solution described above. In some examples, Figure 5 the operations depicted therein may be implemented by processing resources on a UE (such as Figure 1A the UE 111 depicted therein).

[0056] Referring to Figure 5 , at operation 510, the UE first performs a semi-static UL / DL configuration check for a PUSCH opportunity (PO). In some examples, valid POs are only configured on UL time slots, as indicated by the semi-static UL / DL configuration, for example, by the parameter TDD-UL-DL-ConfigurationCommon. Thus, at operation 515, it is determined whether the PO is configured on a downlink time slot. If at operation 515, the PO is configured on a downlink time slot, the control goes to operation 520 and the PO is determined to be invalid. In contrast, if at operation 515, the PO is not configured on a downlink time slot, the control goes to operation 525.

[0057] At operation 525, it is determined whether the PO has been allocated to a flexible symbol in the radio frame time slot structure. If at 525, the PO is not allocated to a flexible symbol (e.g., it is allocated to a UL symbol), the control goes to operation 530 and the PO is considered valid and the verification is complete. In contrast, if at operation 525, the PO is allocated to a flexible symbol, the control goes to operation 520 and the PO is considered invalid.

[0058] Figure 6 is a diagram showing MsgA PUSCH configurations according to various examples discussed herein. Referring to Figure 6 , the PO resource 325C is only configured on the UL time slot 320 through the semi-static UL / DL configuration. The POs 325A, 325B configured on the flexible symbols 315 are considered invalid POs. Referring to Figure 6 , in some examples, the UE only performs a semi-static UL / DL configuration check for the PO. The flexible symbols can be UL or DL according to the gNB scheduling indication for other users.

[0059] Figure 7 is a flowchart showing operations in a method for MsgA PUSCH verification in a communication system according to various examples discussed herein. In some specific implementations, Figure 7 the operations depicted therein may correspond to the third solution described above. In some examples, Figure 7 the operations depicted therein may be implemented by processing resources on a UE (such as Figure 1A the UE 111 depicted therein).

[0060] Referring to Figure 7, at operation 710, the UE first performs a semi-static UL / DL configuration check for the PUSCH occasion (PO). In some examples, the PUSCH resources of a UE in the RRC_IDLE / INACTIVE state are configured only on UL time slots through semi-static UL / DL configuration. Therefore, the PO resources configured on flexible symbols and / or DL time slots are invalid.

[0061] At operation 715, it is determined whether the UE is in the RRC_CONNECTED state. If, at operation 715, the UE is in the RRC_CONNECTED state, the control goes to operation 720. In contrast, if, at operation 715, the UE is not in the RRC_CONNECTED state, the control goes to operation 750.

[0062] At operation 720, it is determined whether the PO is configured on a downlink time slot. If, at operation 720, the PO is configured on a downlink time slot, the control goes to operation 740 and the PO is determined to be invalid. In contrast, if, at operation 720, the PO is not configured on a downlink time slot, the control goes to operation 725.

[0063] At operation 725, it is determined whether the PO has been allocated to a flexible symbol in the radio frame time slot structure. If, at 725, the PO has not been allocated to a flexible symbol (e.g., it is allocated to a UL symbol), the control goes to operation 730 and the PO is considered valid. In contrast, if, at operation 725, the PO is allocated to a flexible symbol, the control goes to operation 735.

[0064] At operation 735, it is determined whether the flexible symbol to which the PO is allocated is indicated as a DL symbol in the radio frame time slot structure. If, at operation 735, the flexible symbol is not indicated as a DL symbol (e.g., it is a UL symbol), the control goes to operation 730 and the PO is considered valid. In contrast, if, at operation 735, the flexible symbol is indicated as a DL symbol, the control goes to operation 740 and the PO is considered invalid.

[0065] Returning to reference operation 715, if, at operation 715, the UE is not in the RRC_CONNECTED state, the control goes to operation 750. At operation 750, it is determined whether the PO is configured on a downlink time slot. If, at operation 750, the PO is configured on a downlink time slot, the control goes to operation 760 and the PO is determined to be invalid. In contrast, if, at operation 750, the PO is not configured on a downlink time slot, the control goes to operation 755.

[0066] At operation 755, it is determined whether the PO has been assigned to a flexible symbol in the radio frame slot structure. If at 755, the PO is not assigned to a flexible symbol (e.g., it is assigned to a UL symbol), control passes to operation 760 and the PO is considered valid. In contrast, if at operation 755, the PO is assigned to a flexible symbol, control passes to operation 765 and the PO is considered valid, and verification is complete.

[0067] Figure 8A 、 Figure 8B and Figure 8C is a diagram illustrating MsgA PUSCH configurations according to various examples discussed herein. Figure 8A , if the MsgA PUSCH resource is configured for an RRC_CONNECTED UE, PO 325A, 325B are valid because the PO is configured on the flexible UL symbol 317 on the flexible slot 315, and PO 325C is valid because it is configured on the UL slot 320 by semi-static UL / DL configuration signaling. Therefore, PO 325A, 325B and 325C are all valid. Figure 8B If one of the flexible slots 315 is configured as a flexible DL slot 318, the valid PO 325A may become invalid due to dynamic signaling. More specifically, the flexible symbol 315 may indicate UL or DL based on the gNB's scheduling, and the UE will re-verify the PO based on dynamic TDD signaling. If the flexible symbol indicates flexible DL 318, the corresponding PO becomes invalid.

[0068] refer to Figure 8C In some examples, the PUSCH resources of a UE in RRC_IDLE / INACTIVE UE are only configured on the UL time slot 320 by semi-static UL / DL configuration. Figure 8C As depicted in FIG, POs 325A, 325B, and 315C are valid. In contrast, POs configured on DL slot 310 or flexible slot 315 will be invalid.

[0069] Figure 9 Depicted is an exemplary functional block diagram of an information handling system 900 according to an embodiment. Figure 9The information processing system 900 can tangibly embody one or more of any of the exemplary devices, exemplary network elements, and / or functional entities of the network as shown and described herein. In one example, the information processing system 900 can represent an eNB 110 and / or a UE 111 with more or fewer components, depending on the hardware specifications of the particular device or network element. In another example, the information processing system can provide M2M-type device capabilities. Although the information processing system 900 represents an example of several types of computing platforms, the information processing system 900 can include more or fewer elements and / or a different arrangement of elements than Figure 9 shown, and the scope of the claimed subject matter is not limited to these aspects.

[0070] In one or more examples, the information processing system 900 can include an application circuit 910 and a baseband processor 912. The application circuit 910 can be used as a general-purpose processor to run application programs and various subsystems of the information processing system 900, and can provide uplink transmission power control techniques that, in accordance with the subject matter disclosed herein, can reduce the interference experienced at other wireless devices. The application circuit 910 can include a single core, or alternatively can include multiple processing cores, where one or more of the cores can include a digital signal processor or digital signal processing core. Additionally, the application circuit 910 can include a graphics processor or coprocessor disposed on the same chip, or alternatively, a graphics processor coupled to the application circuit 910 can include a separate discrete graphics chip. The application circuit 910 can include on-board memory (such as cache memory), and can further be coupled to an external memory device (such as synchronous dynamic random access memory (SDRAM) 914) for storing and / or executing application programs, such as those that can provide uplink transmission power control techniques that, in accordance with the subject matter disclosed herein, reduce the interference experienced at other wireless devices. During operation, NAND flash memory 916 is used to store application programs and / or data, even when the information processing system 900 is powered off.

[0071] In one example, a list of candidate nodes can be stored in the SDRAM 914 and / or the NAND flash memory 916. Additionally, the application circuit 910 can execute computer-readable instructions stored in the SDRAM 914 and / or the NAND flash memory 916 that generate uplink transmission power control techniques that, in accordance with the subject matter disclosed herein, can reduce the interference experienced at other wireless devices.

[0072] In one example, the baseband processor 912 may control the broadband radio functions of the information processing system 900. The baseband processor 912 may store code for controlling such broadband radio functions in the NOR flash memory 918. The baseband processor 912 controls the wireless wide area network (WWAN) transceiver 920, which is used to modulate and / or demodulate broadband network signals, for example, for communication via a 3GPP NR network, etc., as discussed herein with respect to Figure 1A and Figure 1B The WWAN transceiver 920 is coupled to one or more power amplifiers 922, which are respectively coupled to one or more antennas 924 for transmitting and receiving radio frequency signals via the WWAN broadband network. The baseband processor 912 may also control the wireless local area network (WLAN) transceiver 926, which is coupled to one or more suitable antennas 928 and capable of communicating via: Bluetooth-based standards; IEEE 802.11-based standards; IEEE 802.16-based standards; IEEE 802.18-based wireless network standards; 3GPP protocol-based wireless networks; Third Generation Partnership Project Long Term Evolution (3GPP NR)-based wireless network standards; 3GPP2 Air Interface Evolution (3GPP2AIE)-based wireless network standards; 3GPP-NR-Advanced-based wireless networks; UMTS protocol-based wireless networks; CDMA2000 protocol-based wireless networks; GSM protocol-based wireless networks; Cellular Digital Packet Data (CDPD)-based protocol wireless networks; Mobitex protocol-based wireless networks; Near Field Communication (NFC)-based links; WiGig-based networks; ZigBee-based networks, etc. It should be noted that these are merely exemplary embodiments of the application circuit 910 and the baseband processor 912, and the scope of the claimed subject matter is not limited to these aspects. For example, any one or more of the SDRAM 914, NAND flash memory 916, and / or NOR flash memory 918 may include other types of memory technologies, such as magnetic-based memory, chalcogenide-based memory, phase change-based memory, optical-based memory, or two-way-based memory, and in this regard, the scope of the claimed subject matter is not limited.

[0073] In one or more embodiments, the application circuit 910 may drive the display 930 to display various information or data, and may further receive touch inputs from the user via the touch screen 932 (e.g., via a finger or a stylus). In an exemplary embodiment, the screen 932 displays menus and / or options to the user, which can be selected via a finger and / or a stylus to input information into the information processing system 900.

[0074] The ambient light sensor 934 can be used to detect the amount of ambient light in which the information processing system 900 is operating to control, for example, the brightness or contrast value of the display 930 based on the ambient light intensity detected by the ambient light sensor 934. One or more cameras 936 can be used to capture images that are processed by the application circuit 910 and / or at least temporarily stored in the NAND flash memory 916. Additionally, the application circuit can be coupled to a gyroscope 938, an accelerometer 940, a magnetometer 942, an audio encoder / decoder (codec) 944, and / or a global positioning system (GPS) controller 946 coupled to an appropriate GPS antenna 948 for detecting various environmental attributes, including the location, movement, and / or orientation of the information processing system 900. Alternatively, the controller 946 can include a global navigation satellite system (GNSS) controller. The audio codec 944 can be coupled to one or more audio ports 950 to provide microphone input and speaker output via internal devices and / or via external devices that are coupled to the information processing system via the audio ports 950 (e.g., via headphone and microphone jacks). Additionally, the application circuit 910 can be coupled to one or more input / output (I / O) transceivers 952 to couple to one or more I / O ports 954, such as universal serial bus (USB) ports, high-definition multimedia interface (HDMI) ports, serial ports, and the like. Further, one or more of the I / O transceivers 952 can be coupled to one or more memory slots 956 for optional removable memory, such as a secure digital (SD) card or a subscriber identity module (SIM) card, although the scope of the claimed subject matter is not limited in these respects.

[0075] As used herein, the term "circuitry" can refer to, belong to, or include an application specific integrated circuit (ASIC), an electronic circuit, a (shared, dedicated, or group) processor, and / or a (shared, dedicated, or group) memory that executes one or more software or firmware programs, a combinational logic circuit, and / or other suitable hardware components that provide the described functionality. In some embodiments, the circuitry can be implemented in one or more software or firmware modules, or the functions associated with the circuitry can be implemented by one or more software or firmware modules. In some embodiments, the circuitry can include logic components that are capable of operating at least partially in hardware.

[0076] The embodiments described herein can be implemented into a system using any suitable configured hardware and / or software. For one embodiment, Figure 10 Exemplary components of a user equipment (UE) device 1000 are shown. In some embodiments, the UE device 1000 can include at least an application circuit 1002, a baseband circuit 1004, a radio frequency (RF) circuit 1006, a front-end module (FEM) circuit 1008, and one or more antennas 1010 coupled together as shown.

[0077] The application circuit 1002 may include an application circuit. For example, the application circuit 1002 may include circuits such as, but not limited to, one or more single-core or multi-core processors. The processor may include any combination of a general-purpose processor and a dedicated processor (e.g., a graphics processor, an application processor, etc.). The processor may be coupled to the memory / storage device and / or may include the memory / storage device, and may be configured to execute instructions stored in the memory / storage device to enable various application programs or operating systems to run on the system.

[0078] The baseband circuit 1004 may include circuits such as, but not limited to, one or more single-core or multi-core processors. The baseband circuit 1004 may include one or more baseband processors and / or control logic components to process the baseband signals received from the receive signal path of the RF circuit 1006 and generate baseband signals for the transmit signal path of the RF circuit 1006. The baseband processing circuit 1004 may interact with the application circuit 1002 to generate and process baseband signals and control the operation of the RF circuit 1006. For example, in some embodiments, the baseband circuit 1004 may include a second-generation (2G) baseband processor 1004a, a third-generation (3G) baseband processor 1004b, a fourth-generation (4G) baseband processor 1004c, and / or a fifth-generation (5G) baseband processor 1004d. It should be understood that the baseband circuit 1004 may include one or more additional baseband processors for other existing generations, generations under development, or generations to be developed in the future (e.g., fifth-generation (5G), 6G, etc.). The baseband circuit 1004 (e.g., one or more of the baseband processors 1004a-d) may process various radio control functions for communicating with one or more radio networks via the RF circuit 1006. The radio control functions may include, but are not limited to, signal modulation / demodulation, encoding / decoding, radio frequency shifting, etc. In some embodiments, the modulation / demodulation circuit of the baseband circuit 1004 may include fast Fourier transform (FFT), precoding, and / or constellation mapping / demapping functions. In some embodiments, the encoding / decoding circuit of the baseband circuit 1004 may include convolutional, tail-biting convolutional, turbo, Viterbi, and / or low-density parity-check (LDPC) encoder / decoder functions. The embodiments of the modulation / demodulation and encoder / decoder functions are not limited to these examples, and in other embodiments may include other suitable functions.

[0079] In some embodiments, the baseband circuit 1004 may include elements of a protocol stack, such as, for example, elements of the evolved universal terrestrial radio access network (EUTRAN) protocol, including, for example, physical (PHY) elements, medium access control (MAC) elements, radio link control (RLC) elements, packet data convergence protocol (PDCP) elements, and / or radio resource control (RRC) elements. The central processing unit (CPU) 1004e of the baseband circuit 1004 may be configured to run the elements of the protocol stack for signaling of the PHY, MAC, RLC, PDCP, and / or RRC layers. In some embodiments, the baseband circuit may include one or more audio digital signal processors (DSPs) 1004f. The one or more audio DSPs 1004f may include elements for compression / decompression and echo cancellation, and in other embodiments may include other suitable processing elements. In some embodiments, the components of the baseband circuit may be appropriately combined on a single chip, a single chipset, or disposed on the same circuit board. In some embodiments, some or all of the components of the baseband circuit 1004 and the application circuit 1002 may be implemented together, for example, on a system on a chip (SOC).

[0080] In some embodiments, the baseband circuit 1004 may provide communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuit 1004 may support communication with the evolved universal terrestrial radio access network (EUTRAN) and / or other wireless metropolitan area networks (WMANs), wireless local area networks (WLANs), and wireless personal area networks (WPANs). Embodiments in which the baseband circuit 1004 is configured to support radio communication for more than one wireless protocol may be referred to as multi-mode baseband circuits.

[0081] The RF circuit 1006 may enable communication with a wireless network using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuit 1006 may include switches, filters, amplifiers, etc. to facilitate communication with the wireless network. The RF circuit 1006 may include a receive signal path that may include circuitry for down-converting an RF signal received from the FEM circuit 1008 and providing a baseband signal to the baseband circuit 1004. The RF circuit 1006 may also include a transmit signal path that may include circuitry for up-converting a baseband signal provided by the baseband circuit 1004 and providing an RF output signal for transmission to the FEM circuit 1008.

[0082] In some embodiments, the RF circuit 1006 may include a receive signal path and a transmit signal path. The receive signal path of the RF circuit 1006 may include a mixer circuit 1006a, an amplifier circuit 1006b, and a filter circuit 1006c. The transmit signal path of the RF circuit 1006 may include a filter circuit 1006c and a mixer circuit 1006a. The RF circuit 1006 may further include a synthesizer circuit 1006d for synthesizing frequencies for use by the mixer circuits 1006a of the receive signal path and the transmit signal path. In some embodiments, the mixer circuit 1006a of the receive signal path may be configured to down-convert an RF signal received from the FEM circuit 1008 based on a synthesized frequency provided by the synthesizer circuit 1006d. The amplifier circuit 1006b may be configured to amplify the down-converted signal, and the filter circuit 1006c may be a low-pass filter (LPF) or a band-pass filter (BPF) configured to remove unwanted signals from the down-converted signal to generate an output baseband signal. The output baseband signal may be provided to the baseband circuit 1004 for further processing. In some embodiments, although not required, the output baseband signal may be a zero-frequency baseband signal. In some embodiments, the mixer circuit 1006a of the receive signal path may include a passive mixer, but the scope of the embodiments is not limited in this regard.

[0083] In some embodiments, the mixer circuit 1006a of the transmit signal path may be configured to up-convert an input baseband signal based on a synthesized frequency provided by the synthesizer circuit 1006d to generate an RF output signal for the FEM circuit 1008. The baseband signal may be provided by the baseband circuit 1004 and may be filtered by the filter circuit 1006c. The filter circuit 1006c may include a low-pass filter (LPF), but the scope of the embodiments is not limited in this regard.

[0084] In some embodiments, the mixer circuit 1006a of the receive signal path and the mixer circuit 1006a of the transmit signal path may include two or more mixers and may be arranged for quadrature down-conversion and / or quadrature up-conversion. In some embodiments, the mixer circuit 1006a of the receive signal path and the mixer circuit 1006a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuit 1006a of the receive signal path and the mixer circuit 1006a of the transmit signal path may be arranged for direct down-conversion and / or direct up-conversion. In some embodiments, the mixer circuit 1006a of the receive signal path and the mixer circuit 1006a of the transmit signal path may be configured for superheterodyne operation.

[0085] In some embodiments, the output baseband signal and the input baseband signal may be analog baseband signals, although the scope of the embodiments is not limited in this regard. In some alternative embodiments, the output baseband signal and the input baseband signal may be digital baseband signals. In these alternative embodiments, the RF circuit 1006 may include an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) circuit, and the baseband circuit 1004 may include a digital baseband interface to communicate with the RF circuit 1006.

[0086] In some dual-mode embodiments, separate radio IC circuits may be provided to process signals for each spectrum, although the scope of the embodiments is not limited in this regard.

[0087] In some embodiments, the synthesizer circuit 1006d may be a fractional-N synthesizer or a fractional N / N+1 synthesizer, although the scope of the embodiments is not limited in this regard, as other types of frequency synthesizers may also be suitable. For example, the synthesizer circuit 1006d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer including a phase-locked loop with a frequency divider.

[0088] The synthesizer circuit 1006d may be configured to synthesize an output frequency based on a frequency input and a frequency divider control input for use by the mixer circuit 1006a of the RF circuit 1006. In some embodiments, the synthesizer circuit 1006d may be a fractional N / N+1 synthesizer.

[0089] In some embodiments, the frequency input may be provided by a voltage-controlled oscillator (VCO), although this is not required. The frequency divider control input may be provided by the baseband circuit 1004 or the application circuit 1002 based on the desired output frequency. In some embodiments, the frequency divider control input (e.g., N) may be determined from a look-up table based on the channel indicated by the application circuit 1002.

[0090] The synthesizer circuit 1006d of the RF circuit 1006 may include a frequency divider, a delay-locked loop (DLL), a multiplexer, and a phase accumulator. In some embodiments, the frequency divider may be a dual-mode divider (DMD), and the phase accumulator may be a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide an input signal by N or N+1 (e.g., based on a carry) to provide a fractional division ratio. In some example embodiments, the DLL may include cascaded, tunable, delay elements, a phase detector, a charge pump, and a set of D-type flip-flops. In these embodiments, the delay elements may be configured to divide the VCO period into Nd equal phase bins, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO period.

[0091] In some embodiments, the synthesizer circuit 1006d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and may be used in conjunction with an orthogonal generator and a frequency divider circuit to generate multiple signals having multiple different phases relative to each other at that carrier frequency. In some embodiments, the output frequency may be the LO frequency (fLO). In some embodiments, the RF circuit 1006 may include an IQ / polarity converter.

[0092] The FEM circuit 1008 may include a receive signal path that may include circuitry configured to operate on an RF signal received at one or more antennas 1010, amplify the received signal, and provide an amplified version of the received signal to the RF circuit 1006 for further processing. The FEM circuit 1008 may also include a transmit signal path that may include circuitry configured to amplify a transmit signal provided by the RF circuit 1006 for transmission via one or more of the one or more antennas 1010.

[0093] In some embodiments, the FEM circuit 1008 may include a TX / RX switch to switch between transmit mode and receive mode operations. The FEM circuit may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuit may include a low noise amplifier (LNA) to amplify the received RF signal and provide the amplified received RF signal as an output (e.g., to the RF circuit 1006). The transmit signal path of the FEM circuit 1008 may include a power amplifier (PA) for amplifying an input RF signal (e.g., provided by the RF circuit 1006); and one or more filters for generating an RF signal for subsequent transmission (e.g., via one or more of the one or more antennas 1010).

[0094] In some embodiments, the UE device 1000 may include additional elements such as, for example, a memory / storage device, a display, a camera, sensors, and / or an input / output (I / O) interface.

[0095] In various examples, the operations discussed herein may be implemented as hardware (e.g., circuitry), software, firmware, microcode, or any combination thereof, which may be provided as a computer program product, e.g., including a tangible (e.g., non-transitory) machine-readable or computer-readable medium having instructions (or software program) stored thereon for programming a computer to perform the processes discussed herein. By way of example, the term "logic" may also include software, hardware, or a combination of software and hardware. The machine-readable medium may include storage devices such as the storage devices discussed herein.

[0096] As used herein, "an example" or "example" means that a particular feature, structure, or characteristic described in connection with the example can be included in at least one particular implementation. The phrase "in an example" that appears in different places in this specification may or may not all refer to the same example.

[0097] Furthermore, in the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. In some examples, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements in direct physical contact or electrical contact. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but may cooperate or interact with each other.

[0098] Accordingly, although the examples have been described in language specific to structural features and / or methodological acts, it is to be understood that the claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claimed subject matter.

Claims

1. One or more non-transitory computer-readable media having instructions that, when executed, cause a processor to: Determine an uplink / downlink (UL / DL) time slot configuration for communicating with a base station; Determine that a MsgA physical uplink shared channel (PUSCH) timing opportunity (PO) is associated with a flexible symbol, at least based on the UL / DL time slot configuration; Identify a first PO verification rule associated with a radio resource control (RRC) connected state, where the first PO verification rule is for indicating that a MsgA PO on a flexible symbol not designated for downlink (DL) is valid; Identify a second PO verification rule associated with an RRC idle / inactive state, where the second PO verification rule is for indicating that all MsgA POs on flexible symbols are invalid; Select, at least based on whether the processor is associated with an RRC connected state or an RRC idle / inactive state, the first PO verification rule or the second PO verification rule as a verification rule; and Determine whether the MsgA PO is valid, at least based on the verification rule.

2. The one or more non-transitory computer-readable media according to claim 1, wherein the instructions, when executed, further cause the processor to: Implement one of a pre-determined number of UL / DL time slot configuration patterns.

3. The one or more non-transitory computer-readable media according to claim 1, wherein the instructions, when executed, further cause the processor to: Implement a flexible UL / DL configuration, at least based on a stored set of UL / DL configuration patterns.

4. The one or more non-transitory computer-readable media according to claim 1, wherein the instructions, when executed, further cause the processor to: Select the first PO verification rule as the verification rule, at least based on the processor being associated with an RRC connected state; Determine that the MsgA PO is valid, at least based on the verification rule; and Generate MsgA for transmission on the MsgA PO, at least based on determining that the MsgA PO is valid.

5. The one or more non-transitory computer-readable media according to claim 1, wherein the instructions, when executed, further cause the processor to: Select the second PO verification rule as the verification rule, at least based on the processor being associated with an RRC idle / inactive state; Determine that the MsgA PO is invalid, at least based on the verification rule; and Discard the MsgA PO, at least based on determining that the MsgA PO is invalid.

6. The one or more non-transitory computer-readable media according to claim 1, wherein the instructions, when executed, further cause the processor to: Configure a resource grid to prevent receiving a DL channel in a time slot overlapping with one or more MsgA PUSCH symbols; and Configure a resource grid to prevent detecting downlink control information (DCI) indicating that a set of symbols used by the MsgA PUSCH is for downlink.

7. The one or more non-transitory computer-readable media according to claim 6, wherein the instructions, when executed, further cause the processor to: Discard the MsgA PO when the processor is associated with the RRC_CONNECTED state and the flexible symbol is configured as a downlink time slot.

8. The one or more non-transitory computer-readable media according to claim 1, wherein the instructions, when executed, further cause the processor to: Select a first PO verification rule as the verification rule based at least on the processor being associated with the RRC connected state; Determine whether the flexible symbol is indicated for downlink DL by a dynamic time slot format or downlink control information; If it is determined that the flexible symbol is not indicated for downlink DL, determine that the MsgA PO is valid based on the verification rule; and If it is determined that the flexible symbol is indicated for downlink DL, determine that the MsgA PO is invalid based on the verification rule.

9. A computer-implemented method of a processor, comprising: Determine an uplink / downlink UL / DL time slot configuration for communicating with a base station; Determine that a MsgA physical uplink shared channel PUSCH opportunity PO is associated with a flexible symbol based at least on the uplink / downlink UL / DL time slot configuration; Identify a first PO verification rule associated with a radio resource control RRC connection state, wherein the first PO verification rule is used to indicate that a MsgA PO on a flexible symbol not designated for downlink DL is valid; Identify a second PO verification rule associated with the RRC idle / inactive state, wherein the second PO verification rule is used to indicate that all MsgA POs on a flexible symbol are invalid; Select a first PO verification rule or a second PO verification rule as the verification rule based at least on whether the processor is associated with the RRC connected state or the RRC idle / inactive state; and Determine whether the MsgA PO is valid based at least on the verification rule.

10. The computer-implemented method according to claim 9, further comprising: Implement one of a predetermined number of uplink / downlink UL / DL time slot configuration patterns.

11. The computer-implemented method according to claim 9, further comprising: Implement a flexible uplink / downlink UL / DL configuration based at least on a stored set of uplink / downlink UL / DL configuration patterns.

12. The computer-implemented method according to claim 9, further comprising: Select a first PO verification rule as the verification rule based at least on the processor being associated with the RRC connected state; Determine that the MsgA PO is valid based at least on the verification rule; and Generate a MsgA for transmission on the MsgA PO based at least on determining that the MsgA PO is valid.

13. The computer-implemented method according to claim 9, further comprising: Select a second PO verification rule as the verification rule, at least based on the processor being associated with the RRC idle / inactive state; Determine that the MsgA PO is invalid, at least based on the verification rule; and Discard the MsgA PO, at least based on determining that the MsgA PO is invalid.

14. The computer-implemented method according to claim 9, further comprising: Select a first PO verification rule as the verification rule, at least based on the processor being associated with the RRC connected state; Determine whether the flexible symbol is indicated by a dynamic time slot format or downlink control information for downlink DL; If it is determined that the flexible symbol is not indicated for downlink DL, determine that the MsgA PUSCH occasion PO is valid based on the verification rule; and If it is determined that the flexible symbol is indicated for downlink DL, determine that the MsgA PUSCH occasion PO is invalid based on the verification rule.

15. An apparatus for wireless communication, comprising: A memory for storing a first PO verification rule associated with a radio resource control RRC connected state and a second PO verification rule associated with an RRC idle / inactive state, wherein the first PO verification rule is for indicating that the MsgA PO on a flexible symbol not designated for downlink DL is valid, and the second PO verification rule is for indicating that all MsgA POs on the flexible symbol are invalid; and A processing circuit coupled to the memory, the processing circuit being configured to: Determine an uplink / downlink UL / DL time slot configuration for communicating with a base station; Determine that a MsgA physical uplink shared channel PUSCH occasion PO is associated with a flexible symbol, at least based on the uplink / downlink UL / DL time slot configuration; Select a first PO verification rule or a second PO verification rule as the verification rule, at least based on whether the user equipment UE is associated with an RRC connected state or an RRC idle / inactive state; and Determine whether the MsgA PO is valid, at least based on the verification rule.

16. The apparatus according to claim 15, wherein the processing circuit is further configured to: Implement one of a predetermined number of uplink / downlink UL / DL time slot configuration patterns.

17. The apparatus according to claim 15, wherein the processing circuit is further configured to: Implement a flexible uplink / downlink UL / DL configuration, at least based on a stored set of uplink / downlink UL / DL configuration patterns.

18. The apparatus according to claim 15, wherein the processing circuit is further configured to: Select a first PO verification rule as the verification rule, at least based on the UE being in an RRC connected state; Determine that the MsgA PO is valid, at least based on the verification rule; and Generate MsgA for transmission on the MsgA PO, at least based on determining that the MsgA PO is valid.

19. The apparatus according to claim 15, wherein the processing circuit is further configured to: Select a second PO verification rule as the verification rule based at least on the UE being in the RRC idle / inactive state; Determine that the MsgA PO is invalid based at least on the verification rule; and Discard the MsgA PO based at least on determining that the MsgA PO is invalid.

20. The apparatus according to claim 15, wherein the processing circuitry is further configured to: Select a first PO verification rule as the verification rule based at least on the UE being in the RRC connected state; Determine whether the flexible symbol is indicated for downlink DL by a dynamic time slot format or downlink control information; If it is determined that the flexible symbol is not indicated for downlink DL, determine that the MsgA PO is valid based on the verification rule; and If it is determined that the flexible symbol is indicated for downlink DL, determine that the MsgA PO is invalid based on the verification rule.

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