A hardware circuit implementation method for fast multi-objective and multi-task allocation

Abstract

The present invention discloses a hardware circuit implementation method for rapid multi-target multi-task allocation, including constructing a distributor circuit module to lock the allocation result of the current target task; constructing a data transmission control circuit module to generate a write data signal based on the acquired allocation result signal and the PCV request signal from the geometry acceleration module; constructing a read address generation circuit module to generate a counter based on the acquired read data enable signal and output the read data address; constructing a write address generation circuit module; and performing simultaneous transmission of multiple target tasks until the data transmission is completed, at which time the next round of data scheduling is performed. By rapidly distributing the result data generated by four PCV geometry acceleration modules to four rasterization modules, the hardware circuit can complete the allocation of multiple targets and multiple tasks within a single tick clock cycle. When the allocation is completed, data transmission channels are automatically established between multiple tasks and multiple targets, allowing for simultaneous data transmission across multiple targets and multiple tasks.

Description

Technical Field

[0001] The present invention relates to the technical field of computer graphics processor design, in particular to a hardware circuit implementation method for rapid multi-target multi-task allocation. Background Art

[0002] A general-purpose graphics processor based on OpenGL (computer graphics) primarily accelerates OpenGL. Rendering 3D graphics using OpenGL requires many pipeline stages.

[0003] Each pipeline stage needs to complete numerous parallel computing tasks, generating a large amount of data that is then sent to the next stage for further computation. The next stage also has many parallel circuits to process this data. This often leads to the problem of multi-target and multi-task allocation.

[0004] Therefore, how to quickly and efficiently distribute the large amount of parallel data generated by multiple parallel pipelines at the upper level to multiple parallel pipelines at the lower level for processing while ensuring that the data generated by the upper level pipeline cannot be distributed due to untimely distribution, and the lower level pipeline cannot obtain the data, resulting in a waste of computing resources, has become a hot topic in industry research. Summary of the Invention

[0005] The present invention aims to provide a hardware circuit implementation method for rapid multi-target multi-task allocation. This method solves the problems of the prior art by rapidly allocating the result data generated by four PCV geometry acceleration modules to four rasterization modules. To achieve this objective, the present invention provides the following technical solutions:

[0006] A hardware circuit implementation method for fast multi-objective multi-task allocation, comprising:

[0007] Constructing a distributor circuit module to distribute target tasks to a rasterizer according to the PCV request signal of the geometry acceleration module in the hardware circuit. After the target task distribution is completed, the target task distributed to the current rasterizer is eliminated, and the distribution result of the current target task is locked and outputted.

[0008] Constructing a data transmission control circuit module, latching the obtained allocation result of the current target task, and synchronously generating an allocation result signal, and then generating a write data signal according to the obtained allocation result signal and the PCV request signal of the geometric acceleration module;

[0009] Constructing a read address generation circuit module, latching the response signal of the geometric acceleration module PCV as a read data enable signal of the geometric acceleration module PCV. Based on the read data enable signal, enabling the counter and outputting the read data address;

[0010] Constructing a write address generation circuit module, latching the response signal of the raster receiving the current target task assignment, generating a write enable signal, and outputting a write data address;

[0011] After the target task allocation transmission channel is built, multiple target tasks are transmitted simultaneously until the data transmission is completed, and then the next round of data is scheduled.

[0012] As an improvement to the hardware circuit implementation method of the present invention for fast multi-target multi-task allocation, the distributor circuit module is composed of four cascaded 1-level distributors, and its specific implementation method is as follows:

[0013] First, based on the PCV request signal req[3:0] of the geometry acceleration module in the hardware circuit and the raster's preparation completion signal rdy[3:0] when the raster performs target task allocation, a request response signal ack_req[3:0], a preparation completion signal response signal ack_rdy[3:0], and an allocation selection signal arb3_pre / arb2_pre / arb1_pre / arb0_pre when the raster performs target task allocation are generated;

[0014] Next, each level 1 distributor performs priority encoding on the response signal ack_req[3:0] of the request to generate an encoding result pri_code; wherein the encoding result pri_code is the code of the geometry acceleration module PCV to be allocated;

[0015] If rdyx is high, it indicates that the raster to be allocated is ready, so pri_code is selected; otherwise, it indicates that the raster to be allocated is not ready and no task allocation is required, so 4'd0 is selected and the first-level allocator does not allocate. Finally, the first-level allocation result arb_o is generated.

[0016] Again, the 1st level allocation result arb_o is compressed or output to the register, and the response signal ack_rdy_o to the receiving data end is generated. Then, the 1st level allocation result arb_o is bitwise inverted and bitwise ANDed with the input geometry acceleration module PCV request signal req[3:0] to exclude the already allocated request and use it as the next level allocation request.

[0017] Finally, the states of the PCV request signal req[3:0] of the geometry acceleration module and the rasterizer's target task allocation completion signal rdy[3:0] are detected, and the lk_en signal is generated to latch the allocation result and related signals.

[0018] As an improvement to the hardware circuit implementation method of the present invention for fast multi-target multi-task allocation, the specific implementation method of the data transmission control circuit module generating the write data signal is as follows:

[0019] First, the data transmission control circuit module latches the four allocation selection signals arb3_pre / arb2_pre / arb1_pre / arb0_pre according to the allocation result of the target task output by the distributor circuit module, and generates four allocation result signals arb3_rlst / arb2_rlst / arb1_rlst / arb0_rls;

[0020] Secondly, selection is made based on the four obtained allocation result signals arb3_rlst / arb2_rlst / arb1_rlst / arb0_rlst and the geometry acceleration module PCV request data signal rdata3-0;

[0021] Finally, four write data signals wdata3 - 0 are generated, wherein the write data signals wdata3 - 0 are write data buses for four rasterizers.

[0022] As an improvement to the hardware circuit implementation method of the present invention for fast multi-target multi-task allocation, the specific implementation method of the read address generation circuit module outputting the read data address is as follows:

[0023] First, latch the response signal ack_req[3:0] of the generated request and output the read data enable signal ren3-0, wherein the read data enable signal ren3-0 is a read data request for the geometry acceleration module PCV request signal req[3:0]. When the signal is valid, data transmission begins;

[0024] Secondly, the read data enable signals ren3-0 are used to generate four counters respectively. When the value of each counter is equal to the attribute number signal attr_num, the counter is cleared and the read enable signal is invalid, completing a data transfer. Among them, the signal attr_num is the configuration information of the primitive, mainly indicating the number of primitive attributes;

[0025] Finally, four read data addresses are output based on the value of each counter.

[0026] As an improvement to the hardware circuit implementation method of the present invention for fast multi-target multi-task allocation, the specific implementation method of the write address generation circuit module generating a write enable signal and outputting a write data address is as follows:

[0027] First, the response signal ack_rdy[3:0] of the ready completion signal is latched to generate four signals wen0_pre / wen1_pre / wen2_pre / wen3_pre. These four signals are delayed by one beat to generate wen3-0. Among them, signal wen3-0 is the write enable for the raster. When the signal is valid, the corresponding raster starts to receive data. At the same time, the response signal ack_rdy[3:0] is the response signal for the target task assignment to the raster. When the response signal is valid, it indicates that the corresponding raster has been assigned a task and can start to receive the assigned data.

[0028] Secondly, the response signal ack_rdy[3:0] of the latched ready completion signal is delayed by one clock cycle to generate the write data enable signal wen3-0;

[0029] Again, the wen0_pre / wen1_pre / wen2_pre / wen3_pre signals generated by the latch response signal are used to enable the four counters respectively. When the value of each counter is equal to the attribute number signal attr_num, the counter is cleared, the write enable signal is invalid, and a data transmission is completed. Among them, the signal attr_num is the configuration information of the primitive, which mainly indicates the number of primitive attributes;

[0030] Finally, the values of the four counters are delayed by one clock cycle, and four write data addresses are output.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The present invention quickly distributes the result data generated by four geometric acceleration modules PCV to four rasterization modules, so that the hardware circuit of the fast multi-target multi-task distribution in the general graphics processor can complete the distribution of multiple targets and multiple tasks in just one beat clock cycle. When the distribution is completed, it has the advantage of automatically establishing a data transmission channel between multiple tasks and multiple targets, and simultaneously transmitting data among multiple targets and multiple tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the peripheral working environment structure principle of a hardware circuit for fast multi-target multi-task allocation proposed in one embodiment of the present invention;

[0034] Figure 2 This is an abstract circuit diagram of a hardware circuit proposed in one embodiment of the present invention that quickly distributes the results generated by four geometry acceleration modules PCV to four rasterization modules;

[0035] Figure 3A schematic diagram illustrating the implementation principle of a distributor circuit module proposed in one embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the implementation principle of a one-stage distributor proposed in one embodiment of the present invention;

[0037] Figure 5 This is a block diagram of the implementation principle of the data transmission control circuit module proposed in one embodiment of the present invention;

[0038] Figure 6 This is a block diagram showing the implementation principle of a read address generation circuit module proposed in one embodiment of the present invention;

[0039] Figure 7 This is a block diagram of the implementation principle of the write address generation circuit module proposed in one embodiment of the present invention. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0041] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as limiting the present invention.

[0042] The present invention will be described in further detail below with reference to the accompanying drawings, but this does not limit the present invention.

[0043] As an understanding of the technical concept of the present invention, a hardware circuit for fast multi-target multi-task allocation in a general-purpose graphics processor is mainly used to quickly allocate the results generated by the four geometric acceleration modules PCV to the four rasterization modules raster. At the same time: (the signal attr_num is the configuration information of the primitive, which mainly indicates the number of primitive attributes; the signal req indicates the data sending request of the four modules PCV3-0; the signal ack_req indicates the corresponding request response. Once the response signal is valid, it indicates that the corresponding data sending request has been allocated and data transmission can be carried out; the signal raddr3-0 is the attribute address of the output data of PCV3-0, which is the address bus for data transmission; the signal ren3-0's read data request to PCV3-0 is the read data enable signal for data transmission. When this signal is valid, data transmission begins. Signal rdata3-0 is the read data returned by PCV3-0 and serves as the data bus for data transmission. Signal rdy indicates whether the four rasterization modules can receive data. Signal ack_rdy is the response to the assignment of tasks to the four rasterization modules. Once the response signal is valid, it indicates that the corresponding rasterization module has been assigned a task and can begin receiving the assigned data. Signal waddr3-0 is the attribute address to be written to the four raster modules and serves as the data transmission address bus on the raster side. Signal wen3-0 is the write enable signal for the four rasters. When this signal is valid, the corresponding raster begins receiving data. Signal wdata3-0 is the write data bus for the four rasters.

[0044] like Figure 1 As an embodiment of the present invention, a hardware circuit implementation method for fast multi-objective multi-task allocation is proposed, including

[0045] Construct a distributor circuit module to distribute target tasks to a raster according to the PCV request signal of the geometry acceleration module in the hardware circuit. After the target task distribution is completed, the target task distributed to the current raster is eliminated, and the distribution result of the current target task is locked and output.

[0046] like Figure 2 As shown, it can be understood that the main idea of the allocator circuit module is to first assign tasks to a raster, and then when assigning the next raster, eliminate the tasks that have been assigned to the previous raster. When assigning a raster, priority coding is used for PCV requests to find the first request for assignment, and then the assigned PCV request is eliminated, and the remaining requests are used as the next assignment requests again until all tasks are assigned or the target is assigned.

[0047] Based on the above technical concept, the distributor circuit module is composed of four 1-stage distributors in cascade, such as Figure 3-4 As shown, the specific implementation is as follows:

[0048] First, based on the geometry acceleration module PCV request signal req[3:0] in the hardware circuit and the rasterizer's preparation completion signal rdy[3:0] for target task assignment, a request response signal ack_req[3:0] is generated (it can be understood that the signal ack_req indicates the corresponding request response. Once the response signal is valid, it indicates that the corresponding data transmission request has been assigned and data transmission can be performed), a preparation completion signal response signal ack_rdy[3:0] (it can be understood that the signal ack_rdy is a response to the task assignment to the four rasterization modules. Once the response signal is valid, it indicates that the corresponding rasterization module has been assigned a task and can start receiving the assigned data), and an assignment selection signal arb3_pre / arb2_pre / arb1_pre / arb0_pre when the rasterizer performs target task assignment (it can be understood that the assignment selection signal is to assign the result to the four rasterization modules);

[0049] Secondly, each level 1 distributor preferentially encodes the response signal ack_req[3:0] of the request to generate a coding result pri_code; wherein, the coding result pri_code is the code of the geometry acceleration module PCV to be allocated; if rdyx is high, it indicates that the raster to be allocated is ready, and pri_code is selected; otherwise, it indicates that the raster to be allocated is not ready and does not need to be allocated, and 4'd0 is selected, and finally the level 1 allocation result arb_o is generated. The code value of arb_o is the code of the corresponding PCV allocated to the current raster;

[0050] Again, the 1st level allocation result arb_o is compressed or register output to generate the response signal ack_rdy_o to the receiving data end, and then the 1st level allocation result arb_o is bitwise inverted and bitwise ANDed with the input geometry acceleration module PCV request signal req[3:0] to exclude the already allocated request and use it as the request for the next level allocation.

[0051] Finally, the state of the PCV request signal req[3:0] of the geometry acceleration module and the rasterizer's ready completion signal rdy[3:0] for target task allocation is detected, and the lk_en signal is generated to latch the allocation result and related signals.

[0052] Construct a data transmission control circuit module, latch the obtained allocation result of the current target task, and synchronously generate an allocation result signal, and then generate a write data signal based on the obtained allocation result signal and the geometric acceleration module PCV request signal.

[0053] Based on the above technical concept, Figure 5 As shown, it can be understood that the specific implementation method of the data transmission control circuit module generating the write data signal is:

[0054] First, the data transmission control circuit module latches the four allocation selection signals arb3_pre / arb2_pre / arb1_pre / arb0_pre according to the allocation result of the target task output by the distributor circuit module, and generates four allocation result signals arb3_rlst / arb2_rlst / arb1_rlst / arb0_rls;

[0055] Secondly, selection is made based on the four obtained allocation result signals arb3_rlst / arb2_rlst / arb1_rlst / arb0_rlst and the geometry acceleration module PCV request data signal rdata3-0;

[0056] Finally, four write data signals wdata3-0 are generated, where the write data signals wdata3-0 are the write data buses corresponding to the four rasterizers.

[0057] Construct a read address generation circuit module, latch the PCV request signal of the geometry acceleration module and output the read data enable signal, then generate a counter based on the obtained read data enable signal and output the read data address

[0058] Based on the above technical concept, Figure 6 As shown, the specific implementation method of the read address generation circuit module outputting the read data address is:

[0059] First, the latch generates the response signal ack_req[3:0] of the request (it can be understood that the signal ack_req indicates the corresponding request response. Once the response signal is valid, it indicates that the corresponding data transmission request has been allocated and data transmission can be performed), and outputs the read data enable signal r en3-0 (understandably, the signal r en3-0 is a read data request for PCV3-0, which is a read data enable signal for data transmission. When this signal is valid, data transmission begins. The read data enable signal ren3-0 is a read data request for the geometry acceleration module PCV request signal req[3:0]. When this signal is valid, data transmission begins.

[0060] Secondly, the read data enable signals ren3-0 are used to generate four counters respectively. When the value of each counter is equal to the attribute number signal attr_num (it can be understood that the signal attr_num is the configuration information of the primitive, mainly indicating the number of primitive attributes), the counter is cleared and a data transfer is completed.

[0061] Finally, four read data addresses are output based on the value of each counter. At this point, the values of the four counters are the four read data addresses. Next, you need to:

[0062] Construct a write address generation circuit module, latch the raster to receive the response signal when the current target task is assigned, generate a write enable signal, and output the write data address.

[0063] Based on the above technical concept, Figure 7 As shown, the writing address generating circuit module realizes the same idea as the reading address generating circuit module, that is,

[0064] First, the response signal ack_rdy[3:0] of the ready completion signal is latched (it can be understood that the signal ack_rdy is a response to the assignment of tasks to the four rasterization modules. Once the response signal is valid, it indicates that the corresponding rasterization module has been assigned a task and can start receiving the assigned data). The four signals wen0_pre / wen1_pre / wen2_pre / wen3_pre are generated. These four signals beat together to generate wen3-0. Among them, the signal wen3-0 is the write enable for the raster. When this signal is valid, the corresponding raster starts to receive data.

[0065] Secondly, the latch result wen0_pre / wen1_pre / wen2_pre / wen3_pre of the response signal ack_rdy[3:0] is delayed by one clock cycle to generate the write data enable signal wen3-0;

[0066] Again, using the latch results wen0_pre / wen1_pre / wen2_pre / wen3_pre, four counters are generated respectively. When the value of each counter is equal to the attribute number signal attr_num, the counter is cleared, the read enable signal is invalid, and a data transmission is completed. Among them, the signal attr_num is the configuration information of the primitive, which mainly indicates the number of primitive attributes;

[0067] Finally, the values of the four counters are delayed by one clock cycle and four write data addresses are output.

[0068] After the target task allocation transmission channel is built, multiple target tasks are transmitted simultaneously until the data transmission is completed, and then the next round of data scheduling is carried out.

[0069] Based on the above circuit implementation, it can be understood that a hardware circuit for fast multi-target and multi-task allocation in a general-purpose graphics processor can complete the allocation of multiple targets and multiple tasks in one beat. Once the allocation is completed, a data transmission channel is automatically established between the multiple tasks and multiple targets, and multiple targets and multiple tasks can transmit data simultaneously. Therefore, when a large amount of parallel data generated by multiple parallel pipelines at the upper level is quickly and efficiently allocated to multiple parallel pipelines at the lower level for processing, it is ensured that the data generated by the upper pipeline cannot be allocated due to untimely allocation, and the lower pipeline cannot obtain the data, resulting in a waste of computing resources.

[0070] The basic principles, main features and advantages of the present invention are shown and described above. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is limited by the appended claims rather than the above description. Therefore, it is intended that all changes that fall within the meaning and scope of the equivalent elements of the claims are included in the present invention, and any figure signs in the claims should not be regarded as limiting the claims involved.

[0071] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A hardware circuit implementation method for fast multi-target multi-task allocation, characterized in that: The following steps are included Constructing a distributor circuit module to distribute target tasks to a rasterizer according to the PCV request signal of the geometry acceleration module in the hardware circuit. After the target task distribution is completed, the target task distributed to the current rasterizer is eliminated, and the distribution result of the current target task is locked and outputted. Constructing a data transmission control circuit module, latching the obtained allocation result of the current target task, and synchronously generating an allocation result signal, and then generating a write data signal according to the obtained allocation result signal and the PCV request signal of the geometric acceleration module; Constructing a read address generation circuit module, latching the response signal of the geometric acceleration module PCV as a read data enable signal of the geometric acceleration module PCV, enabling a counter according to the read data enable signal, and outputting a read data address; Constructing a write address generation circuit module, latching the response signal of the raster receiving the current target task assignment, generating a write enable signal, and outputting a write data address; After the target task allocation transmission channel is built, multiple target tasks are transmitted simultaneously until the data transmission is completed, and then the next round of data is scheduled.

2. The hardware circuit implementation method of a fast multi-objective multi-task allocation according to claim 1 is characterized in that: The distributor circuit module is composed of four 1-stage distributors in cascade, and its specific implementation is as follows: First, based on the PCV request signal req[3:0] of the geometry acceleration module in the hardware circuit and the raster's preparation completion signal rdy[3:0] when the raster performs target task allocation, a request response signal ack_req[3:0], a preparation completion signal response signal ack_rdy[3:0], and an allocation selection signal arb3_pre / arb2_pre / arb1_pre / arb0_pre when the raster performs target task allocation are generated; Next, each level 1 distributor performs priority encoding on the response signal ack_req[3:0] of the request to generate an encoding result pri_code; wherein the encoding result pri_code is the code of the geometry acceleration module PCV to be allocated; If rdyx is high, it indicates that the raster to be allocated is ready, so pri_code is selected; otherwise, it indicates that the raster to be allocated is not ready and no task allocation is required, so 4'd0 is selected and the first-level allocator does not allocate. Finally, the first-level allocation result arb_o is generated. Again, the 1st level allocation result arb_o is compressed or output to the register, and the response signal ack_rdy_o to the receiving data end is generated. Then, the 1st level allocation result arb_o is bitwise inverted and bitwise ANDed with the input geometry acceleration module PCV request signal req[3:0] to exclude the already allocated request and use it as the next level allocation request. Finally, the states of the PCV request signal req[3:0] of the geometry acceleration module and the rasterizer's target task allocation completion signal rdy[3:0] are detected, and the lk_en signal is generated to latch the allocation result and related signals.

3. A hardware circuit implementation method for fast multi-objective multi-task allocation according to claim 1 or 2, characterized in that: The specific implementation method of the data transmission control circuit module generating the write data signal is as follows: First, the data transmission control circuit module latches the four allocation selection signals arb3_pre / arb2_pre / arb1_pre / arb0_pre according to the allocation result of the target task output by the distributor circuit module, and generates four allocation result signals arb3_rlst / arb2_rlst / arb1_rlst / arb0_rls; Secondly, selection is made based on the four obtained allocation result signals arb3_rlst / arb2_rlst / arb1_rlst / arb0_rlst and the geometry acceleration module PCV request data signal rdata3-0; Finally, four write data signals wdata3 - 0 are generated, wherein the write data signals wdata3 - 0 are write data buses for four rasterizers.

4. A hardware circuit implementation method for fast multi-objective multi-task allocation according to claim 1 or 2, characterized in that: The specific implementation method of the read address generation circuit module outputting the read data address is as follows: First, latch the response signal ack_req[3:0] of the generated request and output the read data enable signal ren3-0, wherein the read data enable signal ren3-0 is the read data request in the geometric acceleration module PCV request signal. When the signal is valid, data transmission begins; Secondly, use the write data enable signal ren3-0 to generate four counters respectively. When the value of each counter is equal to the attribute number signal attr_num, the counter is cleared and the read enable signal is invalid, completing a data transfer. Among them, the signal attr_num is the configuration information of the primitive, mainly indicating the number of primitive attributes; Finally, four read data addresses are output based on the value of each counter.

5. A hardware circuit implementation method for fast multi-objective multi-task allocation according to claim 1 or 2, characterized in that: The specific implementation of the write address generation circuit module generating a write enable signal and outputting a write data address is as follows: First, the response signal ack_rdy[3:0] of the preparation completion signal is latched to generate four signals: wen0_pre / wen1_pre / wen2_pre / wen3_pre. Among them, the signal wen3-0 is the write enable for the raster. When the signal is valid, the corresponding raster starts to receive data. The response signal ack_rdy[3:0] is the response signal for the target task assignment to the raster. When the response signal is valid, it indicates that the corresponding raster has been assigned a task and can start to receive the assigned data. Secondly, the response signal ack_rdy[3:0] of the latched ready completion signal is delayed by one clock cycle to generate the write data enable signal wen3-0; Again, using the latch response signal results wen0_pre / wen1_pre / wen2_pre / wen3_pre, four counters are generated respectively. When the value of each counter is equal to the attribute number signal attr_num, the counter is cleared, the write enable signal is invalid, and a data transmission is completed. Among them, the signal attr_num is the configuration information of the primitive, which mainly indicates the number of primitive attributes; Finally, the values of the four counters are delayed by one clock cycle, and four write data addresses are output.

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