Interval inspection methods, systems, devices, and storage media with bus interfaces

Abstract

This invention relates to the field of computer storage technology, specifically to a method, system, device, and storage medium for interval checking with a bus interface. The method includes: initializing an array memory; wherein, after initialization, all values ​​in the array memory are 0; acquiring required data, generating message configuration information based on the required data, and configuring the message based on the message configuration information; reading from the array memory, comparing the message with data read from the array memory, and checking for overlap; further processing the message based on the message configuration information and the comparison result between the message and the data read from the array memory: deleting or adding; and outputting message processing completion information. This invention can determine whether overlap exists in LBAs and, by checking overlapping areas, perform addition and deletion of logical intervals.

Description

Technical Field

[0001] This invention relates to the field of computer storage technology, and in particular to a method, system, device, and storage medium for interval checking with a bus interface. Background Technology

[0002] Current tape drives primarily support backup technologies such as DAT, 8mm, DLT, LTO, AIT, and VXA. Storage capacity refers to the maximum amount of data a tape drive can store before compression. This value depends on two factors: the storage capacity of a single tape cartridge and the number of tapes the drive can hold. Because tape drives employ various backup technologies, their storage capacities vary.

[0003] Logical Block Address (LBA) is a common mechanism for describing the block of data located on a computer storage device, typically used in auxiliary memory devices like hard drives. An LBA can refer to the address of a specific data block or the data block pointed to by a given address. In modern computers, a logical block is usually 512 or 1024 bits. The ISO-9660 standard CD uses 2048 bits as the size of a logical block.

[0004] LBA is a very simple addressing mode; it starts numbering blocks from 0, with the first block having LBA=0, the second block having LBA=1, and so on. This addressing mode replaces the previous method where the operating system had to deal with the hardware structure of the storage device. The most representative example is CHS (cylinders-heads-sectors) addressing mode, where a block must be specified by an address composed of the hardware location of a specific cylinder, head, and sector on the hard drive. CHS mode has little use for devices other than hard drives (such as tape or network storage devices), so it is usually not used in these places. In the past, MFM (Modified Frequency Modulation) and RLL (Run Length Limited) storage devices used CHS mode, and ATA-1 devices also used Extended Cylinders-Heads-Sectors (ECHS).

[0005] Existing LBAs suffer from overlap, resulting in insufficient use of LBA space. To address this technical problem, a method, system, device, and storage medium for interval checking with a bus interface are proposed. Summary of the Invention

[0006] To address the technical problems existing in the prior art, the present invention provides an interval checking method, system, device, and storage medium with a bus interface. It provides an AXI bus interface, which can perform interval checking on continuous intervals (generally LBAs) and can add and delete logical intervals.

[0007] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0008] In a first aspect, in one embodiment of the present invention, an interval checking method with a bus interface is provided, the method comprising the following steps:

[0009] Initialize the array memory;

[0010] After initialization, all values ​​in the Array memory are 0;

[0011] Obtain requirement data, generate message configuration information based on the requirement data, and configure the message based on the message configuration information;

[0012] Read from the array memory, compare the message with the data read from the array memory, and check for overlap;

[0013] Based on the message's configuration information and the comparison results between the message and the data read from the array memory, the message is further processed: deletion, addition;

[0014] Output a message indicating that the message processing is complete.

[0015] As a further aspect of the present invention, the initialization of the array memory includes obtaining register configuration information and configuring the registers according to the register configuration information;

[0016] The configured registers issue an initialization command for the array memory, thus initializing the array memory.

[0017] As a further aspect of the present invention, the message configuration information includes: operation mode, operation ID, interval length, and interval start address.

[0018] As a further aspect of the present invention, the message is further processed according to the message configuration information and the comparison result between the message and the data read from Arraymemory: deletion, addition, including writing the message processing information into a pending queue.

[0019] As a further aspect of the present invention, the processing completion information of the output message includes: generating completion information in the process;

[0020] Output the OutQueue information.

[0021] As a further embodiment of the present invention, the requirement data and register configuration information are obtained in AXI format, and the message processing completion information is output in AXI protocol format.

[0022] Secondly, in another embodiment provided by the present invention, an interval inspection system with a bus interface is provided, the system comprising: an interface conversion unit 100 and an interval inspection unit 200;

[0023] The interface conversion unit 100 is used to convert input or output data into AXI protocol format; and to realize the conversion from AXI bus to private interface.

[0024] The interval checking unit 200 is used to receive and process demand data and message configuration information from the interface conversion unit; initialize the array memory, generate message configuration information according to the demand data, configure the message based on the message configuration information; read the array memory, compare the message with the data read from the array memory, and check for overlap; further process the message according to the message configuration information and the comparison result between the message and the data read from the array memory: delete, add; and output message processing completion information.

[0025] As a further embodiment of the present invention, the interval inspection unit 200 includes a configuration module 201 and a control module 202;

[0026] The configuration module 201 is used to receive and process requirement data, message configuration information and instruction information from the interface conversion unit;

[0027] The control module 202 is used to initialize the array memory, generate message configuration information according to the required data, configure the message based on the message configuration information, read the array memory, compare the message with the data read from the array memory, and check for overlap; further process the message according to the message configuration information and the comparison result between the message and the data read from the array memory: delete, add; and output the message processing completion information.

[0028] Thirdly, in yet another embodiment of the present invention, an apparatus is provided, including a memory and a processor, the memory storing a computer program, the processor loading and executing the computer program to implement the steps of an interval checking method with a bus interface.

[0029] Fourthly, in another embodiment of the present invention, a storage medium is provided storing a computer program that, when loaded and executed by a processor, implements the steps of the interval checking method with a bus interface.

[0030] The technical solution provided by this invention has the following beneficial effects:

[0031] This invention provides a method, system, device, and storage medium for interval checking with a bus interface. The invention initializes an array memory; after initialization, all values ​​in the array memory are 0. It acquires required data, generates message configuration information based on the required data, and configures the message based on the message configuration information. It reads the array memory and compares the message with the data read from the array memory to check for overlap. Based on the message configuration information and the comparison result between the message and the data read from the array memory, it further processes the message: deleting or adding; and outputs message processing completion information. This invention can determine whether there is overlap in LBAs and, by checking overlapping areas, completes the addition or deletion of logical intervals.

[0032] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention.

[0033] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart of an interval check with a bus interface according to an embodiment of the present invention.

[0036] Figure 2 This is a structural block diagram of an interval inspection system with a bus interface according to an embodiment of the present invention.

[0037] Figure 3 This is a structural block diagram of an interval inspection system with a bus interface according to an embodiment of the present invention.

[0038] In the diagram: Interface conversion unit-100, interval inspection unit-200, configuration module-201, control module-202. Detailed Implementation

[0039] Various embodiments and / or forms are described below with reference to the accompanying drawings. In the following description, numerous specific details are disclosed for illustrative purposes to provide a general understanding of more than one form. However, those skilled in the art will understand that these forms can be implemented without specific details. Specific examples of more than one form will be described in detail in the following description and drawings. However, these forms are merely illustrative and may utilize a portion of the principles and methods of various forms; the descriptions are intended to encompass all forms and their equivalents. Specifically, the terms "embodiment," "example," "form," "illustration," etc., as used in this specification can be interpreted as meaning that any form or design described may be better or more advantageous than other forms or designs.

[0040] Furthermore, various forms and characteristics can be embodied in systems that include more than one device, terminal, server, equipment, component, and / or module. It should be understood and recognized that various systems may include additional devices, terminals, servers, equipment, components, and / or modules, and / or may not include all of the multiple devices, terminals, servers, equipment, components, and modules shown in the figure.

[0041] The terms "computer program," "component," "module," and "system" used in this specification are used interchangeably, and "computer" refers to related entities, hardware, firmware, software, combinations of software and hardware, or the execution of software. For example, a component can be a process executing on a processor, a processor, an object, a thread of execution, a program, and / or a computer, but is not limited thereto. For example, it can be an application program executing on a computer device and / or all components of the computing device. More than one component can be installed within a processor and / or a thread of execution. A component can be localized within a single computer. A component can also be distributed between two or more computers.

[0042] Furthermore, these components can be executed by various computer-readable media constructed to internally store various data. These components, for example, can communicate locally and / or remotely based on signals having more than one data packet (e.g., data emitted by a component interacting with other components on a local system or a distributed system, and data transmitted to other systems via networks such as the Internet).

[0043] Hereinafter, regardless of the symbols used in the drawings, the same or similar constituent elements will be assigned the same symbols, and repeated descriptions of these elements will be omitted. Furthermore, when describing the embodiments disclosed in this specification, detailed descriptions of well-known technologies will be omitted if it is determined that such detailed descriptions would obscure the essence of the invention. Moreover, the accompanying drawings are only for easier understanding of the embodiments disclosed in this specification, and the technical concepts disclosed in this specification are not limited to the drawings.

[0044] The terminology used in this specification is for illustrative purposes and not for limiting the invention. Unless otherwise specified, the singular includes the plural. The use of “comprises” and / or “comprising” in this specification does not exclude the presence or addition of more than one other constituent element in addition to the mentioned constituent elements.

[0045] The terms "first," "second," etc., can be used to describe various elements or components, but the elements or components are not limited to those terms. The terms are used to distinguish one element or component from others. Therefore, the first element or component mentioned below can also be a second element or component within the technical concept of this invention.

[0046] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) are to be understood in the sense commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should not be interpreted ideally or excessively unless specifically defined otherwise.

[0047] Furthermore, the term "or" does not mean exclusive "or" but inclusive "or". That is, unless otherwise specific or contextually ambiguous, "X uses A or B" implies one of the natural connotations. That is, "X uses A or B" can be any of the above when X uses A or B; X uses B or X uses both A and B. And it should be understood that the term "and / or" as used in this specification refers to all possible combinations of more than one of the related items listed.

[0048] In addition, the terms “information” and “data” used in this specification are generally used interchangeably.

[0049] The suffixes “module” and “section” used in the following description of the constituent elements are merely assigned or used interchangeably for the convenience of writing the specification, and they do not have any distinguishing meaning or function in themselves.

[0050] Existing LBAs exhibit overlap, resulting in insufficient utilization of LBA space. This invention aims to determine whether overlap exists in LBAs and to add or delete logical intervals by checking overlapping areas. It provides an interval checking method, system, device, and storage medium with a bus interface.

[0051] Specifically, the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0052] Please see Figure 1 , Figure 1 This is a flowchart of an interval checking method with a bus interface provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the interval inspection method with a bus interface includes steps S10 to S50.

[0053] S10. Initialize the array memory;

[0054] In an embodiment of the present invention, after initialization, all values ​​in the Array memory are 0.

[0055] In an embodiment of the present invention, the initialization of the array memory includes obtaining register configuration information and configuring the registers according to the register configuration information;

[0056] The configured registers issue an initialization command for the array memory, thus initializing the array memory.

[0057] S20. Obtain the requirement data, generate message configuration information based on the requirement data, and configure the message based on the message configuration information.

[0058] In an embodiment of the present invention, the message configuration information includes: operation mode, operation ID, interval length, and interval start address.

[0059] S30. Read the array memory; compare the message with the data read from the array memory to check for overlap;

[0060] S40. Based on the message's configuration information and the comparison results between the message and the data read from the array memory, further process the message: delete or add.

[0061] In an embodiment of the present invention, the message is further processed according to the message configuration information and the comparison result between the message and the data read from the array memory: deletion, addition, including writing the message processing information into the pending queue.

[0062] S50. Output message processing completion information.

[0063] In an embodiment of the present invention, the processing completion information of the output message includes: generating completion information in the OutQueue;

[0064] Output the OutQueue information.

[0065] In embodiments of the present invention, the requirement data and register configuration information are obtained in AXI format.

[0066] The message processing completion information is output in AXI protocol format.

[0067] The AXI (Advanced eXtensible Interface) is a bus protocol.

[0068] The fifo(first in, first out) is a first-in, first-out (FIFO) algorithm.

[0069] This invention initializes the array memory; after initialization, all values ​​in the array memory are 0; it acquires the required data, generates message configuration information based on the required data, and configures the message based on the message configuration information; it reads the array memory, compares the message with the data read from the array memory, and checks for overlap; based on the message configuration information and the comparison result between the message and the data read from the array memory, it further processes the message: deletion and addition; it outputs the message processing completion information; this invention can determine whether there is overlap in LBA, and by checking the overlapping area, it completes the addition and deletion of logical intervals.

[0070] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0071] In one embodiment, see Figure 2 As shown, an interval inspection system with a bus interface is also provided in an embodiment of the present invention. The system includes an interface conversion unit 100 and an interval inspection unit 200, which are communicatively connected.

[0072] The interface conversion unit 100 is used to convert input or output data into AXI protocol format; and to realize the conversion from AXI bus to private interface.

[0073] In an embodiment of the present invention, the interface conversion unit 100 further includes a read, write, and response channel FIFO and a corresponding logic unit.

[0074] In an embodiment of the present invention, the interface conversion unit 100 includes an AXI interface, which is an AXI4slave interface and can be connected to a bus with an AXI4 master interface.

[0075] In an embodiment of the present invention, the interval checking unit 200 is used to receive and process demand data and message configuration information from the interface conversion unit; initialize the array memory, generate message configuration information according to the demand data, configure the message based on the message configuration information; read the array memory, compare the message with the data read from the array memory, and check whether there is overlap; further process the message according to the message configuration information and the comparison result between the message and the data read from the array memory: delete, add; and output message processing completion information.

[0076] In an embodiment of the present invention, the interval checking unit 200 includes a configuration module 201 and a control module 202;

[0077] In an embodiment of the present invention, the configuration module 201 is used to receive and process demand data, message configuration information and instruction information from the interface conversion unit.

[0078] In an embodiment of the present invention, the configuration module 201 consists of a register and in / out queues. The register is used to receive register configuration information and configure the register.

[0079] In an embodiment of the present invention, the control module 202 is configured to receive demand data, message configuration information, and instruction information; initialize the array memory; generate message configuration information based on the demand data; configure the message based on the message configuration information; read the array memory; compare the message with the data read from the array memory to check for overlap; further process the message according to the message configuration information and the comparison result between the message and the data read from the array memory: delete or add; and output message processing completion information.

[0080] In an embodiment of the present invention, the control module 202 includes a control state machine and a storage array. The control module 202 is the main module for implementing interval checking, deletion, and addition.

[0081] This invention can determine whether there is overlap in LBA and add or delete logical intervals by checking the overlapping areas.

[0082] In one embodiment, an apparatus is also provided, including at least one processor and a memory communicatively connected to the at least one processor. The memory stores instructions executable by the at least one processor. The instructions, when executed by the at least one processor, cause the at least one processor to perform the interval checking method with a bus interface, wherein the processor, when executing the instructions, implements the steps in the above method embodiment:

[0083] S10. Initialize the array memory;

[0084] In an embodiment of the present invention, after initialization, all values ​​in the Array memory are 0.

[0085] In an embodiment of the present invention, the initialization of the array memory includes obtaining register configuration information and configuring the registers according to the register configuration information;

[0086] The configured registers issue an initialization command for the array memory, thus initializing the array memory.

[0087] S20. Obtain the requirement data, generate message configuration information based on the requirement data, and configure the message based on the message configuration information.

[0088] In an embodiment of the present invention, the message configuration information includes: operation mode, operation ID, interval length, and interval start address.

[0089] S30. Read the array memory; compare the message with the data read from the array memory to check for overlap;

[0090] S40. Based on the message's configuration information and the comparison results between the message and the data read from the array memory, further process the message: delete or add.

[0091] In an embodiment of the present invention, the message is further processed according to the message configuration information and the comparison result between the message and the data read from the array memory: deletion, addition, including writing the message processing information into the pending queue.

[0092] S50. Output message processing completion information.

[0093] In an embodiment of the present invention, the processing completion information of the output message includes: generating completion information in the OutQueue;

[0094] Output the OutQueue information.

[0095] In embodiments of the present invention, the requirement data and register configuration information are obtained in AXI format.

[0096] The message processing completion information is output in AXI protocol format.

[0097] This invention can determine whether there is overlap in LBA and add or delete logical intervals by checking the overlapping areas.

[0098] The device includes user equipment and network equipment. The user equipment includes, but is not limited to, computers, smartphones, and PDAs. The network equipment includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing, which is a type of distributed computing consisting of a loosely coupled set of computers forming a super virtual computer. The device can operate independently to implement the invention, or it can connect to a network and interact with other devices within the network to implement the invention. The network in which the device operates includes, but is not limited to, the Internet, wide area networks (WANs), metropolitan area networks (MANs), local area networks (LANs), and VPN networks.

[0099] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0100] In one embodiment of the present invention, a storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps in the above method embodiments:

[0101] S10. Initialize the array memory.

[0102] In an embodiment of the present invention, after initialization, all values ​​in the Array memory are 0.

[0103] In an embodiment of the present invention, the initialization of the array memory includes obtaining register configuration information and configuring the registers according to the register configuration information;

[0104] The configured registers issue an initialization command for the array memory, thus initializing the array memory.

[0105] S20. Obtain the requirement data, generate message configuration information based on the requirement data, and configure the message based on the message configuration information.

[0106] In an embodiment of the present invention, the message configuration information includes: operation mode, operation ID, interval length, and interval start address.

[0107] S30. Read the array memory; compare the message with the data read from the array memory to check for overlap;

[0108] S40. Based on the message's configuration information and the comparison results between the message and the data read from the array memory, further process the message: delete or add.

[0109] In an embodiment of the present invention, the message is further processed according to the message configuration information and the comparison result between the message and the data read from the array memory: deletion, addition, including writing the message processing information into the pending queue.

[0110] S50. Output message processing completion information.

[0111] In an embodiment of the present invention, the processing completion information of the output message includes: generating completion information in the OutQueue;

[0112] Output the OutQueue information.

[0113] In embodiments of the present invention, the requirement data and register configuration information are obtained in AXI format.

[0114] The message processing completion information is output in AXI protocol format.

[0115] This invention can determine whether there is overlap in LBA and add or delete logical intervals by checking the overlapping areas.

[0116] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Furthermore, any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include at least one of non-volatile and volatile memory.

[0117] Finally, it should be noted that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0118] The various exemplary logic blocks, modules, and circuits described herein can be implemented or performed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and / or any other such configuration.

[0119] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0120] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0121] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0122] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for interval check with bus interface, characterized in that, The method comprises: initializing the Array memory; wherein, after the initialization, the values in the Array memory are all 0; obtaining requirement data, generating message configuration information according to the requirement data, and configuring the message based on the message configuration information; reading the Array memory, comparing the message with the data read from the Array memory, and checking whether there is an overlap; further processing the message according to the configuration information of the message and the comparison result of the message and the data read from the Array memory: deleting, adding, which comprises writing the message processing information into the pending queue; outputting the processing completion information of the message.

2. The method of claim 1, wherein, The initialization of the Array memory comprises obtaining register configuration information and configuring the register according to the register configuration information; the configured register sends an initialization instruction of the Array memory to initialize the Array memory.

3. The method of claim 1, wherein the bus interface is a PCI bus interface. The message configuration information comprises: operation mode, operation ID, interval length, and interval start address.

4. The method of claim 1, wherein the bus interface is a PCI bus interface. The outputting of the processing completion information of the message comprises: generating completion information into the OutQueue; outputting the OutQueue information.

5. The method of claim 2, wherein the bus interface is a PCI bus interface. The requirement data and the register configuration information are obtained in the AXI format.

6. A spacing checking system with a bus interface, characterized in that The system comprises: an interface conversion unit and an interval checking unit; the interface conversion unit is used for converting the input or output data into the AXI protocol format, and realizing the conversion from the AXI bus to the private interface; the interval checking unit is used for receiving and processing the requirement data, the message configuration information, and the instruction information from the interface conversion unit, initializing the Array memory, generating the message configuration information according to the requirement data, configuring the message based on the message configuration information, reading the Array memory, comparing the message with the data read from the Array memory, checking whether there is an overlap, further processing the message according to the configuration information of the message and the comparison result of the message and the data read from the Array memory: deleting, adding, which comprises writing the message processing information into the pending queue, and outputting the processing completion information of the message.

7. The gauging system with bus interface according to claim 6, characterized in that The interval checking unit comprises a configuration module and a control module; the configuration module is used for receiving and processing the requirement data, the message configuration information, and the instruction information from the interface conversion unit; The control module is configured to initialize the Array memory, generate message configuration information according to demand data, configure the message based on the message configuration information, read the Array memory, compare the message with data read from the Array memory, check whether there is overlap, further process the message according to the message configuration information and the comparison result of the message and the data read from the Array memory, and output processing completion information of the message.

8. An apparatus comprising a memory and a processor, wherein the memory stores a computer program, and the processor loads and executes the computer program to implement the steps of the interval checking method with bus interface according to any one of claims 1-5.

9. A storage medium storing a computer program, wherein the computer program is loaded and executed by a processor to implement the steps of the interval checking method with bus interface according to any one of claims 1-5.

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