Timing signal generating system and control method thereof

Abstract

The present invention discloses a timing signal generation system and a control method thereof. The timing signal generation system includes: a host computer, a field programmable gate array (FPGA), and a timing signal generation device, wherein the FPGA is connected to the host computer and the timing signal generation device, respectively. The FPGA is configured to, upon receiving a parameter write instruction for a target timing signal from the host computer, write the parameters of the target timing signal in the parameter write instruction into a random access memory (RAM) of the FPGA, and, upon receiving a play instruction from the host computer, control the timing signal generation device to play the target timing signal based on the data in the FPGA's RAM. The system has a simple structure, is easy to operate, and can be implemented at a low cost.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a timing signal generating system and a control method thereof. Background Art

[0002] Quantum computers are being extensively researched and developed because their computing speed far exceeds that of classical computers. Through a series of processes, including qubit preparation, calculation, and readout, their computing speed increases exponentially with the number of qubits, which has disruptive implications for the computer industry. Trap ion quantum computers achieve synchronous computation of qubits by manipulating the quantum states of ions, with lasers playing a crucial role in this manipulation process. Indirectly controlling the quantum states of ions by controlling the frequency, amplitude, and phase of lasers is a universal method. Direct Digital Synthesis (DDS) provides a comprehensive and reliable laser control approach for qubit cooling and preparation, calculation, and state readout.

[0003] During the experiment, the ion quantum state DDS control device proposed in the related art mostly requires manual intervention in the switching and repeated playback of sequence control signals. At the same time, the frequency, phase, amplitude and duration parameters of the waveform are switched and controlled through machine instructions. For multi-channel signals, multiple operations are required one by one, which has the disadvantages of complex configuration, cumbersome operation and high cost. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, one object of the present invention is to provide a timing signal generation system that has a simple structure, is easy to operate, and can be implemented at a low cost.

[0005] A second objective of the present invention is to provide a control method for a timing signal generating system.

[0006] To achieve the above-mentioned objectives, a first aspect of an embodiment of the present invention proposes a timing signal generating system, comprising: a host computer, a field programmable gate array (FPGA), and a timing signal generating device, wherein the FPGA is connected to the host computer and the timing signal generating device, respectively; wherein the FPGA is configured to, upon receiving a parameter write instruction for a target timing signal sent by the host computer, write the parameters of the target timing signal in the parameter write instruction into the random access memory (RAM) of the FPGA, and upon receiving a play instruction sent by the host computer, control the timing signal generating device to play the target timing signal according to the data in the RAM of the FPGA.

[0007] To achieve the above-mentioned objectives, a second aspect of an embodiment of the present invention proposes a control method for a timing signal generating system, wherein the timing signal generating system includes a host computer, a field programmable gate array (FPGA), and a timing signal generating device. The method is used for the FPGA, and includes: upon receiving a parameter write instruction for a target timing signal sent by the host computer, writing the parameters of the target timing signal in the parameter write instruction into the random access memory (RAM) of the FPGA; and upon receiving a play instruction sent by the host computer, controlling all channels of the timing signal generating device to simultaneously play the target timing signal according to the data in the RAM of the FPGA.

[0008] According to the timing signal generating system and control method thereof according to the embodiments of the present invention, the parameters of the target timing signal can be written and stored through the internal resources of the FPGA itself, and the data in the RAM can be called in a timely manner when playback is required. Without human intervention, the timing signal generating device is controlled by the FPGA to play the target timing signal according to the data in the FPGA RAM. The system has a simple structure, is easy to operate, and can be implemented at a low cost.

[0009] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a structural diagram of a timing signal generating system according to an embodiment of the present invention;

[0011] Figure 2 is a structural diagram of a timing signal generating system according to an example of the present invention;

[0012] Figure 3 is a structural diagram of a timing signal generating system according to another example of the present invention;

[0013] Figure 4 It is a structural diagram of a timing signal generating system according to a specific embodiment of the present invention;

[0014] Figure 5 is a structural diagram of a timing signal generating system according to another embodiment of the present invention;

[0015] Figure 6 is a structural diagram of a timing signal generating system according to another specific embodiment of the present invention;

[0016] Figure 7 The figure is a flow chart of a control method of a timing signal generating system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0018] Please refer to the following Figure 1-7 The specific implementation manner describes the timing signal generating system and control method thereof according to the embodiment of the present invention.

[0019] Figure 1 FIG. 1 is a schematic diagram of the structure of a timing signal generating system according to an embodiment of the present invention. Figure 1 As shown, the timing signal generating system 1 includes: a host computer 101, a field programmable gate array (FPGA) 102, and a timing signal generating device 103. The FPGA 102 is connected to the host computer 101 and the timing signal generating device 103 respectively. Specifically, upon receiving a parameter write instruction for a target timing signal from the host computer 101, the FPGA 102 is configured to write the parameters of the target timing signal in the parameter write instruction into the random access memory (RAM) of the FPGA 102. Furthermore, upon receiving a play instruction from the host computer 101, the FPGA 102 controls the timing signal generating device 103 to play the target timing signal according to the data in the RAM of the FPGA 102.

[0020] Specifically, through the connection between FPGA102 and the host computer 101, when FPGA102 receives a parameter write instruction for the target timing signal sent by the host computer 101, it can write the parameter data about the target timing signal carried in the instruction into its own RAM, so that when it subsequently receives a play instruction sent by the host computer 101, FPGA102 can access the data previously written in the RAM of FPGA102, and through the connection between FPGA102 and the timing signal generating device 103, it controls the timing signal generating device 103 to generate a corresponding timing signal according to the data in the RAM, that is, the target timing signal, to respond to the play instruction sent by the host computer 101.

[0021] Different from related technologies, the timing signal generation system in the embodiment of the present invention can realize the parameter writing and storage of the target timing signal through the internal resources of the FPGA itself, and call the data in the RAM in time when playback is required, and can realize the generation of timing signals without human intervention. The system structure is simple, the operation is easy, and the cost is low.

[0022] As a possible implementation method, in an embodiment of the present invention, the target timing signal includes at least all timing signals required for an experiment, the parameters of the target timing signal include basic waveform parameters and repeat playback parameters of the target timing signal, and the RAM of FPGA102 includes a timing signal RAM for writing the basic waveform parameters of the target timing signal and a timing signal repeat playback RAM for writing the target timing signal repeat playback parameters, wherein each address bit of the timing signal RAM corresponds to a set of basic waveform parameters, and each address bit of the timing signal repeat playback RAM corresponds to a set of repeat playback parameters.

[0023] Specifically, in the host computer 101, the target timing signal parameters of the current experiment are set according to all the timing signals required for the experiment (i.e., the target timing signal). Since the parameters of the target timing signal include the basic waveform parameters and repeat playback parameters of the target timing signal, the RAM of FPGA102 needs to include a timing signal RAM for writing the basic waveform parameters of the target timing signal and a timing signal repeat playback RAM for writing the repeat playback parameters of the target timing signal, so as to realize the writing and storage of the basic waveform parameters and repeat playback parameters in the target timing signal. At the same time, since the timing signal RAM and repeat playback RAM include multiple addresses Each address bit in the timing signal RAM of this embodiment can correspond to a set of basic waveform parameters, and each address bit in the repeat playback RAM can correspond to a set of repeat playback parameters, so that when FPGA102 receives the playback instruction sent by the host computer 101, it can control the timing signal generating device 103 to play the target timing signal according to the data in the corresponding timing signal RAM and repeat playback RAM without manually switching instructions, and without occupying more memory, it can achieve the specified number of repeated playbacks of any basic waveform, while ensuring the reliability of the playback work, reducing the achievable cost of the timing signal generating system of the embodiment of the present invention.

[0024] Figure 2 This is a structural diagram of a timing signal generating system of an example of the present invention. In some feasible implementations, the timing signal generating device 103 may include a direct digital frequency synthesis DDS (Direct Digital Synthesizer) timing signal generating device 301, the target timing signal includes a DDS timing signal, the timing signal RAM includes a DDS RAM, the timing signal repeat playback RAM includes a DDS Repeat RAM, a set of basic waveform parameters of the DDS timing signal may include frequency, phase, amplitude and duration, and a set of repeat playback parameters of the DDS timing signal may include a start address, an end address and a number of repeat playback times.

[0025] Specifically, because the target timing signal includes a DDS timing signal, the DDS timing signal also has corresponding basic waveform parameters and repeat playback parameters. Therefore, the DDS RAM is required to write and store the basic waveform parameters of the DDS timing signal. Similarly, the DDS Repeat RAM is required to write and store the repeat playback parameters of the DDS timing signal. It can be understood that the start address, end address, and repeat count of the repeat playback parameters specify the address of the basic waveform to be played in the DDS Repeat RAM and the repeat count.

[0026] For example, if the DDS Repeat RAM specifies a starting address of 3, an ending address of 10, and a repetition count of 5 for the basic waveform currently being played, upon receiving the play command, FPGA 102 first controls the playback of the basic waveform data at DDS RAM address 3. Simultaneously, during playback, the parallel processing algorithm within FPGA 102 pre-fetches the basic waveform data at address 3 and prepares it for playback. It then waits for the current pulse width to end before seamlessly generating the basic waveform data corresponding to address 4. Furthermore, the frequency, amplitude, phase, and duration of addresses 3 and 4 can differ. Following this pattern, when the basic waveform data at DDS RAM address 10 begins playing, the basic waveform data at DDS RAM address 3 is again pre-fetched and prepared for playback. When the pulse width of the basic waveform data at address 10 ends, the first repetition is complete, and the basic waveform data corresponding to DDS RAM address 3 is seamlessly generated, initiating the second repetition. Following this playback pattern, five repetitions of data from addresses 3 to 10 are completed, and the next designated playback sequence continues until the experiment concludes.

[0027] Unlike related technologies, in which manual intervention is required for switching and repeating experimental sequence signals in experiments, the parameter switching control of the frequency, phase, amplitude and duration of the waveform through machine instructions requires multiple operations one by one, which leads to complex configuration, cumbersome operation and high cost. In this embodiment, because a set of basic waveform parameters of the DDS timing signal include frequency, phase, amplitude and duration, a set of repeat playback parameters of the DDS timing signal include a start address, an end address and a number of repeat playbacks, after a set of basic waveforms with fixed frequency, phase, amplitude and duration are played according to their corresponding number of repeat playbacks, the next DDS basic waveform with different frequency, phase, amplitude and duration or multiple parameters can be output without interval. This switching control process does not require manual operation or multiple operations one by one, and is easy to operate.

[0028] Figure 3This is a structural diagram of a timing signal generating system of another example of the present invention. In some feasible implementations, the timing signal generating device may further include a transistor-transistor logic circuit TTL (TransisterTransisterLogic) timing signal generating device 302, the target timing signal also includes a TTL timing signal, the timing signal RAM also includes a TTL RAM, the timing signal repeat playback RAM also includes a TTL Repeat RAM, a set of basic waveform parameters of the TTL timing signal may include the high and low polarity of the level and the duration of the high and low polarity of the level, and a set of repeat playback parameters of the TTL timing signal may include a starting address, an end address and the number of repeated playbacks.

[0029] In this embodiment, because a set of basic waveform parameters of the TTL timing signal includes the high and low polarities of the level and the duration of the high and low polarities of the level, and a set of repeated playback parameters of the TTL timing signal includes the starting address, the ending address and the number of repeated playbacks, therefore, after a set of basic waveforms with fixed high and low polarities of the level and fixed duration of the high and low polarities of the level are played according to their corresponding number of repeated playbacks, the next TTL basic waveform with different high and low polarities and duration of the high and low polarities of the level from the current one can be output without interval, and this process does not require manual switching and does not require machine instructions.

[0030] Optionally, in some embodiments, FPGA102 is connected to the host computer 101 via a USB (Universal Serial BUS) interface, and FPGA102 is specifically used to write the timing signal parameters corresponding to each channel into the RAM of FPGA102 one by one according to the valid signal in the parameter write instruction transmitted by the USB interface.

[0031] Specifically, the connection between FPGA 102 and host computer 101 via the USB interface enables FPGA 102 to promptly receive parameter write instructions for target timing signals from host computer 101. Optionally, in some embodiments, before the experiment begins, FPGA 102 can write the timing signal parameters corresponding to each channel (e.g., basic waveform parameters and repeat playback parameters in the embodiment of the present invention) into the RAM of FPGA 102 one by one based on the valid signals in the parameter write instructions corresponding to all timing signals required for the experiment.

[0032] Furthermore, in some embodiments of the present invention, the FPGA 102 is further configured to complete writing of RAMs of all DDS and TTL channels upon receiving a parameter transmission completion instruction from the host computer 101 and wait for a play instruction.

[0033] Specifically, when FPGA 102 receives a parameter write instruction for the target timing signal from host computer 101, it writes the parameters of the target timing signal in the parameter write instruction into the RAM of FPGA 102, that is, it performs the writing and storage of the target timing signal parameters until the host computer sends a parameter transfer completion instruction, which indicates that all timing signal parameters required for this experiment have been transferred, and the RAM write of all DDS and TTL channels has been completed. The system then waits for the host computer 101 to send a play instruction. In this embodiment, after all timing signal parameters have been transferred, the host computer 101 sends a parameter completion instruction, so that FPGA 102 can promptly complete the channel RAM write when the instruction is parsed, thereby improving the timeliness of the parameter transfer work and shortening the experiment duration.

[0034] Furthermore, after completing the RAM writing work for all DDS and TTL channels, it is necessary to wait for the play instruction and play the target timing signal according to the data in the RAM. In some feasible implementations, when the FPGA102 receives the play instruction, it can be specifically used to control all DDS and TTL channels to start the play sequence according to the parameters in the corresponding RAM at the same time; Figure 4 As shown, the TTL timing signal generating device 302 may include a buffer 3021 . When controlling the TTL channel playback sequence, the FPGA 102 may be specifically configured to generate 16 aligned TTL timing signals with adjustable delays and output them via the buffer 3021 .

[0035] It is understandable that, since the DDS RAM of the FPGA 102 in the embodiment of the present invention stores the DDS timing signal parameters of multiple channels, and the TTL RAM stores the TTL timing signal parameters of multiple channels, when it receives a play instruction, it can promptly call the parameters in the corresponding RAM and control all channels of DDS and TTL to play the experimental sequence according to the parameters in the corresponding RAM.

[0036] Further, if Figure 5 As shown, in some embodiments of the present invention, the timing signal generating system 1 may further include a clock generating device 104, which is connected to the FPGA 102 and the DDS timing signal generating device 301 respectively, and is used to provide corresponding clock signals to the FPGA 102 and the DDS timing signal generating device 301.

[0037] As a possible implementation, Figure 6As shown, the clock generating device 104 in the embodiment of the present invention may include: a crystal oscillator 401, which is used to generate a local clock; a clock power divider 402, which is connected to the crystal oscillator 401, the FPGA 102 and the low-noise clock phase-locked generating circuit 403, and is used to generate three first clock signals under the action of the local clock, two of which are given to the low-noise clock phase-locked generating circuit 403, and one is given to the FPGA 102; the low phase-noise clock phase-locked generating circuit 403, which is connected to the DDS timing signal generating device 301, and is used to generate four second clock signals as system clocks under the action of one first clock signal, and give them to the first four channels of the DDS timing signal generating device 301, and generate 12 third clock signals under the action of another first clock signal, and give them to the last 12 channels of the DDS timing signal generating device 301 as system clocks.

[0038] That is to say, after the crystal oscillator 401 generates a local clock, the clock power divider 402 generates three first clock signals under the action of the local clock, one of which is given to the FPGA 102 and two are given to the low-noise clock phase-locked generation circuit 403. One of the two first clock signals acts on the low-noise clock phase-locked generation circuit 403 to generate four second clock signals used as the system clock, and the other acts on the low-noise clock phase-locked generation circuit 403 to generate 12 third clock signals, and these 12 third clock signals are used as the system clocks of the last 12 channels of the DDS timing signal generating device 301.

[0039] The timing signal generation system of an embodiment of the present invention uses the timing signal RAM and timing signal replay RAM included in the FPGA's RAM to write and store target timing signal parameters. Upon receiving a playback instruction, the system uses the FPGA's internal resources to repeat any basic waveform a specified number of times, without requiring additional memory, thereby generating the target timing signal. This system simplifies configuration, facilitates operation, and reduces implementation costs. Furthermore, without requiring manual intervention or machine instructions, it enables the sequential coordination of sixteen DDS channels and sixteen TTL channels, reducing the complexity of the experimental process.

[0040] Furthermore, an embodiment of the present invention also proposes a control method for a timing signal generating system, the timing signal generating system comprising a host computer, a field programmable gate array (FPGA), and a timing signal generating device, and the control method for the timing signal generating system can be used for the FPGA. In some embodiments, Figure 7 As shown, the control method of the timing signal generating system may include:

[0041] S101 , when a parameter write instruction of a target timing signal sent by a host computer is received, the parameters of the target timing signal in the parameter write instruction are written into a random access memory RAM of the FPGA.

[0042] S102 , when receiving a play instruction sent by the host computer, controlling the timing signal generating device to play the target timing signal according to the data in the RAM of the FPGA.

[0043] It should be noted that, for other specific implementations of the control method of the timing signal generating system according to the embodiment of the present invention, reference may be made to the specific implementations of the timing signal generating system according to the above embodiment of the present invention.

[0044] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device), or in conjunction with such instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transmit a program for use by an instruction execution system, apparatus, or device, or in conjunction with such instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0045] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0046] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0047] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0049] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0050] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0051] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A timing signal generating system, characterized in that: The system comprises: a host computer, a field programmable gate array (FPGA) and a timing signal generating device, wherein the FPGA is connected to the host computer and the timing signal generating device respectively; The FPGA is configured to, upon receiving a parameter write instruction for a target timing signal sent by the host computer, write the parameters of the target timing signal in the parameter write instruction into a random access memory (RAM) of the FPGA, and upon receiving a play instruction sent by the host computer, control the timing signal generating device to play the target timing signal according to the data in the RAM of the FPGA; The target timing signal includes at least all timing signals required for one experiment, the parameters of the target timing signal include basic waveform parameters and repeat playback parameters of the target timing signal, the RAM of the FPGA includes a timing signal RAM for writing the basic waveform parameters of the target timing signal and a timing signal repeat playback RAM for writing the repeat playback parameters of the target timing signal, wherein each address bit of the timing signal RAM corresponds to a set of basic waveform parameters, and each address bit of the timing signal repeat playback RAM corresponds to a set of repeat playback parameters; The timing signal generating device includes a direct digital frequency synthesis (DDS) timing signal generating device, and the target timing signal includes a DDS timing signal; A set of basic waveform parameters of the DDS timing signal includes frequency, phase, amplitude and pulse duration, and a set of repeated playback parameters of the DDS timing signal includes the starting address, ending address and repeated playback times of the basic waveform parameter RAM.

2. The timing signal generating system according to claim 1, wherein: The timing signal RAM includes a DDS RAM, and the timing signal repeat playback RAM includes a DDS Repeat RAM.

3. The timing signal generating system according to claim 2, wherein: The timing signal generating device also includes a transistor-transistor logic circuit TTL timing signal generating device, the target timing signal also includes a TTL timing signal, the timing signal RAM also includes a TTL RAM, and the timing signal repeat playback RAM also includes a TTL Repeat RAM. A set of basic waveform parameters of the TTL timing signal include the high and low polarities of the levels and the duration of the high and low polarities of the levels, and a set of repeat playback parameters of the TTL timing signal include a starting address, an end address, and a number of repeated playback times.

4. The timing signal generating system according to claim 3, wherein: The FPGA is connected to the host computer via a USB interface. The FPGA is specifically used to write the timing signal parameters corresponding to each channel into the RAM of the FPGA one by one according to the valid signal in the parameter write instruction transmitted by the USB interface.

5. The timing signal generating system according to claim 4, wherein: The FPGA is further configured to complete writing of the RAM of all DDS and TTL channels upon receiving a parameter transmission completion instruction sent by the host computer, and wait for the play instruction.

6. The timing signal generating system according to claim 3, wherein: When the FPGA receives the play instruction, it is specifically used to control all channels of DDS and TTL to start the play sequence according to the parameters in the corresponding RAM at the same time; The TTL timing signal generating device includes a buffer. When controlling the TTL channel playback sequence, the FPGA is specifically used to generate 16-channel aligned TTL timing signals with adjustable delays and output them through the buffer.

7. The timing signal generating system according to claim 3, wherein: The system further includes a clock generating device, which is connected to the FPGA and the DDS timing signal generating device respectively, and is used to provide corresponding clock signals to the FPGA and the DDS timing signal generating device.

8. The timing signal generating system according to claim 7, wherein: The clock generating device comprises: Crystal oscillator, used to generate local clock; a clock power divider connected to the crystal oscillator, the FPGA, and the low-noise clock phase-locked generation circuit, configured to generate three first clock signals under the action of the local clock, two of which are supplied to the low-noise clock phase-locked generation circuit and one to the FPGA; A low phase noise clock phase-locked generation circuit is connected to the DDS timing signal generating device and is used to generate four second clock signals under the action of one first clock signal as system clocks, and to supply the first four channels of the DDS timing signal generating device, and to generate twelve third clock signals under the action of another first clock signal, and to supply the last twelve channels of the DDS timing signal generating device as system clocks.

9. A control method for a timing signal generating system, characterized in that: The timing signal generating system includes a host computer, a field programmable gate array (FPGA), and a timing signal generating device. The method is applied to the FPGA, including: When receiving a parameter write instruction of a target timing signal sent by the host computer, writing the parameters of the target timing signal in the parameter write instruction into the random access memory RAM of the FPGA; When receiving the play instruction sent by the host computer, controlling the timing signal generating device to play the target timing signal according to the data in the RAM of the FPGA; The target timing signal includes at least all timing signals required for one experiment, the parameters of the target timing signal include basic waveform parameters and repeat playback parameters of the target timing signal, the RAM of the FPGA includes a timing signal RAM for writing the basic waveform parameters of the target timing signal and a timing signal repeat playback RAM for writing the repeat playback parameters of the target timing signal, wherein each address bit of the timing signal RAM corresponds to a set of basic waveform parameters, and each address bit of the timing signal repeat playback RAM corresponds to a set of repeat playback parameters; The target timing signal includes a DDS timing signal; a set of basic waveform parameters of the DDS timing signal includes frequency, phase, amplitude and pulse width duration; a set of repeated playback parameters of the DDS timing signal includes the starting address, ending address and number of repeated playbacks of the basic waveform parameter RAM.

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